Note: Descriptions are shown in the official language in which they were submitted.
L'7~
The present invention relates to a video game
apparatus, particularly a business-use video game
apparatus which can be played Eor pay i..e. by i.nsertion of
a valuable medi.um such as coin through an inlet slot.
There has been known and in practical use the
so-called TV game or video game apparatus in which game
characters are displayed on a screen of a display such as
a color CRT and are controlled for play by e.g. joy sticks
or control switches.
The conventional video game machines can be
roughly classi.Ei.ed into two categories i.e. those for home
use and those for commercial use. Hitherto, regardless of
the above categori.es, video game machines were avai.lable
in alternative types, in one of which one video di.splay
screen is used by two players, in another of which one
display screen is used in common by two persons for
simultaneous playing and in yet another of which a
plurality of video display screens are used by one person
for playing alone. So far, however, no proposal has been
made for such a video game machi.ne wherein a plurality of
video di.splay screens are used by a plurality of persons
for simultaneously playing the same kind of game. More
particularly, no such video game machine has been known to
date whereln the same game is displayed on a plurality of
display screens for the game characters, not only on each
player's di.splay screen but also on others' di.splay
screens being controllable by any of the plurality of
players by the use of individual control means.
The simplest idea for making such a video game
machine may be simply putting together or combining
conventional vi.deo game machines. However, such a video
game machi.ne ;s bound to be more than twice as expensive
as a conventional counterpart.
It i.s, therefore, a principal object of -the
present invent;on to provide a novel video game apparatus
with which a plurality of persons can play the same game
displayed on a plurality of screens of a plurality of
displays.
~,3~L'7B~.
Generally, the present invention provides a
v:ideo game apparatus comprising a cabi.net having opposite
sides, a pai.r oE displays mounted on the opposite sides of
the cabinet, a pair of manually operable operating means
S mounted on the cabinet, each oE the operating means being
associated wit:h a separate one of the video displays, a
pair o control means for applying video data signals to
corresponding ones of the displays in response to the
state oE corresponding ones oE the operating means, and
data transfer means for receiving data from one of the
control means and transferring such data to the other of
the control means, whereby data is able to be transEerred
between the pair of control means so that similar game
i.mages can be displayed on the pair of displays in
response to eit.her of the pair of operating means.
~ccording to the present invention, there are
provided corrlmunication means for data transfer between a
plurality of sets of control means, i.e. computer systems,
whereby i.t is possible for a plurality of players to en~oy
the same game heing displayed on a plurality of displays,
each p1ayer with his own set of control means being
capable of controlling also the game characters on the
others' display. Also, since in the present invention the
communication means are used in common for the plurality
~5 of sets of control means, it is defini.tely more compact
and les~ expen~ive than in conventional counterpart video
game machi.nes which are constructed by simply docking a
plurality oE video game machines.
~he present invention w.ill become more apparent
from the following detailed description of the preEerred
embodiments when taken in conjuncti.on with thè
accompanying drawings, in which:-
Figure 1 (which appears on the same sheet as
Figures 4 to 6) is a general perspecti.ve view showing a
preferred embodiment of the present invention;
Figure 2 is a block diagram showing one example
of the electronic circuit of the embodiment in Figure l;
'78~
Figures 3A and 3B are flow charts given Eor
lllustrati.on oE the manipulation or operation oE the
present invel-tjon;
Figures 4 through 6 are views showing the
respect;.ve flags i.n the memory diagrammatically.
Figure 1 is a general perspective view showing
an embo~li.ment oE the present invention. The video game
apparatus of thi.s embodi.ment comprises a cabinet 1 wi.th
legs for installation. Thi.s cabinet 1 includes a table
which i.s subst~lltially T-shaped i.n side view and a cabinet
whi.ch i.s trape~o;.dal in side view and placed on the table.
On opposite sl.anting sides oE the trapezoid-secti.oned
cabinet there ~-?re arranged two di.splays, i.e. CRTs 2 and 3
in back-to-back relationship to each other. ~ther types
of di.splays can also be used, besides the CRT shown in
Figure J., such as known liqui.d crystal displays, plasma
displays, EL d;splays and so on. On the slanting si.des of
the trapezoid-sectioned cabinet there are also provided
coin slots 4 and 5. The coin slots 4 and 5 are inlets for
coins a.s valuahle mèdia as the price for playing the game,
hence the video game machine of the present embodiment is
intended for commercial use. Besides coins, cards such as
magnetic cards or optical cards can be used as valuable
media.
On the opposite sides of the table portion of
the cabinet 1 t.here are provided various operating means,
switche.s, etc. which are manipulated for playing various
games. On Ollf? side of the cabinet (lefthand si.de in
Figure 1) there are provided two sets of operating means
which i.nclude: two joy sti.cks 6 and 12; four operating
buttons 8, 10, 14 and 16; and four mode buttons lB, 20, 22
and 24. On the other side of the cabinet (righthand side
shown in Figure 1) there are similarly two sets of
operating means which include: two joy sticks 7 and 13;
four operating buttons 9, 11, 15 and 17; and, further four
mode buttons 19, 21, 23 and 25. In thi.s video game
machine up to ~our persons can play a game using the four
sets of operat;ng means, respectively. ~s well known, the
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joy sti.cks 6, 12, 7 and 13 are Eor moving game characters
on the screens of C~Ts 2 and 3 vertically as well as
laterally, whi.le the operati.ng buttons 8, 10~ 1~, 16, 9,
11, 15 and 17 ~re for causing the game characters to move
in speci.fic manners such as jumping, shooting or hitting.
~lso with this video game machine any one oE .Eour
alternative mo~les can be chosen for playing the specific
game. The mode buttons 18, 22 and 19, 23 are used for
selecting a fi.rst mode, and the mode buttons 20, 24 and
21, 25 are use(l for selecting a second mode. IE, for
instance, this ~7ideo game machine is for playing a tenni.s
game, the first mode button 18 and the second mode button
20 may he used to select the "singles" mode, whi.le the
first mode button 22 and the second mode button 24 may be
used to select the "doubles" mode. Similarly, the Eirst
mode button 19 and the second mode button 21 may be used
to select the "singles" mode, while the first mode button
23 and the second mode button 25 may be used to select the
"doubles" mode. The first mode buttons 18, 22, 19 and 23
are used to select the first mode of this video game
machi.ne, that is, the mode in which the players on each
side are to play independent games, while the second mode
buttons 20, 24, 21 and 25 are used to select the second
mode in which the players on the opposite sides are to
play the sa~e game, i.e., against each other. This means
that in the f;.rst mode each player is to play the game
against the correspondin~ computer system built i.n the
cabinet 1 as the opponent, while in the second mode he i.s
to play against the player on the opposite side.
The types of games that can be played also
include, besides the aforesaid tennis game, other
simulated ball games, card games, mah-jong and the like.
Figure 2 is a block diagram showing an
embodiment oE the present invention. The left side of
Figure 2 shows one computer system 26 and the right side
thereof sho~7s the other computer system 27. The computer
system 26 is for the CRT 2 on the left side i.n Figure 1,
while the computer system 27 is for the CRT 3 on the right
~3~'7~
si.de in F;.gure 1. The computer system 26 includes a CPU
(central processing unit) to which the relat~d mode
buttons 18, 20~ 22 and 24 are connected. The CPU 28 i.s
further provided with a coin selector 30 for i.dent;.Eyi.ng
the type and l:he value oE the coin i.nserted through the
coin slot 4. Thi.s coin selector 30 may be substituted
with a card reader or the like lf the valuable medium used
is a card. Further, the operating means 6 - 16 are
connected to tlle CPU 28, which are, however, omi.tted in
Figure 2.
.~s tl~e CRU 28, for instance, MOS Technology's
6502 is used. The CPU 28 is connected with a ROM ( read
only memory) 36, a RAM (random access memory) 38 and a PPU
(picture processing unit) 40 through a 16-bit address bus
32 and an 8-bi.-t data bus 34. The ROM 36 stores an
operating program and game program for the CPU 28, and
Intel's 2765, for instance, can be used as ROM 36. As the
RAM 38, for instance, Hitachi's 6116 may be used and the
same is used for storage of the necessary data for
progress o.E the game. For the PPU 40, whi.ch is Eor
processing or controlling of the CRT 2 according to the
data from the (PU 28, for instance, Nintendo's 2C03 may be
usedO Further, a character ROM 42 and a video R~M 44 are
connected to ~.he PPU 40. For both of these, Hit~chi's
6116 may be used, for instance. The character ~OM 42 i.s
for presenti.ng the characters required for the game such
as a ball or player in the case of a ball game or a card,
etc. in the case of a card game. The video RAM 44 i.s
employed for the presentation of the background of the
game e.g. a court, net or goal in the case of, for
instance, a bal.l game.
The ~PU 28 has also connected thereto a sound
generator 46 whi.ch emits effective sounds as necessary.
The other computer system 27 similarly comprises
a CPU 29, and this CPU 29 as well as its related memories
37, 39, 41, 43 and 45 are arranged in the same manner as
with the computer system 26, hence detailed descri.ption
thereof is here omitted to avoid redundancy. The CPU 29
has further conllected thereto the mode buttons 19, 21, 23
and 25 and, E~lrthermore, the operati.ng means 7 - 17 for
game shown i.n Figure 1, although these are omitted i.n
Figure 2. A co;n selector 31 and a sound generator 47 are
connected to the CPU 29 and are identi.cal with the coi.n
selector 30 and the sound generator 46 descri.bed above.
In thi.s embodi.rrlent a C-RAM tcommon random access
memory) 101 i.s provided for constituting communication
means. Thi.s C~~AM 101 may be a static R~M and may be, for
instance, Hi.tachi.'s C-MOS RAM 6116, whose capacity is, for
instance, 2Ks. This C-RAM 101 has connected thereto an
address bus li.ne 103 from an address selector 102 and a
data bus line 106 from tri-state buffers 104 and 107
constituting a gate circuit. As the address selector 102,
for instance, Texas Instruments' 74LS157, which is a TTL,
circui.t is used. Address selector 102 is used for
selectively corlnecting to the address bus li.ne 103 ei.ther
address bus line 32 or 33. The tri-state buffer 104 is
connected betw~en the data bus lines 34 and 106, and the
2n tri-state buEEer 107 between the data bus lines 35 and
106, respecti.vely. As these tri-state buffers 104 and
107, for instance, Texas Instruments' 74LS245 can be used,
which assumes one of the three states, "1", "O" or "high
impedance", acording to the given signalO To selector
1.02 and the tri-state buffers 104 and 107 are connected a
signal line .lO8 from the output port oE the CPU 28
included in tho computer system 26. That is, this si.gnal
line 108 is connected to a terminal IRQ of the CPU 29
included i.n the other computer system 27 and also to a
control term.inal of the address selector 102 and,
furthermore, il. is connected to the tri-state buff~.r 107
and thence to the other tri-state buffer 104 through an
inverter 105. A signal line 109 from the output port of
the C:PU 29 i.s connected to a terminal IRQ of the CP~ 28.
Hence, the C-~AM 101 etc. formi.ng the communication rneans
is basically controlled by the signal line 108 from t.he
output port of the CPU 28 included in the computer system
26. Thi.s means that in communication means network 101
~3~1L'7t3~
109 pri.ority is given in case oE competition to the CPU 29
over the CPU 2~.
Needl.ess to say, the ICs used i.n thi.~ circuit
are not limi.ted to those mentioned above, and sirni.lar or
even diEferent ICs may as well be used, and i.t is even
possible to use sti.ll more di.screte parts.
Although the PPUs 40 and 41 are for display on
the CRTs 2 and 3 with RGB termi.nals, other methods e.g.
NTSC color TV system may as well be used for drivi.ng the
CRTs.
Referring to the embodiment shown in Figure 2,
described below is the manner in which d.~ta transfer i.s
accomplished ~etween computer system 26 and the other
computer system 27 by the use of the communication means
101.
In their initial states the signal lines 108 and
109 of the output ports of the CPUs 28 and 29 are both
disposed i.n tlle logic state "0". Since the tri-state
buffers 104 and 107 are both driven at a low level, the
tri-state buf:Eer 107 is activated at that time, and
therefore the data bus lines 35 and 106 are connected.
Meanwhile, si.nce the logic "1" inverted by the inverter
105 is gi.ven to the tri-state buffer 104, the buffer 104
ls then in the state of "high impedance" and the
connection between the data bus lines 34 and ]06 is
disconnected~ At the same time, the logic state "0" is
given also to the address selector 102, hence this
selector 102 selectively connects the address bus li.ne 33
to the address bus line 103. Thus, C-RAM 101 becomes
accessible for the computer system 27. In this state the
computer system 27 is capable of writing data into the C
RAM 101 and of reading data therefrom. In order to have
the other computer system 26 prevented from usi.ng the C-
RAM 101 while the computer system 27 is using the same, it
is so a.rranged that the CPU 29 outputs the logic "1" to
the signal line 1~9. Then the terminal IRQ ~interrupt
request terminal) of the CPU 28 receives the logic signal
"1", and the C~U 28 recognizes it to know that the C-RAM
8 ~3~
101 i5 unusable at the moment. Meanwhile, the sig~al li.ne
108 from the Cru 28 is then in the logic "0", which logic
l-0ll is transmitted to the terminal IRQ of the CPU 29, and
the CP~ 29 is then accessible to the C-RAM 101 through the
address bus lines 33 and 103 and the data bus line 35 and
106. When the CPU 29 has finished using the C-R~M 101,
the output part of CPU 29 shifts to the logic "0", and
whereby the other computer system 26 is accessible to the
C-RAM 101.
When the signal line 109 from the output port of
the CPU 29 has come to be in the logic "0", the CPU 28
confirms the logic "0" being input to the terminal IRQ and
has its output port raised to the logic "1". Hence, the
logic "l" is then input to the terminal IRQ of the CPU 29,
and the CPU ?.9 then recognizes that the C-RAM 101 is
inaccessible at the moment.
When the signal line 108 from the output port oE
the CPU 28 i.s raised to the logic "l", the address
selector 102 selectively connects the address bus line 32
to the address bus line 103. At the same time, the logic
"0" inverted by the inverter 105 is given to the tri-state
buffer 104 so that the data bus line 34 and 106 can be
connected by the tri-state buffer 104. Meanwhile, the
logic "1" is given to the other tri-state buffer 107, and
hence thi.s buf~er 107 comes to be in the state of "high
impedance" and the connection between the data bus li.nes
35 and 106 is disconnected. Thus, the CPU 28 is then
capable of writing data into the C-RAM 101 or of reading
data therefrom through the address bus lines 32 and 103
and the data b~ls lines 3~ and 106.
When the computer systems 26 and 27 try to
access C-RAM 101 simultaneously, the CPU 28 checks the
state of its terminal IRQ. Since the both CPUs 28 and 29
were then not connected to the C-RAM lOl, the termi.nal IRQ
of the CPU 28 is in the logic "0". Hence, the CPU 28
outputs the logic "l" to its output port, and the logic
"1" is given to the terminal IRQ of the CPU 29 through the
signal line 108. And then the CPU 29 recogniæes that the
9 ~3~'7~3~
C-RAM lnl i.s ;naccessi.ble~ at the moment. Thust priori.ty
if yiven to the computer system 26 when it (CPU ~8
competes wi.t.h l:.he computer system 27 ~CPU 29).
Access to C-RAM 101 ls obtained as described
above, and when, for instance, data :Erom the CPU 28 is
written i.nto a given address i.n the C-RAM 101 and ;.t i.s
later read out oE the same address in the C-RAM 101 by tlle
CPU 29, data is transferred from the CPU 28 to the CPt~ 29.
Data transfer Erom the CPU 29 to the CPU 28, too, can be
done in the same manner by the use of a given address ln
the C-RAM 101.
In tlle above embodiment data transfer between
the two computer systems 26 and 27 is accompli.shed
indirectly through the medium of the C-RAM 101. There
are, however, many other possible means of communication.
For i.nstance, if the CPUs 28 and 29 are both
relatively hi.gh in processing speed, direct data transfer
is feas;.ble through the connèction li.nes ~not shown)
directly link;ng the CPU ports without the medium of a
common memory means such as C-RAM 101.
It i.s also possible to use a DMA (direct memory
access) system. When the CPU 29 demands data rom the CPU
28, the content of RAM 38 may be directly read into RAM
39, and in the opposite case it is feasible by letting the
CPU 28 copy of the content of the RAM 39 into the RAM 38.
Furtller, as communication means addition~l RAMs
(not shown) cc)nnected to CPUs 28 and 29 may as well be
used. It may then be so arranged that the CPUs 28 and 29
write data into the RAMs 38 and 39, respectively, at the
same time the same data is written into the addi.tional
RAMs connected to the opposite side so that the CPU on the
opposite sicle can read data as necessary from the
additional RAMs connected thereto.
Thus, si.nce quite a number oE alternati.ves may
be used Eor the communication means, the best possible one
may be chosen by taking the cost, simplicity of circuitry
and other factors into consi.deration.
10 ~LY~3~7E3~
Next, re.Eerring to the flow charts in Fi.gllres 3A
and 3s as we:Ll ~s to Figures 4 to 6, the mode o~ operation
for the e~nbodi.ment shown i.n Figures 1 and 2 is described
below. In the explanation bel.ow, the cornputer ~ystem 26
or CPU 2n i.s referred to as that of "hi.s own" and the
computer system 27 or CPU 29 as that of the "the
opponent's".
In the first step 201 of the mode of operati.on,
the CPU 28 determines by the data from the coin selector
30 whether hi.s own credit (Cl) is equal to or larger than
half of the amount of credit (Q) (=Q/2) or not. ~[f hi.s
own cred;.t (Cl~ is less than (Q/2), the CPU 28 sets the
second mode flag FL 12 of R~M 38 in Figure 4 to the logic
"0" in the subsequent step 203 so that the player can
recogni3e that the second mode is unfeasible. If it is
"YES" i.n the step 201, the CPU 28 determines in the next
step 205 whether the sum of his own credit (Cl) and the
opponent's credi.t (C2) i.s equal to or larger than the
quantity of credit (Q) required for playing the second
mode or not. If it is "NO" in thi.s step 205, the second
mode flag F:L 12 is set to the logi.c "0" in the step 203.
While if it is "YES", the second mode flag FL 12 is set to
the logic "1". Thus, judgement is made whether the coin
(valuable medi.um~ paid is up to the quantity of credit
2~ required for ~:I.aying the second mode of game or not, and,
if not, select;.on of the second mode is prohibited.
AEter setting or resetting the second mode flag
FL 12 in the step 203 or 207, t~e-CPU 28 determines in -the
next step 209 whether his own credit (Cl) is equal to or
larger than the amount of credit (P) requi.red for playing
the first mode or not. If it is "NO" in this step 209,
the logic "0" i.s written into the Eirst mode flag FL 11 oE
R~M 38 (Fi.gure 4) in the next step 211, and if it is
"YES", tlle logic "1" is written into the first mode flag
FL 11. Then the CPU 28 checks whether the first mode
button 18 (or 22) i.s depressed or not, and if it is "NO",
it proceeds to the step 219 uncondi.tionally, whi.le iE it
is "YES", proceedi.ng to the step 219 only i.n the case
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11
where th~ first-. mode flag FL 11 is not set to the logi.c
"1" in t.he next step 217. In the step 219 the CPU 28
ascertai.ns whether the second mode button 20 (or 24) i.s
depressed or not.
If tlle first mode Elag FL 11 should be set in
the preced;ng step 217, the CPU 28 undertakes processing
're~ui.red for playinq the Eirst mode of game. That is, in
the next step 221 i.t subtracts the quantity oE credit
required Eor p'!ayi.ng the first mode of game (P) from the
player's own credi.t (Cl) and stores the balance as the
player's new ho~di.ng of credit (Cl). And then i.t accesses
a predetermi.necl address in the C-RAM 101 in the method as
aforesaid, and the logic "1'l is written into the first
mode flag FL 1.11 in the step 223 as shown in Figure 6
accordi.ngly. 'tt i.s thus possi.ble to inform to the CPU 29
that the CP~ 2~3 is operati.ve in the first mode. The CPU
28 then executes the first mode of game (in the step 225).
The ~outine of the game may as well be known one, hence
detai.led explallation about it will be omitted here also
because i.t is oF no particular importance with regard to
the present invention. It is as already explained above
that in the first mode of game joy stick 6 and operating
buttons 8 and 10 in Figure 1 and/or joy stick 12 and
operating buttons 14 and 16 are used so that the player
can play ayai.nst: the computer system 27 as the opponent.
When the Eirst mode of game 225 is over, the CPU
28 writes the logic "0" into the first mode flag FL 111 of
the C-R~M lOl.
When the CPU 28 has detected that the second
mode button 20 (or 24) has not been depressed yet in the
step 219, the next step 229 is proceeded to and, there the
CPU 28 judges wllether the first mode flag FL 121 of C-RAM
101 is the lo(~ic "1" or not. This means determini.ng
whether the opponent's game mode is in the first mode or
not. And, if it is "YES" in this step 229, further
checki.ng is made in the step 231 to see whe-ther the first
mode flag FL 1.1 of the player's own RAM 38 is the logic
"1" for the first mode of game to be feasible on the
12
player's own si(le. If the first mode of game i.s feasible,
a di.splay reacling "Press the button 18 (or 22)." i.8 shown
on the CRT 2 (Fi.gure 1) i.n the next step 233. If the
first mode of game is also not feasible, there Eollows
return to the ini.tial step 201.
If i.t is "NO" in the step 229, the CPU 28 checks
to see whether the second mode Elag 122 of the C-R~M 101
is the logic "1" for judging whether the second mode is
selected by the opponent's side. If it is "YES" in thi.s
step 235, a d;.splay reading "Press the button 20 ~or 24)."
is shown on tlle CRT 2 (Figure 1) in the next step 237.
l~ it i.s "NO" in the step 235, the CP~ 28 checks
to see whether the second mode flag FL 12 of the player's
own RAM 38 i.s the logic "1" for the second mode of game to
be feasible Otl hi.s own side. If it is "NO", there follows
a return to the previous step 231, whereas if it is "YES",
a check i.s madc~ to see whether his own ~irst mode ~lag FL
11 is likewise l-he logic "1" for the first mode of game to
be feasible. ~Lf the first mode of game is feasible, in
2l) the step 242 a di.splay readi.ng "Press the button 18 (or
22) or 20 (or 24)." is then shown on the CRT 2 (Figure 1).
After going through the display step 233, 237
and 242 there follows return to the initial step 201.
If i.t is "YES" in the previous step 219 (Fi.gure
3A), the CPU 28 checks to see whether the player's own
second mode flag FL lZ is the logic "1" in the step 241
for the second mode of game to be -feasible. If it is "NO"
in thi.s steps 241, the CPU28 checks to see whether the
second mode flag FL 122 of the C-RAM 101 is the logic "1"
for judging whether the game mode of the opponent's side
is in the secol~d mode.
If i.t i.s "YES" in the previous step 241, the
program proce--ds to the step 245, and there the CP~ 28
writes the logic "1" into the second mode flag FL 112 of
the C-RAM lOl. Then in the step 247 there follows a
predetermined delay time e.g. 5 secondsO When the time is
over, the second mode Elag FL 112 of the C-RAM 101 is
fallen to the ~ogic "0" in the next step 249 beore the
13 ~3~
program returns to the i.ni.ti.al step Z01. If it should be
judged before Ille ti.me is over that the .second mode Elag
FL 122 o:F the C-RAM lOl for the opponent's side i.s the
logic oE "1", that is, the opponent, too, has selected the
second mode, the CPU 28 subtracts half the quanti.ty (Q/2)
of credit. ~Q) reyuired for playing the second mode from
the player's own credit (Cl) in the next step 253, and
stores the bal.i~nce as the player's new holding of credi.t
(Cl~. Therl tlle second mode of game is executed ;.n the
step 255. By the way, as explained above, not only can
the di.splay On the CRT 2 of the player's own side, but
also that on the CRT 3 of the opponent's side can be
changed by oper.ltion of the operati.ng means 6 - 16 (Figure
1), and not on]y can the display on the CRT3/ but also the
display on the CRT2 can be changed by means o~ the
operati.ng means 7 - 17 on the opponent's side. As also
explai.ned above, the data transfer therebetween is to be
carried out in thi.s embodi.ment by the use in common oE the
data region of the C-RAM 101.
When the second mode of game is over, the CPU 28
shi.Ets the second mode flag FL 112 of the C-RAM 101 to the
logic "0", thi~ followed by return of the program to the
initial step 2~)1.
If i.t is "YES" in the above-mentioned step 243
(Figure 3Aj, t~le CPU 29 on the opponent's side subtracts
half the quant;ty of credit (Q/2) required for playing the
second mode from the opponent's credit (C2) and stores the
balance in th~ M 39 as the opponent's new holding of
credit (C2). 'l'hen the CPU 29 shifts the secon~ mode flag
Fl. 112 oE the C'-RAM 101 to the logic "1l' in the step 261,
and the routine of the step 255 for the second mode of
game is entel-ed, the second mode of game being also
feasible thi.s way.
IE it is "NO" in the step 243, the program
proceeds to the step 229 as in the case where it is "NOI'
i.n the step 219.
When i.n the above embodi.ment the first mode of
game is l:o be played on the player's side and the opposite
14 ~23~
~i.e. opponent's) si.de i.ndependent of each other, the
contents oE th-~ games may be i.denti.cal or the possibi.lity
oE choos;.ny Erom a number o.E alternatives may as we:l.l be
provided. In the latter case, a plurality of game
software (I~Ms) may be provi.ded so that any of thereoE is
selectable at wi.11.
~hi.le an embodiment of the present inventi.on has
been describe(1 and illustrated above in detai.l, i.t i.s
clearly understood that the same is by way of illustrati.on
and example only and i.s not to be taken by way oE
li.mitation, the spirit and scope oE the present i.nventi.on
being li.m;.ted by the terms of the appended claims.
