Note: Descriptions are shown in the official language in which they were submitted.
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I field Of The InyentiQn
The invention relates to the field of controllers for
interfacing between a digital computer and a floppy disk drive.
The disclosed invention is particularly suited for implementation
as an integrated circuit.
I Prim Art
Poppy disk controllers for interfacing between digital
computers and floppy disk drives are well known. Such disk
I drive include a motor for rotating a floppy disk, a floppy disk
being comprised of a flexible material shaped such that it is
flat and circular and onto which is bonded a magnetic medium; a
write head for recording data on the magnetic medium and a read
head for reading data from the magnetic medium; a stepper motor
for moving the read and write heads along the surface of the
floppy disk; and electronic and logic circuitry for receiving
binary signals which turn the disk drive motor on and off, move
the read and write heads and cause electrical signals to be sent
to the write head for recording data or receive electrical
signals generated by the read head as the magnetic medium rotates
past it. Disk drive controllers generate the necessary binary
signals to turn the disk drive motor on and off, move the read
and write heads and send appropriate signals to the electronic
and logic circuitry of the disk drive to cause the read and write
heads to read from or write to the magnetic medium of the
rotating floppy disk. Disk drive controllers generate the
appropriate signals to control the operation of disk drives by
appropriate control, data and clock signals received from a
digital Cooper.
~l~3~6~
In United States Patent No. 4r210,959, a floppy disk drive
controller it disclosed comprised of a serial/parallel shift
register controller logic and timing means and latches. The
serial/parallel shift register is used to transfer data to and
from the computer on a data bus. The controller logic and timing
means receives signals from the latches to place the controller
logic means in one of four possible modes of operation namely,
read, sense write protect/write initialize, write record and
write load. ~11 reading and writing is done in a synchronous
manner based upon a clock ~iqnal ILK. The aforesaid invention is
directed to a relatively simple, inexpensive controller suitable
for consumer and small business applications. The present invent
lion is an integration of the controller disclosed in United
States Patent No. 4,210,959 with extensions and improvements
including the capability of multiple modes of operation.
BRIEF SUMMARY OF THE INVENTION
A peripheral device controller for example
a floppy disk drive controller interlace is disclosed which
is implemented in an integrated circuit. The controller connects
to a host computer data bus and one or more floppy disk drives
S Based upon clocking and control signals received from a digital
computer, the controller generates serial encoded data for
recording on a floppy disk and receives serial encoded data
previously recorded on a floppy disk. The controller compare en
read control means including a read data register, write control
means including 2 write data register, a mode register, a status
register, state latches, a decoder and special function
registers. The controller operates by the setting and clearing
of the state latches and reading or writing the mode register,
the status register, the special function registers, the read
data register and tube write data register. The jetting of a
state latch and accessing of a register is done simultaneously
The controller, under software control, operates in a synchronous
or asynchronous read/write mode, and slow or fast read/write
mode.
Control signals received by the controller from the computer
jet or reset one of eight state latches. Two of the latches
select one of two disk drives and turn the drive motor of the
selected disk drive on or off. Four of the latches control a
stepper motor in the disk drive which cause the read and write
heads to move from track to track of the floppy disk. The
remaining two latches are coupled to the decoder which decodes
clocking and control signals received from the computer and
generates signals to the various registers of the controller and
to the read control means and write control means for controlling
the function to be performed by the disk drive.
~3~J~'7
BRIEF D~s~lR~I~L9F THE Roy
Figure 1 illustrates the controller of the present invention
interfacing between a digital computer and a floppy disk drive,
Figure 2 is a block diagram of the controller of the present
s invention.
Figure 3 is a detailed block diagram of the read control
means of the present invention.
Figure 4 is a detailed block diagram of the write control
means of the present invention.
~32~6'~
DETAILED DESCRIPTION OF THE INVENTION
A floppy disk drive controller, implemented as an inter-
rated circuit, is disclosed for providing an interface between
a digital computer and a floppy disk drive. In the following
description, numerous specific details are set forth such as
specific word or byte lengths, etc., to provide a thorough
understanding of the present invention. However, it will be
obvious to one skilled in the art that the present invention may
be practiced without such specific details. In other instances,
well-known circuits have been shown in block diagram form in
order not to obscure the present invention in unnecessary detail.
Unless otherwise stated, for convenience, positive logic will be
used to describe the invention. Thus, the terms set, "1", high
and true are equivalent as are the terms reset, "0", low and
false.
The presently preferred embodiment of the controller provides
an interface between microcomputers manufactured by Apple Compute
or, Inc. of Cupertino, California such as its Apple-II computer
and successors thereto, and floppy disk drives such as Disk II
manufactured by Apple Computer, Inc., and successors thereto.
Referring first to Figure 1, the controller 11 of the
present invention is shown as an interface between a digital
computer 13 and a floppy disk drive 15. The digital computer 13
is coupled to the controller 11 through a bidirectional data bus
17 (DODD), control lines AYE, device select line Diversity
line RESET and clock lines Q3 and FOLK. Although not part of the
present invention, also shown in Figure 1 is boot ROM or PROM 19
which is coupled to the digital computer through data bus 17,
address bus 21 AYE) and an enable line FABLE When the
computer is first turned on, or whenever it is necessary to
*Trade Mark
~232~:36~7
reinitialize the computer operating system, a program stored in
boot ROM 19 is utilized Jo instruct the controller 11 to read a
program recorded on a floppy disk in disk drive 15 and transfer
it over data bus 17 to computer 13. Such boot or boot strap
programs are well known in the art and will no further discussed
herein.
Data on data bus 17, depending upon signals which have been
placed on control lines AYE, comprises a byte of data which has
been received from the disk drive, which is to be sent to the
disk drive or which is to be loaded into or read from registers
within the controller 11. The controller 11 is selected by the
computer by a I on line DEW and is placed in an initial state
by a no" on line RESET. Clock signals generated by the computer
on lines Q3 and FOLK are used by the controller as timing
signals. Clock signals Q3 and FOLK are generated with periods
which depend on the speed of the processor in the computer. In a
preferred embodiment, Q3 is a 2 MHz clock and FOLK is a 7 MHz
clock. Additionally, Q3 may be left at I if only asynchronous
mode is used) and/or FOLK may be 8 MHz.
Data/control lines between the controller 11 and disk drive
15 are as follows. Signals on lines Pi through Pi control a
stepper motor 22 which rotates a unit turn in either a forward or
backward direction depending upon the signals on lines Pi through
Pi. In a typical floppy disk drive, a unit turn is a one quarter
turn, a one eighth turn, or a one sixteenth turn, however, this
value is strictly drive dependent. Each unit turn of the stepper
motor causes the read and write heads to move a unit distance in
a forward Of backward direction. The unit distance the heads
move is also drive dependent, but typical unit distances are one-
half or one-quarter track. The binary signals on lines Pi
'7
through Pi are input to track select amplifiers 23 which convert
the binary signals into a voltage which rotates the stepper motor
22.
Signals on WRDATA are binary signals generated by the
controller and are input into read/write amplifiers 25 of disk
drive 15. Signals on NRDATA cause read/write amplifiers 25 to
energize or de-energize the write head coil 26 to cause data to
be written on the magnetic medium as it spins under the write
head. Signals on WRECK enable or disable write head coil I to
allow or prevent the writing of data based on WRDATA. Similarly,
as the magnetic medium passes under the read head, the read head
coil 26' is energized or de-energized and the detected data is
converted by the read/write amplifiers 25 into a binary signal
which is placed on line RDDATA.
write protect sense signal is generated by the disk drive
15 and placed on the SNOWS line when a switch 28 in the disk
drive is closed to indicate that the disk drive has been placed
in a write protect state. Such switch may be a mechanical witch
operated by a user and/or a switch which detects whether a floppy
disk jacket has a write protect notch, such as, for example a
photocell which causes a transistor switch to close when light to
it is blocked by the floppy disk jacket.
Lastly, drive select signals are generated by the controller
and placed on lines Enable or ENABLE. Enable is input to a first
disk drive and ENABLE is input to a second disk drive. Each of
these Enable or EYEBALL inputs is coupled to a drive motor
amplifier 27 which converts the binary signal into a voltage to
cause a motor 29 in the disk drive to rotate thereby spinning a
floppy disk which has been inserted into the disk drive. On the
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disclosed e~bcdiment, a jingle bit in the controller it used to
venerate a signal on ENA~Ll or ENABLE and, therefore, only one of
two drives can be selected at any given point in time. Of
course, with additional hardware, additional drives can be
connected to the controller. It should be noted that although
only one set of lines is shown as being coupled to controller 11,
with respect to lines such as SENSE, which may be set for one
drive and reset for the other, appropriate logic circuits are
employed to ensure that only signals from the selected drive are
input to the controller logic.
Referring now to Figure 2, the main components of the
controller 11 will now be described. The invented controller
comprises mode register 31; status register 33; read l's register
35; handshake/~nderrun flag register 37; state latches 39;
lo decoder 41; read control means 45 and write control means 47.
Read control means 45 and write control means 47 will be
discussed more fully below with respect to Figures 3 and 4
respectively.
Once the controller 11 has been selected by the computer 13
by a signal on DEW and the controller has keen initialized by a
signal on RESET (which sets the state latches to their default
values), the controller is instructed by the computer to perform
a particular function by signals on AYE which set or reset one
of eight state latches 39 (Pi through Pi and Lo through Lo). It
should be understood that regardless of the states of the latches
Pi through Pi and Lo through Lo, unless the controller has been
selected by a signal on Deaf no operations will be performed by
the controller. DODGY enables the controller when it is low. The
falling edge of DEW latches information on A through I One of
the aforesaid eight latches is set by a I on A and reset by a
2~6~7
I on A. The particular latch to be jet or reset based upon A
is determined by the address set on Al through A. Table 1 shows
the addresses on Al through A which correspond to latches Pi
through Pi and Lo through Lo.
isle
O O O PO
0 0 - 1 Pi
0 1 0 Pi
o 0 1 1 Pi
1 0 0 Lo
1 0 1 Lo
1 1 0 Lo
1 1 1 Lo
Signals on Pi through Pi cause the stepper motor 22 to
operate as follows. Setting Pi causes the stepper motor to be
placed in an initial state readying it for a one unit turn in
either a forward or backward direction depending upon the next
signal received. If the next signal received is Pi it when
latch Pi is set), the stepper motor turns one unit which causes
the read and write heads to move a unit distance forward. If Pi
is set after Pi, then the stepper motor turns one unit in the
opposite direction and the read and write heads step one unit
distance backwards. At this print, both Pi and Pi are set (or Pi
and Pi if the reads are being moved backwards) and Pi is cleared.
After Pi is cleared, assuming additional forward head travel is
desired, Pi is set which causes the stepper motor to turn an
additional unit in the forward direction stepping the read and
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write heads another unit distance forward. If additional head
movement in the forward direction is necessary, Pi is cleared and
Pi is set causing an additional unit turn of the stepper motor
In a similar manner, if backwards mover lent of the read and write
heads axe necessary, and Pi has been set followed by Pi, Pi is
cleared and Pi is set followed by the clearing of Pi and the
setting of Pi, each of which causes the stepper motor to rotate a
unit turn in the opposite direction and step the read and write
heads a unit distance in a backwards direction. Further cycle
of PO, Pi, Pi Pi for forward motion) or Pi, Pi, Pi, Pi (for
backwards head travel), may be issued by the computer 13 by
addresses on A through Awl as appropriate, to cause the read and
write heads to move to any desired track.
The setting and clearing of Lo through Lo determine other
functions to be performed by the controller 11 as described below.
After the controller has been selected by DEW and
initialized by RYE and WRITE MODE REGISTER is set as described
below, Do through Do on the data bus 17 are loaded into the mode
register 31 to select a particular mode of operation for
subsequent reads and writes. The data on Do through Do
correspond respectively to the signals LATCH, SYNCH, OUT, FAST
and I of the mode resister. LATCH will by discussed more fully
below with respect to the read control means 45 and Figure 3.
SYNCH, when cleared, places the controller in a synchronous mode
for subsequent reads and writes. When SYNCH is set, subsequent
reads and writes are performed in an asynchronous mode. Both
synchronous and asynchronous modes of operation will be discussed
more fully below with respect to Figures 3 and 4.
OUT when cleared enables a one second on board timer. When
OUT is set, the timer is disabled. The on board timer will be
TV
discussed more fully below with respect -to Enable and ENABLE
which select one of two disk drives which are coupled to the
controller.
When FAST is cleared, the con-troller operates in slow mode.
Normally, internal -timing of the controller is based upon the
clock signal ILK which is equal to the clock signal FOLK
generated by -the computer. When FAST is cleared, internal
timing, i.e. ILK period, is equal to twice the period of FOLK.
.3/7 also relates to timing and FOLK. When an 8 MHz clock
is in use, 8/7 is set. If FOLK is running at 7 MHz, 8/7 is
cleared. queue value of 8/7 is used by the controller to determine
how many FOLK periods are required for a given unit of time.
For example, if FOLK is 8 MHz, one microsecond will be eight
clock periods; if ELK is 7 MY one microsecond will be seven
I clock periods. This allows computers with 7 MHz clocks and
computers with 8 MHz clocks to read and write equivalently, that
is, data written by a computer with a 7 MHz clock can be read
by a computer with an 8 MHz clock and visa versa.
after the mode register has been loaded to set up particular
modes of operation, one of the two drives is selected by latch
Lo as follows. When latch Lo is cleared, drive 1 is selected.
When latch Lo is set, drive 2 is selected. After a drive has
been selected, setting latch Lo will cause line MOTOR-ON to go
to "1". When latch 1.4 is set, if latch Lo is "O", drive 1 is
enabled by Enable, if Lo is "1", drive 2 is enabled by ENABLE.
OUT mentioned above can now be described. When OUT it
set, if Lo LO cleared, Enable or ENABLE is disabled by logic
circuit 42, which includes the inboard timer depending upon the
sullenly old Lo, thereby shutting down drive motor 29. I~oweveJ-,
if OUT is cleared, then the clearing of Lo will not cause logic
circuit 42 to disable Enable or ENABLE until
11
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a one second timer has elapsed lit LATCH is reset or until a one-
half millisecond timer has elapsed if LATCH is set). Generally
it is preferable that there be a delay before turning off a drive
motor because subsequent disk operations frequently occur in a
very short time frame after prior disk operations. Thus, without
the delay before disabling Enable ox ENABLE, subsequent disk
operations would be subjected to waiting for the motor to achieve
proper speed. Of course, the operation system or other program
in the computer should include appropriate waits or timing loops,
when necessary, to ensure that no disk reads or writes are
requested until the drive motor is up to speed
Additional functions performed by the controller are deter-
mined by the settings of Lo, Lo, and MOTOR-ON. Lo, Lo and MOTOR-
ON select which register is to be read or written as described
below. Registers are read during any operation in which A is
being cleared. Registers are written to when A it being set.
Lo, Lo, MOTOR-ON, A and DEW are input to decoder 41 which
decodes the inputs and, as described below, places a I on one
of the lines READ STATUS REGISTER, WRITE MODE REGISTER, WRITE
DATA REGISTER, READ DATA REGISTER READ l's REGISTER or READ
HANDSHAKE/UNDERRUN SLAG REGISTER. Each of the following
operations take place as the falling edge of DEW is input to
decoder 41.
When Lo, Lo and MATRON are Jon, the decoder 41 places a
"1" on READ l's REGISTER which causes the read l's register 35 to
place a byte ox binary l's on the data bus 17, lines Do through
Do. The I on the data bus are read into the memory of the
computer for use by the operating system or other program.
When Lo, Lo are I and MOTOR-ON is lo the decoder 41
places a I on READ DATA REGISTER. The function performed when
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READ DATA REGISTER is set will be discussed below with reference
to the read control jeans I and Figure 3.
When Lo is I Lo is I and MOTOR-ON is I or I (i.e.
don't care, the decoder 41 places a I on REAR STATUS REGISTER
which causes the contents of the mode register 31 and status
register 33 to be placed on data bus 17, such that the bus takes
on the following values; LATCH is placed on Do, SYNCH is placed
on Do, OUT is placed on Do, FAST is placed on Do, 8~7 is placed
on Do, MOTOR-ON is placed on Do, a 0 is placed on Do and SENSE,
from the disk drivel is placed on Do. The operating system or
other program in the computer 13 is then able to determine the
status of controller 11.
When Lo is "on, Lo is "1" and MOTOR-ON is I or I the
decoder 41 places a I on READ HANDSHAKE/~NDERRUN FLAG REGISTER
which causes the handshake/underrun flag register 37 to place
lo on Do through Do, an underrun flag URN on Do and a
handshake flag HO on Do. The underrun flag URN and the handshake
flag HO will be discussed with respect to the write control means
47 and Figure 4.
When Lo is lo Lo is No" and MOTOR-ON is Jon, the decoder
41 places a I on WRITE MODE REGISTER and the data on Do through
Do of the data bus 17 is written into the mode register 31 with
Do corresponding to LATCH, Do corresponding to SYNCH, Do cores-
pounding to OUT, Do corresponding to FAST and Do corresponding to
8/7. This occurs during WRITE MODE REGISTER at the rising edge
of the logical function Q3 or DEW.
When Lo, Lo and MOTOR-ON are lo the decoder 41 places a
no" on WRITE DATA REGISTER. The function performed when WRITE
DATA REGISTER is set will be discussed below with reference to
write control jeans 47 and Figure 4.
2~7
The read control means 45 will now be discussed with
reference to Figure I As noted above, with Lo and Lo equal to
"0 and MOTOR-ON equal to I the decoder 41 places a I on
READ DATA REGISTER. Of course, prior to reading, the read head
is moved to the desired track of the floppy disk by rotating the
stepper motor 22 according to control signals on Pi through Pi as
described above. As the floppy disk rotates under the read head,
data recorded the track causes the coil in the read head to be
energized and de-energized causing fluctuations on RDDATA
corresponding to jet bits and cleared bits on the magnetic
medium. At this time, neither the controller nor the computer
can determine which portion of a track is under the read head.
Therefore, a method for determining where data reading should be
started is necessary. A method for providing proper
synchronization for such purpose is described in United States
Patent No. 4,210,959.
Once synchronization has been obtained, reading proceeds as
follows. The read data extractor 51 detects negative transitions
of RDDATA synchronized to the CUR clock signal. Each time a
negative transition of RDDATA occurs, it resets an interval
counter. When 8/7 is set, the interval is 16 Elks. When B/7 is
reset, the interval is 14 Claris The information on RDDA~A is
spaced at these intervals or around" these intervals. A lo is
a negative transition at the expected time, i.e. interval. A I
is no transition at the expected time. The expected time is
widened by approximately one-half an interval before and after
the expected time wince the data it not precisely spaced when
read due to variations in drive speed and other external factors
A negative transition of RDDATA is detected as a I and the
read data extractor 51 causes the signal LFTl to pulse to a "1"
I
for one COLIC cycle. The next expected data is nominally at 16 Elks
when 3/7 is set. This may range between 16-8=8 Elks and 16-~7=23
ELKS, Thus, if another negative transition of RDDATA occurs
between 8 and 23 Clucks, another I is detected and LFTl pulses to
a "1" for one ILK cycle. If no negative transition occurs on
RDDATA between and 23 Elks a "0" is detected and LFT0 pulses to
"1" for one ILK cycle.
If a LFTl has occurred within -the expected -time, the
interval counter is reset, otherwise the next expected data is
nominally at 32 Elks. This may range between 32-~=24 ELKS and
32+7=39 Elks. If a negative transition of RDDATA occurs between
24 and 39 Elks, a I is detected and LFTl will pulse to "1" for
one ILK cycle. If no negative transition of RDDATA occurs a "0"
is detected and LFT0 will pulse to "1". Similarly, subsequent
intervals are widened from the nominal number of Elks by minus
Elks and plus 7 Elks with LFTl being pulsed if a negative trays-
it ion of RDDATA occurs within the widened interval and L.FT0 being
pulsed if there is no negative transition of RDDATA. When
I is reset, LFT0 and L,FTl are pulsed as described above, except
intervals are nominally 14 Elks and are widened minus 7 Elks and
plus 6 Clucks.
LFTO and LFTl are input to shut register data logic
circuitry 53 which sets line 55 if LFTl is "1" or Clark line
55 if LFTO is "1" unless SR7 is "1" (as described below), the
data on line 55 being the data input to shift register 57.
The data on line 55, when shift register 57 is signaled by
shift clock 59 by a signal on Line 60, is input to the showoff:
register one bit a-t a time. Shift clock So sets line 60 a:
the end of each LFTl pulse or LFT0 pulse except when .SR7 its swept
SR7 is set after a full byte of data has been shifted into the shift
I
register. This occurs because the initial bit received by the
shift register 57 from the data stored on the disk is always a
I according to the group code coding scheme utilized for
storing data on the diskette. Wherein the leading bit of a byte
is always a n 1 n .
Once SR7 is set, load read data register logic 61 generates
a signal on line 63 which causes the data in shift register 57 to
be parallel loaded into the read data register 65. The shift
register 57 is cleared one half a read shift clock after SR7 is
set so that it it ready to accept the next byte of data.
The signal on line 63 is set by load read data register
logic 61 as follows.
In synchronous mode, i.e. when SYNCH is "on, when X7 is
reset, the read data register 65 is loaded with the data in the
shift register 57 each time the shift register 57 shifts by the
setting of line 63 by load read data register logic 61. However,
when X7 is set, item when the first bit of the byte being read
arrives at the far end of the shift register and is parallel
loaded into the read data register 65, the load read data logic
61 will hold line 63 low for four Elks after Sol (corresponding
to bit 1 of shift register 57) becomes I due to the first bit
of the next byte being shifted through shift register 57. This
delay is to ensure that the byte in the read data register 65 is
there, and therefore available to be routed to buffer 66 and on
data bus 17 Do through Do, long enough to be seen by the computer
13, but not long enough to be seen as a valid byte twice. The
rising edge of Do is delayed by hold read data register logic 67
so that if Do it read by the computer 13 as "in, it is guaranteed
that the data on Do through Do will have been correctly written
into a register in the computer 13. This delay is created by the
16
~LZ3~ I
hold read data register logic 67 as follows. When LATCH is
cleared, which it should ye during synchronous mode operation,
and X7, corresponding to bit 7 of read data register 65, is set,
output RR? from hold read data logic 67, which corresponds to
input bit 7 of buffer 66, is not set until 1 CLUE period, when
FAST is (fast mode), and a 1/2 ILK period when FAST is row
(slow mode after X7 is set.
In asynchronous mode, i.e. when SYNCH is set, read data
register 65 is parallel loaded from shift register 57. This
occurs by the load read data register logic 61 setting line 63
when SR7 it set. To ensure that the data in read data register
65 is properly loaded into a register in computer 13, in
asynchronous mode, LATCH should always be set. When LATCH is
set, the data on X7 is placed on RR7 by hold read data register
logic 67 at the rising edge of READ DATA REGISTER. This ensures
that Do will meet the set up and hold requirements of the
computer 13. If Do is read by the computer 13 as lo Do through
Do are correctly written into a register of the computer 13. X7
will be reset by clear X7 logic 69 fourteen Folks after READ
DATA REGISTER is set and Do is "1" (ire., the byte has been read
by the computer) so that X7 will be clear and the computer 13
will not retread the byte as valid during subsequent polling,
it setting of READ DATA REGISTER.
Write control means 47 will now be described with reference
to figure 4. Write control moans comprises write data register
81 for receiving a byte of data to be written on the disk, shift
register 83 for converting the parallel data in write data
register 81 to serial form, and toggle 85 for generating the
bit stream which is to be written onto the disk Write control
means 47 further comprise load/shift logic 87, handshake/
isle 7
underrun logic 89, write shift clock 91 and WRECK logic 93, all
of which control the timing of the write control means.
To initiate a write Lo is set, Lo is cleared to set up a
prorate Nate. The prorate state initializes the write shift
clock 91 and loads hit logic circuit 87 setting line 99, sets
WRDATA and WRECK, resets underrun flag URN in handshake/underrun
flag register 37 and initializes a toggle clock in toggle 85.
Prior to actual writing, Lo and Lo should be placed in appropriate
states to select the desired drive and set MOUTON. when Lo, Lo
and MOTOR-ON are "in, the decoder places a "1" on WRITE DATA
REGISTER which loads data from data bus 17, Do through Do, to the
write data register 81 at the rising edge of the logical function
Q3 or DEW. This register is in turn parallel loaded into shift
register 83 as follows. As noted above, when load/shift control
logic I is initialized, line 99 is set. When line 99 is set, a
puree from the write shift clock 91 on line 97 causes data in
write data register 81 to be latched into shift register 83. In
asynchronous mode (SYNCH is set), the load will be completed
approximately eight Clockwise after WRITE DATA REGISTER has been set.
In synchronous mode, the load will be completed between four and
five Q3 periods after WRITE DATA REGISTER has been set.
In synchronous mode, (SYNCH is reset writing continues as
follows. Once the data has been loaded into shift register 83,
the most significant bit in the shift register will be shifted
onto line 95 which will cause (after two Q3 periods) the WRDATA
TV toggle from I to "D" since WRDATA is initialized at I and,
according to the group code coding scheme used, the first bit of
a byte must be a lo Shift register 83 will shift every eight
Q3 periods after it has been loaded, followed two Q3 periods
I later with a toggle, if the date on line 95 is a "in, and will
18
continue such shift and toggle until the byte has been written.
Thus, a byte of data is shifted out and written in 64 Q3 periods
and a new byte of data can then be parallel loaded into shift
register 83. With this timing, a I must be placed on WRITE
DATA RESISTER every 64 Q3 periods, otherwise Ohs will be shifted
out of swift register 83. During synchronous mode URN is always
reset so that URN does not prevent writing data on disk by
causing WRECK to be set.
When the controller is in asynchronous mode (SYNCH it set),
10 the timing constraints of synchronous wry en are relaxed. When in
asynchronous mode, write control means 47 operates as follows.
after shift register 83 has been parallel loaded with the data
from write data register 81, the most significant bit in shift
register 83 will be shifted onto line 95 and after eight more ILK
periods, toggle 85 will cause IRRADIATE to toggle from I to I
since, as noted above, the most significant bit must be a "in.
Subsequent shifts and toggles are separated by eight Elks. After
all eight bits have been shifted out of shift register By,
load/shift logic 87 places a I on line 99 which parallel loads
shift register 83, with data from write data register 81. When
I is set, shifts and toggles are separated by 8 Clucks. When 8/7
is reset, toggles occur 6 Elks after shifts, and shifts occur 8
Elks after toggles
Due to the relaxed timing which occurs during asynchronous
I writes as compared to synchronous writes, the following
additional operations are needed Jo ensure that data is being
properly written. Handshake flag HO is set by handshake/underrun
logic 89 upon the completion of a parallel loading of shift
register 83, as determined by signals on lines 97 and 99 and
reset by the handshake/underrun logic 89 when WRITE DATA REGISTER
19
is enabled. Since computer 13 can issue a command to clear Lo
which will cause the decoder to enable READ HANDSE3ARE/UNDERRUN
FLAG REGISTER, the status of the handshake flag HO can be deter-
mined by the computer That is, the computer can poll the
handshake/underrun flag register 37 until the HO flag is I
indicating that the write data register 31 has been parallel
loaded into the shift register 83 and the write data register it
available for another byte of data. Once the computer detects
that the write data register 81 is available, it may issue a
command to jet Lo which will enable WRITE DATA REGISTER which
will cause the byte on data bus 17 to be written into write data
register 81.
To ensure that a new byte of data has in fact been loaded
into the write data register 81 prior to loading the shift
register 83, the underrun flag URN in handshake/underrun flag
register 37 is employed as follows. As noted above, during the
prorate state when writing is initiated, underrun flag URN is
reset, i.e. when Lo is Jon. The underrun flag URN is set by
handshake/underrun logic 89 when the parallel load of the shift
register 83 ends, if the handshake flag is set, indicating a new
byte has not been written into the write data register 81. Since
the current state of underrun flag URN is input to WRECK logic 93
through line 101, if URN is set then no new data has been loaded
into write data register 81 before loading the shift register 83,
25 and WRECK logic 93 will enable WRECK before the next transition
of WRDATA occurs. When WRECK is lo the write head is disabled
preventing the same byte of data from being rewritten. URN can
only be reset by exiting from writing, it when Lo is I
For an example showing how latches Lo through Lo are set by
the computer during asynchronous writes, Lee Table 2. For an
~3~t~6'~
example showing how latches Lo through Lo are set by the computer
during synchronous writes, see Table 3.
I
(Asynchronous Writes)
Lo I Lo 11 MoToB=Q~ Action
0 0 0 0 0 initial state
0 0 1 0 0 set Lo
o o 1 1 n set Lo; write data on bus
into the mode register
0 0 1 0 0 clear Lo
0 0 0 0 0 clear Lo
1 0 0 0 1 set Lo; select drive 1, set
MOTOR-ON
1 0 1 0 1 set Lo; prorate state;
initialize write shift
clock 91; initialize load/
shift control; set WRDATA;
set WRECK; reset URN
1 0 1 1 1 set Lo; enable WRITE DATA
REGISTER
1 0 0 1 1 clear Lo; read US and
URN flags
1 0 0 1 1 continue polling HO flag
until it has been set
1 0 1 1 1 set Lo; enable WRITE DATA
REGISTER
1 0 0 1 1 clear Lo; read HO and URN
flags
1 0 0 1 1 continue polling HO flag
until it has been set
1 0 1 1 1 jet Lo; enable WRITE DATA
. REGISTER
1 0 1 0 1 clear Lo; exit write mode
1 0 0 0 1 clear Lo
0 0 0 0 1 clear Lo;
0 0 0 MORON clears
after timer counts down
I
synchronous Writes)
ho Lo 1 MATTOCK cation
9 0 0 0 0 initial state
0 0 1 0 0 set Lo
0 0 1 1 0 set Lo; write data on bus
into mode register
0 0 1 0 0 clear Lo
0 0 0 0 0 clear Lo
1 0 0 0 1 set Lo; select drive 1, set
MOTOR-ON
1 0 1 0 1 set Lo; prorate state;
initialize write shift
clock; initialize load/
shift control; set
WRDATA; set WRECK
1 0 1 1 1 set Lo; place a byte of data
on data bus 17 every 64 Q3
clocks
1 0 1 0 1 clear Lo; exit write mode
when done
1 0 0 1 clear Lo
0 0 0 0 1 clear Lo
0 0 0 0 0 MOTOR-ON clears
after timer counts down
The disclosed controller may be packaged in a standard I
pin, 600 mix plastic DIP using well known prior art methods. All
of the punts are shown in Figure 1, except for voltage source
Vcc and ground.
thus, a disk controller for interfacing between a digital
computer and a floppy disk drive which may be implemented as an
integrated circuit has been described. The controller is capable
of performing multiple modes of operation, including fast and
slow clocking and synchronous and asynchronous reading and
WriteNow
