Note: Descriptions are shown in the official language in which they were submitted.
~3~
This invention relates to interface systems to transmit
and receive variable rate dat~ through a fixed rate transmi.ssion
channel. More particularly this invention relates to a method and
apparatus able to transmit and receive telemetry data through a
standard fixed rate communications channel.
A requi.rement exi.sts to buffer variable rate telemetry
data into and out of a microwave communications system operating
between a testing center and a data processing center. One
problem is to transmi.t real-ti.me (lec.s than l0 ms delay) telemetry
data at rates that can vary between 5 Kbits per second ~Kbps) and
l Mbps through, say, a Tl rate ll.5~4 M~z) digi.tal service
channel. The bit rate of the data entering the telemetry
processing equipment must be kept essentially the same as that of
the original telemetry signal to preserve data integrity.
During a test missi.on, for example, an airborne
telemetry system would provide a continuous serial PCM data stream
to ground-based receiving and processi.ng equipment using IRIG
standard ~RZ or biphase (Bi ~) coding.
The data rate is variable between 5 Kbps and l Mbps as
determined by the individual data word length and the sample rate
selected for each parameter in the airborne telemetry system.
Input to and output from the microwave system is fixed at the Tl
rate (a Bell system standard). The interface unit at the
processing end of the link must provide a continuous serial PCM
data stream to the telemetry processing equipment at essentially
the same bit rate as that of the signal input to the testing
center interface unit.
. ~
3~
A present method used for routing the telemetry data
from the testing center to the processing center is to record data
on a magnetic tape which is then played back in the data
processing center~ However, this method does not allow the
real-time data reduction which may be required.
It is therefore an object of this invention to provide
an improved method and apparatus able to transmit and rece-ve
telemetry data through a standard fixed rate communication channel
~hich overcomes the disadvantages of non real-time systems.
According to one aspect of this invention there is provided a
method of encoding, at a transmitting unit, a variable rate
continuous bit stream of data on a fixed rate digital service
channel, comprising the steps of:
a. triggering the transmission of an n-bit burst for
each n-data bit of said variable rate continuous bit
stream received at said transmitting unit;
b~ adding a start and stop bit pattern to each data
burst;
c. converting said variable rate continuous bit stream
to a fixed rate continuous bit stream; and
d. converting said fixed rate continuous bit stream
from NRZ-L to bipolar form so as to allow
transmission oE data by suitable means to a
receiving unit.
Another aspect of this lnvention is to provide a method
of decoding, at a receiving unit, data and bit rate information
from an encoded signal in order to reproduce the original bit
stream and data rate entered in a transmitting unit~ comprising
the steps of:
aO recovering a fixed clock rate from said encoded
signal,
b. converti.ng a bipolar data input at sai.d recei.vi.ng
unit to NRZ-L data;
c. detecting a start and stop bi.t pattern present in
each burst of information received;
d. generating a square wave at burst frequency;
e. multiplyi.ng said burst frequency by n to obtain said
original bit stream data rate;
f. generating a continuous NRZ data bi.t stream at
var.iable rate from an NRZ-L data burst at fixed rate
by first-in-first-out memory means;
g. converting said NRZ-L data to a biphase-L data
output.
Yet another aspect of this invention is to provide a
transmitter unit used to encode a variable rate continuous bit
stream of data on a fixed rate di.gital service channel,
compr i.5 ing:
a. n bit burst generator means for triggering a burst
. for each n-data bit of said variable rate continuous
bit stream received at said transmitting unit;
b. start and stop bit adder means for adding a start
and stop bit pattern to each data burst triggered;
c~ clock generator means for providing a fixed rate
transmit clock;
d. a data rate converter means for converting said
vari.able rate continuous bit stream to a fixed rate
continuous bit stream; and
e. bipolar converter means for converting said fi.xed
rate conti.nuous bit stream from NRZ-L to bipolar
form so as to allow transmission of data by sui.table
means to a receiving unit.
And, yet another aspect of this invention is to provide
a receiver unit used to decode data and bit rate information from
an encoded signal in order to reproduce the original bit stream
and data rate entered in a transmitting unit, comprising:
; a. a clock recovery and extraction circuit means for
recovering a fi.xed clock rate from said encoded
signal and converti.ng a bipolar data input at said
receiving unit to NRZ-L data;
b. burst detector means for detecting a start and stop
bit pattern present in each burst of information
received;
c. burst frequency generator means for generating a
square wave at burst frequency;
d. dlgital phase-locked loop multiplier means for
multi.plying said burst frequency by n to obtain said
original bit stream data rate;
e. first-in - first-out memory means for generating a
conti.nuous NRZ data bit stream at variable rate from
an NRZ-L data burst at f;.xed rate;
f. NRZ~L to bi.phase-L converter means to obtain
biphase-L data output.
3~
Particular embodiments of the invention will be
described i.n conjunction with the accompanying drawings in which:
Figure 1 i.s a block diagram depicting the inter-
connecti.on oE the transmi.tti.ng and receiving interface uni.ts with
other elements of the telemetry equi.pment.
Figure 2 is a block diagram of th~e transmi.tter i.nterface
uni.t used in the present invention.
Figure 3 is a more detailed block diagram of the
transmitter interface unit used in the present invention.
Figure 4 is a block diagram o the receiver interface
unit used i.n the present invention.
Figure 5 is a more detailed block diagram of the
receiver interface unit used in the present inventi.on.
Fi.gures 6A and 6B are flow charts of the program
executions of the receiver interface~
Referri.ng now to figure 1, shown at 10 is a
representation of a telemetry transmission system for use in the
present invention. It is comprised of a transmitting section 11
~hich can be located at the testing center and a receiving section
12 located at the processing center.
The PCM signal 13 that must be processed at the
processing center comes from a telemetry receiver 14 at the
testlng center. Since the telemetry receiver 14 may output many
PCM codes, a bit synchroni.zer 15 is required between the telemetry
receiver 14 and the transmitter interface unit 16 to obtain clean
NRZ-L data 17 and a 0 clock 18 from the many possible PCM codes
from the receiver 14.
The transmitter interface unit 16 outputs bipolar data
to a multi.plexer 19 at Tl rate for transmi.ssion by, say, a
microwave link 20 to the receiving section 12 located at the
processing center. Upon arrival, the multiplexed bi.polar data is
demultiplexed at 21 before bei.ng recelved at the receiver
interface 22. The receiver interface 22 e~tracts the data and the
rate at which this data was entered into the transmi.tter interface
unit 16 from the received pulse train 17. The outputs of the
receiver interface 22 are the clock signal 23, NRZ-L data 24 and
biphase-L data 25. This data is then sent to another bi.t
synchronizer 26 which provi.de PCM continuous serial data stream
originally entered at 13 in the transmitting section 11. This
data is further processed by the telemetry data processing
equipment 27.
The transmitter i.nterface unit is shown in fi.gure 2 and
in more detai.ls in flgure 3. The transmitter interface operates
as a PCM-to-Tl data rate converter. The principal elements are
the 6-bit burst generator 30, start and stop bit adder 31, Tl
clock generator 32, data rate converter 33 and NRZ-to-bipolar
converter 34.
The inputs of the transmi.tter interface are an NRZ-L
data input 35 and a 0 clock input 36. The output is a continuous
Tl bipolar data stream containing a series of bursts of
information. Each burst begins with a 0 start bit, followed by
six data bits and at least two stop bits. This number oE bits in
each burst is derived as follows;
In order to be detected at the recei.ver end, a burst
must contain one start bit and at least two stop bits. Since a
~ 6 --
3~
minimum number of one's must be transmitted in order to maintaln
synchronizatj.on of the communicati.ons system~ one's are selected
as stop bits and zeros as start bits. Detection of the beginning
of a burst at the receiver end becomes a matter of detecting the
sequence l, l, 0. The minimum number of bits in each burst i.s
dictated by the maxi.mum PCM data rate requi.red and the Tl clock
period. For each burst, a zero start bi.t is yenerated by the
transmi.tter i.nterface, followed by data bits, and at least two
stop bits. The burst period i.s equal to n times the input clock
period.
During a burst peri.od, at least n + 3 bits have to be
transmitted at the Tl frequency (n data bits, one start bit and 2
stop bits). For a PCM data rate of l Mbps, the burst frequency
will be l MHz, hence the burst period will be n . If
we want one start bit at least two stop bits, (n + 3 bits) x Tl
clock period must be smaller than n times the PCM data period.
This implies that n + 3 bits must be smaller than or equal to
1.~44 MHz
n , hence, n must be greater thant 5.51. The minimum value
l MHz
for n is then six~
Since the number of consecutive ze-ros must be kept to a
mi.ni.mum in order to insure proper synchronization of the
communication system, a number of six bits per burst was selected.
This also contributes to minimizi.ng the data delay in the
transmitter interface, which becomes more i.mportant at low PCM
data rates, since this delay i.s equal to n times the bit rate
period.
~L232~
The number of stop bits (NSB) is variable and can be
derived from the followingO
NSB = (~6 x input data rate period) - (7 x Tl period)
Tl Period
NSB = 6 x Tl rate - 7
PCM data rate
For example, the NSB for a PCM data rate of 1 MHz is
2.26 and for a rate o~ 5KHz, is 1845.8. Since these are added in
integer numbers, an NSB of 2.26 means that 2 or 3 stop bits are
added between each burst and an NSB of 1845.8 means that 1~45 or
1846 stop bits are added.
If we now refer to figure 3 we see that the 6-bit burst
generator 30 is formed by circuits 37, 38, 39 and 40. Circuit 37
is an 8 - bit parallel output serial shift reyister in which the
NRZ-L DATA IN signal 35 is clocked by the 0 CLOCK IN signal 36.
The divider by six 38 and the one-shot 39 are used to load a 6-bit
burst into regi~ster 40 and to trigger the transmission of the
burst at Tl frequency.
The addition of start and stop bits is performed by
register 40. The transmitter interface sends a continuous Tl data
stream which is taken from output QH of register 40. Between
bursts, QH is always 1 since a 1 is present at the serial input
during each burst transmission and the clock is inhibited between
bursts. Using this circuit, the required number of stop bits can
be generated between each burst. The start bit is generated by
loading a 0 at input G of register 40 at the same time as six
input data bits are loaded, and a 1 is loaded at input H. After
each loading of the register 40, data is shifted in register 40
and output QH becomes: a last stop bit, the start bit and six
data bits.
The Tl 1.544 MHz clock 32 is obtained at the output of
counter 41 whi.ch di.vi.des by 4 the 6.17000 MHz output of oscillator
42.
The data rate converter 33 is co~posed of flip~flops 43,
44 and counter 4~. Each time six input bits are received, i.nput D
of flip-flop 43 goes to zero for one input clock period. This
causes output Q of flip-flop 43 to become low on the next risi.ng
edge of the Tl clock 32. This low level triggers flip-flop 44
which clears counter 45. The clock inhibit input of register 40
stays low for eight Tl clock periods to output the burst.
The NRZ-to-bipolar conversion is performed by converter
34 which is made up of a NAND gate 46, flip-flop 47 and bi.polar
li.ne driver 48. The output of the NAND gate 46 goes low for half
the Tl clock period when output QH of register 40 is one and stays
high otherwise. This output dri.ves the sink and source inputs of
the bipolar line driver 48 which are enabled by a 0.
Flip-flop 47 is used to alternate the source and sink
outputs of the bipolar line driver 48 to obtain the bipolar
output.
A 100 OHM resistor (not shown) at the output of the
bi.polar line drive 48 matches its impedance to the balanced
transmission line of the T1 multiplexer 19 shown in figure 1.
The receiver interface 22 (Figure 1) is a Tl-to~PCM data
rate converter. The i.nput data is a bipolar waveform at 1.544 MHz
Tl frequency. It consists of burst containi.ng -the information
necessary to recover the telemetry data and present i.t to the
i36
processing equipmen-t at exactly the same bi-t rate as that of the
signal input to the transmitter interface unit.
A block diagram of the receiver interface is shown in
figure 4. The input shown at 50 is a bipolar signal at Tl
fre~uency which is entered into a clock recovery and data
extraction circuit 51. The recovered T1 clock 52 synchronizes the
input data into a first-in first-out (FIFO) memory 53. The data
at 54 is entered into a burst detector circuit 55 whose output 56
generates the burst frequency at 57 which is multiplied by six by
a digital PLL 58 to yield the original telemetry clock frequency.
This clock frequency at 59 serves to output the data at
60 from the FIFO 53. The three outputs available from the
receiver interface are the PCM 0~ Clock 61, NR~-L data 62 and
biphase-L data 63. The receiver interface is controlled by a
microcomputer system 64 which measures the input bit rate,
displays it at 65, adjusts the Pl,L center frequency to cover the
range from 5Kbps to 1 Mbps, and performs real-time throughput
monitorlng.
The block diagram shown at figure 5 contains all the
electronics of the receiver interface except for the display 6S
shown in figure 4 ~hich need not be described any further.
The microcomputer 70 is based on an Intel* 8085-A2
8-bit microprocessor 71. The EPROM memory 72 provides 2K bytes of
program storage and the RAM memory 73 provides lK byte of static
storage. An Intel 8755 EPROM was used as the EPROM memory 72
and an 8185 RAM was used for the lK memory. Sixteen parallel
input/outputs 74 are provided by the EPROM 72.
* Trade Mark
-- 10 --
'~:
~3~
Two i.nterval timer chi.ps 75 and 76 provide six timers.
timer 0 (TO) of i.nterval timer 75 is used to divide by 24 the
output 77 of the di.gital PLL 78. Timer l (Tl) of interval ti.mer
75 i.s used a lOms. real-ti.me clock. Ti.mer 2 (1'2) of interval
timer 75 i.s a counter that measures the PLL output frequency
di.vided by 2~. Ti.mer 0 (T0~ of i.nterval ti.mer 76 is a counter for
measuring the PLL outpu~ frequency or the frequency of the burst
divi.ded by 2. Timer l (Tl) of interval ti.mer 76 divi.des the 3 M~lz
microcomputer clock frequency reference by lO or 120, depending on
the burst frecluency. Timer 2 (T2) of interval ti.mer 76 i.s used as
the frequency measuring period. Address decoding is performed at
79. A watch-dog ti.mer 80 has been incorporated into the reset
circuitry of the microcomputer 70 i.n order to generate automatic
reset should the microprocessor program enter an endless loop for
some reason. Two hex Schmi.tt-tri.gger inverters 81 and a dual
retriggerable monostable multivibrator with clear 82 are used for
thi.s purpose.
In operation, when the power is turned on or when the
system is reset, a risi.ng edge is applied to CL~AR input of the
monostable 82, which generates a positive pulse on the lQ output.
This output is maintained high by continuous retriggering of the
monostable 82 by the microprocessor 71 during program execution
via output Y7 of the address decoder 79. I~ the monostable 82 is
not retriggered for a period longer than the duration of the lQ
output pulse, approxi.mately 2 seconds, then the lQ output goes low
generating a reset to microprocessor 71.
A PCM carrier repeater 83 is used to obtain a unipolar
signal and to recover the Tl clock from the bi.polar input 84. The
output of the data and clock recovery ci.rcui.t 85 goes -through
input QA of shift register ~6 before being clocked i.nto flip-flop
87.
The beginni.ng of each burst is found by detecting the
bit pattern 1, 1, 0. The last three data bits received are
compared conti.nuously with 1, 1, 0 by magnitude comparator 88.
When this bit pattern is detected, a 80-ns pulse from monostable
89 goes through the magnitude comparator 88 to reset counter 90
and i.ncrease the burst counter 91. Output QB of the burst counter
91~ which provides the burst divided by two, goes through data
selector 92 to timer 0 ~TO) of interval timer 76 which is used to
measure the burst frequency. Output O~C of the burst counter 91,
whi.ch provides the burst divided by four, goes through level
shifter 93 to the i.nput of the di.gi.tal PLL 78. The telemetry
frequency is obtained by multiplying the burst/4 frequency by 24
with the digital PLL 78.
As soon as a new burst is detected, counter 90 counts
during eight input clock periods and enables eight data bits from
flip-flop 87 to be clocked into the FIFO memory 94. However, the
circuit formed by gates 95 generates a waveform 0 which prevents
the start and stop bits from being inputted in the FIFO memory 94
through gates 96.
As indicated above, the generation of the telemetry
frequency is performed by the di.gital PLL 78 which multiplies the
burst/~ input by Z~. In order to cover the complete range of
telemetry frequenci.es from 5 RHz to 1 Mllz, the center frequency
and the low-pass filter of the digital PLL 78 are adjusted by
resistors and capacitors (not shown) controlled by relays Kl to K9
shown at 97. Relay K~ would, for example select low or high
frequencies and relays K1 to K8 provi.de 255 different adjustments
for each frequency band. These relays are controlled by the
mi.croprocesso~ 71 through the EPROM 72.
Output 77 of the digital PLL, 78 feeds the unload clock
of the FIFO memory 94 through gates 96 when QD of counter 98 is
high. The output 77 i.s low at re~et or when the FIFO memory 94 i.s
cleared at 99 by the microprocessor 71 through EPROM 72, but
becomes high after eight input data bi.ts have been entered into
the FIFO memory 94. Output 100 of the FIFO 94 is inverted at 101
and buffered by buffer 102 to generate the N~Z-L data output 103.
The clock output 104 is the FIFQ unload clock 105 inverted at 106
and buffered at 102.
The biphase-L output 107 is obtained by performi.ng an
exclusive OR 108 of the inverted clock with the NRZ-L data
fi.ltered at 109 to remove transient spikes and is buffered at
102.
The number of data bits output from the FIFO memory 94
is checked continuously against the number of data bits input in
the FIFO memory by the circuit formed by monostable 110, flip-flop
111 and gates 112. This is achieved by latching the IR signal
from the FIFO memory 94 after a load clock pulse and latching the
OR signal after an unload clock pulse. These signals indi.cate a
FIFO full or a FIFO empty situation. The occurrence of a FIFO
full or FIFO empty generates an interrupt to the microprocessor
71 which then resets the FIFO 9~, activates a buzzer ~not shown)
for 1 second and turn on a fault LED (not shown).
3~i
The software of the receiver interface is contained in
the 2K bytes of EPROM 720 The flow chart of the program
executions is shown in Fiyures 6A and 6B~ The software was
developed using an Intellect Microcomputer Development System
MDSZ30 from Intel~
The initialization of the program is executed just after
the reset. It initializes the stack pointer to the last address
of RAM available, blanks the display on the front panel, activates
the no data LED, and extinguishes the fault LED if the reset is a
power-up one or activates it if the reset comes from the push
button or from the watchdog timer. A power-up reset is detected
by checking the value of a byte in memory. When the power is
turned on, its value is random until after a first frequency
adjustment has been made by the microprocessor. The input/output
ports and the timers are then initialized and the initial burst
frequency is me~asured. As soon as valid bursts are received, the
no data LED is extinguished. The PLL center frequency is
adjusted, and another burst measurement is performed to check the
validity of the adjustment. If it is validr the program jumps to
the execute routine.
The subroutine continuously checks that the PCM output
frequency is locked onto the burst one. If the telemetry
frequency changes by a factor of ~ 12% of its previous value at
the moment of adjustment, the subroutine makes the display flash
on the front panel. If the lock onto the burst frequency is lost,
the buzzer is activated during 4 s, the fault LED is turned on,
the display is blanked and the program jumps back to the
initialization subroutine.
Another subroutine performs all the frequency
measurements by counting the number of clock transitions in a
timer durir)g a certain period of time. The three timers of
interval timer 76 and timer 2 of interval timer 7~ are used for
this purpose. rrhe reference is the 3 ~z microprocessor clock
output. The measuremen~ period is obtained by dividing this
reference using timers 2 and 3 of interval timer 76. The bit rate
readings are obtained in timer 0 of interval timer 76 and timer 2
of interval timer 75. The precision of the measurement is ~ 100
EIz for telemetry frequencies greater than 70 kHz, and ~ 10 Hz
for those smaller than 70 kHz. The burst frequency is measured by
counting the number of transitions in the burst/2 signal during
120 ms for the high frequency or 1.2 s for the low one.
The telemetry bit rate is obtained directly from this
measurement since the burst/2 frequency is 12 times smaller than
the telemetry one. The PLL frequency is obtained by counting the
PLL output transitions during 10 ms for the high band and 100 ms
for the low one. This frequency is measured at the output of the
PLL when it is locked onto the burst. The PLL center free-running
frequency is measured differently for low and high bands. The low
PLL center frequency is obtained by counting the transitions of
the PLL output over a period of 100 ms. The high PLL center
frequency is measured by counting the number of transitions of the
PLL output divided by 24 over a period of 240 ms. This extended
measuring period is necessary to average the jitter present on the
high PLL free-running frequency.
~i~3~
A subroutine adjusts the center frequency of the PLL
according to the PCM bit rate derived from the burst frequency
measurement.
Another subroutine measures the input burst frequency.
At the beginning, a high burst frequency measurement is tried. If
the resulting count is ~maller than 700 r the program performs a
low burst frequency measurement. This is the way the high or low
frequency flag is set at the beginning.
An interrupt service routine is executed each time the
fault reset push button on the front panel is depressed, it
extinguishes the fault LEDo Another interrupt service routine is
executed when a FIFO full or empty condition has been detected.
The FIFO is cleared, the buzzer is activated for l s and the fault
LED is turned on. Another interrupt routine controls the display
flashing and the buzzer duration.
- 16 -
