RETRY MECHANISM FOR RELEASING CONTROL OF A COMMUNICATIONS PATH IN A DIGITAL COMPUTER SYSTEM

MECANISME DE RELANCE POUR DEBLOQUER UN TRAJET DE COMMUNICATION DANS UN ORDINATEUR NUMERIQUE

English Abstract

Abstract of the Disclosure
A retry mechanism facilitates release of a
communications path by a device which is either unable
to respond to a requested operation or which is unable
to do so within a reasonable length of time. The
mechanism is easily implemented and has a wide variety
of applications, including use in operations requiring
a number of transactions on "interlocked" type
communications paths to accomplish a given function.
It is also particularly useful in facilitating
interconnection of communications paths controlled
from independent control sources.

Claims

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

l. For connection to a common communications path in a
data processing system, which path carries data signals that re-
present data being read or written, the path including address
lines for carrying signals that designate a memory location from
which data are to be read, command lines for carrying commands,
including interlock-read commands that request that data be read
from a memory location designated by the address signals and unlock-
write. commands that request that data be written into a memory
location designated by the address signals, and response lines for
carrying one of at least three response signals, namely, an acknow-
ledgement signal, a no-acknowledgement signal that results when
no device places signals on the response lines, and a retry signal,
a memory device comprising:
A. acknowledgement means including at least one interlock-
bit register, each interlock-bit register being associated with at
least one address, being arranged selectively to assume one of a
retry-enabled state and a retry-disabled state, and, when the mem-
ory device is connected to the common communications path, being
responsive to address signals representing the address associated
therewith to:
i) assume its retry-enabled state when it receives an
interlock-read command and it is in its retry-disabled state; and
ii) assume its retry-disabled state when it receives an
unlock-write command and it is in its retry-enabled state,
said acknowledgement means responding to the presence on the common
communications path of an interlock-read command and an address



associated with any included interlock-bit register thereof to:
i) place retry signals on the common communications
path when the interlock-bit register associated with the address
signals on the common communications path is in its retry-enabled
state; and
ii) place acknowledgement signals on the common communica-
tions path when the interlock-bit register associated with the
address signals on the common communications path is in its retry-
disabled state; and
B. a plurality of memory locations for containing data,
each memory location being associated with an address and, when
the memory device is connected to the common communications path;
i) being responsive to the presence on the common com-
munications path of the address associated therewith, to an inter-
lock-read command, and to the state of the interlock bit associated
with the address of that memory location to place on the common
communications path data signals representing the data stored in
that location if the interlock-bit register associated with the
address of that location is in its retry-disabled state and to re-
frain from placing on the common communications path data signals
representing the data stored in that location if the interlock-bit
register associated with the address of that location is in its
retry-enabled state, and
ii) further being responsive to its address on the common
communications path and to an unlock-write command to store therein
data represented by data signals carried by the common communica-
tions path.

56


2. For connection to a common communications path in a data
processing system, which path includes lines for carrying commands
that specify a transaction to be performed, for carrying stall
signals that request extension of the length of the transaction,
for carrying no-acknowledgement signals that cause termination of
the transaction in one way, and for carrying retry signals that
cause termination of the transaction in another way, a slave
device comprising:
A. transaction means responsive to a command from a master
device on the common communications path for performing a trans-
action with the master device that has placed the command on the
path when the slave device is connected to the common communica-
tions path;
B. stall means responsive to the transaction means for
placing a stall signal on the communications path during the de-
vice's performance of the transaction specified by the command sig-
nal when the slave device is connected to the common communications
path if the time required by the transaction means to complete a
step of that transaction is more than an allotted period of time;
and
C. retry means for monitoring the stall means to keep track
of how long the device has asserted the stall signal and for plac-
ing the retry signal on the common communications path when the
device has asserted the stall signal for more than a predetermined
maximum time.

57


3. A memory device as defined in claim 1 wherein:
A. the communications path to which the bus device is
adapted for connection includes control lines for carrying timing
signals that define cycles and multicycle transactions;
B. each interlock-bit register is responsive to the
timing signals and to an interlock-read command and address
signals representing an address associated with that interlock-bit
register to assume its retry-enabled state when it is in its retry-
disabled state only if the interlock-read command and the address
signals are present on the communications path during the first
cycle of a transaction;
C. each interlock-bit register is responsive to the
timing signals and to an unlock-write command and address signals
representing an address associated with that interlock-bit regis-
ter to assume its retry-disabled state when it is in its retry-
enabled state only if the unlock-write command and the address
signals are present on the communications path during the first
cycle of a transaction;
D. the acknowledgement means responds to the timing
signals and to the presence on the common communications path of
an interlock-read command and an address associated with an
interlock-bit register to place a retry signal on the communica-
tions path only if the interlock-read command and the address
signals are present on the communications path during the first
cycle of a transaction;

58


E. each memory location is responsive to the timing
signals and to the presence on the common communications path of
the address associated therewith and an interlock-read command to
place on the common communications path data signals representing
the data stored in that location only if the interlock-read command
and the address are present during the first cycle of a trans-
action; and
F. each memory location is responsive to the timing
signals and to the presence on the common communications path of
the address associated therewith and an unlock-write command to
store therein data represented by data signals carried by the
common communications path only if the unlock-write command and
the address are present during the first cycle of a transaction.
4. A slave device as defined in claim 2 wherein:
A. the common communications path to which the slave
device is adapted for connection includes control lines for
carrying timing signals that define cycles and multi-cycle trans-
actions; and
B. the retry means counts the number of cycles during
which the stall means has asserted the stall signal during a
given transaction, and it places the retry signal on the common
communications path when the number of cycles of the stall signal
during the given transaction reaches a predetermined maximum.

59

Description

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Baek~round of the Invention
A. Field o~ the Invention
The invention relates to digital computer architecture
and, more partieularly, to eireuitry for lntereonneetinq for
eommunieation with each other such diverse devices as proees-
sors, memory (main memory) and I/O devices such as mass storage
(e.g. disks and tapes), console terminals, printers, and other
s~eh deviees in a di~ital eomputer system. The particular
invention elaimed herein relates to an improved mechanism for
releasing control of a communications path in a di~ital computer
system when a device on the eo~munieations path is unable
immediately to respond to a request by anothér device on the
eommunieations path to enter into a transaetion with it.
~. Prior Art
As thP eost of digital eomputer systems and their
eomponents eontinues to deerease, more and more different
types of data handling deviees are being intereonneeted into
these systems. The deviees have widely varyin~ eharacteristics
with respeet to s~eed (i.e., the rate at which they can accept
or transmit data), required eontrol information, data format,
and other such eharaeteristi~cs, yet they must eommunieate with
eaeh other. For exam~le, processors must often eommunieate
with main memory (very high speed), mass storage deviees sueh
as disk memory (high speed), and output deviees sueh as printers
(very low speed). An important aspeet of any interconneeting
means is its ability to support arbitra-tion among the eom~eting


'~

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demands of devices ~Jishing to communicate ~7ith each other.
Some form of arbitration must be performed to grant a request
r~ for access to the communications path, and thus it is essential
that the arbitration process be efficient, since it ~ay other-
~ise consume an undue portion of the computer system's resources.
Further,

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it is generally desirable that the arbitration process
provide some measure of flexibility in allocating the
communications path among the requesting devices. In
environments which allow a wide variety of devices to
be attached to the communications path, particularly
in environments which additionally allow the
connection of multiple processors to the
communications path, the competing demands on the
arbitration mechanism often lead to undesirable
constraints on system operation and flexibility.
Another important aspect of an interconnecting
means is its support of interrupts. The manner in
which these interrupts are posted often results in
significant restrictions on the achievable flexibility
of device attachment to the communications path.
In addition to providing communications among
devices attached to a single central processor, it is
frequently desirable to provide access between such
devices and one or more additional processors, as well
as between the several processors themselves. This
requirement of communication among processors adds
substantially increased complexity to the
interconnection problem because of the need to insure
coordinated operation. One aspect of interprocessor
communications that requires particular attention is
the problem caused by utilization of caches on one or
more of the processors. Such caches can cause
processing errors if appropriate steps are not taken
to insure that access to the cache is allowed only
when the cached data is "valid", that is, has not been
altered in main memory since it was cached. If cache
control is not performed efficiently, the performance
of ~he system as a whole may be significantly
degraded.

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Brief Description of the Invention

A. Objects of the Invention
.
Accordingly, it is an object of the invention to pro-
vide an improved means for interconnecting diverse devices in a
digital computer system.
Further, it is an object of the invention to provide
an improved means for interconnecting devices in a digital
computer system tha-t allows attachment of a wide variety of de-


vices with minimal attachment restrictions.
Still a further object of the invention is to provide

an improved means for interconnecting devices that allows
termination of a transaction in an efficient manner.
Yet another object of the invention is to provide a
means for interconnecting devices in a digital computer system
that allows devices on an i'interlocked" type path that are viable
to provide a requested response within a given time to terminate
a transaction.
B. Summary Description of the Invention
This application is directed to one of several related
aspects o~ the interconnecting means
It is a divisional of an application related to
four other concurrently filed applications, namely:
Canadian Patent Application Serial No. 463,721, inven-
tors Frank C. Bomba, William D. Strecker and Stephen R. Jenkins;
Canadian Patent Application Serial No. 463,722,

inventors Frank C. Bomba and Stephen R. Jenkins;

6~

_a,_

Canadian Patent Application Serial No. 463,720,
inventors Frank C. Bomba, Dileep P. shandarkar, J.J. Grady,
Stanley ~. I.ackey, Jr., Jeffrey ~. Mitchell and Reinhard
Schumann; and
Canadian Patent Application Serial No. 463,719,
inventors Frank C. ~omba, Stephen R. Jenklns, Reinhard Schumann
and Paul Binder.
Specifically, it is directed to the means by which
devices unable to provide a requested response to a transaction
may cause termination of the transaction for the moment, thereby
freeing the communications path for other transactions. Beeause
of the interrelation among the separate aspects of the complete
system, the strueture of the eomplete system will be described
as a whole first, and those aspeets specific to the present
invention will then be deseribed in somewhat fur~her dekail.
l. General Deseri~tion Of The Intereonneetinq
. . ~
Means
The interconnecting means described herein is asso-
ciated with, and preferably forms part of, each device to be
`20 intereonnected. It controls the transmission and reception of
signals on a communications path (e.g., a parallel wired bus)
interconnecting each of the devices. The interconnecting means
provides uniform eontrol of co~nunieations amon~ the deviees
intereonnected by the communications path. These devices are
eonneeted in

.,

~1 ~3;;~ L o ~



parallel to the communications path, and their
operation is independent of physical placement on the
path. Each device connected to the communications path
is assigned an identification number ("ID") which is
used for a number of purposes as described hereafter.
In one implementation of the interconnecting means,
the assignment is made by a physical plug inserted
into the device and wire to specify the identi~ication
number. Since this physical plug may be moved from
slot to slot, there is no logica~ dependency between
the device and the slot in which it resides. This
number is loaded into a control register during system
initialization, and is thereafter available for use by
the device.
The interconnecting means implements a specific
.. . .
set of commands providing efficient communication
between devices. These commands are implemented and
transmitted in a number o~'different operations
~hereinafter called "transactions"). Each transaction
is subdivided into a number of cycles, including a
Command/Address cycle in which the operation code for
the particular transaction (e.g., Read, Write,
Interrupt, etc.) is transmitted over the bus to other
devices, together with information identifying the
devices to which the command is directed or providing
other information pertinent to the command; an
Imbedded Arbitration cycle for identifying the device
which will next be allowed access to the
communications path; and one or more data cycles in
which user data (i.e., the ultimate object of the
processing) or other information is transmitted. The
transaction signals are transmitted over the
communications path via separate groups of lines




re~erred to herein as Information Transfer Class
lines, Response Class lines, Control
Class lines, and Power Class lines. E~cept for Time
and Phase Signals (described later) these signals are
detected as being asserted whenever one or more
interconnecting means asserts them. The Information
Transfer Class lines, in turn, comprise Information,
Data and Parity lines, and transmit command, data
status and certain other information used in the
transactionv
The Response Class Lines provide positive
confirmation of error-free reception, as well as
additional responses to control or alter the
transaction. This error monitoring significantly
contributes to system reliability, requires little or
no additional bandwidth, and allows the respondin~
device to alter the normal progress of the
transaction, thus contributing greatly to system
flexibility. For example, a device which requires
additional time to respond to a command directed to it
beyond that normally provided for by the command may
utilize one or more of the response signals to delay
completion of the transaction (within predetermined
limits) until the device is ready to respond, or may
notify the device of its inability to respond at that
time and thus free the communicationS paths for other
transactions.
A set of control signals is generated and
utilized by the interconnecting means in each device
to provide efficient and orderly transfer of access to
the communications path from one device to another.
Additionally, each device generates local timing
signals from a common system clock to thereby insure
synchronous operation. These signals, as well as test

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control signals, are also transmitted on separate llnes
over the bus. Finally, the devlces monitor the status of
the AC and DC power within the sys-tem, and provide sicmals
indicating the status of these power sources so that appro-
priate action may be taken when necessary.
The interconnec-ting means described herein is unusu-
ally powerful and versatile, and readily lends itsel.f to
economical manufacture by larue scale inteqration techni~ues
currently available. This results from the relatively limited
nu~ber of physicallv separate wires required to carry the
command, control, information and data signals among devices,
arising from thè efficient selection and.distribution of
functions among these lines. Nonetheless, the interconnec-
ting means imposes essentially no restrictions on the physical
placement of the devices attached to it. Further, it allows
interconnection of a wide variety of dev-ices, and efficiently
accommodates both sinsle-processor and multi-processor con-
figurations.
2. General Descri~tion of the Specific Invent1on
Defined Herein
In accordance with the invention specifically defined

~8--


in this application, a master device --i.e., a device that
has obtained control of the communications path-- places
signals on the communications path to specify the intended
transaction and deslgnate the device or devices with which
it is to engaae in the transaction. Typically, the desig
nated device indicates that it has received the co~mand and
can perform it by placing a particular response si~nal,
denominated an acknowledgment signal, on the communications
path. The master device senses the acknowledgment signal and
proceeds with the steps of the transaction. In contrast, if
the designated device for some reason ~id not receive the
command or was not present to do so, a different response,
denominated a no-acknowledqment signa:L, is present on the
communications ath, and the master device does not proceed
with tke ste~s of the transaction.
The improvement of the present invention is the
provision of a further type of signal, called a retry signal,
that causes the master device to break off the transaction
but to re-initiate it at a later time. This increases the
flexibility of this type of system, as can be appreciated
when one considers the response of a master aevice to a no-



3~


acknowledgment si~nal. A no-acknowledgmen-t signal is orclin-
arily an indication that an error has occurred; -the device
with t^7hich the master device attempted the transaction has
incorrectly received slgnals or has failed to respond to
them properly. Conse~uently, it wouid be inefficient for
the master device to continue attempting to perform a trans-
action with that particular device. ~ithou-t the retry mech-
anism of the present invention, however, the reason for
the absence of an acknowledament signal might also be that
the device received the request to enter into the transaction
but was not in a state in which performance of the trans-
action was possible within an acceptable period of time.
Accordin~ly, failure of the master device to attempt the
transaction again might be inappropriate. Therefore, rela-
tively elaborate steps might have to be taken to determine
what caused the no-acknowled~ment si~nal,`and this would re-
duce the speed of the system. Withou-t the improvement of the
present invention, therefore, there is some lack of flexibility
in the co~munications path; either its use must be restricted
~0 to devices that will always be ready to enga~e in a trans-
action when the transaction is requested, or some scheme must


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be eMployed to identify the reason for a no-acknowledgement sig-
nal.
According to the present invention, the flexibility of
the communications path is improved because slave devices that
sometimes are and sometimes are not ready to engage in a trans-
action can respond with a retry signal to indicate that, although
performance of the transaction is not currently desirable, the
master device should attempt to engage in the transaction again
at a later time. Thus, the master device is able to distinguish
between transactions that are likely to be able to be completed
at a later time and those that are not likely to be completed at
all. This greatly increases the flexibility of the communications
path.
In summary, according to one broad aspect, the present
invention provides for connection ~o a common comrnunications path
in a data processing system, which path carries data signals that
represent data being read or written, the path including address
lines for carrying signals that designate a memory location from
which data are to be read, command lines for carrying commands,
including interlock-read commands that request that data be read
from a memory location designated by the address signals and unlock-
write commands that request that data be written into a memory
location designated by the address signals, and response lines for
carrying one o at least three response signals, namely, an acknow-
ledgement signal, a no-acknowledgement signal that results when
no device places signals on the response lines, and a retry signal,

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a memory device comprising:
A. acknowledgement means including at least one interlock-
bit register, each interlock-bit register being associated with
at least one address, being arranged selecti.vely to assume one of
a retry-enabled state and a retry-disabled state, and, when the
memory device is connected to the common communications path, be-
ing responsive to address signals representing the address asso-
ciated therewith to:
i) assume its retry-enabled state when it receives an
interlock-read command and it is in its retry-disabled state; and
ii) assume its retry-disabled state when it receives an
unlock-write command and it is in its retry-enabled statej
said acknowledgement means responding to the presence on the common
communications path of an interlock-read command and an address
associated with any included interlock-bit register thereof to:
i) place retry signals on the common communications path
when the interlock-bit register associated with the address signals
on the common communications path is in its retry-enabled state;
and
ii) place acknowledgement signals on the common communi-
cations path when the interlock-bit register associated with the
address signals on the common communications path is in its retry-
disabled state; and
B. a plurality of memory locations for containing data,
each memory location being associated with an address and, when
the memory device is connacted to the common communications path;

- lOb -


i) being responsive to the presence on the common
communications path of the address associated therewith, to an
interlock-read command, and to the state of the interlock bit
associated with the address of that memory location to place on
the common communications path data signals representing the data
stored in that location if the interlock-bit register associated
with the address of that location is in its retry-disabled state
and to refrain from placing on the common communications path data
signals representing the data stored in that location if the inter-

lock-bit register associated with the address of that location is
in its retry-enabled state, and
ii) further being responsive to its address on the common
communications path and to an unlock-write command to store there-
in data represented by data signals carried by the common communi-
cations path.
According to another broad aspect, the present inven-
tion provides for connection to a common communications path in a
data processing system, which path includes lines for carrying
commands that specify a transaction to be performed, for carrying
stall signals that request extension of the length of the trans-
action, for carrying no-acknowledgement signals that cause termina-
tion of the transaction in one way, and for carrying retry signals
that cause termination o~ the transaction in another way, a slave
device comprising:
A. transaction means responsive to a command fr~m a master
device on the common communications path for performing a trans-

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action with the master device that has placed the command on the
path when the slave device is connected to the common communica-
tions path;
B. stall means responsive to the transaction means for
placing a stall signal on the communications path during the de-
vice's performance of the transaction specified by the command
signal when the slave device is connected to the common communica-
tions path if the time required by the transaction means to
complete a step of that transaction is more than an allotted period
of time; and
C. retry means for monitoring the stall means to keep track
of how long the device has asserted the stall signal and for plac-
ing the retry signal on the common communications path when the
device has asserted the stall signal for more than a predetermined
maximum time.
Detailed Descrlption
The foregoing and other and further objects and features
of the invention will more readily be understood from the follow-
ing detailed description of the inventionj when taken in conjunc-
tion with the acco~panying drawings, in which:
Figures lA-lC are block and line diagrams of various
processor and device configurations which can be imple-


mented with the interconneetin~ means deseribed hereini
Fiaure 2 illustrates the signal structure of the
intereonneeting means;
Figures 3A-3C illustrate various ti~ing sic~nals
used in a ?artieular implementation of the intereonnecting
means, the manner in which loeal timing signals are genera-
ted, and their use in defining a "transaction" among devices
eonneeted to the interconneetinc means;
Figure 3D illustrates th-e arbitration function
se~uence;
Fiqure 3E illustrates BSY and MO AB~B seauences;
Figures 4A-4H are tables settina forth the structure
of eaeh of the transaetion types utilized by the interconnec-
ting means;
Figure 5A is a table su~marizing the co~mand eodes
of the intereonnecting means, while Figure 5E is a table
su~marizing the data status eodes of the interconnectina
means;
Figure 5C is a su~mary of data length cocles of the
intereonneeting means;
Figure 6 is a P~esponse Code Su~mary table;

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Figures 7A-7I are diagrams of the basic register
set utilized by the interconnecting means sho~r~ing the spec-
ific utilization of various hits within each reaister; and
Figures ~A-8D are block diagrams of devices that
imlement the retry mechanism of the present invention.
l. Detailed Description of the Interconnectinc~
~leans
Figure lA illustrates the utilization of the inter-
connecting means described herei.n in a configuration typical
of small and relatively inexpensive computer systems. As
there illustrated, a processor lO, memory 12, terminals 14
and mass storage units (disks~ 16 are interconnected to each
other via interconnecting means 18 and a communications
path 20. In the case of processor lO anc~ memory 12, the
interconnecting means 18 are preferably located integrally
within the device and thus provide the communications inter-
face to the device. In the case

~.232G9'~


of the terminals 14 and storage u~its 16, intermediate
adapters 22, 24, respectively, may be provided in
order to allow the connection of a number of terminal
or storage devices to a single interconnecting means
18. The adapters serve to interface the
communications path 20 to the remainder of the device.
As utilized herein, the term "device" denotes one or
more entities connected to the communications path by
a common interconnecting means. Thus, in Fig. lA, the
terminals 14 and adapter 22 comprise a single device
26; similarly, processor 10 and main memory 12 are
each devices. In Fig. lB, the processor 32 and memory
34, together with adapter 40,comprise a single device~
In Fig. lA, it will be noted that the processor
10 shares the memory 12 with the other devices
connected to communications path 20. This results in
lower system cost, but limits system speed because of
the need to share the path 20. In Fig. lB, this
problem is resolved by providing a separate memory
path 30 between a processor 32 and a memory 34. The
processor and memory are then connected to terminal
devices 36 and mass storage devices 38 via an adapter
40, a path 42, and adapters 46 and 48. The adapter 40
has an interconnecting means 18 integral with it and
connecting the adapter to the path 42. Similarly
adapters 46 and 48 each have an interconnecting means
18 integral therewith and connecting them to the path
42. A system of this type offers higher performance,
but at a higher cost. However, it is still fully
compatible with the interconnecting means described
herein.
Finally, Fig. lC illustrates the use of the
device interconnecting means in a multi-processor
system. In this Figure, processors 50 and 52 are

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14

connected to primary memories 54, 56, respectively, by
memory paths 58, 60, respectively. The processor-
memory pairs, in turn, are connected to the remainder
of the system via adapters 62, 64, respectively,
having interconnecting means 18 incorporated
integrally therewith and interconnected by path 68. A
cache memoryl90 is associated ~ith one of the
processors, e.g., processor 52. The remainder o~ the
system is then essentially that shown in Fig. lB,
namely, one or more terminals 70 connected to the path
68 via an adapter 72 having an interconnecting means
18 therein, and a mass storage device 74
interconnected to the path 68 via an adapter 76 having
an interconnecting means 18. In this configuration,
not only can each processor communicate with each
device in the system, but the processors can
communica.te directly with each other. Further, cache
memoryl90is effectively accommodated. Despite the
. . ,
differing nature and level of complexity imposed by
this demanding mixture of devices in the same system,
the interconnecting means described herein efficiently
controls all the communications in essentially the
same way.
Turning now to Figure 2, the various categories
of signals generated and utilized by interconnecting
means are s~mmarized in accordance with their
principal functional class. Within each class, they
are grouped by their separate subfunctions.
Additionally, the specific wires of the group of wires
(or communications path) 78 which carry these signals
from one device to another are also shown in order to
faciliate subsequent discussion. A line is considered
to be asserted if any device attached to the line
asserts it. The line is deasserted only if no device

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is asserting it. For purposes of illustration, two
separate interconnecting means, designated A and B,
respectively, and integral with the corresponding
physical devices whose communications they control,
are illustrated schematically by the signals utili~ed
by them, and are shown as interconnected for signal
exchange purposes by path 78. However, it should be
understood that path 78 will typically physically link
more than two devices at any one time, although only
~hose devi~es selected by the Current Master will
actually participate in a transaction. The remaining
devices remain physically connected to ~he
communications path but do not participate in the
transaction.
As illustrated in Fig. 2, there are four broad
classes of signals utilized by the interconnecting
means, namely, Information Transfer class signals;
Response class signals; Control class signals; and
,
Power class signals. The "Information Transfer" class
signals include an Information field, designated
I[3:0~, which is transmitted and received over four
separate lines 80 of the path 78. The ~nformation
field carries information such as the command code,
code identifying the device initiating the transaction
~the "Current Master"), and information specifying the
status of data transmitted during the cycle, among
other information. A thirty two bit data word
transmitted over lines 82, labeled D[31:0] in Fig. 2,
provides certain information needed in the
transaction, such as the length of a data transfer
that is to take place (used in Read-type and Write-
type transactions); the identity of a device which is
selected to participate in the transaction; the
address of me~ory locations which are to be accessed

~32~
.



16

~or data transfer; and the data which is to be
transferred. This word is transmitted and received
over thirty two separate lines 82. Two lines, 84 and
86, designated "PO," used for indicating the parity on
the information and data lines, and BAD, signalling an
error condition, are also provided.
The "Response" class of signals comprises a
three-bit field, designated C~F~2:0] and transmitted
over lines 88, which provides a response to various
information transmitted to a device and which allows
the devices to alter the progress of the transactions,
as described in more detail subsequently.
The "Control" class signals are transmit`ted over
a group of eight lines 90-104. ~he first of these
signals, NO ARB, controls the arbitration process.
The second of these, BSY, indicates current control of
the communications path by a device. These two
signals are used in conjunction with each other to
provide an orderly transition of control among devices
seeking control of the communications path.
Of the remaining signals in the control class,
; the Time (+) and Time (-) signals comprise waveforms
generated by a single source connected to the path 98
and transmitted over lines 94, 96, respectively; they
are used in conjunction with the Phase (~) and Phase
(-) waveforms, also generated by a single source, and
transmitted over lines 98 and 100, respectively, to
establish the local timing reference for operation of
the interconnecting means at each device.
Specifically, the interconnecting means of each device
connected to the path 78 generates local transmitting
and receiving clock signals, TCLK and RCLK,
respectively, from the Time and Phase signals.
Finally, the STF signal, transmitted over line 102,

23~2~9~


is used to enable a "Fast Self Test" of the local
devices, as described in more detail hereinafter,
while the RESET signal, transmitted over line 10~,
provides a means of initializing (setting to a known
status) the devices attached to the communications
path.
In the "Power" signal class, the AC LO and DC LO
signals are transmitted over lines 104, 106,
respectively and are monitored by each device to
determine the status of the AC and DC power within the
system. A Spare line 110 provides for f~ture
expansion.
The interconnecting means described herein
performs its function of establishing communication
among selected devices by performing a sequence of
operations that are specific to the type of
communication to be undertaken. Each operation
comprises a sequence of cycles during which various
elements of information are placed on, or received
from, the communications path in order to effectuate
the desired communication with another device or
devices also connected to this path. These cycles are
defined by the Time and Phase clocks as may be
understood more clearly on reference to ~ig. 3A which
shows Time (~) and Time (-) clock signals 120 and 122,
respectively, as well as Phase (~) and Phase (-)
signals 124 and 126, respectively. These signals are
generated by a single Master clock connected to the
communications path. The~ are received by the
interconnecting means ofeach device and used to
generate the local TCLK and RCLK signals 128 and 130,
respectively, which control the transmission and
reception of information by them.


....

~3
.; ~


Thus, as shown in Fig. 3B, a number of devices
140l 142, etc. are connected in parallel to the
communications path so as to transmit and receive
information over these lines. These devices may be
input/output (I/O) devices such as printers, display
terminals, etc. or may be devices such as processors.
The physical placement of the devices on the path is
immaterial. A Master Clock 144 also connected to the
path generates the Time and Phase signals which are
transmitted to each device over lines 94-100. Each
interconnecting means includes timing circuitry for
generating local transmitting and receiving clocks
TCLK and RCLK, respectively. For example, device 140
may include a flip-flop 146 whose Q output produces
TCLK. The flip flop is set from a gate 148 and is
clocked by the Time (+) signal from line 94. Gate 148
in turn is enabled by line 98 and the Q bar output.
In similar fashion, the local Slave receive clock,
RCLK, is generated from the received Time (+) and
Phase (-) signals.
As shown in Fig. 3C, the time between successive
TCLK signals defines a cycle. A seq~ence of
successive cycles which is utilized to perform a
desired interchange of information is herein called a
"transaction." Although the detailed characteristics
of each transaction vary in accordance with the
operation performed by it, each transaction consists,
generally, of a Command/Address cycle; an Imbedded
Arbitration cycle; and one or more additional cycles,
~ost commonly designated as "Data" cycles. For
purposes of illustration only, two such data cycles
are shown in Fig. 3C. In general, information is
placed on the communications path 78 at the leading

~;23~6~

19

edge of TCLK and is latched into the interconnecting
means of a device during RCLK of the same cycle.
A state diagram of the arbitration function
performed by each interconnecting means is shown in
Fig. 3D. The arbitration function remains in the idle
state 150 until some element in the device causes it
to seek to initiate a transaction as indicated by REQ
in Fig. 3D. Whén this occurs, the interconnecting
means determines whether it is free to assert its
arbitration signals on the path 78 by examining the ~O
ARB line. As long as NO ARB is asserted, the
arbitration function must remain in the idle s~ate.
However, as soon as N0 ARB is deasserted, the~device
may arbitrate during the following cycle, provided
that REQ is still asserted. Under these conditions,
it enters the arbitration state 152 in which the
device arbitrates with other devices seeking access to
the communications path. The manner of arbitration
will be described in more detail hereinafter.
A device losing the arbitration returns to the
idle state 150, from which it may again seek to
arbitrate as long as REQ is asserted. Conversely, a
device winning the arbitration enters either the
Current Master state (if BSY is deasserted) or the
Pending Master state (if BSY is asserted.) A Pending
Master remains Pending Master as long as BSY is
asserted, and becomes Current Master following the
deassertion of BSY.
Before describing the operation sequence of each
of the transactions provided for by the interconnect,
it will be helpful to obtain a more detailed
understanding of some of the Control, Response, and
Information Transfer class signals themselves, as

~L;23~ig~


~hese are common to essentially all the transaction
types.

Control Signals: NO ARB, BSY
The NO ARB signal controls access to the data
lines for purposes of arbitration. Devices may
arbitrate for use o~ the communications path only in
those cycles for which NO ARB has been deasserted for
the previous cycle. The device which has control of
the interconnect (the "Current Master") asserts NO ARB
throughout the transaction except during the first
cycle and the last expected data cycle. (The last
expected data cycle of a transaction is usually the
last data cycle in fact; however, as described more
fully hereafter, devices may delay completion of a,
transaction under certain conditions. When they do,
the cycle that is expected to be the last data cycle
no longer is, and subse~uent cycles follow before all
the data is transferred.) NO ARB is also asserted by
the Pending Master until it becomes the Current
MasterO At any one time, there is at most only one
Current ~aster and one Pending Master.
NO ARB is also asserted during an arbitration
cycle by all arbitrating devices. During an Imbedded
Arbitration cycle, this assertion is in addition to
the assertion of NO ARB by the Current Master. During
an Idle Arbitration cyclej assertion of NO ARB by an
arbitrating device will preclude subsequent
arbitrations until one of the devices currently
arbitrating becomes Current Master.
` NO ARB is additionally asserted by Slave devices
(devices selected by the Current ~aster) for all
cycles in which the Slave asserts STALL, as well as
for all data cycles except the last. It is also

~32~g~

21

~sserted by a device (coincidentally with assertion of
BSY) during special modes when the interconnecting
means is occupied servicing its own device. In these
modes, the device does not use any communications path
lines other than BSY and NO ARB. Due to the potential
of being selected as Slave, a ~evice is prevented from
entering a special mode during a command/address
cycle. A device may operate in a special mode, for
example, in order to access registers in the
interconnecting means without requiring use of
Information Transfer class lines of the comm~nica~ions
path. Further, it may also be desirable to allow the
Current Master to continue assertion of NO ARB beyond
its usual termination cycle to thereby perform a
sequence of transactions without relinquishing control
of the communications path. This would be
particularly useful for high speed devices to allow
extended information transfer cycles, and thus
effectively increase the available bandwidth for that
device.
BSY indicates that a transaction is in progress.
It is asserted by the Current Master during the entire
transaction, except during the last expected cycle.
- It is also asserted by Slave devices which need to
delay progress of the transaction (e.g., a memory
device which needs additional time to access a
particular memory location); the delay is accomplished
by asserting BSY and NO ARB together with a STALL
response code ~to be described later). In addition,
BSY is also asserted for all data cycles except the
last. A device may also extend the assertion of BSY
in order to delay the start of the next transaction,
or when operating in the special modes discussed
above.

.~ .

3L23~6~
-22-
BSY is examined by devlces at the end of each cycle;
when deasserted, a Pending Master may assert it and assume control
as Current Master.
Figure 3E is a state diagram of possible sequences of
the BSY and NO ARB control lines in the present implementation.
It will be used to illustrate the manner in which the joint obser-
vation of these signals efficiently controls the exchange of in-
formation from devrice to device on the communications path.
On the power up all devices assert NO ARB (State 'rA")
effectively preventing access by any device until all devices
deassert the line (State "B"), at which time the communications
path enters the IDLE state. This allows time for all devices to
complete any power up initialization sequence if required. Once
NO ARB is deasserted and State "B" is thereby entered, devices may
freely seek to contend for control of the communications path.
Once a device arbitrates, State "A" is again entered whereupon the
"winning" device enters Command/Address State "C". It is'impor-
tant to note that this Command/Address cycle is recognized by all
devices not only by the transition of BSY from the deasserted to
the asserted state but in conjunction with the assertion of NO ARB
in the previous cycle. The observation of NO AR~ is necessitated
for devices to ignore the special mode state as a Command/Address.
The first entry of State "D" from the Command/Address
state is indicative of the Imbedded ArbitratiOn cycle of a trans-
action. It is this cycle that devices update their dynamic prior-
ity (if in "dual round robin" ~ode) by observation of the encoded
Master ID. Depending on the data length of the


~L~3~6~



transaction, control may remain in this state for
subsequent cycles. If no arbitration occurs, the
Master and Slave eventually relinquish control of the
communications path and flow proceeds again back to
State "B", the deassertion of both control signals.
If, however, a Pending Master exists, state F will be
subsequently entered, whereupon the device asserting
NO ARB will notice the deassertion of BSY in this
cycle and proceed either to Command/Address "C" or "G"
depending on whether the decision to preclude further
arbitration by other devices (referred to as 'tB~RST
MODE" in the diagram) is determined by the Master.
Note that in State "G" the Command/Address control
signals show that NO ARB and BSY are both asserted
which differentiates this from Command/Address State
"C" .
If the previous transaction was extended by the
assertion of BSY, and no Pending Master had existed,
control would have sequenced from State "D" to "E",
and remain in State "E" for one or more cycles as
required. The witnessed assertion of BSY wouid cause
control to remain in this state for one or more
cycles, whereupon the seguence may continue back to
IDLE State "B" and relinquish the communications path
for future transfers.
As described above, a special mode of operation
may have alternatively caused control to return to
State "D" for one or more cycles if one particular
device wished preclusion of selection as a Slave by
any other device. The simultaneous deassertion of BSY
and NO ARB would then again return control to State
"B", the IDLE condi~ion.
The figure therefore shows that the joint
operation of NO ARB and BSY regulates the orderly flow

.

24

of control exchange as well as information trans~er on
the comm~nications path.

Response Signals: ACK, NO ACR, STALL, RETRY
~ . . . _
System reliability is greatly increased by
requiring a response to transmissions over the
Information and Data lines. Generally, response is
expected exactly two cycles after'the particular
transmission. The response code for these devices is
shown in Fig. 6, where a "O" bit indicates assertion
(low level) and a "1" bit indicates deassertion (high
level).
The ACK response indicates success~ul completion
of a transmission reception by the intended recipient
of the transmission. For all transaction types, the
assertion of ACK during the first data cycle of the
transaction confirms correct receipt (i.e., no parity
error) of the Command/Address information transmitted
two cycles earlier. Additionally, in the first data
cycle as well as in subsequent data cycles in Read-
type and Ident transactions, ACK also indicates thatread or vector data is being asserted by the Slave,
while in Write-type transactions ACR also indicates
that the ~lave is prepared to accept Write data.
NO ACK indicates either a failure in the
transmission/reception or that no Slave has been
selected. Both ACK and NO ACK are permissible
responses to command transmissions, as well as to data
transmissions; in the latter case, the responses occur
thLough the two cycles following the last data cycle,
even though these cycles may coincide with a
subseq~ent transaction. NO ACK is the default state
of the response lines. It is defined in such a way
that any other code may override it.

~3~6~
, .


STALL may be asserted by a Slave device during
data cycles. For example, it is used by memories to
extend the time allowed for a read access or to
provide time for a refresh or error correction cycle
during a transaction. It is also used by memories to
delay further data transmission from the Master when
the memory write buffer is f~ll. It is ~sed by
devices to synchronize to another comm~nication path.
One or more STALLS may be used to dèlay an ACK or NO
ACK command confirmation if the device recognizes that
it is the Slave.
RETRY is asserted by a Slave device which cannot
immediately respond to a transaction. For example, it
is used by devices requiring a long internal
initialization sequence; by devices waiting for access
to another communications path; and by memories which
have been locked by an Interlock Read command as
described below. The Current Master responds to the
Slave RETRY response by terminating the transaction~
In the present implementation, RETRY is not used after
the first data cycle of a transaction. This simplifies
the interconnection logic. One or more STALLS may
precede the assertion of RETRY.
In order to prevent a device from monopolizing
the communications path, a limit is placed on the
extensions or successive assertions of STALL, RETRY,
BSY and NO ARB.
System Architecture: Specific Transaction Seq~ences
.. . .. . .. _
Figs. 4A-H set forth in detail the specific
characteristics of the transactions provided for by
the interconnecting means. In particular,
transactions for reading and writing data (READ, READ
WITH CACHE INTENT, INTERLOCK READ WITB CACHE INTENT,
WRITE, WRITE WITH CACHE INTENT, WRITE MASK WITH CACHE

~ .

~3~

26

INTENT, and UNLOCK WRITE MASK ~ITH CACHE INTENT); for
invalidating obsolete cached data (I~VALIDAI'E); for
handling interrupts (INTERRUPT, INTERPROCESSOR
INTERRUPT, IDENTIFY); for halting transaction
generation by devices (STOP); and for transmitting
information to a number of devices simultaneously
(BROADCAST) are illustrated in detail. In each of the
Figures, the range of permissible'CNE~ responses is set
forth, and the particular response illustrated is
marked by a dot (.). Further, for purposes of
illustration only, the transac~ions are shown as
including only two cycles of data transfer although a
larger or smaller number of cycles may be used.
The commands described herein are of two general
types, namely, single responder commands (Read-type,
~rite-type commands, and IDENTIFY) and multi-responder
commands (STOP, INVALIDATE, INTERR~PT, INTERPROCESSO~
INTERR~PT, and BROADCAST). In order to insure the
unique recognition of responses when multiple
responses are being asserted on the same lines, the
permissible responses to multi-responder commands are
limited to ACK and NO ACK.
Read-Type Transactions
Referring now to Fig. ~A, the characteristics of
a Read type transaction are set forth in detail. This
type of transaction includes not only the READ
command, but also the READ WITH CACHE INTENT and the
INTERLOCK READ WITH CACHE INTENT commands as well.
The four-bit codes for these commands are shown in
Fig. 5A, together with the codes for the other
commands utilized by the device interconnecting means.
Note that additional codes may subsequently be added,
as indicated by the dash (-) in this Figure. The
transaction comprises a number of successive cycles,

~;23~
27

nam-ely, a command/address cycle 180, an Imbedded
Arbitration cycle 182, and a number of data cycles.
For purposes of illustration only, the transaction is
shown as including two data cycles 184, 186,
respectively. The principal lines on which information
is transmitted (cf. Fig. 2) are indicated by their
functional names, namely, the Information lines
I~3:0], the Data lines D[31:0], the Confirmation lines
CNF[3:0], and the NO ARB, BSY and P (parity) lines.
For clarity of illustration, the remaining lines
(i.e., Time, Phase, STF, RESET, AC LO, DC LO, ~AD and
SPARE) are omitted in Fig. 4 since they are not
essential to understanding the operation of the
transactions.
As indicated in Fig. 4A, during the
command/address cycle of a ~ead-type transaction, the
four-bit command code is placed on the information
lines I[3:0]. Additional data required in connection
with the command is placed on the data lines D[31:0].
Specifically, a two-bit data length code specifying
the length of the transfer which is to take place is
applied by the interconnecting means to data lines
D[31:30], while the "address" of the device with which
the trans~er is to take place is applied to data lines
D[29:0]. The fact that these signals are asserted on
the appropriate lines by the device which currently
has control of the interconnect ~the "Current Master")
is indicated by the letter "M" in the appropriate
block in Fig. 4A. The assertion of information on a
given line or set of lines by a Slave device is
indicated by the letter "S" in Fig. 4A. In similar
fashion, the letters "AD", "AAD", "APS" and "PM"
(i.e. "All Devices", "All Arbitrating Devices, "All
Potential Slaves", and "Pending Master",

~S J ~
` ~2326g'~

28

respectively) indicate various other devices which may
assert signals on seleeted lines of the communieations
path during partieular eycles.
The address eomprises a single thirty-bit word
designating the specific storage lo,cation with which a
Read-type or Write-type transaetion is to take place.
A separate bloek of addresses is assigned to each
device. The loeation of the block is based on the
identification number of the associated device.
During the Command/Address cycle, the Current
Master deasserts NO ARB as shown at 158 in Fig. 4A.
(For purposes of discussion herein, a signal is
eonsidered "asserted" when at a low level, and
"deasserted" when at a high level). Deassertion of NO
ARB allows other devices desiring control of the
communieations path to arbitrate for such access
during the following cycle. At the same time, the
device asserts BSY to prevent other deviees from
gaining eontrol of the eommunieations path while the
eurrent transaetion is in process. No signals are
applied to the CNF lines at this time by the Current
Master, although it should be understood that, in the
course of a sequence of transactions, one or more
Response signals may be applied to the CNF lines by
other devices during a transaction by a Current
Master.
The second cycle of the transaction comprises an
arbitration eycle. It is referred to as an "imbedded"
arbitration eycle since it is contained within a
transaetion. Arbitration which oecurs outside of a
transaction is referred to as an "Idle" arbitration
eycle. During the Imbedded Arbitration eyele of Fig.
4A, the Current Master plaees its identifieation
number ~ID) on the information lines I[3:0]. This

~L23~

29

co~e is used by all devices to update their
arbitration priority, as previously described.
At this time also, those devices seeking use of
the communications path assert a single-bit signal
corresponding to their identification number on either
the low priority level lines, D[31:1~), or the high
priority level lines D115:0], e.g., device 11 asserts
line D[ll] if arbitrating at high priority and asserts
line D[27~ if arbitrating at low priori~y.
The level at which the device arbitrates is
determined by its arbitration mode as well as by the
ID of the previous Master. In the present
implementation, the arbitration mode is defined by
bits 4 and 5 of the particular device's control and
status register, i.e., CSRl5:4] (see Fig. 7C3. As
presently implemented, four modes are provided for,
namely, fixed high priority, fixed low priority, "dual
round robin'i, and arbitration disabled. The
interconnecting means supports mixing these modes at
will by appropriately setting the arbitration mode
bits CSR~5:9].
In the case of arbitration in a fixed-priority
mode, whether fixed high or fixed low, the priority
does not vary from transaction to transaction. In
contrast, in the case of "dual round robin"
arbitration the priority of a device may change from
one transaction to another as described previously.
In particular, in the "dual round robin arbitration"
mode, during a given transaction, a device will
arbitrate at a low priority level (i.e., on lines
D[31:16]) if its ID number is equal to or less than
the ID number of the Master in the immediately
preceding transaction, and will arbitrate at a high
priority level (i.e.-, lines D~15:0~) otherwise.
.

3~



-- Continuing on with the transaction of Fig. 4A, at
the conclusian of the Imbedded Arbitration cycle, a
device which has arbitrated during this cycle and won
the arbitration becomes Pending Master, and asserts NO
ARB until it becomes Current Master, as shown in
dotted lines in Fig. 4A. This prevents other devices
from subsequently arbitrating for, and possibly
yaining control of, the communications path before the
Pending Master can assume such control.
The arbitration cycle is followed by one or more
data cycles. For purposes of illustration, Fig. 4A
shows two such data cycles only. As noted previously,
the actual amount of data to be transferred in each
transaction, and thus the number of data cycles
utilized by the transaction, is specified in the
command/address cycle by bits D[31:30]. In the
particular implementation described in Fig. 4A, from
one to four cycles of data (here, 32 bits per cycle)
may be transmitted in a transaction. Of course, by
providing fewer or more bits for the data length
specification, a lesser or greater- number of data
cycles, and thus transaction cycles, may be provided
for.
In the case of a Read-type transaction as shown
in Fig. 4A, the data called for by the transaction is
s~pplied by the Slave to which the transaction is
addressed. This device may be a memory device or it
may be some other device such as an input/output
terminal. In either event, the device so selected
asserts its data on the data lines D[31:0] during the
data cycle. ~t this time, also, it asserts a code on
lines I[3:0] which indicates the status of the data.
For example, for memory references, the code may
indicate whether the data is data that has been

,

~23~6~


retrieved without utilization of any correction
algorithms (referred to simply as "read data"), data
that has been corrected before being asserted on the
data lines (referred to as "corrected read data"); or
data that, for one reason or another, cannot be relied
on ("read data substitute"). Further, the status code
indicates whether or not, for each of these data
categories, the data may be cached. The use of the
"don't cache'` facility will greatly enhance
performance in some systems. These codes are
illustrated in Fig. 5B.
During the first data cycle, the Slave returns to
the Master a confirmation code on lines CNF[2:0] which
confirms receipt of the Command/Address information
from the Master and which may provide further
information to the Master with respect to the Slave's
response. Thus, the first assertion of the
confirmation signals, for the current transaction, is
made during the first data cycle, two cycles after the
Command/Address cycle which began the transaction.
For the Read transaction described in Fig. 4A, the
permissible responses in the first data cycle are the
ACK ~"Acknowledge"), NO ACK ("Not Acknowledge"), STALL
and RETRY. These are largely common to all
transactions, with certain exceptions which will be
described in connection with the particular
transactions.
In general, the assertion of ACK during the
first data cycle indicates correct receipt of
Command/Address information, together with the ability
of the-Slave to take the requested action, i.e.,
ret~rn read data. Conversely, the assertion of N0 ACK
indicates either an error in transmission of the
command or some other inability of a Slave to respond.

. ~ ~

~2326~'~

32

The assertion of STALL allows the Slave to extend the
transaction in order to prepare itself to provide the
read data requested by the Master, while the assertion
of RETRY indicates current inability to respond to the
command, accompanied by a request that the Master try
again at a subsequent time. R~TRY is appropriately
used when the expected response time of the Slave
would be so long that it would be undesirablé to
extend the transaction an excessive number of cycles
by asserting general STALL responses.
In Fig. 4A, the ACK response (designated by a dot
.) before the response) is illustrated. If the
response were NO ACK, the action taken by the Master
would di~fer from that taken in response to ACX, e.g.,
the Master may seek to repeat the transaction a
limited number of times, may call for an interrupt,
etc. A STALL response is similar to an ACK response
but the transaction will be extended by one or more
"blank" cycles ~cycles in which no valid data is
present on the data lines) before the requested data
is returned.
The second, and last, data cycle in Fig. 4A is
similar to the preceeding data cycle, that is, the
Slave asserts the requested data on lines D[31.0]
together with a code indicating the status of the data
on lines I[3:0]. At the same time, it asserts a
confirmation signal on CNF~2:0~. Unlike the Slave's
response to the first data cycle, however, the Slave
may respond only with ACK, NO ACK, or STALL; it may
not assert R~TRY. Further, since the second data
cycle is the last data cycle of the transaction in
Fig. 4A, the Slave deasserts both NO ARB and BSY. If
the Slave were to extend the transaction by asserting
STALL so that the return of read data would be

,

~3~ u~ ~1

.
33

deferred a subsequent eyele, the Slave would eontinue
its assertion of NO ARB and BSY until the last data
eyele in faet oeeurred. It would then deassert NO ARB
and BSY during that last data eycle. As noted
previously, deassertion of BSY allows a Pending Master
to assume eontrol of the eommunications path on the
following cycle, while the Slave's deassertion of NO
ARB is preparatory to allowing subsequent arbitration
to occur for access to the eommunieations path.
With the eompletion of the second and last data
cyele, the prineipal information transfer functions of
the transaction of Fig. 4A are eompleted. However, it
is still necessary to confirm the correct receipt of
the data. This is accomplished during the two cycles
following the last data eyele during whieh the Master
asserts the appropriate confirmation signal on
CNF12:0] with respect to receipt of the data. As
shown, the appropriate eon~irmation is either ACK or
NO ACK. Note that the eonfirmation extends beyond the
last data eyele and may thus overlap with the
Command/Address and Imbedded Arbitration eycles of a
following transaction. However, no error will arise
from this since the confirmation lines are not used by
the following transaetion during its first two eycles.
During the Command/Address eycle parity is
generated by the Current Master on the I[3:0] and
D[31:0] lines, and is checked by all deviees. During
the Imbedded Arbitration cycle, it is generated by the
Master on the I[3:0] lines only and eheeked by all
deviees. During the data eyeles, parity is generated
by the Slave on the I[3.0] and D[31:0] lines and is
eheeked by the Current Master. The speeifie
eonsequenees of a parity error will depend on the
nature of the information being transmitted during the

.,

~L~3~6!~

34

given cycle when the error~ occurs. At a minimum,
devices detecting a parity error during the
Command/Address cycles should not respond to
selection; additionally, they may indicate the parity
error by setting an error flag, initiating an
interrupt, or other such action.
As noted previously, the Read With Cach~ Intent
command has the same format as the Read transaction.
It is generated by devices with cache to indicate to
the Slave that the requested read data may be placed
in the Master's cache. When this command is used in
conj~nction with the INVALIDATE command described
below, it can provide a significant performance
enhancement in cértain systems with cached devices.
The Interlock Read transaction also has the same
format as the Read transaction. It is used with
shared data structures to provide exclusive access to
data by processors and other intelligent devices.
Slaves supporting the Interlock Read command have one
or more interlock bits corresponding to designated
storage locations. When accessed by an Interlock Read
Command, a Slave sets the appropriate bit
corresponding to the addressed location. This
prevents subsequent Interlock Read accesses to the
location until the bit is reset to thereby unlock the
given location. This bit is typically reset by the
UNLOCK WRITE MASK WITH CACHE INTENT Command described
below. The INTERLOCK READ command is especially
useful in systems having processors which provide
read-modify-write operations to insure that
intervening devices using the Interlock Read Command
are precluded from access ~o data after the
initiation, but before the completion, of such an
operation. Slaves addressed by INTERLOCK R~ADS while

1~3~9'~ 83-312



the interlock is set issue a RETRY~ Note that the
interlock bit is set only if the Interlock Read
transaction is successful~ i.e., the Master confirms
correct receipt of the Slave's read data.

Write-Type Transaction
Turning now to Fig. 4B, the ~rite-type
transactions (as implemented, WRITE, WRITE WIT~ CACHE
INTENT, WRITE MASK WITH CAC~E INTENT, and VNLOCK WRITE
MASK WITH CACHE INTENT) are shown in detail. Starting
1~ with the Command/Address cycle, the c~rrent Master
places the appropriate four bit code for the command
on information lines I[3:0]; a two-bit code
identifying the length of the data transmission on
data lines D[31:30]; and an address on data lines
D[29:0]~ At the same time, it asserts BSY to indicate
the occupied status of the communications path, and
deasserts NO ARB to signal the availability of the
data lines for arbitration during the immediately
foIlowing cycle.
During the second cycle, the Current Master
places its ID on information lines I13:0). Devices
seeking control of the communications path for a
subsequent transaction assert a single bit
corresponding to their ID on the data lines at this
time. As was previously the case, the assertion is
made of one of the low priority data lines D~31:16]
for arbitration at the low priority level, and is made
on the high priority data lines D[15:0] for
arbitration at the high priority level. The Master
continues to assert BSY at this time, and the Master,
as well as devices participating in the arbitration,
assert ~O ARB at this time also.

~ 3~2~g~

36

In the example shown in Fig. 4B, the third and
fifth cycles are data cycles. Although two data
cycles are shown, a lesser or greater number may be
utilized, in accordance with the transfer length
specified on lines D[31:30] in the Command/Address
cycle. The data being written by the Master is
applied to data lines D[29:0] d~ring these cycles.
The Information lines I~3:0] carry either a write mask
(in the case of a Write Mask transaction) during the
data cycles to indicate the selected byte or bytes
~hich are to be written d~ring the transaction, or are
"undefined" (in the case of ~rite and Write With Cache
Intent transactions). The "undefined" stat~s of the
I[3:0] lines indicates that any information on these
lines is to be ignored by the devices for purposes of
the transaction.
During the first data cycle, the Current Master
continues to assert BSY and NO ARB. During the fourth
data cycle, which the Current Master expects to be the
last data cycle, the Current Master deasserts both BSY
and NO ARB to prepare for an orderly transition of
communications path control.

In order to illustrate the capability of a Slave
to extend a transaction, the fourth cycle ~Data 2) is
shown as stalled by way of the Slave's assertion of
STALL. For example, this may be done when the Slave
is unable to accept the second data word at this time.
The Slave asserts BSY and NO ARB during this cycle.
The last data cycle of this transaction is cycle 5.
During this cycle the Master responds to the assertion
of STALL by retransmitting Data 2. The Slave asserts
ACK on the CNF lines; and the Slave deasserts both BSY
and NO ARB. In the two cycles following the last data

~L~32~i9~

37

cycle, the Slave continues to assert ACK ~o conEirm
the correct receipt of Write data.
When a Write-type transaction occurs on the
communications path, devices connected to the path and
having resident cache memory invalidate any cached
data within the address range of the write command.
As was the case with the READ WITH CACH~ INTFNT
command, the WRITE WITH CACHE INTENT command, when
used with the Invalidate command offers significant
performance advantages in certain systems.
The write mask is a foLr-bit code indicating, by
the presence of asserted bits in one or more of the
four-bit positions, the selection of the corresponding"
eight-bit bytes to be written. Thus, the code 1001
indicates that only the first and fourth bytes
~corresponding to D[7:0] and D[31:24], respectively)
of a four byte (32 bit) word are to be written.
The UNLOCK WRITE MASK WITH CACHE INTENT command
is used in conjunction with the Interlock Read command
to implement indivisible o2erations such as a read-
modify-write operation.
As may be seen from Fig. 4~, during a WRITE-type
transaction, parity is generated by the Master during
all cycles of the transaction. It is checked by all
devices during the Command/Address and Imbedded
Arbitration cycle; and by the Slave during the data
cycles.

Invalidate Transaction
The Invalidate transaction is used by systems
having cache memories associated therewith. It is
issued by devices under certain conditions to
guarantee that obsolete data that may be present in
the caches of other devices is not used. In the
.

~L~3~6~ 51'

38

Command/Address cycle of this transaction, as shown in
Fig. 4C, the Current Master asserts the Invalidate
command on information lines I[3:0] and the starting
address of the data to be invalidated on data lines
S D[29:0~. The number of consecutive locations of
cached memory to be invalidated is indicated by the
data length code on lines D[31:30]. The
Command/Address cycle is followed by the usual
Imbedded Arbitration cycle, and a data cycle during
which no information is transmitted. As with other
multi-responder commands, the specified permissible
responses are ACK and NO ACK.

Interrupt and Identify Transactions
An Interrupt transaction is illustrated in Fig.
4D. The purpose of the transaction is to notify other
devices (typically, processors) of the need to
interrupt current activities in order to take other
action. The interrupted device responds with an IDENT
- command to solicit the Interrupt Vector. This vector
serves as a pointer to the address of an interrupt
routine stored in memory which will establish the
required action.
The Interrupt transaction comprises a
Command/Address cycle, an Imbedded Arbitration cycle,
and a data cycle in which no information is
transmitted. During the Command/ Address cycle, the
Interrupt command code is asserted on the Information
lines I[3:0] by the device seeking to interrupt.
During this cycle, the interrupting device also
asserts one or more interrupt priority levels on data
lines D[19:16] to identify the immediacy of requested
services. The interrupting device also places an
interr~pt destination mask on data lines D~15:0]. This

~ ~3Z~9'~ V_

39

mask specifies the devices to which the interrupt is
directed. All devices on ~he communications path
receive this mask. If any asserted bit in the mask
corresponds to the device's decoded ID, then the
device is selected. This device will later respond
with an Identify transaction.
Devices which have been selected by the interrupt
respond by transmitting an ACK signal two cycles after
the Command/Address cycle. ~s with all other multi-
responder commands, ACK and NO ACK are the onlypermissible responses.
Devices selected during an interrupt may be
expected to engage in a subsequent transaction with
the interrupt-requesting device in order to complete
lS the interrupt process. Accordingly, each responding
device maintains a record for each interrupt level to
indicate whether an interrupt was received at the
corresponding level. Typically, the "record"
comprises a flag bit in a flip flop (hereinafter
referred to as an Interrupt Pending Flip-Flop). Each
bit remains set until the corresponding interrupt has
been serviced. ^
The second and third cycles comprise the usual
Imbedded Arbitration cycle as previously described, as
well as a data cycle in which no further information
is transmitted. Confirmation is made by one of the
confirmation codes permissible for multi-responder
commands, ACK or NO ACK.
Fig. 4E illustrates an Identify transaction.
This transaction takes place in response to an
Interrupt transaction. During the Command/Address
cycle, the Current Master asserts the Identify command
code on Information lines I[3:0] and asserts on data
lines D[19:16] a code corresponding to one or more

3~9~


interrupt levels to be serviced. It also asserts BSY
and deasserts NO ARB. The following cycle is the
usual Imbedded Arbitration cycle.
In the next cycle, the Current Master reasserts
its ID number, this time in decoded form on data lines
D[31:16]. Each device that requires service at an
interrupt level specified in the Command/Address cycle
compares the decoded Master ID with the interrupt
destination mask that it had earlier transmitted in
order to determine whether it is one of the devices to
which the Identify command is directed. If it
determines that it is, it manifests its status as a
Potential Slave participating in the Interrupt
Arbitration cycle. During both the Decoded Master and
1~ the Interrupt Arbitration cycles, the interrupting
Slaves also assert BSY and NO ARB. During the
Interrupt Arbitration cycle, the devices arbitrating
to transmit their interrupt vector assert their
decoded ID number on the appropriate one of the data _
lines D[31:16]. Arbitration takes place in the manner
previously described, that is, the device having the
highest priority ~lowest ID number) "wins" the
arbitration, thereby becoming the Slave. The Slave
then asserts its interrupt vector on the data lines.
This vector points to a location in memory which
contains a further vector identifying the start of the
interrupt service routine. At the same time, the
Slave transmits a vector status code on information
lines I[3:0] indicating the status of the vector in
much the same manner as the data status indicated the
status of the read data on these lines during a Read
transaction.
As was the case with previously described
transactions, the BSY siynal is asserted by the Master

~3~ 3-312

~1

during the transaction from the first cycle to the
last expected cycle, while NO ARB is asser~ed from the
Imbedded Arbitration cycle to the last expected cycle.
ACK, NO ACK, STALL and RETRY may be asserted by
the Slave in response to the Identify command. This
response occurs in cycle five, which is two cycles
later than for all other transaction types. During
the two cycles following the vector cycle, the Master
asserts the ACK confirmation code to indicate
successful completion of the transaction. On receipt
of the Slave's acknowled~ement o~ the Identify
command, the Master resets the Interrupt Pendin~ flip
flop corresponding to the interrupt level for which
the interrupt vector was transmitted. If the Slave
does not receive the Master's acknowledgement to its
transmission of the Interrupt Vector, it retransmits
the Interrupt transaction.
A device may not participate in the interrupt
- arbitration cycle if it has detected a parity error in
either the Command/Address or the Decoded Master ID
cycles.
Devices which have arbitrated during the
Interrupt Arbitration cycle but which have los~ the
arbitration are required to reissue the Interrupt
Command. This prevents loss of previously posted
interrupts.

Interprocessor Interrupt Transaction
A simplified form of interrupt is provided for
multiprocessor systems when one processor seeks to
interrupt one or more other processors. The
Interprocessor Interrupt transaction, illustrated in
Fig. 4F, comprises a Command/Address cycle, an

~:3~
.

42

Imbedded Arbitration cycle, and a data cycle in which
no information is transmitted.
In the particular implementation used to
illustrate the intercommunicating means herein, this
transaction makes use oE three registers, namely,
Interprocessor Interrupt Mask, Destination, and Source
Registers 212, 214, and 216 respectively (Fig. 7A).
The Mask Register contains a field that identifies the
processors from which Interprocessor Interrupt
commands will be accepted. The Destination register
contains a field that identifies the processors to
which an Interprocessor Interrupt Command is to be
directed; the Source Register contains a field that
identifies the source of Interprocessor Interrupt
transaction received by a processor.
During the Command/Address cycle, the
interrupting processor asserts the interprocessor
interrupt command code on the information lines
I[3:0]. At the same time, it asserts its decoded
Master ID on the data lines D[31:16] and asserts a
destination code (e.g., from its Interprocessor
Interrupt Destination Register) on data lines D[15:0].
During the following Imbedded Arbitration cycle, the
interrupting processor asserts its ID on the
Information lines I~3:0], and arbitration proceeds in
the usual manner.
During the third cycle, the devices addressed by
_ the Destination Code asserted in the Command/Address
cycle compare the decoded Master ID with the mask in
the Mask Register to determine whether the Master is a
device to which they may respond. If so, in addition,
the Decoded Master ID is preferably stored in the
Interprocessor Interrupt Source register in order to
maintain the identity of interrupting devices. This

~23~ 0~
.

43

saves the processor the overhead of later seeking an
Interrupt Vector as is done in the Interrupt
transaction. The permissible Slave conf;rmation
signals are ACK and NO ACK as for any other multi-
responder command.

Stop Transaction
The Stop transaction is illustrated in Fi~. 4G.
It facilitates diagnosis of failed systems by stopping
further generation of transactions by selected devices
while allowing them to continue responding as Slaves.
Devices selected by a Stop Transaction must abort any
Pending Mastec state and deassert NO ARB. In order to
facilitate error dia~nosis, it is preferred that such
devices maintain at least certain minimum information
concerning error conditions existing at the time of
the Stop Transaction. For example, it is desirable
that the information contained in Communications Path
Error Register 204 (Fig. 7D) be maintained for
subsequent analysis.
2C During the Commcnd/~dress cycle, the Current
~laster performing a Stop transaction asserts the -
appropriate command on information lines I~3:0] and
asserts a d~stination mask on data lines ~ ~. The
mask comprises a number of bits which, when set,
identify the devices which are to be stopped. The
Command/Address cycle is followed by the usual
Imbedded Arbitr~tion cycle and a data cycle during
which no inforamtion is transmitted. The information
transmitted during the Command/Address cycle is
confirmed two cycles later by all devices selected by
the Stop transaction.

~ Z~69'~

44

Broadcast Transaction
The Broadcast transaction, illustrated in Fig.
4H, offers a convenient means of broadly notifying
devices on the communications path of significant
events while avoiding the overhead costs of Interrupt
transactions. During the Command/Address cycle of the
transaction, the Current Master initiating the
Broa~cast transaction asserts the appropriate command
code on Information lines I~3:0] and places a two-bit
data length code on data lines D[31:30]. At the same
time, it places a destination mask on ~ata lines
D[15:0]. This mask specifies the devices which are
selected by the broadcast transaction. For exanple, a
"one" bit asserted on data lines 2, 3, 5, 9, 12, 13,
and 19 will select devices 2, 3, 5, 9, 12, 13, and 14
for receipt of the Broa~cast. The ComT,and/Address
cycle is Eollowed ~y the usual Imbedded Arbitratio
cycle which in turn is followed by one or more 3at~
cycles. For purposes of illustration only, t~o ~ta
cycies are shown. The data itself is asserted on data
lines D[31:0] by the M~ster. As with ~rite-type
transactions, the Slaves issue either ACK or N~ A-C~
two cycles later.

Register Co~plement
Fig. 7A shows the register file contairled in the
present implementation of the interconnecting means.
These comprise a Device-Type Re~ister 200, a Control
and Status Register 202, a Bus Error Register 204, an
Error Interrupt Control Register 206, an Error Vector
Register 208, an Interrupt Destination Register 210,
an Interprocessor Interrupt Mask Register 212, an
Interprocessor Interrupt DestinatiOn Register 219, and
an Interprocessor Interrupt Source Register 216.

~23~6~ 83-312



These registers comprise both 32 bit registers (e.g.,
registers 200, 204) and 16 bit registers (e.~.,
registers 202, 206, 208, 210, 212, 214 and 216.
In the Device-Type Register 200, ~Fig. 7B), the
code for the device-type is stored in the lower half
(DTR[15:0]) of the re~ister. The device-type is
loade3 into this re~ister on system power-up or on
subsequent initialization of the syste~n. This
re~ister may be interro~ated by other elements in the
system, usually a processor, to deter~ine what ~e~ices
are conne_tei to the system for purpos~, o~ opti~nizin3
and dynamically rearranging, the system confi3uration.
A Revision Code field (DTR[31:15}) is provided for in
the upper half of the Device-Type reyister.
l; The Control and Status Register 202 contains a
nu~ber of bits indicating the status of ~arious
conditions within the device, as ~ell as within the
interconnectiny means to which it is attached.
Additionally, it stores infor~ation ~rilize3 in
arbitrating for control of the comlnunications 2ath.
~hus; bits CSR13:0] store the encoded form oE the
device ID which also is loaded into this re~ister on
power up or on subseq~ent initialization.
Bits CSR[5:4] specify the arbitration mode in
~, which the device will ari>itrate. ~, described
earlier, these modes comprise "Dual ~ound Robin",
Fixed High, Fixed Low, and Arbitration Disabled modes.
On power up or on subse~uent InitializatiOn, the
arbitration mode is set to "dual round robin."
However, this mode ~ay be changed by writing to these
bits ~uring system operation.
CSR[7] and CSRE6] are Hard Error Interrupt Enable
and Soft Error Interrupt Enable bits, respectively.
~hen set, they enable the device to generate an

~23;~G9'J~
46 6822-42D
Interrupt transaction (referred to hereafter as an Error
Interrupt transaction) whenever the Hard Error Summary Bit
CSR[15] or Soft Error Summary bit SCR~14], respectively, are
set. These latter bits are set when a hard or ~ soft error,
respectively, is detected. A "hard" error is one which affects
the integrity of data on this system; for example, a parity
error detected on the data lines during transmission of data is
a hard error. Conversely, a "soft" error is one which does not
affect the integrity of -the data in the system;for example, a
parity error detected on the Identification I [3 :0] lines during
the Imbedded Arbitration cycle may lead to an incorrect calculation
by a device but will not affect the integrity of data on the
communcations path. Accordingly, it is a soft error.
The Unlock Write Pending bit CSR~8] indicates that an
Interlock Read transaction has been successfully transmitted
by the device but that a subsequent unlock Write Mask with Cache
Intent command has not yet been transmitted. Start Self Test
bit CSR[10], when set, initiates a self test which checks out
the operation of the interconnect logic. The Self Test
status CSR[ll] remains reset until the self test has been
successfully completed, at which time -the STS bit is set
to indicate successful completion of the test. The Broke bit
CSR[12] is also set if the device has failed its self test.
The Initialization bit CSR[13] is used in conjunction with
system initialization. ~or example, it may be used as a status
indicator while the device is undergoing Initialization. CSR[23:
16] specifies the particular design of the interconnecting means.
Bits CSR[31:24] are presently not used.




. .
~ ,~.,,

~;~3;26~

-47-
The Bus Error Register 204 records various error con-
ditions during system operation. The Null Parity Error bit BER[0],
the Corrected Read Data Bit BER[l] and the ID Parity Error Bit
BERE23 records soft errors, while the remaining bits record hard
errors. The Null Parity Error Bit is set if incorrect parity was
de~ected during the second cycle of a two~cycle se~uence during
which NO ARB and BSY were deasserted. The Corrected Read Data
bit is set if a Corrected Read Data Status Code is received in
response -to a Read-type transaction. The ID parity error bit is
set if a parity error is detected on the I[3:0] lines carrying
the encoded Master ID during an Imbedded Arbitration cycle.
Illegal Confirmation Error bit BER[16] indicates receipt
of an illegal confirmation code during a transaction. Nonexistent
Address bit BER[17] is set on receipt of a NO ACK response to a
read-type or write-type command. Bus timeout bit BER[18] is
set if a Pending Master ever waits more than a prede-termined num-
ber of cycles to assume control of the interconnect. In the spe-
cific implementation described herein, a timeout of 4096 cycles is
implemented. STALL timeout bit BER[l9] is set if a responding
(Slave) device asserts STALL on the response lines CNFE2:0] for
more than a predetermined number of cycles. In the present imple-
mentation, the stall timeout occurs after 128 cycles. The RETRY
timeout bit BERE20~ is set if a Current Master receives a pre-
determined number of consecutive RETRY responses from a Slave with
which it is communicating. In the present implementation, this
timeout is set for 128 consec~tive RETRY responses.


~23;~

-48-
The Read Data Substitute Bit BER[21] is set if a dat~
status comprising a Read Data Substitute or a Reserved Status Code
is received during a Read-type or Identify transaction and there
has been no parity er.ror during this cyc:le. The Slave Parity
Error bit BER[22~ is set when a Slave detects a parity error on
the communication path during a data cycle o~ a ~rite-type or
Broadcast transaction. The Command Parity Error bit BER[23~ is set
when a parity error is detected during a Command/Address cycle.
The Identify Vector error bit BER~24] is set by a Slave
on receipt of any confirmation code other than ACK from the Master
Identify transaction. The Transmitter During Fault bit BER[25] is
set if a device was asserting information on the data and infor-
mation lines (or, during Imbedded Arbitration, just on the infor-
mation lines) during a cycle resultlng in the setting of the SPE,
MPE, CPE, or IPE bit. The Interlock Sequence Error Bit BER~26]
is set if a Master success~ully transmitted a Write Vnlock trans-
action without having previously transmitted the corresponding
Interlock Read transaction. The Master Parity Error bit BER[27]
is set if the Master detects a parity error during a data cycle
having an ACK confirmation on the CNF[2:0] lines. The Control
Transmit Error bit BER[28~ is set when a device detects a deasser-
ted state on the NO ARB, BSY, or CNF lines at a time when the
device is attempting to assert these lines. Finally, the Master
Transmit Check Error bit BER[29~ is set when the data that the
Master is attempting to assert on the Data, In~ormation or Parity
lines fails to match the data actually present on these lines.


2~

~49-
However, the assertion of the Master ID during an Imbedded
~rbitration is not checked.
Turning now to Fig. 7E, the structure of the Error
Interrupt Control Register 206 is shown in detail. When a bit is
set in the Bus Error Register, and the appropriate Error Interrupt
Enable bit is set in the Control and Status Register, or when the
force bit is set in the Error Interrupt Control Register, an Error
Interrupt will occur. Bits EICR~13 21 contain the Error Interrupt
Vector. If the Force bit EICR[20] is set, the interconnecting
means will generate an Error Interrupt -transaction at the levels
specified by bi-ts EICRrl9:16]. The Sent bit EICR[21] is set after
an Error Interrupt has been transmitted. When set, it prevents
the generation of ~urther interrupts by this register. This bit
is reset on losing an Interrupt Arbitration for the Error Inter-
rupt. The Interrupt Complete Bit EICR[23] is set on successful
transmission of the Error Interrupt Vector.
The Interrupt Abort bit EICRE243 is set if an Error
Interrupt transaction is no-t successful.
Turning now to Fig. 7F, the Interrupt Des-tination Regis-
ter 210 contains an interrupt des-tination field IDR[15:0] which
identifies which devices are to be selected by interrupt commands
originated by this device, as previously described.
The Interprocessor Interrupt Mask Regis-ter 212 is shown
in Fig. 7G. This register contains a Mask Field II~R[31:16] which
identifies devices fro~ which interprocessOr interrupts will be
accepted. Similarly, the interprocessor interrupt destination

3~9~L

-5~-
register ~14 contains a destination field IIDR~15:0] which iden-
tifies devices to which interprocessor interrupt commands are to be
directed. Finally, the Intexprocessor Interrupt Source Register
216 contains a source identification field IISR[31:16], which
stores the decoded ID of a device sending an interprocessor inter-
rupt command to this device provided the ID of the sending device
matches a bit in the Interprocessor Interrupt Mask Register of
this device.
2 Further S~ecific Descri~tion of the Retr~ Mechanlsm

The Re-try response described above increases system per-
formance by allowing devices to cause termination of operations
which might otherwise require excessive time to comple-te on "inter-
locked type" communications paths. In an "interlocked type" path,
once control is granted to perform a transaction, the transaction
must contlnue to completion. In addition, it increases system
flexibility in providing a means of adapting to other buses or dual
port memories. Some situations in which the capabilities provided
by this transaction are especially useful are shown in FigsO 8A
through 8D.
In Fig. 8A, a device 300 has a Command Decode unit 302,
an Interlock.Bit Reglster 30~ and an AND gate 306. The Command
Decode unit 302 produces an output to gate.306 whenever an INTER-
LOCK READ command is received by the device. The INTERLOCK READ
command also sets register 304. The register is cleared by a sub-
sequent Unlock command, such as UNLOCK WRITE. For purposes of
illustration only, the register shown is "set" only after

~ 3~

-SOa-
completion of a success~ul Interlock Read transaction.
When a second INTERLOCK command is received prior to an
UNLOCK WRITE to the device, register 304




:


.

~;~;3~


51

is set and AND gate 306 is thereby enabled. The
outp~t of Command decode unit 302 is then applied to
gate 306 to cause this gate to generate an output
which may then serve as a RETRY responseD This
- 5 response is returned to the Current Master as part of
the Command Confirmation, as previously described.
The Master then terminates the transaction in a manner
similar to receiving a NO ACK response, and may seek
to RETRY the transaction at a subsequent time or may
take other action as appropriate.
An example of the ~se of the RETRY response in
place of the STALL response is illustrated in Fig.
8B, which shows a device 310 having a counter 312 and
a limit setting unit 314. The counter 312 counts the
number of times the STALL response is asserted by the
device. When this number exceeds a predefined li~it
set in the unit 314, the latter provides an output
which serves as a RE~RY response. This response is
transmitted to the Master to cause termination of the
transaction with respect to which the device 310 is
communicating with the Master. The use of the RETRY
as illustrated in Fig. 8B is appropriate when it is
possible that the device might be able to perform the
operation requested by the transaction, provided that
the transaction is extended by a limited number of
cycles. Placing an upper limit on the number of
possible STALL assertions allows the device to attempt
to respond within a certain time but prevents it from
holding the communications path beyond this time.
This "frees up" the communications path and allows
transactions generated by other devices to proceed.
The device may then complete the transaction with a
lower number of STALLS on a further access attempt by
the Master.

3L~3;2~
.~
52

Dual port memories are often used to enhance
system performance in multiprocessor systems. Such
systems allow access to the memory from either of two
ports. Under certain circumstances, this may cause
problems, unless appropriate precautions are taken.
For example, where a sequence of transactions may be
expected to change stored data at some time after the
first transaction occurs but before the last
transaction is completed, it is necessary to restrict
access to the data by other devices until the change
can be accomplished. This is the case, for example,
read-modify-write operations use a sequence of
transactions to perform the desired operation. The
RETRY response is particularly useful in this
situation. Thus, in Fig. 8C, a dual port memory 330
has a first access port 332 and a second access port
334. A Port Access Register 336 has a first register
section 336a which records current utilization of the
memory through port 332, and a second register section
336b which records current utilization of the memory
through port 334. A first AND gate 338 is enabled by
register section336b. Gate 338 receives a second
input from port 332 whenever this port is accessed by
a device for a transaction. Similarly, a second AND
gate 340 is enabled by register 336a, and receives an
input from port 334 when the later is accessed. The
output of gates 338 and 340 is applied to an OR Gate
342.
When port 332 is accessed by a device seeking to
perform an interlock type transaction such as an
Interlock Read, register 336a records that fact, e.g.,
by setting a status bit; this enables AND gate 340.
I~ port 334 is now accessed, gate 340 generates an
output which serves as a Retry response to the device

~L~3~69~

.
53

seeking access to the memory 330 via port 334. The
device seeking access then terminates its transaction
as previously described. A similar result is obtained
when port 334 is accessed by a device seeking to
perform an Interlock-type sequence and port 332 is
thereafter accessed while the interlock condition is
still in effect.
The increasing need for communication between
devices has greatly multiplied the need for
interconnecting the differing "interlocked"
communication paths used by such devices. Such paths
are typically controlled from independent control
sources imposing differing constraints on the paths.
When interconnected, it is possible that each path may
seek access to the other path at the same time but for
wholly different operations. When this occurs, both
paths may "hang up", with consequent adverse
consequences for communications efficiency. The Retry
response procedure of the present invention provides
an extremely simple and thus efficient mechanism for
resolving the dispute among the contending
communications paths.
Thus, as illustrated in Fig. 8D, a communications
path 78 of the present invention is connected ~o a
separate communications path 340 via an interface 342.
Interface 342 includes a controller 344 which monitors
one or more signal lines on each path to determine -
when that path is being used. For example, the
controller 344 monitors for selection as Slave on
communications path 78 to determine whether that path
is currently being accessed by path 340 for a
transaction. Simi~arly, the controller monitors the
appropriate one or more si~nals on path 340 for the
same purpose. On detecting coincident requests for

~;26~3~

54

connection to the other path, the controller 344
generates a RETRY command which is returned on the
communications path 7~ during the command confirmation
response cycle of the transaction seeking control of
the path 340. This signals the device seeking control
of path 340 that the latter path is currently occupied
and thus appropriate action may be taken.
Conclusion
The RETRY mechanism described herein provides an
efficient means of releasing the communications path
when a device engaging in a transaction is unable to
complete the transaction without requiring an
excessive delay. This may arise from a need for a
long access time by the responding device or may arise
from other factors, e.g., the need to insure that a
certain operation (e.g, a read-modify-write operation)
requiring a sequence of transactions is completed
before other transactions should be allowed. Further,
the RETRY mechanism is useful in helping to
limit the extent to which a transaction may be
extended by other responses. Finally, it is
particularly useful in facilitating transactions
between "interlocked" types of communications paths.