Note: Descriptions are shown in the official language in which they were submitted.
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QUEUED ACCESS OF COMMON COMMUNICATIONS
LINK WITH EXPANDED ADDRESSING AND
ERROR CHECKING PROTOCOL
Background of the 'Invention
This invention relates in general to the art of
communicating a plurality of devices with one another over
a single communications link. More specifically, the
invention relates to arrangements permitting communications
link access to devices competing against one another for
that assess.
There has been developed a system for remotely
controlling electrical loads distributed over a wide area
(such as a large office building or factory) from a micro-
processor based central controller. That system is disclose din US. Patent 4,367,414, issued January 4, 1983 to Miller
et at. In the Miller '414 system, control instructions
are issued by the central controller 50 and are transmitted
to various transceiver-decoders 56 via a twisted pair cable
58 constituting a bidirectional communications channel.
A particular transceiver-decoder that is "addressed"
carries out the command by actuating one or more particular
relays to make or break an electrical connection as desired.
The central controller issues its control instructions in
accordance with a predetermined schedule, in response to a
measured parameter (such as light level or temperature) or
in response to a user switch actuation sensed by a switch
processor in the transceiver-decoder and transmitted to
the central controller over the bidirectional communications
US link, or in response to a user command telephonically
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transmitted to the central controller.
The transceiver-decoder is configured in a
modular fashion. Separate switch and relay "modules" are
provided to allow a user of the product to configure a
remote control panel to meet his specific application
needs. This modular construction is field adaptable
allowing an electrician who has no electronic expertise
to easily install, replace and service the panels. To
do this, small modules are developed so that they can be
easily handled and configured in the field.
The preferred embodiments of the present
invention are improvements on the system described in
the aforementioned Miller US. Patent 4,367,414. There
is a need to more fairly and equitably distribute the
access of a common communications link (such as data
line 58 in the aforementioned Miller US. Patent 4,367,414)
among devices of different priority and/or condition.
Specifically, this need exists where communication is
held between remotely located transceiver devices and
a central control facility. Devices can conic for the
use of a communication link data line by simultaneously
accessing when a message is to be sent. A collision
avoidance, listen-while-talk, bus arbitration scheme
is employed which has been described in aforementioned
US. Patent 4,367,414. An improvement was made to that bus
arbitration scheme to allow devices within a given priority
level to have a still further higher priority on accessing
the bus when they have backed off due to bus arbitration
to access the bus ahead of first time users. This will
effectively allow devices waiting to send a message who
have made at least one attempt to have a temporary higher
priority than devices attempting to transmit for the
first time. This, therefore, will distribute in a more
fair and equitable manner the waiting time for bus access
and reduce the propensity for device lock-out needed
particularly in areas of high data communications
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traffic.
There is provided an improved error checking
scheme over that described in the aforementioned Miller
US. Patent 4,367,414. This improved error checking
scheme is used to detect errors that may cause the
entire transmission to be received as a fixed homogeneous
packet; that is, all data bits including the error check
word are either Logic 1 or Logic 0. Since it is possible,
particularly in carrier communication schemes, for cyclic
noise to cause the reading of a homogeneous message an
extra safeguard must be employed to eliminate the
possibility of a correct message having all data and
error bits in the same logic state.
There is also provided the ability to address
all communicating points distributed on a common
communications link with one command thereby reducing
the traffic on broadcast messages - such messages may
include reset commands, time of day, or requests for
status and eliminate the need for long polling techniques
that tie up the bus. Additionally, there is a need to
provide messages of varying data length accommodating
many different applications which is a further improvement
over the communications subsystem described in the alone-
mentioned Miller US. Patent 4,367,414.
Summary of the Invention
This invention provides an arrangement
(including apparatus and method) for accessing a common
data communications link, typically a bus topology
connecting a multiplicity of communicating devices.
This link is of bidirectional nature and requires
random access to send information on a randomly initiated
event. This protocol or process is an improvement on
and is distinguishable over the access protocol described
in aforementioned US. Patent 4,367,414. A multiple
level of bus access is provided to distribute the use
of the bus among contending devices. Additionally, an
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improvement is made in the data format and error
checking protocol of aforementioned Miller US. Patent
4,367,414 to insure the avoidance of homogeneous
messages and the addressing of all points on a link with
a single command.
An object of the present invention is to provide
a multi-level deterministic priority bus access protocol
such that each of a plurality of communication points has
a predetermined priority classification and a rank within
the priority classification determined by its having made
at least one previous unsuccessful attempt at accessing
the link
A further object of the present invention is
to provide an error check protocol such that a bit
homogeneous transmitted message is avoided and increases
the system's ability to detect cyclic errors that may
force a particular logic level condition.
Another object of the invention is to provide
a universal addressing scheme such that devices of particular
families can be accessed through one single command.
Another object of the invention is to provide
variable data length message or packets where the packet
size is delineated by the timing of an inter-block gap.
Remotely located transceiver panels randomly
access the communications link, which in the presently
preferred embodiment is a single twisted pair bus, upon
a randomly initiated input or response to a command. The
transceiver devices are classified as low priority devices
while the central controller is given high priority. As
already described in the aforementioned Miller US.
Patent No. 4,367,414, a high priority classified device
will gain access of the bus over a low priority device
when they are simultaneously contending for it.
The levels of bus access are provided by a
timing relationship referenced to the end of the last
transmitted message. High priority devices are allowed
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to start transmissions before low priority devices giving
them the higher priority. In the present invention,
within the high priority time interval is still higher
priority shorter interval is provided to allow high
priority devices that have been queued after being forced
off an arbitrated transmission to have higher access
priority than high priority devices attempting to transmit
their message for the first time. A queued device is
defined as one which previously attempted to transmit a
message and was Betsy arbitrated using the process
depicted in the aforementioned Miller US. Patent 4,367,414
thereby forced to back off the wait for the next line-free
condition. In other words, within a priority classification,
a device that has been queued will have a shorter line-free
timing threshold allowing it to attempt access ahead of
first time non-queued communicating points. Similarly,
this queued access timing protocol is also defined for
lower priority devices such that a queued lower priority
device will have a higher access priority than first time
lower priority communicating points. It should be noted
that at no time will low priority devices have a higher
priority than high priority devices whether they are
queued or unyoked. Furthermore, this queued higher
priority access level of transmission is only a temporary
condition and is removed upon the successful completion
of the pending message.
A fifth level of bus access protocol has been
added which can be used by non-important messages in
either of the high or low priority classes. This fifth
level which is the lowest priority is called the
Deferred Process Level. This is where messages of non-
important nature can be queued to wait for low bus activity.
This will insure that the more important control information
be transmitted ahead of any non-important status type or
confirmation messages.
A provision for eliminating bus lockout for
use in high traffic situations was made such that all
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devices whether they are classified as high or low
priority will fall back to the deferred level of access
after completing a successful transmission. This will
insure that the high traffic bus is equitably distributed
among the communicating points such that no point can
access after the completion of one message. This will
allow all devices during high traffic periods to have a
chance to transmit their message. The maximum timing is
thereby dependent on the maximum number of communicating
points on the link. It should be noted that depending on
the importance of the message in the particular application,
not all devices, even after a successful transmission,
will be forced to fall back to deferred access. However,
the provision has been made to allow a high traffic bus
the ability to insure that at least all communicating
points, no matter what level of priority, have an
eventual change to transmit a pending message thereby
eliminating absolute bus lock-out. It should be further
noted that this worst case scenario would only arise
as the bus reaches 100% utilization.
An improvement is made to the error check
protocol of the aforementioned Miller US. Patent 4,367,414
utilizing a so complement 8 bit muddle checksum word.
This checksum word is appended to all the data packets in
a transmitted message. In order to guard against home-
generous data packets causing a homogeneous checksum, the
checksum register is initialized to the value of 128. This
insures that the entire packet transmitted will always
have a non-homogeneous bit quantity such that there some
combination of Logic 1 and O's. The avoidance of
homogeneous messages is particularly important when applied
to carrier communications systems such as used on purloin
or through the airway where cyclic noise or a continuous
noise source may force the entire transmitted message to
be received as all bits having the same logic value.
Therefore, to avoid this possibility an initialization
of the checksum register at the beginning of the checksum
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process to a value of 128 has been added over the prior
art. Since the maximum byte length of a transmitted
message is less than 128, it is therefore impossible for
a homogeneous message to be transmitted.
A universal and family universal broadcast
addressing scheme is included. This allows a reserved
address number to be defined so that broadcast commands
such as system resets, or status check can be transmitted
with a single message to all receiving devices. This
reduces communication traffic and increases system
throughout.
Messages themselves are of variable length
which is a modification of the fixed 40 bit package
used in the aforementioned Miller US. 4,367,414
arrangement. Due to this variable message length, there's
a need to detect the end of a data packet in a transmission
stream. Data packets, as previously disclosed, are
separate by inter black gaps. However, a threshold of
the time between packets has the time to process received
messages and ready themselves for the next data packet.
This threshold is determined during the intermit intervals
in the preamble sequence.
Brief Description of the Drawings
FIGURE 1 is a graphical representation of a
typical signal on the common data line for communicating
information between the central controller and a
transceiver-decoder;
FIGURE 2 is a timing diagram illustrating
typical message timing including the definition of line
free intervals;
FIGURE 3 is a diagram illustrating message
packet data format, also known as "new" format; and
FIGURES 4-27 are flow charts explaining in detail
system operation.
Detailed Description of the Preferred Embodiments
it
The invention is generally applicable to the
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type of system typified by the aforementioned Miller
use Patent 4,367,414 and particularly illustrated by
Figure 1 of that patent. The principles of the present
invention have application to many types of communication
systems and are not limited to systems such as shown in
the aforementioned Miller US. Patent 4,367,414 even though
such systems represent the presently preferred embodiment.
Transceiver decoders are classified as low priority devices
while the central controller is given a high priority. As
described in the aforementioned Miller US. Patent 4,367,414,
a high priority classified device will gain access of the
bus over a low priority device.
The levels of bus access are provided by a
timing relationship referenced to the end of the last
transmitted message. High priority devices are allowed
to start transmitting before low priority devices thereby
giving them higher priority. The timing relationships
are shown in the following chart:
LINE FREE BUS ACCESS PROTOCOL
0 (earliest time) end of last transmission
elf minimum time for line free reset all
receivers, no bus access allowed
tLFQH Access of high priority Quad devices
allowed
25 tLFH Access of non-queued high priority devices
allowed
tLFQL Access of non-queued low priority
devices allowed
tLFL Access of non-queued low priority
devices allowed
tdef(latest tire) Access of deferred messages allowed
The above time periods are the minimum access
periods of free link (high impedance or active state of
the line) referenced from the end of the last message
and are ordered chronologically.
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Message Format
The ENS Communications Message format is shown
in the following charts. Note the fax fob format bits
specify the type of message or packet structure or format.
There are thee types of message formats that are supported.
These are: "old", "new", and "extended". The "old" format
is described in the aforementioned Miller US. Patent
4,367,414. The "new" and "extended" formats are described
below:
10 (1) f5 f4 f3 2 if 0 fax fob
(2) A A A A A A Al A
(3) Aye Alp Aye Alp Allah 9 A
(4) Do Do Do Do Do Do Do Do
.
(5) C7 C6 C5 C4 C3 C2 Of C0
where fax fob = 1, 0, respectively (new format)
Key
Chart line 1: fax and fob are message format
bits and fife are the function bits of the function
word; the above format is for fax fob = 1, 0.
Note: The format bits fax fob determine the format
of the message.
Chart lines 2-3: address word Aye
Chart line 4: data words, variable
length bytes (0-4 bytes)
Chart line 5: checksum word-modified
2's complement format
32 bit min., 64 bit Max packet size
- Each word is 8 bits, 1 Byte
- Each word has a fixed number of bits
The packet size is determined by the
function word.
- Need for packet synchronization to insure
the function word is always read.
The EMS Communications Message Format in
expanded Norm is shown in the following chart:
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Al) f5 f4 3 f2 l 0 fax fob
(2) fly fly fit fly f9 f8 f7 f6
(3) A A A A A A Al A
(4) Alp Alp Alp Alp All Aye 9 A
(5) A A A A A A Al A
(6) Aye Aye Aye Aye All 10 9 A
.
(7) C7 C6 C5 C4 C3 C2 Of C0
(8) 15 C14 C13 C12 Oil C10Cg C8
where fax fob = 1, l indicates extended format.
lines 1-2 : fax fob message format bits and
function word f0-f13
lines 3-4 : destination address
lines 5-6 : source address
between lines 6 and 8: data field 0 to 8 bytes
lines 7-8 : error check word
64 bit mint 128 bit Max
The message format and protocol are shown
in Figure 1.
In Figure 1, the various data line states and
data are represented as timing relationships of electrical
signals similar to that disclosed in the aforementioned
Miller US. Patent 4,367,414.
T50=50~ Pulse width used for logic threshold
To = Logic 0 pulse = .33 (2T50), maximum
To = Logic 1 pulse = .66 (2T50), minimum
Go ILL unit = Initial interlock gap
IBM = Regular interlock gap = 3 (2T50) = 6 T50,
typical
IBITG = Inter-bit-gap interval = 200 use
minimum, fixed
.IBITG - In~er-Bit-Gap is constant and is
NOT USED in determining the logic level but is used in
determining an IBM
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The IBITG is the "don't care" state of
the transmission must be less than IBM
. The DATA & Clock are transmitted in the state
electrical states
. IBGinit is long enough to get the attention
of the Recovers
. sup Masters & Slaves differences
- Defines priority of access on conflict
- Bus Masters are allowed to transfer
lo control of the BUS
Differences:
IBGinit - Masters have longer one, omit
Line Free - Masters have short one
Common Data Line Communication Format
The data communication format utilized by an
enhanced transceiver (enhanced with respect to the
transceiver/decoder disclosed in the aforementioned Miller
US. Patent 4,367,414) is a modification of the original
format disclosed in the aforementioned Miller US.
20 Patent 4,367,414. The modifications fall into two
categories: those that reflect changes in the timing
characteristics of messages on the data line (which, for
the most part, are simply more formalized definitions of
the timing characteristics); and those concerning modifica-
lions to the format of the data transmitted over the common
data line (which are modifications allowing greater
flexibility).
A message transmitted over the common data line
consists of the following: a period of inactivity on
the data line (which corresponds to a high impedance or 24
volt condition) also known as the line free interval; a
period of time in which the time is accessed by the device
desiring to transmit the message (a low impedance or 0
volt condition) known as an initial IBM or talc; five or
more preamble bits which define the bit rate and subsequent
timing characteristics of the message; a regular IBM
(interlock gap;) one or more block of data (separate by
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a regular IBM if more than one block is sent); and a final
IBM which is followed by a line free interval signaling
the end of the transmission.
Referring now to Figure 2 there is shown a timing
5 diagram showing typical message timing.
The following table summarizes the meaning of
the numbered portions of FIGURE 1.
(1) Line is tree (7) Data block (4 to 8 bytes)
(2) Line is accessed, initial IBM (8) IBM (IbG<2*Ibit)
(3) Preamble bits (min. 5, typically 7) (9) Data bit = 1 (T50~ 2*T50)
(4) Ibit-Inter-bit gap (timed) (10) Data bit = 0 ("ought)
(5) T50 bit (timed) (11) Final Is (IsG~2*Ibit)
(6) Regular Is (interlock gap) (12) Line is free (LFR>2*T50)
(1) indicates the line free interval for the enhanced
transceiver. Three line free intervals have been defined
(plus the shortest possible line free interval which would
be used in the interactive or bus transfer mode of
communication). A normal line free interval for the
transceiver is defined to be 15 milliseconds. This line
free interval would be utilized in a transmission of
switching actuation messages. A collision line free has
been defined to be 12 milliseconds. This line free
interval would be used in all subsequent attempts to
transmit a message that has been collided with on the
initial attempt. The deferred line free interval, 20
milliseconds in duration, can be used in response to a
request for data from a controlling device. Finally,
there is an access time defined for use in an interactive
transfer of control of the data line. This period of
time should be as short as possible but never exceeding
the interval of time corresponding to a line free
detection of the device which is to receive the message.
In the enhanced transceiver, this time is on the order of
a few lows of microseconds. It should be noted that the
different lengths of access time define relative priorities
of messages. The immediate or interactive mode line free
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would be the highest possible priority message. This
guarantees that a transceiver responding to an interactive
request for data will access the data line before any
other transceivers or devices. The collision line free
is the next highest priority message. Any message with
collision line free access protocol will be transmitted
before those with normal or deferred access. The normal
line free protocol which is only used for random type
transmission from the transceiver will guarantee trays-
lo mission before those messages with deferred access time sand will wait for transmission allowing collision and
interactive line free protocol messages to transmit first.
The deferred line free access protocol is the lowest
priority. This protocol is used in response to requests
for data in the deferred mode. It should be noted that as
embodied in the enhanced transceiver a deferred transmission
will always be sent with deferred line access and never
switch to the higher priority collision line free access.
Following the line free an initial IBM also
known as the talc is transmitted by the device desiring
access the data line (2). An interval of 6 milliseconds
has been chosen for the access time in the enhanced TRY.
This falls in the window of times allowed for a low
priority (slave) device. Since the higher priority t c
is of greater duration, it is possible for a Master device
to override a slave by using the longer talc in
conjunction with the slave's collision detection.
Following this at (3) is a transmission of the
preamble bits which are used to define the timing
characteristics for the remainder of the transmission.
In the enhanced transceiver 7 preamble bits are transmitted
and a minimum of 5 must be received in order to calculate
the thresholds. The preamble consists of alternating
intervals of T50 and Ibis intervals corresponding to the
high and low impedance respectively. The bit rate for the
enhanced transceiver has been selected to be 2,000 bits
per second. This corresponds to a T50 and Ibis time of
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250 microseconds each for an entire period of 500 micro-
seconds. Once the thresholds for the receiving device
have been established for the T50 and Ibis all further
timing relationships have been established (a detection
of an IBM is defined to be a low impedance condition
whose duration is greater than 2 times Ibis; a line free
detection is defined to be 2 times T50). (4) indicates
the Ibis while (5) indicates the T50 interval.
Following the preamble bits a regular IBM
(interlock gap) is sent as indicated by (6). This
delineates the end of the preamble and the beginning
of the data block. A regular Is will be used to separate
multiple blocks of data, if required. For the enhanced
transceiver, the regular IBM is defined to be 2.5 Millie
seconds. There are no messages transmitted by the enhanced transceiver that would require more than one block of
data.
After the preamble, which is sent only once
per transmission, follows one or more blocks of data
as indicated in (7). For the enhanced transceiver, a
block of data can vary from length from 4 to 8 bytes.
This block of data is sent in a Betsy serial fashion
beginning with the least significant bit of each byte
to be sent. Each bit is separated as indicated in (8)
by an Ibis. A data bit 1 is illustrated at (9) while
a data bit 0 is indicated at (10). For the enhanced
transceiver, a data bit 0 corresponds to one-third the
total bit period of T50 and Ibis; while a data bit 1
corresponds to two-thirds of that interval. Both of these
times meet the assumptions that a data bit 1 must be
less than 2 times T50 but greater than T50 and a data bit
0 must be less than T50.
At (11) a final IBM is transmitted completing
the message. For the enhanced transceiver a final IBM
of 2.5 milliseconds is used. At the end of the final IBM
the line goes high as indicated by (12). Any device
receiving a message will detect the line high condition
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-- 15 -- LD--09145
receiving a message will detect the line high condition
as a line free after an interval of 2 times T50 has
expired. The detection of a line free indicates to
receiving devices that the line is no longer in use and
5 that the thresholds calculated from the preamble are to be
disregarded in any subsequent accesses of the data line.
It should be noted that the interval of time needed to
detect the line free is subtracted from the line free time
needed for transmission of a message for the enhanced
transceiver.
The message format (sometimes referred to
herein as the "old" format) utilized by the original
transceiver/detector in the aforementioned Miller US.
Patent 4,367,414) is illustrated in Figure 6 of that
15 patent. A message in the old format consists of 5 bytes
of information as indicated. These are, in the order of
transmission: the function word, address word, data
field O (or the auxiliary flag word), data field 1 and a
nibble parity word. In order to allow for the expansion
of the data formats and to provide the two data formats
recognized by the enhanced transceiver (hereinafter
referred to as old or new format), the function word was
modified slightly from that used in the aforementioned
Miller US. Patent 4,367,414. Address bit A is no longer
25 allowed and must be equal to O at all times. This
restricts the range of possible addresses in the revised
old format to 512 . The least significant bit of the
function word continues to correspond to address bit A.
The remaining 6 bits, FOX to F5, indicate the desired
function for the message. This allows for a maximum of
64 different functions in the old format. However, in
the enhanced transceiver only 4 of the old format commands
are recognized. These commands are: Ouch, old type set
relay states for entire bank; SHEA, old type mode 4
(auxiliary command in data field 0); OATH, old type relay
state; and OOZE, old type switch leg actuation message.
. ",
1;;~33~3
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These 4 commands are a subset of the 8 function words
provided in the original TRY. However, they provide access
to all necessary commands in order to Support the relay
and switch TRY.
Following the function word, the address word
is transmitted. This word consists of the 8 least
significant bits of the address, A to A, and is
transmitted least significant bit first (A). Following
this data field 0, data field 1 and finally the parity
word.
Data field 0 can be used as an auxiliary
function word in the old type mode 4 (mode 4 of the
aforementioned US. Patent 4,367,414). When used as an
auxiliary function or flag word, data field 0 is
considered as two nibbles. The least significant nibble
contains 4 bits representing the auxiliary function, while
the most significant nibble contains the complementary
redundancy bits for use in error checking of the other
nibble. Referring to the least significant bits only, the
following auxiliary functions are provided: 0, individual
relay OFF (the relay number 1 to 16 is contained in data
field l); 1, individual relay OFF; 4 and 9, return the
relay states (two commands were originally provided in
order to have one that would not clear out switch legs and
another which would. Since the switching transceiver is
now a separate product, both of these functions can be
combined as one and operated upon identically).
Data field 1 would contain additional relay
data or switch leg data as needed. The parity word
contains an 8 bit even nibble parity bit generated from
the 4 previous words of information. Parity bit Pi would
correspond to the least significant nibble of the
function word, parity bit Pi would correspond to the
most significant nibble of the function word, and so on,
as indicated on Figure 6 of the aforementioned Miller
US. Patent 4,367,414. If there are an even number of
l's in the nibble, then the parity bit will be set to a
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value of 0. Therefore, the parity of the nibble and
parity bit taken together is said to be even.
As mentioned above, the least 2 significant
bits of the function words used by the aforementioned
Miller US. Patent 4,367,414 transceiver/decoder have
been modified to take on new meanings and allow the
expansion of the communication format. These 2 bits,
which have been redefined as fax fob, when set to a value
of 1, 0 and 1, 1 indicate a new or extended format
message. (In the modified old (the aforementioned Miller
US. Patent 4,367,414) format message, the fax bit would
be set to 0 and the fob bit would be utilized as address
bit A). The new (this application) format for messages
can be more efficient and versatile, and involves
slightly more complex procedures. The chief advantages
of the new format are: the expanded addressing range,
the different modes of addressing, the variable number
of data fields which can be utilized (ranging from no data
fields to 4), and a modified checksum word (which, for 8
bit microprocessors, is easier to generate than the nibble
parity).
Referring to Figure 3, there is shown a diagram
of the message packet data format (new format improved over
the aforementioned Miller US. Patent 4,367,414) . In
FIGURE 3, where:
. Checksum word = us complement of the sum
(80H + function high ADD + low ADD +
(all present data fields)).
. U = 0, normal addressing Aye
. U = 1, universal addressing
If A -A all "1" then master
universal address (family = A to Aye)
. Least significant bits are sent first
starting with bit "0".
` 35 The function word is transmitted first (least significant
bit first), followed by the high address word, low address
. ,
.. . .
1233~3
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word, any data fields that are present beginning with data
field 0 (if present) and extending to data field 3 (if
present) and completing with the modified checksum word.
The functions supported in the new format are
as follows: function #0, flag word equals to 002H, new
type reset command; function #1, function word 006H, new
type read data with immediate response; function #2,
function word equal to NOAH, new type read data with
deferred response; function I OWE, new type set relay
states for entire bank; function #4, 012H, new type set
individual relay state (DFl contains the number in
DB3-DB0, Ds7 if 1 means ON); function #5, 016H , new type
set switch leg mask; function #6, OH, new type system
status power-up for a relay transceiver; function #7,
022H, new type receiver thresholds for relay; function I
026H, new type data line counters relay; function #9, AYE,
new type TOM code version for relay function #10, EYE,
new type relay states; function #11, 032, new type switch-
in mask; function #12, 036H, new type read actual switch
20 contacts; function #13, EYE, new type switch accumulated
buffer; function #14, 042H, new type switch transmission
for secured switches; function #15, 046H, new type switch
transmission for normal switches; function #16, AYE,
new type acknowledgement of secured switch legs; function
25 #17, EYE, new type system status power-up for a switch leg
transceiver; function #18, 052H, new type receiver threshold
for switch leg transceiver; function #19, AYE, new type
data line counters for switch leg; function #20, EYE,
new type ROM code version for switch leg; and, finally,
function #21, 062H, new type relay state on over current
detection. A more complete description of the new format
functions and auxiliary functions can be found in -tabular
form in the "Documentation for Flag Field".
The high address word which follows the function
35 word in the transmission of a message contains the 7 most
significant address bits followed by the U bit in the most
significant position. The U bit is used to indicate the
~3;~2~i3
- 19 - LD-09145
addressing mode of the function. When U is equal to 0
then normal addressing is being used in the range of A to
Aye (as embodied in the enhanced transceiver only 9 of the
possible 15 address bits are used. The remaining bits are
set to 0). When the U bit is equal to 1, then universal
addressing is being utilized. There are two possible
universal addresses. The first, when all of the address
is being utilized and all products will react to the
command accordingly. Otherwise, when all of the bits A
to Aye are not 1, then a family universal address is being
utilized (the family number is contained in A to Aye).
For the enhanced transceiver, three family addresses are
recognized. Family 0 is all relay transceivers; family 1
is all switch leg transceivers; and family 2 is all pulse
output transceivers.
The next byte sent of the new format message
is the low address word containing A to A. Following
this, any required data field from none to four are sent
beginning with data field 0 and continuing through a maximum
of data field 3. Data field 0 can be used as an auxiliary
function command for the Read functions number 1 and
number 2. The auxiliary commands supported are as follows
(out of 256 possibilities): 0, return the system status;
1, return the receiver threshold; 2, return the data line
counters; 3, return the ROM code version; 4, return the
relay state; 5, return the switch leg mask; 6, return the
actual switch contact closures; and, finally, 7, return
the accumulated switch buffer.
The final byte transmitted of the new format
messages is the modified checksum word. This word is the
8 bit 2's complement of the sum 80 hexadecimal plus the
value of all preceding words (80H plus function plus high
ADD plus low ADD plus (all present data fields)).
The revised data format for the enhanced
transceiver provides numerous advantages. To begin with,
the means of communicating have been expanded in an way
1;~332t~3
- 20 - LD-09145
that retains the original old format method while expanding
to allow greater versatility. The new form messages are
more efficient since only the amount of data necessary is
transmitted with the message. In addition, chanced
addressing has been provided allowing three modes; normal
addressing, a master universal address and a family
universal address. The revised function format allows for
64 new format commands as well as 64 possible commands
in the old format. Also an additional extended mode of
communication is provided for when the fax fob wits are
equal to 1, 1.
Transceiver/Decoder Specifications
The following is a tabulation of the transmitter
specifications for the transceiver/decoder used in this
invention
_
VALUE MIX MIX TYPO COMMENTS
Taccl ems 13ms ems length of initial line low for low priority
______________________________________________________________________________
Teach 15ms 25ms 20ms length of initial line low for high priority
______________________________________________________________________________
Tlfhc ems 8.5ms line free for high priority after contention
______________________________________________________________________________
Tlfh ems 11.5ms line free before access for high priority
______________________________________________________________________________
Tlflc 12ms 14.5ms line free for low priority after contention
______________________________________________________________________________
Till 15ms line free before access for low priority
______________________________________________________________________________
Maxtl 400ms Max line use time for low priority device
______________________________________________________________________________
Math 1000ms Max line use time for high priority device
______________________________________________________________________________
Told 1000ms 50ms Max time to hold bus for high priority only
______________________________________________________________________________
Tbusf 1.5s mix time before line clear (fuse blow)
______________________________________________________________________________
Speed 300bps 2700bps 2000bps baud rate
____________________________________________________________________________
T50 .18ms 16.6ms time of preamble for threshold
______________________________________________________________________________
IBIS* .19ms ohms ems length of inter-bit gap (must be constant)
______________________________________________________________________________
IBM** elms 49ms 2.5ms length of inter-block gap
______________________________________________________________________________
Tweaks ohms Max time for access in interactive mode
______________________________________________________________________________
*note: IBIS must remain constant within a transmission
**note: IBM transmitted should be greater than 3 IBITG but no less than 2.1ms
. i
`:
~L2~3;~63
-- 21 -- LD--09145
Flag yield
The following chart documents in detail the
flag field:
FLAG BITS:NUMB:HEX COMMENTS
___ _ ____ _ _ _ _____ _ _ _ __,_________ ___ ____ _ _
0000 0010 #0 002H NEW TYPE RESET COMMAND
__ _ _ ___________________ __ _ ___
0000 0110 #1 000H NEW TYPE READ DATA WITH IMMEDIATE RESPONSE
__ _ _ __~___ __ _ _
0000 1010 #2 AYE NEW TYPE READ DATA WITH DEFERRED RESPONSE
__ _ I_ _____ __ _ _
0000 1110 #3 EYE NEW TYPE SET RELAY STATES FOR ENTIRE BANK
______ _ _ ___________ _ _ _
0001 0010 #4 012H NEW TYPE SET INDIVIDUAL RELAY STATE
___ __ _ ___________ __ _ ____
0001 0110 #5 016H NEW TYPE SET SWITCH LEG MASK
_____ __
0001 1010 #6 AYE NEW TYPE SYSTEM STATUS/POWER UP FOR AL
__ _ __ ____ ____ _ _ __
0001 110X #0 SHEA OLD TYPE SET RELAY STATES FOR ENTIRE BANK
__ __ _____________ __ ____
0010 0010 #7 022H NEW TYPE RECEIVER THRESHOLDS FOR AL
___~,___ __ _ _ _________ _ _ _
0010 0110 #8 020H NEW TYPE DATELINE COUNTERS FOR AL
__ _ _ ___~_ _ _ ___
0010 1010 #9 AYE NEW TYPE ROM CODE VERSION FOR AL
_____ __ _ _____ _ I_
0010 1110 #10 EYE NEW TYPE RELAY STATE
__ __ _ __ __________ _ _ ___
0011 0010 #11 032H NEW TYPE SWITCH LEG MASK
I_ ___ ___ I___. ____~___ _ __ _
0011 0110 #12 030H NEW TYPE SWITCH CONTACTS ACTUAL
______ __ ___ _ ______________________ _ ___ ____
0011 100X #1 038H OLD TYPE FIRST OMIT (NOT SUPPORTED)
____ _ _ ___________________ _ __ __
0011 1110 #13 EYE NEW TYPE SWITCH ACCUMULATED BUFFER
______ _ ___ ____________________ _ __ __
0100 0010 #14 042H NEW TYPE SWITCH OMIT FOR SECURE SWITCHES
_____ __ _ _____________________________ _ _ __
0100 0110 #15 046H NEW TYPE SWITCH OMIT FOR NORMAL SWITCHES
______ __ __ _________ ______________ __ ___ ___
0100 1010 #16 AYE NEW TYPE ACKNOWLEDGE OF SECURE SWITCH LEGS
_ __ _ _ _ _ ____ _____ _ I____ __ _ _ _
0100 1110 #17 EYE NEW TYPE SYSTEM STATUS/POWER UP FOR SO
___ _ _ ___________ ____ __ __ _ _
I,
- 1233263
-- 22 -- LD--09145
0101 0010 #18 052H NEW TYPE RECEIVER THRESHOLDS FOR SO
0101 010~ #2 054H OLD TYPE SECOND KNIT SNOT SUPPORTED)
_____ ____ __ _ __
0101 1010 #19 AYE NEW TYPE DATELINE COURTERS FOR SO
__ __ _ ________ __ __ _ _
0101 1110 #20 EYE NEW TYPE ROM CODE VERSION FOR SO
0110 0010 #21 062H NEW TYPE RELAY STATES ON OVER CURRENT
_ __ ____ _____ ___________ _ _ _
0110 0110 #22 060H
___ _ _ __ ___ ______ __ _
0110 1010 #23 AYE
___ _ _ ________________ _ _
0110 1110 #24 EYE
__ _ _ _____ _____ ________ _ __ _
0111 000X #3 070H OLD TYPE INTERACTIVE VERIFY (NOT SUPPORTED)
__ _ _ ___ ___ __________ __ __ _
0111 0110 #25 070H
__ ___ ___________
0111 1010 #26 AYE
______ __ __ _________ _____ _
0111 1110 #27 EYE
___ __ _ ____ ____________ _ ___ _ _
1000 0010 #28 082H
___ _ _ _ ______ _ _ _
1000 0110 #29 086H
_________ __ ____ ______ _ __ __ __
1000 1010 #30 AYE
___ _ _ _____ _________ __ _ _
1000 110X #4 SHEA OLD TYPE MODE 4 (AX COMMAND IN DEW)
_____ _ _ _____ _ _____ __ ___ _
1001 0010 ~t31 092H
__ _ _ I_ ____ _~__ _
1001 0110 #32 090H
___ _ ____ _ ____ _ _ _ _______ _
1001 1010 #33 AYE
___ __ _ ____ __ _ ________ _ _ ___
1001 1110 #34 EYE
_______ _ __ ____ ____ _ __ _____ __ __ Jo
1010 0010 #35 OATH
_ __ __ _ ___ _____ __ _______ __ _ _
1010 0110 #36 OATH
_ _ __ ___ _ _ _ _ _ _ _ ___ _ _____ _ ___ _ ____ _ ___ _ _ _ _
1010 100X #5 OATH OLD TYPE RELAY STATE
____ _ _ __ _ _ ______ _ ___ ____ _______ _ _ _ _ _ _ _ _
1010 1110 #37 OATH
_ _ ____ _ _ ____ _ _ _ ___ _ _ ___ _ ________ _ _ _
25 1011 0010 #38 982G
__ _ __ __ _ ____ _ __________ __ _
1011 0110 #39 0130H
__
.
. .
I,
1233~63
-- 23 - LD-09145
1011 1010 #40 OBOE
_____ _
10111110 #41 OBEY
_________~ _ _ _
1100 0010 #42 OOZE
_ __ __ _______________ _ _
1100 919X #6 OOZE OLD TYPE SWITCH LEG STATE
__ _ _ _ _________ _ _
1100 1010 #43 OOZE
__ _ _ _____. _ _ _
loo Lowe #44 OOZE
__ _____~______ _ _ _
1101 0010 ~t45 ODE
1101 0110 #46 ODE
__~__ _ _ _
1101 1010 #47 ODE
___ _ _ ____ __ _ _ ._ _
1101 1110 #48 ODE
I_ __ _ ___~---- -- --
Lowe COOK #7 OWE OLD TYPE SENSOR/STATUS (NOT SUPPORTED)
_____ __ _ _______ _ _ __ _ _
1110 0110 #49 OWE
__ __ _ ____ Jo _ _ _
1110 loo #50 YEAH
__ _ _________________ __~__ _ ___
1110 1110 #51 OWE
__ __ _ __________ __ __ _ __
11110010 #52 OFF
_______ __ _ __________________ _ __ ___
1111 0110 #53 OFF
__ _ I_ __~_____ _ _ _ _
11111010 #54 OFF
_ _ ___ _ _ _______ ___ __ _
1111 1110 #55 OFF
_______ __ I_ ___ ___~______ ____ _ _ _
.
3~3
-- 24 -- LD--09145
FLAY (OR FUNCTION) BITS ARE THE BIT PATTERN (UNWISE FA,FB OR ABE
NUMB IS THE NUMBER OF THE MESSAGE
HE IS THE Hexadecimal VALUE OF THE FLAG BITS
AX COMMAND TABLE FOR Owl:) TYPE MODE 4 (IN LOWER 4 BITS, UPPER 4 ARE
COMPLEMENT)
_______ __ _______
______ ______
0 INDIVIDUAL OFF
1 INDIVIDUAL ON
2 ASK VALID PATTERN (NOT SUPPORTED)
3 NAY VALID PATTERN (NOT SUPPORTED)
10 4 STATES RELAY (NO CLEAR SLY
6 STATUS SYSTEM (NO CLEAR SLY NOT SUPPORTED)
8 SENSOR REQUEST (NOT SUPPORTED
9 STATES RELAY (CLEAR SLY
10 STATUS SYSTEM (CLEAR SLY NOT SUPPORTED)
5, 7, 11-15 WERE NOT USED
THERE IS NO DIFFERENCE IN TRY It
FROM I AND 9/10 SINCE NO SWITCH LEG
AX COMMAND TABLE FOR NEW TYPE READ
______ =__
0 SYSTEM STATUS (RETURNS 2 BYTES: JUMPERS, STATUS)
1 RECEIVER THRESHOLDS (RETURNS 4 BYTES: IBGTHR=2*1BIT, LFRTHR=2~ 50)
2 DATELINE COUNTERS RETURNS 4 BYTES: CORD MUGS, BAD Musts
3 ROM CODE VERSION (RETURNS 1 BYTE: VERS+DB7(0 FOR RELY, 1 FOR SO))
4 RELAY STATES (RETURNS 2 BYTES: LOW 8 RELY, HIGH 8 RELY)
5 SWITCH LEG MASK (RETURNS 2 BYTES: RED MASK, BLACK MASK)
SWITCH Contacts ACTUAL RETURNS 2 BYTES: RED SWITCHES, BLACK
SWITCHES)
7 ACCUMULATED SWITCH BUFFER (RETURNS 2 BYTES: MASK, STATES)
NOTE: . INFORMATION IS ALWAYS SENT WITH THE LOW BYTE FIRST FOR 16 BIT
NUT MYERS
. IBGTHR AND LFRTHR HAVE 1 ADDED TO THE HIGH BYTE
. STATUS BITS: DIREST, DBl=OVERCURRENT, DB2=UNDERCURRENT,
DB3=l=MAN RESET
Data Receiver Process
The data format section previously
described the bit serial modified ratio signaling
technique used for communications over the common
1233~63
- 25 - LD-09145
data line. It is the purpose of the data receiver
process to monitor the data line, detect activity,
establish and test the required timing characteristics
and then input the incoming serial data stream in order
to receiver the complete message. Any errors which are
violations of timing characteristics are detected,
annunciated and counted (for future analysis if desired).
The inputting of data must be the highest
priority task. When the data receive process is embodied
in a microprocessor-based system, the process is accomplished
with the minimum possible overhead in order to allow the
processor to perform other tasks while inputting data
from a data line. This is accomplished by detecting inter-
block-gaps between elements of the message and allowing
the processor to perform other tasks during the inter-block-
gap time.
Bits are input over a common communications
line connecting a plurality of transceiver-decoded
devices and then compared to thresholds in order to
determine their logical value or other special conditions
that might have occurred on the data line. The three
thresholds used by the receiver device are: the LFRTHR,
or Line Free Threshold; IBGTHR, or Inter Block Gap
Threshold; and T50THR, the T50 Threshold. The line free
threshold is used to determine when the data line has
gone from its active condition to a line free. Referring
to FIGURE 1, this threshold is dynamically determined
and is equal to two times the T50 bit input during the
readings of a preamble. The IBM threshold is used in
order to determine the beginning of an interlock gap.
This threshold is equal to two times the Ibis value read
during the preamble. Finally, the T50 threshold, which
is the average of the T50 bits read during the preamble,
is utilized to determine the logic value of bits entered
over the data line.
Because of the high priority assigned to the
receiving of data, it would be possible for a condition
~2~3XÇi3
- 26 - LD-09145
to arise in which the data line might become stuck in
either a line high or a line low condition. This might be
the case, for example, if the data line became shorted
resulting in a line stuck in the low impedance condition.
Because of this possibility and the desire to continue
processing of other tasks if it occurs, it was necessary
to "Loop Protect" the inputting of data over the data
line. This is done by counting the number of bytes
that are input to forbid inputting more than the maximum
number. Also, time-out values are used for the inputting
of data such that if a line was stuck low or high for a
period greater than that allowed, an error condition would
be flagged and the procedure would abort.
A maximum of 6 bytes can be input by the enhanced
transceiver in any one given message. There are four
maximum time-out values: MAXLFT the Maximum Line Free time-
out; MAXIBG, the Maximum Interlock Gap Timeout; MAX BIT,
the Maximum Duration of a Intermit Gap; and MAXT50, the
Maximum Duration of a T50 during the preamble. These
maximum values are used as defaults before the actual
values of line free, IBM and T50 thresholds have been
determined. They have been calculated in such a manner
as to allow a minimum data rate of 300 bits per second.
In addition to the threshold registers
described above, additional data structures are also used
by the receiver handler. There is a status byte, RVSTAT,
that is used to keep track of the condition of the data
line. Also, a receiver buffer, RCVBUF, is maintained and
it contains the data being input over the data line.
Finally, there is a counter register called the Bad Message
Counter which is used to record errors detected over the
data line for subsequent later analysis by a controlling
device. The receiver status register contains the
following flags: the Line Use, LINUS, flag which
indicates that the data line is actively in use by a
I; transmitting device; the Line Free Error Flag, LFRERR,
which indicates that a maximum line free condition
' "
'
~X33263
- 27 - LD-09145
corresponding to the amount of time needed to detect a
line free at the slowest bit rate of 300 baud must be
detected before any further information can be received
over the data line; the Good Preamble Flat, GODPRE, which
indicates that the receiver thresholds have been defined
for a message; the IBGSYN, or Interlock Gap Synchronism
Flag, which indicates that the data line is currently in
an interlock gap; finally, there is the Receiver Flag,
RCVFLG, that indicates that a valid message is waiting
decoding in the receiver buffer.
The receiver status register is monitored by
the receiver service, RCVSRV, routine which is called
by the executive in order to input data from the data
line. Receiver service monitors the various conditions
of the data line and dispatches to the proper procedures
in order to establish the timing thresholds, input the
data correct for line stuck errors and synchronize on
interlock gaps. The receiver service procedure is
described in Figure 4.
Initially on entering the receiver services
routine, the receiver status byte is checked to determine
if the line is already in use. If not, then a check is
made of the serial input data line of the processor to
determine if the line is in an active condition. If not,
then the procedure aborts and control returns to the
executive. Otherwise, if the line is indeed active, then
the line is filtered to determine if this is a false
indication due to noise. For a period of 20 microseconds
the line is constantly monitored and if at any point it
changes from the active to inactive condition, it is
considered to be noise and then the procedure exits.
Otherwise, if a valid line active condition is detected,
then the line use, LINUS, flag is set in the receiver
status register and control returns to the executive.
If it was determined on entry to receiver
service that the line was indeed in use, then a further
check of the receiver status register is performed to
12~263
- 28 - LD-09145
determine if the line free error has been set. If so, then
the transmitter of the TRY is disabled (this is in case
the data line is being stuck due to improper action by the
Triodes own transmitter). The serial input data line is
then checked to determine if the line is still in a low
condition. If so, then the process exits. Otherwise,
if the line is high, the maximum line free timeout is
moved to the line high timeout register and the siting
routine is invoked in order to time the inactivity of the
data line. If at the end of this procedure the line is
still Slot free, then the process exits and control returns
to the executive. Otherwise, the receiver service status
register is cleared indicating a line free condition and
the process completes.
If the line is not stuck then receiver service
is tested to determine if a valid preamble has been input
by testing the GODPRE flat. If this flag is not set, then
the preamble is to be input and the thresholds determined
by the PARCEL or Parameter Calculate routine. Once this
task is complete, the process then exits and returns to
the executive. If a valid preamble had been entered,
however, then a test of the receiver service status
register is made in order to determine if the line is in
an interlock gap. If not, then the CPYGET procedure is
invoked in order to detect an interlock gap. It should
be noted that CPYGET will return with an error condition
if an IBM was detected indicating that the line low time-
out had underfold to a 0 condition; the requirement for
detection of an interlock gap. If no error is detected
by the Copy and Get routine, then this indicates a valid
data bit was entered and the process completes and
exits as indicated in the figure. Otherwise, if an error
was detected, then a test is made to determine if it is a
line free. If so, then the receiver status byte is
cleared and the process exits. Otherwise, the IBGSYN
flag is set and the process exits as indicated.
. .
1~332~3
- 29 - LD-09145
If after performing the previously described
four tests of the receiver status byte, if it is
determined that the line is in use, not stuck with a
line free error, that valid preamble data has been
entered and that the line is in IBM synchronism then
the message is input by the RCVMSG routine. As indicated,
upon inputting a complete message, the receiver service
routine terminates returning control to the executive.
The timing characteristics of the data line are
determined and the proper thresholds calculated by the
PARCEL or Parameter Calculator procedure. This routine
is responsible for inputting the preamble information in
order to establish the value for the T50 threshold, line
free threshold, and IBM threshold. A flow description of
the process is given in Figure 5.
Upon entry to the PARCEL routine, since new
thresholds are to be determined and a new message will
be input over the data line, the previous threshold
registers and any data in the receiver buffer are cleared.
The maximum IBM timeout value of 49 milliseconds is then
moved to the line low timeout register, the maximum T50
timeout is moved to the line high timeout register, and
the PARGTl routine is invoked in order to input the first
preamble bit. (The first preamble bit is ignored.) If
an error is detected after inputting the bit, then the
line free error is detected after inputting the bit, then
the line free error aborts. Otherwise, the routine is
set up to input four preamble bits. PARGTl is invoked
using the maximum Ibis and maximum T50 values as timeouts
for the line low and line high timeout registers
respectively. Any error detected results in the setting
of the line free error and termination of the routine.
Otherwise, the counts remaining in the line low timeout
register are summed into low bit sum register and the
counts remaining in the line high timeout register are
summed into a high bit sum register. A test is then made
to determine if all preamble bits have been input and
~233263
- 30 - LD-09145
summed. If not, the process continues to input a bit,
sum the low counts into the low bit sum register, and
sum the high bit counts into the high bit sum register,
as indicated. After inputting and summing all four bits
of data, then the offsets needed to yield 4 times the Ibis
duration are subtracted from the low bit sum. This value
is then divided by 2 to form the IBM threshold which is
then saved. In a similar fashion, offsets required to
yield 4 times the T50 interval are subtracted from the
high bit sum. This value is then divided by 2 in order
to form the line free threshold and saved. A further
division by 2 is performed resulting in the average T50
threshold which is then saved. Finally, the good preamble
flag is set in the receiver status register and the process
completes and exits as indicated. It should be noted
that the offsets subtracted take into account both processing
time and inherent offsets needed by the BITING routine.
Figure 6 describes a simple procedure, CPYGET,
which is used to copy the thresholds determined by the
PARCEL process into the timeout registers used by the
bit input routine. As indicated by the figure, the IBGTHR
register is moved into the line low timeout register.
Following this, the line free threshold is moved into the
line high timeout register and control is immediately
transferred to the BITING routine in order to input a
data bit.
The bit input routine, BITING is responsible
for inputting the actual data bit from the common data
line. In order to maintain the integrity of the
communications system, the bits are filtered to remove
noise. Timeout counters, along with proper error indict-
lions, are maintained in order to avoid endless loop
conditions.
Referring to Figure 7, the flow description of
BITING, the procedure begins by testing the serial input
data line of the TRY to determine if the line is high.
~l23"26~
V I,
-- 31 -- LD--09145
If not, then the line low timeout register is decrement Ed
and a test is made to determine if the line low timeout
has reached a value of 0. If not, then the loop of
testing the line to determine if it is high and decrement-
in the line low timeout register continues until such time that the line does go high or that the line low time-
out register reaches a value of 0. If the line times out,
then a line stuck error is indicated and the bit input
routine aborts.
If it was determined that the line had gone
high, then a 20 microsecond noise filter is established
during which time the line is constantly sampled. If
at any time the line is determined to have returned to
the low condition, then the previous line high detection
is considered to be noise and the countdown of the line
low timeout register continues as indicated by the diagram.
However, once the noise filtering is over and it is
determined that indeed the line has gone high, then the
control continues at BITING.
BITING (Figure 3) is responsible for timing
the interval that the data line is in a high impedance
condition. This process is essentially identical to that
described before for timing the line low condition of the
data line. A loop is entered in which the line is checked
to determine if it has transition Ed from the high to low
state. If not, then the line high timeout register is
decrement Ed and a test is then made to determine if the
line high timeout had reached a 0 value. This loop
continues until such time that the line is determined to
have gone low or the line high timeout has reached a
value of 0 in which case a line free error is indicated
and the process aborts. If the line had transition Ed to
a low impedance state, then a 20 microsecond noise filter
is established and the line is constantly sampled in order
to determine if the line low indication was due to a noise
condition. If not, then a value bit has been input, the
~L~332~3
- 32 - LD-09145
duration of which can he determined from the counts
remaining in the line low and line high timeout registers.
The procedure completes and control returns as indicated
by the figure.
It should be noted that in order to provide
the largest possible range of baud rates for use over the
common data line, it was necessary to use 16 bit registers
for the line low and line high timeout counters. However,
as embodied in the enhanced transceiver, two discrete 8
bit down counters were used for each of the two line
timeout registers. This implementation results in a
special case condition which must be dealt with. This
condition is described in Figure 8. This figure describes
the BITING routines as actually embodied in the enhanced
transceiver taking into account the synthesis of the 16
bit timeout registers. Since the Figures 7 and 8 are
functionally essentially identical, only the differences
due to the 8 bit realization of the 16 bit timeout
counters will be described.
When the transceiver device is based upon an
8049 microprocessor, a special case exists when simulate
in a 16 bit down counter using two discrete 8 bit values.
This condition occurs when the low byte of the counter
is equal to 0. If that is the case, then a borrow from
the high byte must be performed before the low byte can
be decrement Ed. This is indicated in Figure 8 by the
test of the low byte for a 0 value followed by the branch
if true to a decrement of the high byte as indicated on
the diagram. Because of this borrow before the decrement
of the low byte, a further test is needed to detect
the final special condition. After determining that the
proper transition of the data line has occurred the low
byte of the timeout register is examined and tested for
a 0 condition. If at that point the byte is 0, this
indicates that a borrow was made from the high byte that
was not necessary. Therefore, the high byte is incremented.
Otherwise, if the low byte is not equal to 0, then the low
~2~3~63
- 33 - LD-09145
and high byte both contain the proper values and the
process can continue.
Figure 10 depicts the flow of two subroutines
utilized by the parameter calculate routine. As indicated
in the figure, on entry to the PARGTl routine, the line
low timeout register is set for the maximum Ibis time
and control transfers to the PARGT2 routine. PARGT2 is
responsible for setting the line high timeout register
to the maximum T50 time. At this point control then
passes directly to the bit input routine.
RVSORL, RVSCLR and RVSANL are three sub-
routines used to manipulate the flag bits of the receiver
status byte. These subroutines are described in Figure
11. RVSORL is used to set desired flag bits within the
receiver status byte. This is accomplished as indicated
by merging the bits to set in receiver status with the
original receiver status byte by an Owing process. The
updated receiver status byte is then saved and the process
completes. RVSCLR is used to indicate a line free
condition and clears all of the bits of the receiver
status byte by indicating a desire to clear all bits
and continuing with the process RVSANL. Flag bits are
removed, or cleared, from the receiver status byte by
RVSANL. This is accomplished by Aiding the bits to clear
with the original receiver status byte. This updated
status byte is then saved and the process completes.
Figure 12 describes the error routine which
is invoked any time that an error is detected in the
process of receiving information from the data line.
The bad message counter is incremented as indicated and
the process completes.
Serial data is input from the data line and
converted to parallel data in the receiver buffer by
the RCVMSG or Receiver Message procedure. In addition to
performing the required serial to parallel conversion,
RCVMSG tests to determine that more than the minimum
~33~63
- 34 - LD-09145
number of bytes and less than the maximum number of bytes
have been input. In addition, it monitors various error
conditions and indicates appropriate actions to be
performed in the receiver status byte. Finally, on
inputting a complete and proper message in the receiver
buffer, the receiver flag, RCVFLG is set indicating a
message awaiting decoding in the receiver buffer.
The receiver Message process begins as
indicated in Figure 13 by setting a pointer to the
receiver buffer, indicating a maximum of 6 bytes to be
input, and initializing the byte so far register to a
value of 80H. The line low timeout register is then set
to the maximum IBM time and the line high timeout register
is set to the line free threshold. The first bit of the
message is then input by using the BITING process. If an
error is detected on this first bit of the first type,
then the process continues at Connector D of Figure 15.
Otherwise, continuing at Connector A, the remaining counts
in the line high timeout are compared to the T50 thresh
hold. If a data bit 1 was input, then the carry flag will be set. Otherwise, if there is no carry, resulting
then a data bit 0 was input. (This process is performed
by summing the 2's complement of the T50 threshold with
the remaining counts of the line high timeout). following
the comparison, the byte so far is rotated to the right
resulting in Bit DB7 set if a data bit 1 was input and the
carry flag was set. A test is performed to determine if
data bit 0 was equal to 1 before the rotate occurred. If
not/ then the process continues as indicated by inputting
the remaining bits of the byte using the process CPYGET
which sets the line low and line high timeout registers
to the IBM threshold and line free threshold respectively.
If on inputting the subsequent bitts of the byte an error
is determined, then the process continues at Connector E
of Figure 16. Otherwise, comparisons of the bits input
and the rotation and position input continue until a
lZ33263
- 35 - LD-09145
complete byte has been input at which point the process
continues at Connector s of Figure 15.
Continuing the description of the Receiver
Message process with Figure 14, whenever a complete
byte of information has been input, the process at
Connector B is invoked. The byte that was input is saved
in the receiver buffer and the receiver buffer pointer
is updated to point to the next storage location. In
addition, the byte so far register is set back to its
initial value of 80H and the CPYGET routine is used to
input the first bit of the next byte using the IBM threshold
and line free threshold in their respective timeout
registers. If an error is detected, then the process
continues at Connector C of Figure 15. Otherwise, a
valid bit has been input and the byte counter is then
decrement Ed. If the byte counter reaches a value of 0,
then too many bytes have been input, the process exits via
the error routine without indicating IBM synchronism
or a valid message. On the other hand, if fewer than
the maximum number of bytes have been input then the
process continues at Connector A of Figure 13 as indicated
in the diagram.
Connector C of Figure 15 is invoked at any time
an error has been determined on the first bit input for
bytes 2 and up. A test is determined to see if the error
was detection of an IBM. If so, then the process continues
at Connector F of Figure 16. Otherwise, the error was a
line free detection. The bad message counter is incremented
by the error process and the receiver status byte is
cleared to show the detection of a line free interval and
the process aborts on completion of the RVSCLR routine.
Connector D of Figure 15 is entered any time
an error on the first bit of the first byte is detected.
If that error was a line free error, then a normal
condition has been detected which is actually not an error
(since the line would be expected to go free after the
'
, .
~233263
-- 36 -- LD--09145
final IBM of a message In this case, the receiver
status byte is cleared and the receive message routine
aborts. Otherwise, a line free error is indicated in
receiver status by the RVSORL routine. Once a line free
5 error has been set the line must go free before any
further input can be attempted (this would be the case
if the line was determined to be stuck). The process then
aborts by invoking the error routine to increment the
bad message counter.
Figure 16, describes two additional error
handling procedures for the receive message routine.
At Connector E, which is entered any time an error is
detected on bits other than the first bit of a byte, a
test is made to determine if a line free error occurred.
lo If not, then the line is in IBM synchronism and the
process aborts by calling the error routine to increment
the bad message counter. Otherwise, if the line did
go free, then the receiver status byte is cleared and
the process exits through the error routine. At
Connector F, an error condition that would be entered on
an IBM detection on the first bit of a byte (which might
be a normal end of a message), a test is performed to
determine if at least 4 bytes have been input from the
data line. If not, then the line is in IBM synchronism
and it aborts without indicating a valid message in the
receiver buffer via the error routine. On the other hand,
if at least 4 bytes had been input from the data line.
If not, then the line is in IBM synchronism and it aborts
without indicating a valid message in the receiver buffer
via the error routine.
The completes the description of the Receiver
Process which provides a means of inputting serial data
from the common data line and converting it to a
parallel form in the receiver buffer; a means of using
a modified rationed method for determining 0 or 1 date
bits; a means of protecting from endless loop conditions
1233~G3
- 37 - LD-09145
due to the data line remaining in the low or high impedance
state for longer than a maximum allowable time a means
of aborting the receive process when an attempt is made
to input more than the maximum allowed number of bytes;
a means of setting a valid message flag to indicate when
at least a minimum number of bytes have been input; a
means of allowing non-related processing to occur during
the interlock gap intervals of a message being received;
a means of establishing timing characteristics or
thresholds from a minimum of 5 preamble bits received
from a message; a means of accumulating the number of
errors that have occurred for possible subsequent
analysis by a controlling device; a means of simulating
a 16 bit down counter with 2 discrete 8 bit down counters;
a means of filtering noise digitally from the received
information in order to avoid improper detection of a
transition; a means of allowing multiple blocks of data
to be received by using the same receiver thresholds by
detecting regular interlock gaps between blocks of data;
a means of allowing a variable length message to be
received by detecting the final or regular interlock
gaps; a means of providing true averaging of the
preamble bits input; and a means for correcting the
thresholds determined while inputting the preamble bits
to eliminate the effects of calculation time and other
process related constants.
Data Transmitter Process
The data transmitter process is a collection
of routines responsible for transmitting a desired
message over the common data line. Messages from one of
two possible output buffers (corresponding to the two
banks of the transceiver) are converted from their
internal parallel representation to the bit-wise serial
format needed for transmission over the data line taking
into account various timing priorities for the different
messages; such as the line free access times described
1~33~3
- 38 - LD-09145
in the data format section. In addition to those routines
responsible for the actual transmission of the message,
various other routines exist for placing the data into
the output buffer in a format that can be transmitted, and
routines for the generation of the modified checksum and
even nibble parity words that are transmitted at the end of
the message.
In order to get the data to be transmitted into
the output buffer in a format that can be utilized, the
procedure sLDTBF, or Build the Transmitter Buffer, is
invoked. The purpose of this routine is to place the
data bytes (from 0 to 4) into the output buffer, surround-
in this information with the proper function, address,
and check words as required. It recognizes both new and
old format messages and can perform the formatting required
for both.
Referring to Figure 17, on entry to the BLDTBF
process a test of the transmitter status byte for the
desired bank is made to determine if a high priority
message is already present in the output buffer (this
message would be a power-up status message). If so,
then the build the transmitter buffer routine aborts
and control returns back to the calling process.
Otherwise, as indicated, the proper output buffer is
pointed for the location of the first data byte.
A test is then made to determine if it is an old type
message in which case the pointer to the output buffer
has already been set to the proper location. Otherwise
1 must be added to the pointer in order to point to the
first data byte location (to offset for the 2 address
fields required in the new format). The number of data
bytes to copy is then determined and the data bytes are
copied into the desired output buffer. The buffer pointer
is then restored to the head of the buffer and a test is
made to see if a new or old type message is being sent.
If a new type message is being placed into the output
~;~332~;~
- 39 - LD-09145
buffer, then the flag so far it set to a value of 2 (indict-
tying that the FAX Us equals 10). If, on the other hand, an
old type message was being placed into the output buffer,
then bit A of A8JUMP (Duo) is isolated and then saved
as the flag so far. Next the flag bits corresponding to
the desired message are then Owed together with the flag
so far in order to form the complete flag byte.
Figure 18 continues with Connector A as
indicated. The complete flag byte is saved at the
head of the output buffer. The address field is then
pointed to by incrementing the pointer, and a test is
made to determine if the message is in the old format.
If so, then the process continues as indicated. Other-
wise, the address bit A is isolated from the A8JUMP
register. It is saved as the high address word with all
other bits equal to 0. The low address word is then
pointed to and the ADRLOW register is moved and saved
as the low address word. A test is then performed to
determine if the message being inserted into the output
buffer is for bank 0 or bank l. If it is not for bank 0,
then bit A of the low address word is set to a l. A
further test is then performed to determine if it is an
old format message. If so, the process continues at
Connector C of Figure lo, and if not, the process continues
at Connector B of Figure lo.
Connector C of Figure lo is entered for an old
type message. It adds 3 to the buffer pointer in order
to point to the location for the nibble parity check
word. Connector B is utilized for new format messages.
It adjusts the pointer to the check location of the
output buffer by adding the number of data bytes to the
current pointer location (which would be pointing to the
low address field). The updated pointer is then saved
for later use as the last word pointer. A test is then
made to determine if the message is of the old type. If
so, then the process continues at Connector D (Figure 20).
~L233~
- 40 - LD-09145
otherwise, the number of bytes to check is set equal to
the number of data bytes plus 3 (the flag and 2 address
bytes). The checksum register is then initialized to a
value of 80H. A byte is then fetched from the buffer.
The checksum register is then set equal to the checksum
register plus the value of the byte. The buffer pointer
is then decrement Ed to point to the next byte and a test
is made to determine if all bytes have been checked. If
not, the process continues by fetching a byte, adding
it to the checksum register and decrementing the pointer.
Once all bytes have been checked, then a 2's complement
of the checksum register is formed and the process continues
at Connector E of Figure 20.
Figure 20, Connector D is entered in order to
form the parity word for an old format message by invoking
the PARITY procedure. The process continues with
Connector E. The pointer to the last word is restored
and the parity or check word is saved as required as the
last word in the output buffer. The number of bytes to
transmit is then set to be equal to the total number of
bytes in the output buffer. This completes the BLDTBF
routine which then returns control to the invoking
procedure.
Figure 21 describes the PARITY routine and
PAR SUB subroutine necessary for the generation of the
even nibble parity word for use in the old format
messages. A description of the spatial relationship
of the parity bits to the nibbles of the preceding four
bytes, as well as a description of the even parity kirk-
teristics was given in the data format section. As indicated by Figure 21, the parity routine clears the
parity byte and indicates 4 bytes to check. The pointer
to the output buffer is then decrement Ed and a byte to be
checked is fetched from the buffer. The high nibble is
then checked by invoking the PAR SUB routine again to
generate the corresponding parity bit for that nibble.
lZ3~263
- 41 - LD-09145
A test is then performed to determine if all bytes have
been checked. If not, the process continues to decrement
the pointer and form the two check bits for the high and
low nibble of the byte until such time that all bytes
have been checked, at which time control returns to the
calling procedure.
Figure 21 also describes the PAR SUB subroutine
used to generate the parity bit for a nibble. This is
done in a lockup approach. As indicated, a pointer is
set to the parity table. An index is then formed to the
desired parity bit by adding the value of the nibble to
the pointer to the parity table. The parity bit is then
retrieved from the table. Next, the parity byte so far
is fetched and rotated left one position. The parity
byte is then updated by Owing in the new parity bit with
the parity byte so far which is then saved for subsequent
use, completing the process which then returns.
The transmitter service routine (Figure 22),
XMTSRV, is the main routine of the data transmitting
process. Transmitter service is invoked by the executive
and is responsible for maintaining the proper status bits
to indicate various line free detections, determining if
anything is available for transmission, invoking the
procedure for the parallel to serial conversion and
subsequent transmission of a message of the output buffer,
and testing for collisions with transmitted messages and
the required updating of the status information. Two
bytes of information are required by the transmitter service
routine; the LOONIEST or Line Status Byte, which indicates
the current detected line free status from collision to
deferred; and the transmitter status byte for banks 0
and 1 which indicates the required line free timeout
and actions for transmission and subsequent detection of
a collision.
A flow description of the XMTSRV routine is
given on Figure 22. On entry to the transmitter service
a test is performed to determine if the data line is in
1233263
- 42 - LD-09145
use by examining the receiver status byte. If so, at
Connector A, the transmitter line status byte is cleared,
the receiver line use flag is set in receiver status byte
by the routine RVSORL, which upon completion exits. If
the data line was not in use, a test is performed by the
XMTEST routine to determine if anything is available
for transmission. If so, then the process continues with
Connector C of Figure 21. Otherwise, a check is made
of the line status byte to determine if the line is
totally free. If so, then the process completes and
returns to the invoking procedure. If the line was not
complete free for transmission, then further tests are
performed to determine additional line free times needed.
As indicated in the Figure, a test is performed to
determine if a deferred line free is needed. If so, then
the line high timer is set for the incremental line free
needed for the deferred line free and a deferred line
free is indicated for the line status byte. If there is
not a need for a deferred line free, then a test is made
to see if there is a need for a normal line free. If
so, then a line high timer is set for the incremental line
free needed for a normal line free and a normal line free
is indicated for the line status byte. If the line is
not totally free, and a deferred line free and a normal
line free are not needed, then a collision line free
must be needed and, as indicated, the line high timer
will be set to the collision timeout minus the receiver
line free thresholds and a collision line free will
be indicated for the line status byte. The amount of
line high time for either deferred, normal or collision
line frees is then timed out by the BITING routine.
If there is no error, then control continues with
Connector A (Figure 22). Otherwise, the proper line
free indication is set in the transmitter line status
byte and the process continues at Connector B of Figure
23.
Connector B (Figure 23) is invoked upon
."
1~33~63
-- 43 -- LD--09145
completion of any of the line free timeouts. A test
is performed by the XMTEST routine to determine if
there is anything to transmit. If not, this completes
the transmitter service routine and control returns to
the executive. Otherwise, at Connector C (Figure 23),
which is the XMTSR6 routine, the data line is pulled to a
low impedance condition and then the contents of the
output buffer are transmitted over the common data line
by the PLAYACT routine. If a collision is detected while
transmitting, when a test will be made of the collision
set request for the proper transmitter status byte to
determine if it is set. If so, then a collision line free
request will be set in the proper transmitter status byte.
The process continues with Connector A of Figure 22 as
indicated. On the other hand, if a collision was not
detected on transmitting the message over the common data
line, then the transmitter line status and bank status
registers are cleared and the process XMTEND is invoked
in order to send the final IBM of the message and then
release the data line completing the transmitter
service routine.
As was mentioned before, the three line free
timeouts (collision, normal and deferred) establish the
relative priority of messages to be transmitted over the
common data line. Since a two address transceiver decoder
contains two output buffers, each with independently
configurable transmitter status bytes, it would be
entirely possible for the output registers to contain
message with different priorities for transmission. It
is the purpose of the transmitter test routine, XMTEST,
to establish the relative priorities of the messages and
insure that the bank with the highest priority will be
transmitted first. If both banks are of equal priority then
the message contained in bank 1 will be transmitted
first, followed by the message in bank 0.
Figure 24 describes the XMTEST routine. The
line status byte is fetched and the transmitter status
~2~3~3
44 - LD-09145
for bank 1 is pointed to while indicating bank 1. A test
is then made to determine if this TRY is a two address
device. If not, there is nothing for bank 1, and a test
is performed to see if there is a match between the bank
0 transmitter status and the line status byte while
indicating a bank 0. The process then returns to the
transmitter service routine as indicated. If a device is
a two address TRY, then a test is performed to see if
there is a match in the line status and bank 1 transmitter
status byte. If there is not a match, then there is
nothing for bank 1 and a further test is performed to
determine if anything exists for transmission in bank 0.
Bank 0 is then indicated and the routine returns to the
transmitter service routine.
If a match was detected between the transmitter
status byte for bank 1 and the line status byte then a
further test is made to determine if that match was due
to a collision line free requirement for bank 1. If so,
then the routine returns with the bank 1 indication. If
there was not a collision request for bank 1, then a similar
test is performed for bank 0 to determine if it has a
collision line free requirement. If so, then control
continues as indicated on the diagram, setting the bank
0 indication and exiting to the transmitter service
routine. If there was not a collision requirement for
either bank 1 or bank 0, a test is made to determine if there
is a normal line free requirement for bank 1. If so, the
process returns, otherwise a further test is performed
to determine if there is a normal line free requirement
for bank 0. If this does not exist, then bank 1 must
have had a deferred line free requirement which is so
indicated upon exiting the routine. If bank 0, on the
other hand, had a normal line free requirement then the
process continues as indicated on the diagram setting a
bank 0 indication and returning to the transmitter service
routine.
There are three subroutines, shown in Figure 25,
._
- ~2332~i3
- 45 - LD-09145
used in the process of transmitting a message over the
common data line. They are: the XMTGAP routine, which
is responsible for transmitting an interlock gap over
the data line; the XMTDAT or Transmit Data Routine which
is responsible for transmitting actual data bits over
the data line; and the XMTEND or Transmit End of Message
routine which is responsible for sending the final IBM
and releasing the data line. Figure 25 describes these
routines in detail.
XMTGAP begins by decrementing the gap timer.
A test is then made to determine if the gap timer has
reached a value of 0. If not, the process of decrementing
and testing the timer continues until such time that the
timer has reached a value of 0; at which time the process
completes and control returns to the calling routine.
The XMTEND routine will set the gap timer to
the final IBM time and then delay the final IBM time by
invoking the XMTGAP procedure. Upon completion of the
delay, the data line is released to its high impedance
state and the process completes.
The XMTDAT routine which is responsible for
transmitting individual bits over the common data line,
begins by releasing the line to a high impedance
condition (it was left in a low impedance condition by
the interlock gap or preceding data bits). A fixed
amount of time then delayed to allow the line to return
from its low impedance to high impedance condition (50
microseconds). A test is then performed to determine
if the line has remained in a low impedance condition.
If so, then a noise filter process is established in
which the line is constantly tested to determine if the
line is returning to a high impedance condition, indicating
the presence of noise. This continues until such time
that the filter time interval has expired (25 microseconds)
upon which a collision detection is indicated and the
procedure aborts. If no line low condition was determined
I
1~:33~63
- 46 - LD-09145
on completion of the rise time after the release of the
data line, then the line high timer is decrement Ed and a test
is made to determine if the line high timer has reached a
0 value. If not, the process continues to check for a
low impedance condition that would indicate a collision
and the decrementing of the line high timer until such
time that the high impedance interval has transpired. At
this point the line will be set to its low impedance
condition and the line low timer will be timed down until
a 0 value is reached completing the process which then
returns to the calling routine.
The PLAYACT routine, shown in Figure 26, is
responsible for performing the parallel to serial
conversion and subsequent transmission of the information
contained in the output buffer over the common data line.
In addition to the parallel to serial conversion, it will
transmit out the required preamble information and format
the message with the required interlock gaps.
Figure 26 begins the description of the PLAYACT
process. The number of preamble bits to transmit is set
to seven (7) and the gap timer is set to the talc or
initial IBM time. The initial IBM time is then delayed
by the XMTGAP process at which point the line high timer
is set to the T50 value and the line low timer is set to
the Ibis. The preamble bit is then transmitted by the
XMTDAT routine and a test is made to determine if a
collision has resulted. If so, the routine aborts and
returns as indicated. Otherwise, a test is performed
to determine if all preamble bits have been sent. If
not, the process of establishing the line high and line
low timers, transmission of the data bit and tests for
collision continues until such time that all bits have
been sent. Once all bits of the preamble have been
transmitted, the gap timer is set to a regular IBM
interval and the regular IBM is timed out by the XMTGAP
routine at which point control continues at Connector A
3~63
- 47 - LD-09145
of Figure 27.
Continuing with the description of the PLAYACT
routine, at Connector A of Figure 27, the number of bytes
to transmit is fetched and a pointer is placed to the
head of the proper output buffer. The byte to be sent is
then fetched and saved in a temporary storage location.
The byte to be sent is then restored from the temporary
location and rotated right once in order to position the
bit to send into DB7. This rotated byte is then saved
in the temporary location and a test is made of the DB7
value to determine if it is a 1. If so, then the line
high and line low timeouts are established for a data 1
bit; otherwise, they are established for a data 0 bit.
The bit is then transmitted by the XMTDAT routine and a
lo test is made to determine if a collision has occurred on
the bit. If so, the process aborts. Otherwise, a test
is made to determine if all bits of that byte have been
sent. If not then the process continues as indicated to
rotate the position of the bits send the proper data bit 0
or data bit 1 and test for collisions until such time that
all bits have been sent. When a byte is complete a test
is made to determine if all bytes have been transmitted.
If not, then the pointer is updated to the next byte to
send in the output buffer. That byte is fetched and
saved in a temporary location as indicated, and then the
process for transmitting the eight bits in the serial
fashion is repeated. This continues until all bytes
have been transmitted, at which point the PLAYACT routine
completes and returns control to the calling procedure.
This completes the description of the data
transmitting process which provides: a means of placing
the data to transmit into one of two output buffers
formatted in one of two transmission formats; a means of
detecting the presence of a high priority message in the
output buffer in order to avoid overriding same; a means
of generating a modified checksum check word for trays-
23;~;3
- 48 - LD-09145
mission in the new format (modified to avoid an all 0
message); a means of forming the even nibble parity word
for transmission in the old format utilizing a table
look-up for higher throughput; a means of monitoring
the line free condition of the data line and providing
a prioritized set of line free timeouts required for
transmission of data; a means of providing an immediate
or bus transfer line free protocol; a means of providing
a collision line free protocol; a means of providing a
normal line free protocol; a means of providing a deferred
line free protocol; a means of testing the relative
priority of messages contained in the output buffer to
insure that the highest priority message is transmitted
first; a means of providing a collision line free set
indicating a desire to require a collision line free
timeout on subsequent attempts to transmit a message
that has been collided with; a means of detecting a
collision on transmission of a message; a means for
eliminating noise that might result in an improper detect
lion of a collision; a means of allowing a rise time forth low impedance to high impedance transition to avoid
false detection of a collision; a means of converting
from a parallel to serial format the message to transmit
in the output buffer; a means of establishing a lower
priority initial IBM, or talc, which would allow a master
device of higher priority to gain control of the data
line at need; and a means of providing two discrete output
buffers and associated transmitter status registers
(corresponding to the two addresses of a TRY) for independent
use as message buffers.
While the invention has been described in
connection with what is presently considered to be the
most practical and preferred embodiments, it is Jo be
understood that the invention is not limited to the
disclosed embodiments but on the contrary, is intended
to cover various modifications and equivalent arrangements
included within the spirit and scope of the appended
~233Z6,~
- 49 - LD-09145
claims which scope is to be accorded the broadest
interpretation so as to encompass all such modifications
and equivalent structures
