Note: Descriptions are shown in the official language in which they were submitted.
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This invention relates to the fabrica-tion of very large
scale integrated (VLSI) metal oxide semiconductor -field effect
transistor (MOSFET) circui-tsO
In the fabrica-tion o-f high performance VLSI MOSFET
circuits polycrystalline silicon (polysilicon) is normally used for
gate and interconnect regions. However, the high resistivity of
polysilicon gives rise to RC time delays which limit device
performance. Also, as the MOSFETs are scaled down to the sub-micron
regime, the shallow source and drain junctions result in high sheet
resistances.
To reduce the delay due to high sheet resistance of
polysilicon gate and interconnects, refractory metal silicide or
composite refractory metal silicide/polysilicon compositions have been
proposed -for gate and interconr)ects. ("1 um MOSFET VLSI technology:
part VII - metal sil icide interconnection technology - a future
perspective", lEEE, Journal of Solicl State Circuits, SC-14, page 291,
1971, Crowder et al).
In adclition, to lower the sheet resis-tance of shallow
source and drain junctions, the silicidation of source, drain and
polysilicon gate has been attempted and the resulting so-called
SALICIDE structure is known, ("An optimally designed process for
sub-micron MOSFETS", IEDM, Technical Digest, page 647, l9Sl, Shibata
et al). In this SALICIDE technology, source, drain and polysilicon
ga-tes of MOSFETS are formed with a silicide layer at the same time.
Sidewall oxide regions are used to separate the source and drain from
the gate. In the silicida-tion process, a noble or refractory metal is
deposited over the entire surface and then selectively reacted with
the underlying silicon a-t the source, drain and polysilicon gate.
After the reac-tion, the unreacted metal is etched off selectively by
chemical etchants. ~lo~ever in practice, a thin layer oF metal must be
used for the silicidation -for two reasons. Firstly during the
silicidation process, silicon is consumed as me-tal silicide is
formed. The thickness oF silicon which is to be consumed must be
equal or thicker than -the deposited metal thickness, depending on the
phase of silicide formed. For example, in the case of -titanium
silicide (TiSi2) -the polysilicon thickness is double the thickness
of metal. To avoid the formation of Schottky junctions with
consequent junction leakage, the thickness oF metal should be less
than a quarter of the source and junction depths. The other reason
for using a thin me-tal layer is to avoid the formation of silicide
over sidewall oxide used to isolate the gate from the source and
drain. Any silicide over this region would electrically short the
source ancl drain to the gate.
Thus for VLSI MOSFET circuits with source and drain
junctions approaching 0.1 micron in depth, the thickness of me-tal used
should be less than 200 angstrom units. For a polysilicon gate of
about 0.3 micron thickness, the thin layer oF 500 angstrom units of
silicide which can be Formed From 200 angstrom units of metal
deposited on the gate is not enough to lower the sheet resis-tance to
the required order of about 1 ohm/square. In fact~ since the lowest
resistivity oF silicide is of the order of 20 um ohm.cm, the sheet
resistance of silicide (500 angstrom units) on polysilicon (2000
angstrom units) is higher than 4 ohm~square. Therefore the SALICIDE
technology does not provide optimal sheet resistance of gate and
interconnects for submicron clevices.
To overcome these problems there is proposed according
to one aspect of the present invention a process for fabricating VLSI
circuits using refractory metal silicide, comprising the steps of:
forming regions of field oxide on a semiconductor substrate; forming
gate oxide within device wells defined by the field oxide; forming a
conducting gate layer on the gate oxide and defining gate regions
therein, the conducting gate layer having a refractory metal or
refractory metal silicide content; forming source and drain regions in
the semiconductor; forming a thin metal layer over the source, drain
and gate regions, the metal layer being in contact with the refractory
metal or refractory metal silicide layer of the conducting gate layer;
and forming a thin iunction silicide layer on the source, drain and
gate regions using said thin metal layer.
Th~ conducting gate layer can be formed by first
depositing a layer of polysilicon and then depositing a layer of
refractory metal or refractory metal silicide. The conducting gate
layer is alternatively deposited as a single layer of refractory metal
such as Mo or W or refractory metal silicide.
The refractory metal silicide can be deposited directly
by one of a plurality oF techniques such as co-evaporating, co-
sputtering, sputtering of a composite target, or chemical vapour
deposition (CVD). The refractory metal can be deposited by
evaporation, sputtering or CVD.
The structure should be annealed aFter gate definition
although the heat of subsequent oxidation and diffusion stages can
also function to lower the gate sheet resistance. The gate regions
within the gate conducting layer can be defined by reactive ion
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etching. The source and drain regions can be produced by ion
implantation followed by annealing. Surface isolating oxide regions
for elec-trically isolating the gate from the source and drain regions
can be Formed by depositing an oxide layer over the wafer and etching
back the oxide by reactive ion etching. Oxide is completely removed
over the gate, source and drain regions but no-t at gate sidewall
regions where the oxide is initially relatively thick.
The thin junction silicide layer formed over the
source, drain and gate regions can be deposited as a refractory me-tal
such as Ti and then sintered to form metal silicide where the metal
overlies silicon. Other metals such as Co, Ni, Pt and Pd can also be
used. Unreacted metal from over the -field and isolating oxide regions
is subsequently dissolved. Alterna-tively refractory metal such as
tungsten ancl molybdenum can be selectively deposited onto the source,
drain and gate regions to shunt the sheet resistance of the underlying
layer.
The refractory metal used to form the gate conduc-ting
layer can be one oF the group of metals consisting of titanium,
tantalum, tungsten and molybdenuln. If subsequent processing is not
performed at high temperatures greater than 900C, the noble metals
platinum and palladium can alternatively be used in the ga-te
conducting layer. The thickness of the refractory metal or refractory
metal silicide layer within the gate conducting layer is preferably in
the range 1500 to 2500 angstrom units and the refractory metal or
silicide iunction layer is preferably in the range 300 to 1000
angstrom units.
Device in-terconnects can be formed simultaneously with
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the gate conduc-ting layer.
An embodiment of the invention will now be described by
way of example wi-th reference to the accompanying drawings in which:-
Figure 1 is a sectional view showing a VLSI MOSFET
5 according to the invention; and
Figures 2 to 4 show successive stages in thefabrication of the Figure 1 transistor using a fabrication technique
according to the invention.
Figure 1 shows in detail a metal-oxide-semiconductor
field effect transis-tor (MOSFET) formed on a p-type silicon substrate
10. Isolating field oxide regions 12 are underlain by p~~-type
regions 140 Within the substrate are n+-type source and drain
regions 16, 18. Extending between the source and drain regions and
overlying a channel r.egion 20 within the substrate 10 is a gate oxide
layer 22. Over the gate oxide layer is a yate having a lower 2500
angstrom Ullits thick polysilicon layer 24 ancl a 2500 dngstrom unit
thick titanium silicide upper layer 26. A-t side edges oF the gate are
isolating oxide regions 28. Laterally adjacent the oxide regions 28
are 300 angstrom units thick titanium silicide layers 30 overlying the
source and drain regions 16, 18. A corresponding thin titanium
silicide layer 32 also overlies the gate.
Referring to Figure 2, to fabrica-te the device, boron
ions are implanted at locations 14 to establish channel stop or
isolation regions and a device active area is defined by thermally
oxidizing regions of the silicon substrate 10 at 1000~C using a known
local oxidation of silicon (LOCOS) technique. As shown in Figure 3
the polysilicon layer 24 is then deposited by low pressure chemical
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vapour deposi-tion (LPCVD) at 625C and is doped with phosphorus -from a
POC13 gaseous source to give a sheet resistance of 40 ohm/square.
Next, the titanium silicide layer 26 is deposited by DC magnetron
sputtering a-t ambient tempera-ture using a composite targe-t. After
annealing in argon at 900C for 30 minutes, the combined titanium
silicide/polysilicon layer yields a sheet resistance of 1 ohm/square.
If MoSi2 and WSi2 are used instead oF titanium silicide, a
temperature of 1000C For 30 minutes is required. The resulting
structure retains the properties oF a polysilicon/silicon dioxide
interface in that the work function of polysilicon on oxide is very
well known and a smooth interface can be obtained with good oxide
layer integrity. The structure is compatible wi-th other high
temperature processing steps used in the fabrication oF integrated
circuits. The combined silicide/polysilicon gate layer 24, 26 is then
patterned in a reactive ion etching (RIE) system using a chlorine
based gas etchant to define the device gate. The gate patterning can
also be performed prior to annealing.
~eferring to Figure ~, shallow junc-tion source and
drain regions 16, 18 are formed at the source and drain by implanting
As~ ions with an energy of 50 kev and a dose of 5 x 1015/cm2
followed by a subsequent annealing step For 30 minutes at 925C. The
sidewall oxide regions 28 are produced by low pressure chemical vapour
depositing a 0.5 micron silicon dioxide layer over the source, drain
and gate and then etching back the layer using reactive ion etching in
a fluorine based plasma. Since oxide is thicker at the gate sidewalls
and since ma-terial is etched vertically by reactive ion etching, then
although oxide is totally removed from over the gate, the sidewall
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oxide portions remain.
The thin titanium silicide layer 32 is then formed by
sputter depositing a 300 angstrom unit layer of titanium and then
sintering the titanium layer a-t 600C. Where the ti-tanium overlies
silicon at the gate, source and drain regions, a thin layer of
ti-tanium silicide is -Formed. Ti-tdnium which overlies field and
sidewall oxide regions remains unreacted and is removed by etching
with a solution composed oF H202:NH~OH:H20 with a volume ratio
of 1:1:5. After removing the unreacted titanium, the ti-tanium
silicide is again sintered at 800C to further lower the sheet
resistance.
Although in the specific embodiment described the
silicide present in the gate and over the source and drain is titanium
silicide, other silicides such dS those of tungsten, molybdenum and
tantalum can also be used and in addition to these refrac-tory metals
some noble metals such dS platinunl and palladium can make eFFective
junction silicldes~
Although when using titanium in the formation oF the
thin junction silicide layer, unreacted titanium must be removed From
over the isola-ting oxides, the step oF metal removal may be
unnecessary when using other metals. Thus For example, tungsten (~)
can be chemically vapour deposited selectively over source, drain and
gate from an ambient of WF6o No etching is required since no metal
deposition occurs on the oxide regions.
In a further me-thod, the silicide layer over source and
drain is formed simultaneously with, and over regions accurately
vertically aligned with, the source and drain regions by first
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depositing the layer oF reFractory metal and then bombarding -the
regions with ions of selected conductivity type at an elevated
temperature. The ions, for example As+ ions in n-channel devices
and BF2~ ions for p-channel devices both pene-trate the silicon to
Form a doped source or drain region and have sufficient energy to
promote interface mixing between the refractory metal and -the
underlying silicon with the resulting formation of silicide,
Although in the embodiment specifically described the
gate conducting layer is formed by deposi-tion and doping of a
polysilicon layer followed by the deposition of a metal silicide
layer, the gate conducting layer can alternatively be deposited as a
single layer oF re-Frac-tory metal silicide of uniForm composition.
Although the thin layer of metal of the junction
silicide layer is consumed by the Formation oF silicide over the
source and drain, the metal deposited onto the gate merely renders an
upper layer oF the gate rich in the metal. If a deposition/etch
method is used then an upper nletal-rich part of the gate layer may be
removed when the metdl overlying the oxide layers is etched away. The
refractory or noble metal used in the gate silicide Formation may be
difFerent From -that used in the gate conducting layer.
