Note: Descriptions are shown in the official language in which they were submitted.
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SEMICOND~1C~OR DI~VICE UITEI POLYCRYSTALLINE SILICON ACTIVE
RE:GION A~ OD OF l?ABRICATIO',la l~ERE:OF
BACI~G~OUND OF ~IIE: INVE2~TION
The present invention relates generally to a
semiconductor device, such as a field-effect transistor
~FET) suitable for production as a MOS thin-film
transistor (MOS TFT). More particularly, the invention
relates to a semiconductor device having a
polycrystalline silicon layer acting as an active region
with high effective mobility, relatively low threshold
voltage, and low leakage current between the source
region and the drain region when used in ~OS TFT.
It has been known that semiconductor devices
with polycrystalline silicon active regions formed by
chemical vapor deposition processes and the like are
less efficient than semiconductor devices with
single-crystal silicon active regions due to relatively
low effective mobility, relatively high threshold
voltage, and relatively high leakage current while ~he
MOS TFT is turned OFF. This is believed to be due to
the characteristics of the polycrystalline silicon layer
serving as the active region.
The inventors have found that the effective
mobility ~eff of the polycrystalline silicon film is
significantly enhanced within a specific thickness
range~ Specifically, when the thickness of the
polycrystalline silicon film is held to within a
specific range thinner than that conventionally employed
in semiconductor devices, its effective mobility becomes
much higher than typically expected. This fact has not
been exploited before because it has generally been
believed that the effective mobility of a thin
polysilicon film is almost independent of thickness in
films thinner than l500A. The results of experiments by
the inventor indicate that effective mobility becomes
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much greater than conventionally assumed in a range of
thickness far thinner than is used conventionally.
The inventor has also found that if the
effective mobility of the polycrystalline silicon film
is sufficiently great~ a thin film of polycrystalline
silicon can be used to simplify the geometry and
fabrication of complementary MOS (C-MOS) integrated
circuits and so facilitate, for example, the fabrication
of high-density C-MOS inverters.
5~MMARY OF THE IDVENTION
Therefore, it is an object of the present
invention to provide a semiconductor device with a thin
polycrystalline silicon film ~erving as an active region
which has an effective mobility matching that of
single-crystal silicon.
Another and more specific object of the
present invention is to provide a semiconductor device
having an active region made of polycrystalline silicon
film of a specific thickness, specifically significantly
ZO thinner than conventional devices.
A further object of the invention is to
provide a high-density C-MOS integrated inverter circuit
employing a polycrystalline silicon thin film.
In order to accomplish the aforementioned and
other objects, a semiconductor device, according to the
present invention, is provided with a thin
polycrystalline silicon film formed on a semiconducting
or insulating substrate. The thickness of the film is
adjusted so as to afford the film a relatively high
effective mobility and low threshold voltage.
In the preferred embodiment, the thickness of
the thin film falls in the range of approximately 100A
to 750A. More preferably, the thickness of the thin
film is in the range of approximately 100A to 600A. In
the present invention, the effective mobility is
optimized in the thickness range of 200A to 500A.
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The present invention also cDncerns a
high-density C-MOS inverter IC employing the ~inventive
polycrystalline silicon layer deposited on a
6emiconductor ~ubstrate over an insulating layer.
According to one aspect of the invention, a
polycrystalline ~ilicon layer to be deposited on a
semiconductor 6ubstrate applicable to semiconductor
devices, characterised in that the polycrystalline
silicon layer 6erves as an active region of the
6emiconductor device and has a thickness in a specific
thickness range in which the polycrystalline silicon
layer exhibits a sufficiently high effective carrier
mobility and a 6ufficiently low hreshold voltage.
According to another aspect of the invention,
~5 a field effect transistor comprises a semiconductor
~ubstrate, a polycrystalline silicon active layer formed
on the substrate, the active layer having a thickness in
the range of loOB to 750A and forming therein a source
region and a drain region, a gate electrode formed on
the polycrystalline ~ilicon layer over an insulating
layer, and electrically conductive input/output
terminals in contact with the ~ource region and the
drain region.
According to a further aspe~t of the
invention, a process for fabricating a field effect
transistor having a semiconductor substrate, a thin
polycrystalline silicon film formed on the ~ubstrate, a
gate electrode formed on the polycrystalline silicon
film over an insulating layer, and input~output gates
connected to a source region and a drain region formed
in the polycrystalline silicon film, the process
comprises the steps of:
depositing polycrystalline silicon on the
substrate to a thickness in the range of lOOA to
750A; and
forming the gate electrode and inpu$/output
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terminals subsequent to formation of the polycrystalline
silicon film.
According to a sti:Ll further aspect of the
invention, an IC chip comprises a semiconductor
substrate, an insulating layer formed on the substrate;
a polycrystalline silicon layer formed over
the substrate and the insulating layer, a first
semiconductor device of a first conductivity type formed
on the polycrystalline silicon layer, and a second
~O fiemiconductor device of a second, opposing conductivity
type formed on the polycrystalline silicon layer.
According to a yet further aspect of the
invention, a process for producing an IC chip including
MOS transistors, comprises the steps of:
r5 forming an insulating layer over a
semiconducting substrate, the insulating layer leaving a
section of the semiconductor substrate exposed;
depositing a polycrystalline silicon layer over the
insulating layer and the exposed section;
forming MOS transistors on the polycrystalline
silicon layer over the insulating layer and the exposed
~ection; and
forming input/output terminals providing
external connections to and from the MOS transistors-and
connecting electrodes which connect the MOS transistors
to each other.
BRIEF DESCRIPTION OF TEIE DRAWINGS
.
The present invention will be understood more
fully from the detailed description given herebelow and
from the accompanying drawings of the preferred
embodiments of the invention, which, however, should not
be taken to limit the invention to the specific
embodiments but are for explanation and understanding
only.
In the drawings:
Fig. 1 is a cross-section of the preferred
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embodiment of a MOS TFT in accordance with the present
invention;
Fig. 2 is a gr~ph of the relationship between
effective mobility ~eff and the thickness of the
polycrystalline silicon film serving as the active
region of the MOS TFT of Fig. l;
Figs. 3(A) to 3(E) are cross-sections through
a C-MOS inverter IC according to the present invention
at five stages of its fabrication; and
Figs. 4~A~ to 4(E) are cross-sections through
a ~-MOS inverter IC similar to Figs. 3, showing a
modification to the embodiment of Figs. 3.
DESCRIPTION OF T~E ~REF~RRED EB ODIMæNT
Referring now to the drawings, Fig. 1 shows
t5 the preferred embodiment of a MOS thin film transistor
which will be referred to hereafter as "MOS TFTn.
According to the invention, a thin polycrystalline
silicon layer 12 is formed on a quartz substrate 10. The
polycrystalline silicon layer 12 has n-type regions 14
and 16 at either end, where it is heavily doped with
n-type impurities so as to have a relatively low
resistance to electron conduction. The n-type regions
14 and 16 respectively form a source region and a drain
region. The central section of the polycrystalline
silicon layer defines a channel between the ~ource
region 14 and the drain region 16 and serves as an
active region 18.
A gate insulating layer 20 made of silicon
dioxide ~SiO2) is deposited on the polycrystalline
silicon layer 12 so as to cover the active region 18. A
highly doped polycrystalline silicon (DOPOS) gate
electrode 22 is deposited over the gate insulator 20.
The gate electrode 22 is covered with a silicon dioxide
layer acting as an insulator 24. The insulator 24 is
formed with openings 26 and 23 through which connector
electrodes 30 and 32 are formed in contact with the
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source and drain regions 14 and 16 respectively.
Although it not clearly illust:rated in the drawing,
the gate electrode 22 is also connected to a connector `
electrode fabricated in a Per se well-known manner.
According to the preferred embodiment, the
thickness t of the polycrystalline layer 12 is adjusted
to be in the range of lOOA to 750A, preferably about
200A. This preferred thickness range has been derived
empirically from experiments performed by the inventor
with polycrystalline silicon layers of various
thicknesses. The results of these experiments are
illustrated in Fig. 2.
As will be seen from Fig. 2, the effective
mobility ~eff of the polycrystalline silicon active
region increases significantly as the thickness drops
from about lOOOA to about 200-500A. As the thickness of
the polycrystalline silicon layer drops below 200A, the
mobility decreases at a relatively high rate. Also, as
shown in Fig. 2, the effective mobility ~eff of the
polycrystalline silicon layer is maximized at a
thickness of about 200-SOOA.
In Fig. 2, curve A shows the behavior of the
effective mobility of a polycrystalline silicon layer
which is formed directly into the desired thickness- by
2~ the process of chemical vapor deposition. On the other
hand, curve B represents the characteristics of the
effective mobility of a polycrystalline silicon layer
which is first formed by chemical vapor deposition to a
greater than desired thickness and then reduced to its
final desired thickness by thermal oxidation. In
experiments involving samples A, a maximum effective
mobility of 7.2 cm2/V sec was achieved at a thickness
of 210A. On the other hand, experiments with samples B
revealed a maximum effective mobility of 12 cm2/v sec at
the thickness of 370A.
In the shown embodiment, the thickness of the
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polycrystalline silicon active region is chosen to be
200A, and so the effective mobility of an active region
sf type A will be about 7 cm2/V sec and in a circuit
employing a layer of type B, about 5 cm2JV sec.
Therefore, it should be appreciated that the mobility of
the polycrystalline silicon layer according to the shown
embodiment will be significantly higher than
conventional polycrystalline silicon layers. Since the
production costs of a polycrystalline silicon layer are
much lower than for a single-crystal silicon layer, the
overall production cost of MOS TFT's employing the
invention can be reduced without sacrificing any of the
functional advantages of a single-crystal silicon active
region.
~5 Figs. 3(A) to 3(E) show a sequence of process
steps during fabrication of a C-MOS inverter according
to present invention. In the preferred embodiment, the
thin polycrystalline silicon layer is used to good
effect in simplifying fabrication of the C-MOS inverter.
Fig. 3(A) shows the initial stage of
fabrication of the C-MOS inverter according to the
preferred method of the present invention. Field SiO2
layers 30 are formed on a P-type Si substrate 32 by
localized oxidation of silicon (LOCOS). LOCOS is
carried out over most of the substrate 32, excluding
only the section on which a MOS transistor is to be
formed. ~hereafter, a layer 36 of polysilicon or
amorphous silicon is deposited over the entire surface
by chemical vapor deposition.
If desired, Si+ or Ge+ ion implantation and
annealing for 15 hours at a temperature of 600C may
follow deposition of polycrystalline silicon or
amorphous silicon in the step shown in Fig. 3(B).
In the preferred embodiment, the thickness of
the deposited polycrystalline silicon layer falls in the
range of 20A to 750A, and preferably in the range of
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200A to 400A. ~olding the polysilicon layer to the
preferred range of thickness ensures that the effective
mobility will be adequately high and the leakage
current will be acceptably low.
After performing the process shown in
Fig. 3(B), the sections of the polycrystalline silicon
layer formed on the field SiO2 layer, appearing at the
edges of Fig. 3(B), are removed, as shown in Fig. 3(C).
Gate oxide layers 38 and 39 and gate electrodes 40 and
41 are formed at points on the polycrystalline silicon
layer 36 at which an N-channel MOS drive transistor 44
and a P-type MOS load transistor 46 are to be formed.
N-type ion implantation is performed on the
section 48 of the polycrystalline silicon layer 42 on
which the N-channel MOS drive transistor 44 is to be
formed, as shown in Fig. 3~D). The resulting N+
regions to either side of the gate 40 serve as source
region 50 and drain region 52 of the NMOS drive
transistor 44. Similarly, P-type ion implantation is
performed at the site of the P-channel MOS load
transistor 46 to form its source region 56 and drain
region 58. After this step, a relatively thick layer 60
of SiO2 is deposited over the entire surface of the IC
for insulation. Contact windows are etched through the
oxide layer 60 through which a source electrode 62, a
drain electrode 64 and a bridging electrode 66 which
bridges between the drain region 52 of N-channel MOS
drive transistor and the source region 56 of the
P-channel MOS load transistor can contact the
corresponding doped re~ions 50, 58, and 52~56~ as shown
in Fig. 3~E).
With the shown geometry, since the section of
the polycrystalline silicon layer 42 directly below the
gate oxide 38 is in direct contact with the
3~ single-crystal silicon substrate, the crystal grains of
the vapor-deposited polysilicon layer 36 will tend to
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grow large enough to minimize the effect of carrier
traps along grain boundaries. Furthermore, if an
additional annealing step is added following the Si+ or
Ge~ ion implantation process, the polysilicon layer may
fully recrystallize into a single-crystal silicon layer.
In either case, the source region and the drain region
formed in the polycrystalline silicon layer will have a
sufficiently high effective mobility.
According to the shown embodiment, the
fabrication process for a C-MOS inverter can be
significantly simplified. In particular, as set forth
above, the polycrystalline silicon layer is deposited
onto the areas of the substrate on which the N-channel
MOS drive transistor and the P-channel MOS load
transistor are to be formed prior to formation of the
N-channel MOS drive transistor which is conventionally
formed directly on the single-crystal silicon substrate.
This allows both of the aforementioned transistors to be
formed at the same time in a single step following
vapor-deposition of the polycrystalline silicon layer,
which has conventionally required at least two ~eparate,
independent steps. Furthermore, as the source regions
and drain regions of the N-channel MOS drive transistor
and P-channel MOS load transistor are formed in the same
polycrystalline silicon layer, connection of the drain
region of the N-channel MOS drive transistor to the
source region of the P-channel MOS load transistor is
greatly facilitated, in that the adjoining drain and
source regions can be connected simply by means of the
single bridying electrode. Additionally~ since the gate
electrodes for both of the transistors can be formed in
a single step and at the same time, connecting the
transistors to each otber requires only a single
phto-lithographic step and so obviates the need for the
additional steps needed in fabrication of conventional
transistors. Furthermore, since the source regions and
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drain regions may extend over wider areas than in
conventional devices, the contact windows need not be as
finely delineated, which further expedites the
fabrication process.
Figs. 4~A) to 4(E) show essentially the same
fabrication process for a C-MOS inverter as shown in
Figs. 3 but in this case the step illustrated in Fig.
4tB) includes the Si+ or Ge+ ion implantation and
annealling steps mentioned previously. All of the steps
o other than that shown in Fig. 4(B) are substantially the
~ame s described with reference to Figs. 3(A) to 3(E).
In the modified process, Si+ or Ge~ ion
implantation is performed following the step of
depositing polycrystalline silicon or amorphous silicon
on the P-type silicon substrate. Following ion
implantation, annealing is performed for 15 hours at a
temperature of approximately 600C. This improves
mobility characteristics of the polycrystalline silicon
layer significantly. Specifically, the ion implantation
and annealing steps increases the average polysilicon
grain size in sections ~here the polysilicon layer is in
contact with the single crystal layer to the point where
the layer 36 may be traversed by single crystal grains,
which makes the properties thereof essentially identical
to single-crystal silicon.
Although the illustrated embodiment concerns
an N-channel MOS transistor on a P-type substrate and a
P-channel MOS transistor on a field SiO2 layer, it would
be possible to form a P-channel MOS transistor on an
N-type silicon substrate and an N-channel MOS transistor
on the field SiO2 layer.
As set forth above, in accordance with the
present invention, all of the objects and advantages are
successfully achieved.
It should be appreciated that the present
invention can be embodied in many ways the specific
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embodiments disclosed are to be regarded as mere
examples for facilitating full understanding of the
principle of the invention. Therefore, the invention ~
should be understood as to include all possible
embodiments within the principle set out in the appended
claims.
