Note: Descriptions are shown in the official language in which they were submitted.
~5~5
ENHANCED CVSD APPARATUS
Field of the Invention
The present invention p~rtains to digital encoding of
analog signals, such a~ speech signals, and decoding of
resultan~ digital signals. In particular, the present
invention provide~ for the generation of digital output
signals fxom analog signal and reconstruction of the
analog signals based on the digital output signals.
Back~round of the Invention
Modern speech communication systems, such as common
carrier telephone ~y3tems~ digitally encode analog 3peech
signal~ for transmi~ion as a digital signal. At the
receiving end of the com~unication system, the digital
sign81 is used to reconstruct the analog speech signal.
The ~ommunication system mu~t he able to reconstruct the
speech signal at a quality that i5 intelligible at the
receiving statlon~
An analog speech signal has a characteristic of
continuously varying amplltude with time~ The rate at
which the analog speech slgnal is sampled for digital
encoding has an e~fect on the ability of the system to
reconstruct the analog signal from the digital signal
generated in the encoding process. Theoretically, for
s~andard pulse code modulatlon the encoding and r~covery
~s~
-- 2 --
process can be accomplished without substantially impairing
the reconstructed analog signal if the rate at which
samples are taken is at leas~ ~wice the rate of the highes~
frequency component of the analog signal, ~hat is, a~ the
Nyquist rate. For high quality reconstruction of the
analog signal, an even higher encoding rate is needed.
The rate at which the analog signal is sampled is called
the sampling rate of the encoding scheme. The
corresponding bit rate of the communication link is a
function of the sampling rate and the number of
quantization bits per sample ln the encoding ficheme.
Thus for high quality reconstruction of the speech
signal at the receiving station, a high bit rate is
necPssary. However a high bit rate digital signal requires
a correspondingly widP bandwid~h for transmission. So in
order to maximize ~he utilization of a given co~munication
system, a lower bit rate is desirable.
Several ~chemes are und r investigation for lower bit
rate encoding of analog speech data ~ithout sacrifieing
quality of the speech reconstructed at ~he receiving
station. One technique i5 termed adaptive delta modulation
or continuously variable ~lope delta modulation (CVSD).
The CVSD technique offers nearly the same voice
quality as s~andard 64 kilobit pulse code modulation using
only half of the digital bandwidth requir~d for the
standard ~ystems. See, nLowering PCM Encoding Rates
Provides More Channels~, TELEPHONY, September 12, 1983,
pp. 34-48.
_
~2S~865
-- 3 --
A GVSD ~ncoder operates by compari~g the received
analog signal with the signal ~hat has been r~constructed
from the digital output of the encoder. When the incoming
analog sig~al is at a level le3s than ~he reconstructed
signal, then the digital outpu~ et a~ a first value in
response to a clock~ When the incoming analog signal is
greater than the reconstructed signal, th~n the digital
output is ~et at another value in response to the clock.
The analog signal i~ recon~tructed ~rom t~e digital
signal by supplying the digital signal to an- integrator
with a continuously variable slope. ~he continuously
variable ~lope is cau~ed in response to an algorithm which
detects the occurrence of either a serie~ of ~hree or four
consecutive ones or a series of thre~ or four consecutive
zeros in the digital signal. Upon the occurrence of either
of those events, the Qlope is adjust~d in ord2r to attempt
to track the incoming analog signal m4re closely.
More information about a particular ~VSD encoder can
be found in Motorola, Inc. ~8 product literature for the
MC3417, MC3418, MC3517, MC3518 chip family. See, LINEAR
AND INTERFACE INTEGRATED CIRCVITS, ~otorola, 1983, Series
D, pp. 9-12 et. s~q.
Brie~ Description of ~he Drawin~s
Fig. 1 is a graph used in illustrating the ~VSD
technique as discussed in the Background of the Invention.
Fig. ~ is a block diagram of an encoding apparatus
according to the present invention for generating the
digital output from an analog ~ignal.
Fig. 3 i~ a block diagram of a decoding apparat~s
according to the present invention for receiving the
digital output and generating ~ reconstructed ~nalog
signal.
Figs. 4 and 5 ~oge~her make up a circuit diagram of a
preferred embodimant of a digital encoding apparatus
according to the present invention.
Fig. 1 i6 a graph illustrating the digital encoding of
an analog ~ignal accQrding to the ~VSD technique. The
analog ~ignal 10 shown as a ~inu~oid. The digital encoded
signal is shown at 11. And the reconstructed ~ignal output
from the integra~or of the CVSD apparatu~ hown at 12.
As can be ~een, th& digi~al output 11 iQ high when the
reconstructed signal 12 is at a level below the incoming
analog signal 10. When the reconstructed signal 12 cros3es
the analog signal 10, such as at point 13, the digital
signal ll ~wings low on the next cloc~. Thi~ oau~es the
sign of the ~lope of the recon~tructed signal 12 from the
integrator to rever~e a~ ~hown along the ~e~ment 14. ~t
the next clock cycle, the comparator will indicat~ that the
~2~
~ 5 --
analog signal lO i8 above the recon~tructed ~ignal 12 onc~
again and swing ~he digital output hiyh at point 15 which
reverses the sign of the slope of the recon~truc~ed signal.
This process continue~ for each clock cycle~
As can be seen in Fig. 1, the CVSD techniquP provides
relatively close approximation of the analog ~ignal input.
However, the level tracking of the CVSD output signal 11 is
relatively poor. Likewise the response of the CVSD digital
output signal 11 to fast change3 in the analog signal 10 is
relatively poor.
Summary of the Invention
The present invention provides an encoding technique
related to the CVSD technique just described. ~owever the
present invention provides capability for an improYed level
tracking and improvad response to ast changes in the
analog signal not possible in the prior art without
increases in the bit rate.
The present inYention provides an apparatu~ respon~ive
to a cl~ck ~ignal ha~ing serial clock cycles f~r digital
enc~ding of an analog ~ignal. The apparatus compri6es a
comparator mean for comparing the analog signal to a
reconstructed analog ~ignal and generating, in clock
cycles, digital output~ having a first value when the
analog ~ignal is greater than the reconstructed analog
signal and having a second value when the analog signal is
le~s than the recon~tructed analog signal. An ~ntegrating
means, responsive to a ~lope control signal, ~ included
for generating the recon~tructed analog ~ignal. A 810pe
~5
6 --
control means, responsive to the digital outputs~ generates
a slope control ~ignal in a given clock cycle.
The slope control means includes a means, respon~ive
to n digital outputs from n ~erial clock cycles, for
generating an m-dimensional digital vector signal, where n
and m are integers greater than one. ~urther, the ~lope
control means includes a means respon~ive to the
m-dimensional digital vector signal for generating the
slope control ~ignal for the given cycle.
The m-dimensional digital vector signal identifie a
plur~lity o~ condition~ of th~ n di~ital outputs. Thu~, in
re~ponse to the condition of n digi~al outputs a~ indic~ted
by the m-dimensional digital vector siqnal, the ~lop.
control means opexates to control the intesrating means to
g~nerate the recon~tructed analog signal.
In a preferred embodiment, the mean~ ~or generating a
~lope control si~nal further includes a means for storing
an m-dimensional weighting vector, a means for generating a
scalar product signal indicating a ~calar pr~duct of the
m-dimensional digital vector and the m~dimensional
weighting vector during the given clock cycle, and a means,
responsive to the scalar product signal, for genera~ing the
slope control signal~
,,
-6a-
Detailed Description
With reference to the Figures, a detailed descrip ion
of the present Invention is provided includin~ a system
overview and description of a particular circuit ~bodying
the invention,
A. System Overview
Fig. 2 shows in apparatus 10, according to the present
invention, responsive to a clock signal on line 11 fox
digital encoding of an anal~g i~put signal on line 12. The
i5
- 7 -
apparatu~ 10 comprises a comparatox means 13 for comparing
the analog signal to a reconstructed analog slgnal from
line 14 and for g~nerating durlng serial clock cycle~,
digital outputs on line 15 having a ~ir~ value when the
analog signal from line 12 is greater than th~
reconstruc~ed analog signal from l~ne 14 and a ~econd ~alue
when the analog signal from line 12 i8 less than th~
reconstructed analog signal from line 14.
The comparator means i3 include~ a comparator 16 which
generates an output indicating whe~her the analog signal
from line 12 is greater than or less tha~ th~ reconstructed
analog signal from line 14, and a sampling means 17 for
sampling the output of the comparator 16 in responce to the
clock slynal on line 11. The digital output from the
~ampling means 17 is provided to line 15. The digi~al
output may then be transmitted oYer a communlcation systPm
to a remote station for decoding and reco~truction of the
analog ~ignal as di cussed below wi~h re~rence to Fig. 3~
The reconstructed analog signal on line 14 i8 ~upplied
by an integrating means lB, r~sponsive to a ~lope control
signal on line 19 and digital output~ on li~e 15, for
generating the reconstructed analog signal. The
integrating means 18 includes a slope polarity switch 20
and an integrator 21.. The integrator 21 generates the
reconstructed analog signal by ~upplying an output having a
slope controlled by the slope control signal on line 19 and
a polarity controlled by the slope polarity ~witch 20 in
response the digital output~ from line 15. ~ slope control
_
~.5~
means, shown generally at 22, qenerates tha ~lope control
signal on line 19 in a current clock cycle in response to a
plurality of digital outputs from line 15 from n serial
clock cyclesO The slope eontrol means 22 may include a
shift register 23 or other means for storing digital
outputs from serial clock cycles. The n digital outputs
from n ~erial clock cycles are supplied over line 24 to a
decoder 25.
The decoder 25 comprises a means, responsive to the
digital outputs on line 24, for generating an m-dimensional
digital v~ctor signal on line 26. Last/ a means sho~n
generally at 27, responsive to the m-dimen~ional vector
~ignal from line 26 generate~ a slope control cignal on
line 19.
The means 27 for generating the ~lope ~ontrol signal
includes a means 28 for generating analog scalar product
signal in r~sponse to the digital vector signal from line
26. The means 28 includes a means for storing a constant
m-dimensional weighting vector. The means 28 generates the
scal~r product signal on line 29 which indicates a scalar
product of the m-dimensional digital vector ~ignal and
m-dimensional weighting vector during a given clock cycle.
Last, a means, shown generally at 30, responsiv~ ~o the
scalar product signal on line 29, generates the slope
control ~ignal.
The scalar product signal i~ a multilevel impulse, the
lev~l of which is determined in each clock cycle by changes
in the m-dimensional digital vector signal.
~5.~
g
The means 30, responsive to the scalar product signal
on line 29, includes a filter means 31 for low pa~s
filtering the scalar product ~ignal ~o generate a filtered
scalar produc~ signal on line 32, arld a converter means 3~
for logarithmically converting the scalar produc:lt sigrlal to
generate the slope control signal.
The operation of the slope control means 22 carl 3: e
theoretically described as follos./s. The ~hift register 23
stores n digital outputs from the curren~ ~lock cycle and
the (n-l) preceding ~erial clock cycle Thus, ths outp~t
on liile 24 from the shift register 23 can be r~:presented as
an n~dimensional digital vector (Bi), for i = 1 to n. The
digital vector IBi) will change during each clock cycle as
the digital output from line 15 is passed through the shift
register 23. Note that, in practice, a ~hift register for
all n bits need not be used in all application~ as shown in
the preferred embod~ment de~cribed with refer~nce to Fig~.
4 and 5.
The decoder 25 receive~ the vector ~ a~d generats~
an m-dimensional digital vector signal which indicates a
plurality of conditis:~ns of the n digi~al output as
ref lected in the vector IB~ ) .
In the preferred erlibodiment, the m-dimensional digital
vec~or is defined as (Cj), for j - 1 to m, where C; is true
when Bl through Bm+j are equivalent, and n is equal ~o 2m.
S~tisfactory result~ are obtained with n = 6 and m = 3 for
speech encoding system~.
.~25~8~5
The means 28 for generating the scalar product signal
stores an m-dimensional weighting vector (Wj), for
j - 1 to m. A preferable vector for speech encoding
systems is defined by (Wj~ = 2j lk, for j = 1 to m. Thus
for m = 3, the weighting vec~or (Wj) would equal ~k, 2k,
4k). The constant k is a parameter selected to optimi~e
the companding ratio of the encoding apparatus lO as
discus ed below.
The scalar product signal on line 29 iDdicates tbe
value of the scalar product of the vector (Cj~ and ~he
vector (Wj). Thus, scalar output signal S is equal to the
summation of Wj times Cj~ for j = 1 to m, for each clock
cycle.
~ he scalar product signal S supplied on line 29 passes
~hrough the filter means 31. Preferably, the filter means
31 is low-pass filter having a single pole w~th a time
const~nt of about 33 milli~econds fox a peech enco~ing
system. The filtered ~calar product signal on line 32 is
supplied to a converter 33 which generates a 810pe control
signal on line 19. .In the preferred embodimen~r the
converter 33 has a logaxithmic transfer function so that
the slope control signal on line ~9 increases exponen~ially
as the filtered scalar prod~ct signal on line 32 increases.
For speech encoding ~yst~ms t the combination of the
filter means 31 and the converter mean~ 33 provide a slope
control signal on line 19 which has a time constant o~
approximately 6 milliseconds in the center of the useful
dynamic range of levels for the signal.
~% 5 ~
As mentioned above, the constant k controls ~he
companding ratio for the apparatu~ 10. It i~ found that
good results ~r~ obtalned by ohoosing appropriatQ
companding ratio~ at various audio signal levels for speeoh
encoding sy~tems. It is found that a companding ratio o~
13% i5 desirable for a sign~l level of the analog input on
line 12 of +6 dBm. For a ~ignal level of -40 dBm, a
companding ratio of 3% generate~ gsod results.
The companding ratio ls defined as a relative
frequency of the occurrence o~ either four (4~ consecutive
l's or four (4) consecutive 0'8 ~n the digi al output on
line 15. The companding rati~ ha~ a ~tatistical
correlation to the level o~ the incoming analog signal.
The companding ratio can be decrea~ed by lncreasing the
average ~lope output from the int~grator 21 a~d it can be
increased by decrea~ing the average ~lope o~ the output
from integrator 21. So according to the present invention
by increasing the constant parameter k, the companding
ratio is decreased and, corre~pondingly by decreasing the
constant k, the companding ratio can be increa~ed. Thus
the companding ratio of the encoding apparatu~ 10 can be
controlled hy varying the constant k.
Fig. 3 shows a block diagram of a receiving, or
decoding, apparatu~ 50 according to the present invention
for receiving the digital output 5ignal5 from line 51,
which may be for in tance a transmi~io~ link, and for
g nerating a reconstructed analog ~ignal on llne 52 for use
at the receiving apparatus 50. A~ can be ~een, the
:~`2~
- 12 -
components in the receiving appara~u-~ 50 of Fig. 3 are
identical to the components of the ~lope control means 22
and the integrating means 18 shown in Fig. 2. Accordingly,
the part~ have been given iden ical r~ference numerals
where appropriate. Also the description of the parts as
provided above applies equally to the xeceiving apparatus
of Fig. 3. Fig. 3 illustra~es that a receiving
appara~us 50 need not have the comparator 16 and the
sampler 17 tha a transmitting ~tation must have as shown
in Fig. 2.
By assuring that the 810pe con~rol means 22 and the
integrating means 18 at a receiving apparatus 50 operate in
a manner su~stantially identical to thos~ a~ the
~ransmi~ting station, a true reconstructed analog signal 52
will be generated.
B. Description of ~ircuit Diagram
Figs. 4 and 5 illu~trate an encoder circuit 100
according to the present inventionO The en~oder circuit
100 is made up of th.ree t3) distinct ~ection~; a~ analog to
digltal converter ~ection 6hown yenexally a~ 101, a
logarithmic converter section shown generally at 102, and
decoding logic and filter section shown gen rally at 103.
The decoding logic and filter section 103 is depicted in
Fig. 5, while the analog to digital CQnverter section 101
and the logarithmic converter ~ection 102 are ~hown on Fig.
- 13 -
The analog to digital co~verter section 101 ia
implemented u~ing a Motorola integrated circuit designated
3418. The characteris~ics of the 3418 can be found in
Motorola Inc. data book entitled LIN~AR AND INTERFACE
INTEGRATED CIRCUITS, 1983, Seri~s D. The nu~bered line~
1-16 entering the 3418 correspond to the pin connections
for the chip. Details of the connection of the 341B can be
understood by a study of th~ specifications and
application~ information provided by Motorola i~ ~he LINEAR
AND INT~FACE INTEGRATED CIRCUITS. Basically, the analog
speech signal is received at the input line 104 and
supplied to the pin connection 1 of the 3418. The 3418
compares the input analog signal from line 104 with the
reconstructed analog signal from the integrator 105 which
is fed back through pin 2 of he 34180 The 3418 includes
the comparator 16 and ~ampler 17 a~ shown in Flga. 2 and 3
and gen~r~te~ a dlgltal output vn pin 9 ~or transmi~ion
acros~ line 160. A l~vel ~hi~ting circuit 170 i~
connectPd between pin 9 and line 160 to make th~ ~ignal on
line 160 compatible with com~unication hardware using
TTL-LS circuitry.
The resistor and capacitor network at pins 5, 6 and 7
of the 3418 define the basic characteri~tics of the
integrator.
The signal supplied at pin 15 of the 3418 from line
106 i~ an enabletdisable input which enable~ the 3418 when
it is high and causes an output on line 9 of a 1 - 0
pattern when it is low. The 1 - 0 pattern i8 generated
because the 341B perform~ a function of a receiver
apparatus 50 of Fig~ 3 when connected with a digital input
at pin 13. ~y connecting pin 13 in a faedback relationship
with output pin 9, and disabling the encoding func~ion by a
low input at pin 15, the 1 - 0 digital output is generated.
However when the input at pin 15 acro~s line 106 is high,
the fPed'oack to pin 13 has no effect~
The pins 3, 4 and 11 of the 3418 are i~portant to the
present invention. The pin 3 receives an input from the
filter 107 across line 108~ The filter 107 is shown in
Fig. 5. Thus, the signal on line 108 correspo~d~ to the
iltered scalar pro~uct signal on line 32 of Fig. 2.
The pin 4, which correspo~ds to line 19 of Fig. 2,
r~ceives the ~lope control ~ignal from ~he logari~hmic
converter section 102 which corre~pond~ to converter 33 of
Fig. 2. The 3418 causes a voltage at pin 4 which matches
the voltage of pin 3. Thus, the logarithmic converter in
sec~ion 10~ ~upplies a current at pin 4 which varie~
exponentially with respect to the voltage at pi~ 4O In the
embodiment ~hown, as the voltage at pin 4 varies from about
0.3 - 1.2 volts, the current generated as the slope control
signal varies from about 10 microamps to 2 milliamps.
Pin 11 of the 3418 is an output which indicates the
occurrencs of four ~4) con~ecutive equivalent data bits,
termed the coincidence outputO The coincidenc~ output from
pin 11 is supplied acrosq line 109 and goe~ low upon the
occurrence of four (4) consecutive equivalent data bits.
s
The 3418 include3 a shift regi~ter which s~ores serial
data bits and generate6 the coincidence output at pin 11
upon the occurrence of 4 equivalent serial data bits.
The coincidenc~ output is supplied acro3~ line 109 to
the decoder logic shown generally at 110 of Fig~ 5. The
dscoder logic 110 consi~ts of a serie~ of flip-flops who~e
Q ou~puts respectively make up the vector ~C~) as described
above. When the coincidence output from line 199 goes low,
flip-flop 111 on the next clock cycle will cause Q to go
high and Q to go low. The Q output from ~lip-flop 111 i~
suppliad to the OR-gat~ 112 as one input. Th~ other input
to OR-gate 112 i~ the coincidence output on lin~ 109. ~hu~
when the coincidence output i~ low and Q of flip-flop of
111 i~ low, the D input of flip-flop 113 yoes low. ~hen
the D input of flip-~lop 113 goes low, the Q output gv~s
high on the n~xt clock and the ~ output goes low. The Q
sutput is ~upplied to the OR-gate 114 as one input. The
other input to the OR-gate 114 i~ the ou~put of the OR~gate
112. ~hu~, when the output of OR-gate 112 1~ low and th~ Q
output of flip-flop 113 iQ low, the D ~nput to flip~flop
115 goes low causing the Q output of flip~flop 115 to go
high on the next clockO
A~ shown in Fig. 5, the flip-flop~ 111, 113~ 115 are
implemented using an in~egrated circuit designated 40175B
which includes a ~ourth flip-flop 201 and has a si~gl~
clock input, pin 9, and single power ~upply input, pins 1
and 8, as shown on the fourth flip-10p 231. Thus the
clocX ~ignal at pin 9 of the flip-flop 201 is s~pplied in
- lS -
pha~e to each of the flip-flops 111, 113, ~lS, although the
connections are not explicit in Fig. 5. Al~o, the single
power qupply connection power~ each flip-flop 111, 113,
115.
B~cauce the clock ~ignal from line 151 is supplied a~
a TTL level compatible with the 3418(See, Fig. 4~, a
non-inverting level shift circuit 202 i8 provided that
shifts the clock level to a CMOS level compatible with ~he
40175B.
Thus it can be seen that the Q outputs of the
flip-flops 111, 113~ and 115 correspond to Cl, C2 and C3,
respectively, of the vector ~Cj), for j = 1 to 3, as
discussed above.
The FET trancistor~ 116, 117, 118 recaive the Q
outputs from the flip-flop~ 111, 113 and 115r respectively,
at their gates. When one of the FET tra~ tors, such as
116, receives a high input at it8 gate, it turn~ on
allowing current to pa88 through the re~istor connected to
i~8 drainO The amount of current which i~ draw~ through
the turned on FET is determi~ed by the value of the drain
resistor~ The drain resi~tor~, 119; 120, and 121
correspond to the mean~ for storing the weighting vector
(Wj) in the means 28 for generating the analo~ scalar
product signal. Thus drain resistor 119 is twice the value
of drain resistor 120 whiGh is in turn twice ~he value of
the drain resistor 121. The value of th~ xe~istance also
i~ set in accordance with the paramet~r k a~ discussed
above to provide th~ de~irable compandi~g ratlo for the
- 17 -
apparatus 10. The ~calar product signal i3 supplied as a
current across line 122. The current acros~ line 122 iB
suppliad to the filter 107 which is made up of the
capacitor 123 and the re~i~tor 12~. The t~me csnstant of
the ~ilter 107 is about 33 milli~econd~ in the preferred
ambodiment. This filter 107 corresponds to the low pass
filter 31 of Fig. 2. Thus, the voltage at line 108 is a
filtered ~calar product ~ignal curresponding to line 32 of
Fig. 2 and is supplied to pin 3 of the 3418 (see, ~ig. 4).
As m~ntion~d above, the voltage a~ pin 4 is made to
~rack the voltage at pin 3 and dr~ws a curr~nt from the
logarithmic converter section 102. The logarit~unic
conv~rter section 102 corresponds to the co~verter 33 of
Fig. 2.
The logarithmic converter section 102 (Fig. 4~
comprises diodes 125, 126 and 127 which provide ~he
exponential characteristic for the curre~t flowing into pin
4 of the 3418.
The diodes 128, 129 and 130 in conjunction with the
OPamps 131, 132 and 133 provide temperature compensation to
stabilize the tra~sfer charac~eristic of the logarithmic
converter section 102 over a range of oper~ting
temperatures.
The three stages of the logarithmic converter section
102, corresponding to the three diodes 125, 126 and 127,
combine to provide a superior transfer characteri~tic over
a wide range of currents. The first stags comprisad of
diode 125 provides low current characteris~ics. The second
i5
stage comprised of transistor 126 provides medium current
characteristics. While th~ la~t stage compr~sed of diod~
127 pxovideæ high currsnt charact~ri~tic3. At the high
current characteristics, an additional current booster made
~p of transistors 140, 141 i~ proYided for the embodiment
shown.
The output at line 150 i~ a logic threshold output
utilized for some application~. Input line 151 provide~
the clock input. Although it i~ not show~, ~he clock also
is supplied to the decoder logic flip-flops 111, 113 and
115 for controlling the latching of ~he flip-flops. The
balance of the inputs ~hown provide power supply voltages
as shown.
The values for the resistors and the capacitors and
the part numbers for the diode'~, tran~i~tor~, OPamp~, etc~
are preferred v~lue~ and components for an embodiment of
the invention for ~peech encoding aæ presently understo~d.
The detailed description of some of the connections for $he
particular I/Cs chosen to implement the parts of ~he
circuits shown in Fig. 4 and 5 may not be shown or
discussed in order to simpl fy the specification and
drawing. ~owever, any connections whlch ar~ ~ot shown or
discussed can be determined from a study of th~ product
literature for the part~cular I/C chosen.
A receiving apparatus 50 as shown in Fig. 3 can be
implemented using equivalent components as those shown i~
Figs. 4 and 5, ~upplying the ~ran~mitted digital si~al
such as across line 106 to the pin 13 of the 3~18 (not
- lg -
shown). Pins 1, 2 and 9 ar~ grounded according to the
characteristics of the 3418 in the receiving apparatus
application. A reco~tructed ~nalog signal would be
supplied at the int~grator connected at pi~8 5, ~ and 7 of
the 3418.
In summary, accord~ng to the pre~ent invention, ~VSD
encoding techniques can be improved by de ecting a
plurality selected conditions of a plurality of serial
digital outputs and assigning a weight tv ~ach of tho~e
conditions according to desired operating çharacteristics
to generate a ~lope control signal for tha integrator that
reconstructs the analog ~ignal.
The foregoing de~cription of a preferred embodimPnt of
the inve~tion ha~ been presented for purposes of
illustration and description. It is not intended to be
exhaustive or to limit the invention to th~ pracise orm
di~clo~edt and obviou~ly many modifications and variation~
are possible in light o~ the above teaching. The speech
signal encoding embodiment was chosen and described in
order to best explain the principles of the invention and
it~ practical application to thereby ~nable othar~ skilled
in the art to best utilize the invention in various
embodiment~ and various modifications as are suited to the
particular use contemplated. It is intended that the scope
of the invention be defined by the claims app~nded hereto.
