Note: Descriptions are shown in the official language in which they were submitted.
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DIGITAL DISPLAY TIMEPIECE
CROSS-REFERENCE TO RELATED APPLICATIONS
This relates to my application No. 524,804, filed on Dec.
9, 1986, entitled Variable Colour Digital Timepiece, now
Canadian Patent No. 1,232,144, issued on Feb. 2, 1988, in
which is described a timepiece including a variable colour
display for simultaneously indicating time in digital format
and values of a diverse quantity in variable colour.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to timepieces utilizing variable
colour digital display.
2. Description of the Prior Art
A digital electronic timepiece disclosed in U. S. Pat.
No. 4,044,546, issued on Aug. 30, 1977 to Mitsuo Koike,
utilizes a variable colour liquid crystal 2~digit display on
which seconds, minutes, hours, days, and dates may be
sequentially displayed in respectively different colours.
A digital electronic watch for discriminating a. m. and
p. m. times by altering the colour of a digital indicator
for indicating time is disclosed in Japanese Pat. No. 107984
issued on Aug. 19, 1980 to Toshiyuki Itou.
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SUMMARY OF THE INVENTION
It is the principal object of this invention to provide
an improved variable colour digital timepiece capable of
simultaneously indicating values of time and their relation
to predetermined low and high time limi-ts.
In summary, a timepiece of the present invention includes
a timekeeping device for measuring time and a variable
colour digital display for exhibiting a digital indication
of time. A comparator is provided for comparing the instant
measured value of time with a low time limit and a high time
limit, respectively stored in limit memories, and for
developing comparison signals accordingly. Colour control
responsive to the comparison signals causes the digital
indication to illuminate in a colour in accordance with the
relation of the instant value of time to the low and high
time limits.
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BRIEF DESCRIPTION OF THE DRAWINGS
In the drawings in which is shown the preferred
embodiment of the invention,
FIG. 1 is a simplified schematic diagram of a digital
timepiece with variable colour display.
FIG. 2 is a schematic diagram of one variable colour
display element.
FIG. 3 is an enlarged cross-sectional view of one
display segment in FIG. 2, taken along the line 3 - 3.
FIG. 4 is a schematic diagram showing the detail of the
limit comparator in FIG. 1.
Throughout the drawings, like characters indicate like
parts.
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DESCRIPTION OF THE PREFERRED EMBODIMENT
Referring now, more particularly, to the drawings, in
FIG. 1 is shown a simplified schematic digram of a variable
colour digital timepiece of the invention. The clock pulses
99 of a stable frequency are applied to clock pulse input CP
of decade counter 39a, referred to as Units Counter, for
incrementing its contents at regular time intervals, e. g.,
once a minute. The terminal count outpu~ TC of counter 39a
is coupled to CP input of counter 39b, referred to as Tens
Counter, for incrementing its contents ten times slower.
The circuit including 3-input NAND gate 36 and inverter 35
serves to reset counter 39b when it attempts to reach the
count of 6, thereby allowing it to count only from 0 to 5.
The accumulated counts in counters 39a and 39b, representing
the time code, are available at the outputs Q0, Ql, Q2, and
Q3 of counters 39a and 39b, which are respectively coupled
to inputs A0 to A3 of 7-segment decoders 22a and 22b. The
outputs a, b, c, d, e, f, and g of decoders 22a and 22b are
directly coupled to like inputs a, b, c, d, e, f, and g of
display element 42a, for indicating minutes, and of display
element 42b, for indicating tens of minutes, to exhibit the
value of time in digital format on display 40 in a manner
well understood by those skilled in the art. It would be
obvious to add additional counters and display elements to
provide indication of hours and seconds.
The invention resides in the addition of a limit
comparator 31, having its inputs AO to A7 respectively
coupled to outputs QO to Q3 of counters 39a and 39b, for
comparing the instant value of the time code, representing
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the displayed value of time, with a low time limit, stored
in a low limit memory 33a, and a high time limit, stored in
a high limit memory 33b. Limit comparator 31 develops
active comparison signal WITHIN for the value of the time
code being within the bounds of the low time limit and the
high time limit, active comparison signal BELOW for the
value of the time code being less than the low time limit,
and active comparison signal ABOVE for the value of the time
code being larger than the high time limit. The colour
control inputs R (red), Y (yellow), and G (green) of display
elements 42a and 42b are respectively interconnected, for
causing them to illuminate in a uniform colour, and coupled
to comparator outputs WITHIN, BELOW, and ABOVE. The display
elements 42a and 42b illuminate in green colour in response
to active comparison signal WITHIN, in yellow colour in
response to active comparison signal BELOW, and in red
colour in response to active comparison signal ABOVE. It
would be obvious that the colour sequences could be readily
changed by differently interconnecting the outputs of limit
comparator 31 with the colour control inputs of display 40.
In FIG. 2 is shown a schematic diagram of 2-primary
colour common cathodes 7-segment display ele~ent 42 which
can selectively display various digital fonts in different
colours. The display element 42 includes seven elongated
display segments a, b, c, d, e, f, and g, arranged in a
conventional pattern, which may be selectively energized
in different combinations to display desired digits. Each
display segment includes a pair of LEDs (light emitting
diodes): a red LED 2 ancl green LED 3, which are closely
adjacent such that the light signals emitted therefrom are
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substantially superimposed upon each other to mix the
colours. To facilitate the illustration, the LEDs are
designated by segment symbols, e. g., the red LED in the
segment a is designated as 2a, etc. The anodes of all red
and green LED pairs are interconnected in each display
segment and are electrically connected to respective outputs
of a commercially well known common-cathode 7-segment
decoder 23. The cathodes of all red LEDs 2a, 2b, 2c, 2d,
2e, 2f, and 2g are interconnected to a common electric path
referred to as a red bus 5. The cathodes of all green LEDs
3a, 3b, 3c, 3d, 3e, 3f, and 3g are interconnected to a like
common electric path referred to as a green bus 6. The
colour of the display element may be controlled by applying
proper combinations of logic level signals to colour control
inputs R (red), Y (yellow), and G (green).
The operation of display 42 will be explained on example
of illuminating digit '7' in three different colours. Any
digit between 0 and 9 can be selectively displayed by
applying the appropriate BCD code to the inputs A0, Al, A2,
and A3 of decoder 23. The decoder 23 develops drive signals
at its outputs a, b, c, d, e, f, and g for energizing
selected groups of the segments to visually display the
selected number, in a manner well known to those having
ordinary skill in the art. To display decimal number '7',
a BCD code 0111 is applied to the inputs A0, Al, A2, and A3.
The decoder 23 develops high voltage levels at its outputs
a, b, and c, to illuminate equally designated segments, and
low voltage levels at all remaining outputs, to extinguish
all remaining segments d, e, f, and g.
To illuminate display ~2 in red colour, the colour
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control input R is raised to a high logic level, and colour
control lnputs Y and G are maintained at a low logic level.
As a result, the output of OR gate 60a rises to a high
logic level, thereby forcing the output of inverting buffer
63a to drop to a low logic level. The current flows from the
output a of decoder 23, via red LED 2a and red bus 5, to
current sinking output of buffer 63a. Similarly, the current
flows from the output b of decoder 23, via red LED 2b and
red bus 5, to the output of buffer 63a. The current flows
from the output c of decoder 23, via red LED 2c and red bus
5, to the output of buffer 63a. As a result, the segments
a, b, and c illuminate in red colour, thereby causing a
visual impression of a character '7'. The green LEDs 3a,
3b, 3c remain extinguished, because the output of buffer
63b is at a high logic level, thereby disabling green bus 6.
To illuminate display 42 in green colour, the colour
control input G is raised to a high logic level, while the
colour control inputs R and Y are maintained at a low logic
level. As a result, the output of OR gate 60b rises to a
high logic level, thereby forcing the output of inverting
buffer 63b to drop to a low logic level. The current flows
from the output a of decoder 23, via green LED 3a and green
bus 6, to current sinking output of buffer 63b. Similarly,
the current flows from the output b of decoder 23, via green
LED 3b and green bus 6, to the output of buffer 63b. The
current flows from the output c of decoder 23, via green LED
3c and green bus 6, to the output of buffer 63b. As a
result, the segments a, b, and c illuminate in green colour.
The red LEDs 2a, 2b, 2c remain extinguished because the
output of buffer 63a is at a high logic level, thereby
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disabling red bus 5.
To illuminate display 42 in yellow colour, the colour
control input Y is raised to a high logic level, while the
colour control inputs R and G are maintained at a low logic
level. As a result, the outputs of both OR gates 60a, 60b
rise to a high logic level, thereby forcing the outputs of
both buffers 63a, 63b to drop to a low logic level. The
current flows from the output a of decoder 23, via red LED
2a and red bus 5, to current sinking output of buffer 63a,
and, via green LED 3a and green bus 6, to current sinking
output of buffer 63b. Similarly, the current flows from the
output b of decoder 23, via red LED 2b and red bus 5, to
the output of buffer 63a, and, via green LED 3b and green
bus 6, to the output of buffer 63b. The current flows from
the output c of decoder 23, via red LED 2c and red bus 5, to
the output of buffer 63a, and, via green LED 3c and green
bus 6, to the output of buffer 63b. As a result of blending
light of red and green colours in each segment, the segments
a, b, and c illuminate in substantially yellow colour.
In FIG. 3, red LED 2e and green LED 3e are placed on the
base of a segment body 15, which is filled with a
transparent light scattering material 16. When forwardly
biased, LEDs 2e and 3e emit light signals of red and green
colours, respectively, which are scattered within the
transparent material 16, thereby blending the red and green
light signals into a composite light signal that emerges at
the upper surface of the segment body 15. The colour of
the composite light signal may be controlled by varying the
portions of the red and green light signals.
In the detail of the limit comparator shown in FIG. 4,
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8-bit time code from the outputs QO to Q3 of counters 39a
and 39b, shown in FIG. 1, is respectively applied to
interconnected inputs AO to A7 of digital comparators 32a
and 32b. The 8 bit data stored in low limit memory 33a,
representing the low time limit, are respectively applied
from outputs QO to Q7 to inputs BO to B7 of digital
comparator 32a; the 8-bit data stored in high limit memory
132b, representing the high time limit, are respectively
applied from outputs QO to Q7 to inputs BO to B7 of digital
comparator 32b. The digital comparators 32a and 32b effect
a comparison between the value of the instant time code and
low and high time limits and accordingly develop the output
signals '<', '=', and '>'. When the time code is less than
the low time limit, the output '<' rises to a high logic
level to develop active comparison signal BELOW for
illuminating display 40 in yellow colour. When the time
code is greater than the high time limit, the output '>'
rises to a high logic level to develop active comparison
signal ABOVE for illuminating display 40 in red colour.
When the time code is between the low and high time lirnits,
one of inputs of each OR gates 60c, 60d rises to a high
logic level, thereby forcing both inputs of AND gate 37 to
rise to a high logic ]evel, which in turn causes its output
to rise to a high logic level to develop active comparison
signal WITHIN for illuminating display 40 in green colour.
Although not shown in the drawings 9 it will be appreciated
tha-t the timepiece of the invention may have any conceivable
form or shape, such as a wrist watch, pocket watch, clock,
alarm clock, and the like. Alternatively, the timepiece may
have characteristics of an article for wearing on a body of
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wearer or for securing to wearer's clothing, such as a
bracelet, ring, ear-ring, necklace, tie tack, button, cuff
link, brooch, hair ornament 7 and the like, or it may be
built into, or associated with, an object such as a pen,
pencil, ruler, lighter, briefcase, purse, and the like.
In brief summary, the invention ~escribes a method of
simultaneously indicating values of time and their relation
to predetermined low and high time limits, on a single
variable colour digital display, by causing a digital
indication of time to be exhibited on the display, and by
illuminating the digital indication in one of three
respectively different colours in accordance with its
relation to the time limits.
A variable colour digital timepiece was disclosed which
includes a timekeeping device, variable colour digital
display for providing a digital indication of a value of
time, and a comparator for comparing the instant value of
time with predetermined low and high time limits, defining
three time ranges, to determine in which time range the
value of time lies, and for developing comparison signals
accordingly. Colour control responsive to the comparison
signals is provided for illuminating the digital indication
in respectively different colours in accordance with the
time range in which the value of time lies.
It would be obvious that modifications may be made in the
construction of the preferred embodiment, without departing
from the spirit of the invention as defined in the appended
claims. The principles of the invention may be also applied
to numerous diverse types of display devices, such are
liquid crystal, plasma devices, and the like.
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CORRELATION TABLE
This is a correlation table of reference characters, their
descriptions, and examples of commercially available parts.
# DESCRIPTION EXAMPLE
2 red LED
3 green LED
red bus
6 green bus
15 segment body
10 16 light scattering material
22 7-segment decoder
23 common cathode 7-segment decoder 74LS49
31 limit comparator
32 digital comparator
33 limit memory 74HC373
35 inverter 74HC04
36 3-input NAND gate 74HC10
37 2-input AND gate 74HC08
39 4-bit decade counter 74HC160
20 40 variable colour display
42 2-LED variable colour display element
60 2-input OR gate 74HC32
63 inverting buffer 74LS240
99 clock pulse
