Note: Descriptions are shown in the official language in which they were submitted.
~2~q6~
This i~ a divisional of Canadian application Serial No.
483,270 filed June 5, 1985, which in turn is a divisional of
application Serial No. 404,493 filed June 4, 1982.
~ACKGROUMD ~ND SUMMARY OF THE INVENTI~N
Often one desire6 to digitize an analog signRl which h~s
an input magnitude which fluctuates beyond the lineAr digitizing
r~nge of an ~nalog to digital converter. To handle this problem,
converter having a wider digitizing range must be used, which
increflses costs, or the input signal must be reduced in ~mplitude
prior to being digitized, which may introduce errors into the
digitized value and which requires a multipllc~tion factor to be
used in connection with the digitalized value.
One object of the invention is the provision of a simple
digital automatic gain control circuit which ~uto~tic~lly pl~ces
signal to be digitalized lnto a proper digitizing rAnge and
which also stores a digital indic~tion of how much the signal was
modified to place ~t in the proper digitalizing range.
Another ob~ect of the invention is the provision of an
automatic digital gain control circuit which is used ~n a power
meter employed in ~ centralized d~ta communications system to
adjust the level of ~n incom~ng signal to be within a
predetermined measurement range of power measuring equipment.
These ~nd m~ny other ob~e~t~, ~e~tures ~nd ~dvant~ges of
the invention w}lI become evident fron the following detaiIed
description which is presented in con~unction with the ~ccomp~ny-
lng dr~wings.
BRIEP D~9C~IPTION OF THE DRAWINGS
Fig. I is ~ block diagr~n of the d~td eomnunic~tions
system of th~ invention;
P~g. 2 is ~ schem~tic diagram of the remote stations
IIIustrated in Pig. l;
~ igs. 3 ~nd 4, tsken together, form a sch~matic diagram
of one of the section ~witches Illustrated in ~ig. I;
~ igs. 5, 6A and 6B, taken together, form ~ ~chematic
diagram of the ~ontroller interface illustr~ted in Fi~. l;
6~3~
Fig. 7 is a schem&tic diagrQm of the muster controller
illustrsted in Pig. l;
Figs. 8A and 8B, taken together, form a schematic dia-
gram of the A/D converter illustrated in Fig. l;
Fig. 9 is an overall system flowchart for the operation
of the computer illustrated in Fig. l;
~ig. 10 is ~ flowchart of the initi~lization program
illustrated in Fig. 9;
~igs~ 11 and 12 are ~lowcharts of the m~ster timer in-
terrupt program illustrated in ~ig. 9;
; ~ig. 13 iS R flowchart showing the essential steps of
the datQ collecting ~nd p~o~essing progrnms illustrated in Fig. 9,
~ig. 1~ is a ~lowchart of a sensor interrupt progr~m;
Pig. 15 is a flowch~rt of the program of ~ig. 13 as
specifically configured to gather and process data for & resist-
snce measurement;
~igs. 16A and 16B taken together form a flowchart of the
progr~m o~ Pig. 13 as specifically configured to gather and pro-
cess data for a precision resistance change measurement;
Fig. 17 is a flowchart of the Fig. 13 program as spe-
cificQlly configured to gather snd pro~ess d~ta for a DC voltage
measurement;
Figs. 18A, 18B, 18C and 18D together form a flowchart of
the Fig. 13 program as specifically configured to gather and pro-
cess data for an AC power measurement;
Pig. 19 is a flowchart of a program for processing of
gathered calibration data;
Pig. 20 is a flowchart of a program for processing
gathered AC power measurement data;
3a Fig. al is a flowchart of a program for processing
gathere~ air tempera~ure data;
lZ~6~3~
Fig. 22 is ~ ~lowchart of a progr~m for processing
g~thered fire condition dat~;
~ ig. 23 is a ~lowch~rt of a progr~m for processing
gathered ~luid fIow d~ta;
: Pig. a~ is a ~lowchart of a progr~m for processing
gAthered BTU data;
Figs. ~5A . . . 25M together form a flowchsrt of the OIP
progr~m illustrated in Fig. 9;
Pig. 26 illustrates a current sensor whlch m~y be used
with the invention;
~ig. 27 illustrates sn ~ir fIow sensing system which may
be used with the invention;
: Figs. 28A and 28B il}ust~ate ~ fluid ~low sensing system
whieh m~y be used with the in~ention; and
Fig. 29 illustrQtes a BTU sensing system ~hich n~y be
use~ with the invention.
Certain Figures of the drawin~s which are not arranged
in consecutive order are grou~ed together as follows:
Fig. 5 with Fig. 6B; Fig. 8B with Fig.29; ~ig. 9 with
Figs.26 and 27; Fig. 12 with Figs. 14 and 13B; Fig. 17 with Fi~.18D;
Fig. 19 wi~h ~ig.21; ~ig.20 with ~ig.23; Fig. 22 wi~h Figs.28A an~
28B; Fig.24 with Fig.25D; Fig.25A with Fig.25C; Fig. 25B with Fi~.
25G; Fig. 25E with Fig. 25M; Fig.25F with Fig. 25L; Fig. 25H with
~ig. 25J and Fig. 25I with Fig. 25K.
DETAILED DESCRIPTION OF THE ~NVENTION
The remote station addressing technique and associated
app~r~tus of the invention have ~ppli~ability to any type of datQ
gathering Qnd/or distribution system wherein a central station
communicates with a plur~lity of remote st~tions~ Accordingly,
this ~spect of t~c in~ention will be described first. After this,
fl more det~iled des~ription og the d~ta gathering ~nd/Dr distribu-
- R-
1?,5~6~
tion 6ystem of the inventlon in ~ ~pecific energy m~nagement sys-
tem for monitoring energy consumption and other psrameters ~t a
remote statlon will be provided.
The overall d~ta g~thering ~nd/or distribution system of
the lnvention is lllustrated in Pig. 1 which shows a central com-
puter system a3 which communicates with ~ plurAlity of m~dular
remote stQtions 11 through a master controller 19, a controller
interface 15, Qn A~D con~erter 21 cnd 5 plur~lity of section
, .
~ . - .
switches 17. The computer system 23 is a conventionAl eommercisl-
ly avail~ble system. One which has been found to be particulQrly
suitable fbr use with the invention is known as the North Star
Horizon. It includes ~ central processing unit (CPU) a7, a r~ndom
ccess memory ~RAM) 29 for temporarily storing programs and data,
a disc controller 31, a floppy disc ~system 33 for permanently
storing programs and dat~, an interface 3S for communioating with
an externally connected video input Outpue terminal 37, and a bus
structure 25 to which the CPU 27, RAM 29 disc controller 31, ~nd
interf~ce 35 are connected. The bus 25 is knowm in the industry
as an S-100 bus having l00 ~omnunication lines respectively con-
nected to a like number of terminal pins. Some of the communica-
tions lines are dedicated to signals for communicsting ~mong the
various devices contained within the computer system 23, while
- others are provided for allowing the computer system 23 to commun-
icate with e~ternal devices connected thereto.
Master controller l9 working in conjunction with con-
troller interface 15 provides the necessary signals between com-
puter system 23 and section switches 17 which enables the computer
system (more particularly CPU 27) to address and take data from or
provide data to ~ selected one of the inform~tion channels 10,
e.g~ wire pairs, located Qt the remote stations 11. Data is ~c-
quired from or sent to the remote stations 11 by means of the
section switches l7 which are connected to the remote stations via
a system bus 13 and communicatlon channels, e.g. wire pairs, 12.
Each section switch 17 oontains two identical portions
which connect with respective communic~tions channels and up to 16
separate remote stations can be att~ched to each communiations
channel. If 16 remote stations are connected to each communica-
tions channel and 16 section switches are provided, each handlingtwo communic~tions channels, ~ totsl of ~12 (16 x 16 x 2) remote
stations ~sn be handled by the system. If e~ch remote station in
turn hRs 16 information ch~nnels thereat, the computer system 23
can then ~ddress any one of 8,192 information channels (258 infor-
mation ch~nnels for each communications channel).
The information channels 10 m~y have various sensors S
or operative devices D connected thereto, the outputs or inputs of
which are directly connected to the ~omputer ~ystem 23 through the
section switches 17 end A/D converter 21 when the information
~hannel 10 corresponding thereto is eddressed by the computer
~ 10 system a3. Data coming from the informetion channels via the
: rem~te stations 11 is converted to digit~l data by analog to digi-
tal converter ~I prior to entering ~omputer system 23 which stores
the digitized dats.
Addressing of the remote stat;ons 11 ~nd the ;nformation
channels 10 thereat is accomplishe~ by sequentiRly sending tone
bursts down a communicRtions channel 12 to which a group of remote
stations is connected. The tone bursts are received by each of
the remote stations of the group simultaneously, but each station
; is only en&bled by a preassigned numerical range of tone bursts
(~n Rddress). Upon receipt of the sequenti~l tone bursts in its
preassigned numericQl range, ~ remote station sequenti~lly con-
nects eaah of lts information channels 10 to the communic~tions
chQnnel. For ex~mple, ~ ~irst remote st~tion may only respond to
the first 16 tone bursts trsnsmitted to it to sequentially con-
nect, upon e~ch occurrence of a tone ~urst, a respective inform~-
tion channel 10 to the communications oh~nnel. Other tone bursts
outside the assigned numerical r~nge which ~re received by that
remote station do not cause connection of Any of its information
~hannels 10 to the communications channel. The next remote sta-
tion of the group m~y be responsive, for ex~mple, to the next
_ ~ _
5~6~
sequence of 16 tone bursts, the third remote st~tion responsive to
the next 16 tone bursts, etc.
Thus, for ~ny given com~unicQtions channel interconnect-
ing a section switch 17 with ~ group of remote stations, each of
the remote stations of the group can be addressed by cycling
through a predetermined number of tone bursts. If 16 remote sta-
tions each containing 16 information ohannels are connected to
each communications ohannel, a total of 256 tone bursts will serve
to address and sequentially connect each of the inform~tion ch~n-
nels to the communications channel. By repeating the sequence of
256 tone bursts, the remote stations and information ch~nnels
thereat can be continually addressed by computer system 23. More-
- over, the sequential addressing tone bursts can be sent simultane-
ously over all the communications channels so that every tone
- burst sent will cause 32 addressed inform~tion channels to be
connected to the central station over 32 communications channels.
A more detailed description of the component parts of the Fig. 2
system now follows.
REM~TE STATIONS
A better underst~nding of the ~ddressing of the remote
stations ll can be seen with reference to Fig. 2 whlch shows the
remote statlon apparatus. TerminQls LG and Ll respectively repre-
sent the connection points of the remote st~tion to the communica-
tions channel which leads to a section switch 17~ ~or the purpose
of further discussion, it will be assumed the information channels
10 and communications channel 12 ~re wire p~irs, but other types
of communications links ~n also be employed. The section switch
itself will be described in more detail below.
The information channels 10 comprise Q plurality of
termin~l p~irs across whieh various sensors S or operative devsces
D can be conneoted. ~or purposes of illustration, a sensor 47 and
~2S~6~1
operative device 48 have been ~hown as being respectively con-
nected to the se~ond and sixth information ~hannels of the remote
station illustr~ted. E~ch of the information ch~nnels 10 can be
tone burst addressed in sequence ~nd when addressed are conneeted
by analog switches 41 and 43 to An output line 57 which is in turn
connected through resistor 59 ~nd fuse 61 to termin~l Ll. The
terminsl LG is a ground terminal at the remote station.
Terminal Ll is also connected through fuse 61, a cap~ci-
~ tor 79, and a resistor 81 to A tuned circuit 83 which reacts to
; 10 the frequency of the tone bursts on the line Ll. Each time ~ toneburst of the proper frequency, e.g. 100 KHz, occurs, the output of
tuned cir~uit 83 applies a sign~l to the input of one shot multi-
vibrator 87 which responds by outputting a clo~k pulse to the
clock input of counter 89.
- Counter 89 is a 1 of 1~ counter which supplies data
output signals corresponding to the instantaneous v~lue counted.
These output sign~ls occur on lines 51 w~ich are connected to
; ~nalog switches 41 ~nd 43, and control which information channel
10 is ~onnected to output line 57. An additional data line from
counter 89 is provided to the inputs of NAND gates 89 and 104.
The output of NAND ga~e 99 is connected to the input of NAND gate
103. NAND gfltes 103 Qnd 104 are respectively connected to lnhibit
inputs of ~n~log switches 41 and 43 and accordin~ly serve ~s "en-
abling" gates controlling whether switches 41 dnd 43 are operative
or not. When operQtive, switche~ 41 and 43 connect one of the
information channels 10, ~s determined by the data inputs thereto
from counter 89, to the output line 57.
G~tes 103 and 104 will rem~in off as long as there is no
output signal from NAND gate 101. The latter gate is connected to
the output of B ~omparison counter 97 which receives as inputs the
output vf ~ programmable ~ddress device 90 and the cRrry output of
~ZS~81
counter 89. As counter 89 cycles through its 16 count positions,
it generates 8 earry output signal ea~h time it completes a count-
ing cycle. Comparison counter 97 counts the c~rry outputs, and
~hen the counted number of carry outputs equals the count value
set by programmable address device 90, it provides an output sig-
nal to gate 101 c~using gates 103 Qnd 104 to enable ~nalog
switches 41 and 43. The pro~r~mmable address device 90 determines
the address of the remote station, or stated otherwise, the nu-
merical tone burst range (number of tone bursts) to which the
remote ststion responds. Thus, each group o~ 16 tone bursts
sppearing on line Ll will be directed to a psrticular remote sta-
tion~ By changlng the programmable addrsss in devi~e 90 by a
digital value of "Dne" for each successive remote station, eàch
group of 16 tones appearing on line Ll will address a different
- remote station by the output of the respective comparis~n counter
; 97~ In addition, esch tone burst in the tone burst group will
address the information channels 10 at an Rddressed remote station
by the data output o~ counter 89.
Each remote station also includes a timing circuit in-
cluding capacitor 91, resistor g3 and Q diode 95 in parallel with
resistor 93. This timing circuit responds to ~ tone burst sppear-
ing on line Ll for ~ predetermined time dur~tion lon~er than the
time duration of the tone bursts which are used to address the
information channels. The purpose of this timing circuit i 9 to
recognize a reset tone burst pl~ced on the communications ch~nnel
by the central station and to produce 9 reset signal to comparison
counter 97, counter 89 and one shot multivibrator 87. The centr~l
st~tion sends this reset tone burst just prior to sending ~nother
compIete addressing sequence cf to~e bursts, e.g. 256 tone bursts.
This ensures that all remote s~ati~ns will be reset prior to the
occurrence o~ the next (first) addressing tone burst of the next
~.~5968~
tone burst sequence on the line. Since the ~ddressing tone bursts
are of much shorter duration than the reset tone burst, the timing
circuit will not respond to them and thus counters 89 and 97 are
free to perform tbeir counting functions in response only to the
addressin~ tone bursts.
Each remote station is self-powered ~nd includes M power
supply circuit 63 which consists of a pair of oppositely polled
diodes 67 and 69 conne~ted to the opposite ends of a pair of
series connected capacitors 71 snd 73. The opposite ends of the
series connected capacitors in turn are connected across a series
pair of Zener diodes 75 and 77 with the connection point between
the capacitors 71 and 73 and Zener diodes 75 and 77 being con-
nected together and to ground. A pair of ter~inals Tl and T2 are
connected to opposite ends of the Zener diodes and provide opera-
tive power to switches 41 and 43, all of the gates, one shot mul-
; tivibrator 87, counter 89, comp~rison counter 97 end programmable
address device 90. Power supply circuit 63 deri~es oper~tive
power from the tone bursts which are supplied on line Ll from the
central station snd in this manner, a separate remote station
2Q power supply is not required.
Fig. 2 also illustrates the information channe~ switch-
ing portlon of each remote station by a numeral 39. In some in-
stances, for example where the outputs of two or more sensors are
to be simultaneously connected to the central station over re-
spective communications chsnnels, a plurality of switching por-
tions 3g at a remote stntion are connected in pQrallel. Thus, a
remote station can have one or more switching portions 39 connect-
ed to the outputs of oounter 89 and gates 103 ~nd 104, as illus-
tr~ted in ~ig. 2. E~ch addition~l switching portion 39 would hsve
its owm information channels 10, input and output terminals
~ ` ~
~L2S9~
corresponding to LG and Ll, but all m~y derive their operati~e
power from a common power supply circuit 63.
Two switching devices 39 could be used, for ex~mple, to
simultaneously connect a current sensor connected to one device 39
~nd ~ volt~ge sensor connected to the other to the central station
80 th~t instantuneous power could be calculated (V X 1).
Because of the relative simplicity of the ~ircuit used
and the self-contained power supply, the remote stations mRy be
constructed as low cost modular units of identical construction,
the only difference between units being in the ~ddress assigned
thereto by the programming of address device 90.
A c~libration resistor 49 is also shown connected to the
first in~ormation channel 10. By periodic~lly checking this fixed
resistance value when the first information channel is connected
to the centr~l station, the central station can ensure that there
has been no significant change in the condition of a communica-
tions channel. In other words, resistor 39 is used as a calibra-
tion standard to diagnose ~aulty line conditions.
As noted, a group of remote stations 11 may be commonly
connected to a single wire pair forming a communications channel
to the centr~l station. Thus, the terminals LG ~nd ~l for a p~ur-
ality of remote station3 may be connected }n parallel to the com
munications channel which goes to Q section switah 17. Moreover,
a plurality of communicRtions channels, each having Q group of
remote stations connected to it~ m~y be used. To further illus-
trate the connection o~ the communications channels to the section
switches, reference will be mude to ~igSo 3 and 4 which show in
det~il the construction of each section switch 17. However, be-
~ore further describing the structures of the section switch l7,
as well as the r~maining portions of the system, it is necessary
to underst~nd some of the bus line labeling and nomenclature which
will be used.
~25968~
BUS STRUCI URE
Figs. 3 to 8 show various circuits conne~ted to terminal
areas designated 8S follows:
r
L~,>
where N is a number. These designetions throughout the drswings
refer to pin terminnls. When Qppearing on the drawings for the
master controller 19 (Fig. 7) Qnd the analog to digital converter
21 (Figs. 8A and 8B) they identiîy pin terminals on the S-100 bus
25. When appearing on the drawings for the controller interface
lS (Figs. 5, 6A and 6B) ~nd ~he section switches 17 (Pigs. 3 and
10 4) they identify terminals on system bus 13.
To further facilitQte description of the application, a
brief description of the pin termin~ls used on both the S-100 bus
25 and the system bus 13 follows:
S-100 Bus
Addressing and Data Siç~als
CPU 27 Pin Data Output Pin Data Input Pin
Address Desi~ Lines From Desig- Line To Desi~
Lines nation CPU 27 nation PU 27 nation
A0 79 D0~ 36 Mff 95
A 1 80 D0 1 35 Dl 1 94
A2 81 Dû2 88 D12 41
A3 31 D03 89 DI3 42
A4 30 D04 38 DI4 91
A5 29 D05 39 DI5 92
A6 sa D06 40 DI6 93
A7 83 D07 90 DI7 43
l;;~S96~31
Control Signals
Pin Control ~ignal
Desi~nation Description
PWR 77 Timing signal generated by CPU
durlng output operation
indicating valid data is on
S-100 bus
SINP 46 Sign,ql applied to S-100 bus by
CPU ~uring a data input
operation
sour 45 Signal applied to S-100 bus by
CPU during a data output
operation
PDBIN 78 Sign~l provided by CPU
indicating its reading of data
from S-l 00 bus
PRDY 72 Sign~ placing CPU in wait
state; g~nerated by devices
external to CPU a3
- 2û PINT 73 Interrupt request line
requesting interrupt of (~PU
VI6 10 Highest Priority interrupt
~master interrupt) to CPU
VI5 9 Next highest Priority interrupt
~sensor interrupt) to CPU
VI4 8 Lowest Priority interrupt
(sampling interrupt) to CPU
CLK 24 System clock 4 MHz
PSYNC 76 Synchronizing signal generated
by CPU during input/output
cycles
POC 99 System reset si~,~nal
synchronized to CPU clock
System Bus 13
The system bus 13 may also be a 100 pin bus, but the
signals on the various pin terminals are different from those on
the S-100 bus. Por system bus 13, the pin designations and corre-
sponding signals are as follows:
_ ~_
125~16~31
~i~Data Si,gnals
Data Output Pin DQta Input Pin CPU 27 Pin
Lines From Desi~ Lines To Desip Address Desi~
CPU 27 nation CPU 27 n~tion Lines nation
.
D00 36 D10 95 A0 79
D0 1 35 DI 1 94 A 1 80
D02 88 DI2 41 A2 81
D03 89 DI3 42 A3 31
D04 38 D~4 91
D05 39 D15 92
D06 40 DI6 93
D07 90 D17 43
The system data bus 13 also includes pin terminals for
the output lines of one or re analog to digit~l converters.
These output lines, AD0 . . . AD9, are connected to the pins of
system bus 13 es follows:
Analog to Digital Converter Outputs Pin Design~tions
:: AD~ 74
ADl 75
AD2 76
AD3 a2
AD4 83
AD5 84
AD6 85
AD7 86
AD8 87
AD9 37
The 32 incoming wire pairs from the remote stations 11 may be
grouped into four groups of 8 incoming lines each QS follows: S0L~
. . . S7L~; S~Ll . . . S7Ll; S8L0 . . . S15L0; and S81,1 . . .
S15Ll. These incoming lines are respe~tively assigned to ~he pins
of bus 13 ~s fol lows:
J~
_ ~ _
l~Sg~
lncoming Lines from Remote Stations Pin Desi~tion
S0L0 3
S lLO 5
S2L0
s3La 10
S4L0 13
S5~0 15
S6Lp 1 8
S7L0 20
S0L 1 4
SlLl . 6
S2L 1 - 9
S3Ll 11
:~ S4Ll 14
S5L 1 16
S6L 1 lg
S7L1 21
S8L0 53
S9L0 55
; 20 SlOL0 58
~lII.P 60
S12L0 63
S13L0 65
S14L0 68
S15L0 70
S8L 1 54
S9L1 56
59
SIOLl
~2Sg681
Incoming Lines from Remote St~tions Pin Designation
SllLl 61
S12L1 64
S13L1 66
S14L1 69
S15L1 71
Bus 13 also ~ont~ins vArious control signal lines containing sig-
nals generated by various portions of the system as follows:
Control Si~nals Pin Desi~nation
: 10 SS 23 CPU signal to clock
automatic digital gain
control through
various ~ain values
.~ .
V Test . a4 Supplies a test
voltage to various
portions of the system
~or testing p~poses
15 Khz 25 A clocking signal
used by portions of
i 20 the system.
SSPCL 26 A reset sign~l
used to reset the
automatic digit~ gain
control system
IFIO 2~ Decoded address from
the CPU used to
designate ~ controller
interf~ce input/output
operation
SS~DOFF 30 Control sign~l sent
by CPU to control
on/off operation of
A to D converter on
section switch
LIN13SEL 32 Decoded address from
CPU which ~onditions
section switches for
line assignment
C~GSCL 44 Control signal sent by
CPU to ~ondition the
section switches to
configure them to
operate on a split or
nonsplit blas
configuration
~Z596~3~
Control Si~nals Pin Desi~nation ~5~
Decoded address from
CPU which conditions
section swit¢hes for
input/output operation
ACGRD 46 Control signal sent
by CPU to aetivate
ofset voltage ~ompen-
sation in multiplying
: 10 circuitof section
switch
~SP 47 Control sign~l sent by
CPU to enable
automatic digital gain
control circuit
::
500 Khz 48 Another clocking si~
. nal used by portions
of the system
ToneSigna~ 49 A gated tone signal
~ 20 used for addressing
and control of remote
stations
PWR 77 Same AS PWR on S-100
bus
PDBIN 78 SamePDBIN onS100 bus
ACP.SEN 97 Control signal sent
by CPU to condition
sec~on switches
for AC measurements
SECrl(~W SWITCH
Each se~tion switch includes two identical switching and
signal processing portions shown in ~ig. 41 which are respectively
connected to different colTmunioation~ channels (input lines). The
two identical section switch portions in turn share a coslmon ~d-
dressing and control signal generating portion, illustrated in
~ig. 3.
Since ~ig. 4 represents two identical section s~itch
circuits, the unp~renthesized line labels (nurslbers) are for one of
~;~59~i8~
the two circuits, and those in pQpenthesis are for the other cir-
cuit.
~ ach section switch portion (Fig. 4) is connected to 16
of the 32 incoming lines with the other identical portion being
connected to the remaining 16 incoming lines. Since each section
switch portion (Fig. 4) only services one of the 16 lines connect-
ed the~eto, a pair of analog ~election switches 143 and 145 is
used to connect one of the 16 incoming lines to the remainder of
the section switch circuit. The selec~ing data inputs to an~log
switches 143 and 145 are taken ~rom lines 737, 739, 741 and 743
which are taken from the output of a latch 131 in Fig. 3. The
data inputs to latch 131 originate fr~m CPU 27 data output lines
and are applied to the ~-100 bus 25 and are also connected to
system bus 13 pins 90, 40, 39, 38, 89, 88, 35 nnd 36 by the con-
~ troller interface 15 ~s described in more detail below.
Half of the output data lines (737, 739, 741, 743) of
latch 131 are coupled in parallel to analog switches 143 snd 145
of one section switch portion. The other data output lines 729,
731, 733 and 735 are applied to the ~nalog switches of the other
section switch portion. Line 737 which is coupled to the enable
input of switch 143 is also ooupled through an inverter 147 to the
enable input of switch 145. Line 737 serves to select one of the
two switches 143 ~nd 145 for oper~tion, while the remaining three
d~ta input llnes 739, 741 flnd 743 serve to c~nnect one of the
input lines to respective switches 143 and 145 to respectiYe out-
put lines 151 and 153.
During ~ystem initislization, CPU 27 assigns a section
switch portion to one of the incoming lines connected thereto by
addressing and supplying dat~ to latch 131. Once initialization
is completed, the section switch remains conngcted to the inc~ming
line to which it was assigned.
`1
~.25~6~31
In~erter 147 cnn be disabled by a control signQl C~SEL
~pplied to line 751, in a mQnner described further below, so th~t
the signal applied to line 73~ will en~ble both ~nalog switches
143 ~nd 145 at the sAme time. In cert~in spplications, it is
desir~ble th~t each section switch portion illustrated in Fig. 4
be ~Qpable of communicating with two lines æimultaneously. Por
example, if one incoming line WQS coupled to a volt~ge sensor ~nd
the other to ~ current sensor at ~ remote station, Q section
~witch portion could simultaneously process current and voItage
I0 inforMation to c~lculate the power being monitored at a remote
station. This so-called "split-bus" configurstion, is set by the
CPU which ~ddresses ~ lQtch 371 in the controller interfac-e sup-
plying thereto ~ signal CP~SEL which is ~pplied to the section
switches by a pin 44 of system bus 13. Each section switch re-
~ ceives the signal C~GSEL from pin 44 (Fig. 3) and ~pplies it to
line 751 to control switch 149. When it is desired to have a
"split-bus" oonfiguration, thç C~GSEL signal instructs switch 149
to open while for a norm~l bus configuration the switch 149 re-
: m~ins closed. Sign~l CFGSEL also controls operation of inverter
of 147 so th~t when a split-bus configur~tion is desired both
8Wi tches 143 and 145 are simultaneousiy en~bled to pa99 one of the
incoming lines respectively connected thereto to the respective
output lines 151 and 153.
The output line 151 of ~nslog sw~tch 143 is connected to
~n input sign~l path 150 which is connected to one of the switch
termin~ls of analog switch 175. The output line 153 of anAlog
switch 145 is connected to input signal line 155 directly Qnd
through switch 241 to input signal line 243.
When R sensor which is connected to 8 section swit~h ViQ
~n informRtion ehQnnel ~nd ~n incoming line outputs ~ DC volt~ge
which is to be measured by the system, it is applied to line 155
~ Z~968~
which is connected RS one of the input terminals to switch 199.
When switch 199 is in the position illustrated in Pig. 4 this DC
voltage from the sensor is passed through buffer amplifier 19~ to
an output line 781 (J~) which is one of thirty two input lines to
the A~D converter 21 illustrdted in Pig 1. Switch 199 is con-
trolled by ~ signal ~ signal applied to line 753 which con-
trols whether sn AC measurement or ~C m~surement is to be
performed. The signal ~ WE~ is applied to the section switches ViQ
~ system bus pin 97 which receives it from a latch 373 in the
controller interfRce which is addressed and sent data by CPU a7 in
a manner more fully described below. W~en the signal ~E~ h~s ~n
opposite pol~rity than that which places switch }99 in a positi~n
illustrQted in Fig. 4, the output line 195 of th;s switch is con-
nected to input 191 which in turn is connected to the output of an
~ AC power measurement circuit which is also n~re fully described
below.
Since the output from various sensors connected to the
information channels of the remote stations m~y differ widely in
terms of the type of output generated, i.e. a ~hflnging resistance
or a changing volt~ge, as well as in the level of the output sig-
nal, the section swi$ches incor~orate n volt~ge off~et compensa-
tion c~rcuit for adding to the sensor output a precletermined DC
voltage level which serves to normalize the sensor output voltages
to be within d predetermined voltage r~nge, or to convert a re-
sistance sensor output to a volt~ge signal. The voltage offset
compensation is provided by an analog switch 161 and jumper se-
lectable reference volt~ge bus 159. Analo~g switch 161 contains a
plur~lity of inputs 163J 1~5~ 167, 169, 171 and 173 which c~n be
~umper connected $hrough respective resistors to one of four
reference Yolt~ge lines provided ~t bus 159. For ex~mple, the
1~5968~
four lines illustrated may respectively receive volt~ges of 0,
2.5, 5 and 10 volts.
Two additi~nal inputs to analog switch 1~1 are ~rom line
761 which receives a tone burst sign~l from the controller inter-
face 15 ~nd from pin 24 which receives a test voltage ~s described
below. Thus, the output of analog switch 161 aan be any one of
the reference volt~ges to which lines 163 . . . 173 are connected,
the test voltage9 or the tone on line 761. The tone burst is used
for Addressing the informatiDn channels at the remote stati~ns,
and can also be used to control an operative device connected to
an addressed information ch~nnel. The addressing ~nd control tone
bursts are at different frequencies ~nd the m~nner of generating
different frequency tones will be described below with reference
to the controller interface 15.
The output 152 of ~nalog switch 161 is selectively con-
nected to one of the inputs by means of signals applied to control
lines 719, 721, 723 and 727 (725 for the other section switch
portion). The latter signal is an enable signal while the first
three signals CQUSe selection of one of the input lines to switch
161 to be connected to output line 152. The signals on lines 719,
721, 723 and 727 origin~te from latch 119 of the sectlon switches
(Fig. 3) which is coupled to the data output lines of CPU 27
through the system bus 13 ~nd the S-100 bus 25. CPU 27 addresses
latch 119 and sends to it data enabling switch 161 and instructing
it to connect 8 predetermined one of its inputs to its output.
Assuming for the moment that the output of switch 161 is one of
the reference voltages contained on the input lines, this refer-
ence voltage is supplied to input path 155 (through an associated
resistor) which is re¢elving the output (voltage or resistance)
from a sensor. If the sensor output is a ch~nging rssistance, the
reference voltage will be divided betweerl the resistance of the
~2596~
3ensor and reSistQnce associated with the selected reference volt-
age to supply a D.C. voltage on line 155 ~hich vQries with a
change in sensor resistance. The voltage on line 155 is supplied
to line 193 of switch 199 and through ~mplifier 197 to line 781
(J0) which, as noted, is applied as one of thirty-two inputs to
the A/D converter 21 (Fig~ 1).
A princip~ feature of the system of the invention is
its ability to monitor power consumed in an electrical path lo-
cated at ~ remote station. ~or this purpose, a current sensing
transducer (sensor) is coupled to an inf-ormation channel at a
remote station and its output is multiplied by ~ signal represent-
ing a voltage on the monitored electrical path to produce a signal
representing power consumed. To periorm the power calculation,
each section switch portion illustrated in Fig. 4 includes AC
measurement structures. Included are a power calculation circuit
identified by dotted block 183 in ~ig. 4 whi~h performs ~ctual
power calculations and an ~utomatic digital gain control circuit
~ identified by dotted block 245 in Fig. 4, which is used to ensure
:
that the calculated power value f~lls within Q predetermined digi-
tizing rang~ of A/D converter 21 (~ig. 1).
For AC measurements, switch 199 is switched by the sig-
nal ACMEM fr~m CPU 27 to ~ positlon where output line 195 is con-
nected to input line 191. Input line 191 is connected to the
output of Qmplifier lS9 which receives at its input the output of
~nplifier 187, which in turn receives at its input the output of
~ an ~nalog-to-digital multiplier 185. Multiplier 185 and Qmpli-
; ~iers 187 a~d 189 form a so-called "four quadrant multipliern.
~ultipller 185 c~lculates power consumption by multiplying a digi-
tal representation of a voltage by an analog representation of
current in a monitored electrical path. The current signal origi-
nates from a current sensor having a voltage output which changes
~1
~ 5g~
: with sensed current and is applied to the input terminal 154 of
switch 241, the output 243 of which is ~onnected to Rn ~mplifier
217. The output of ~nplifier 217 is connected to the input of
programmable voltage divider 215 h~ving Qn output connected to the
input of an amplifier 213. The output of Rmpiifier 213 is ~on-
nected to the input of an ~mplifier 211, the output o~ which
passes to amplifier 209 through a capacitor 205. The OlltpUt of
amplifier 209, which is a voltage represent~tive o~ sensed cur-
rent, is applied to an analog input of analog/digital multiplier
185. A digitized voltage input is also ~pplied, via a plurality
of digital input lines, to multiplier 185.
; The digital volt~ge input to multiplier 185 is received
from a tr~cking an~log to digital converter 181 whi¢h receives ~s
an input signal the output of an amplifier 179 which receives on
- its input line 177 A voltage ~hich represents the voltage on the
electrical path at the remote station which is being monitored.
This voltage can be obtained from a number of sources ~nd for this
reason sn an~log switch 175 is provided for selectively connecting
one of four inputs thereto to its output which is connected to
input line 177 of ~mplifier 179. The input voltage to converter
181 c~n be t~ken from pins 33 or 34 of the system bus 13 or ~rom
line 150 which is connected to output 151 of switch 143. As de-
scribed earller, the computer c~n ¢onfigure switches 143 and 145
80 that they are both simultaneously enabled allowing each of
: output lines lSl and 153 to be connected to ~, respective section
switch input line. In this "split bus~ configuration switch 149
i~ also activated to uncouple the outputs of lines 151 and 153 so
that the output on line 15} 3s connected as an input to switch
175. This allows 8 remote station voltage sensor connected to one
of the section switch input lines to be used ~s the vottsge input
to the tracking enalog to digitsl converter 181, while one of the
~9~1
input lines to ~witch 145 supplies the output of Q current sensor
~t the remote stRtion.
As an alternative m~nner for genersting a voltage repre-
sentative of that at the ele~trical path being monitor2d, the
electrical service entrance to a building can be tApped for a
voltage which represents the voltage at the monitor~d electrical
path. System bus 13 pins 33 ~nd 34 which ~re inputs to switch 175
provide a voltage which is taken ~ran the servi~e entran~e. A
more detailed description of how these voltages are applied to
; 10 pins 33 and 34 follows in the detailed des~ription of the con-
troller interface.
~ Switch 175 connects one of the inputs thereto to line
; 177 under control o ~ignals N~DESEL ~nd VSSEL applied to lines
715 (7l3 for the other half of the section switch~ flnd 717. These
signals originate at latch 119 (~ig. 3) and ~re ~upplied thereto
by CPU 2q which sddresses the latch. The CPU thus determines
which of the voltdge inputs to switch 175 is used by the tracking
A to D converter 181. Switch l75 also has an additional voltage
input whieh is re~eived from pin 24 of the system bus 13. This is
n test voltage pin whi~h can also be selected under control of the
CPU by the M~DESEL and VSSEL sign~ls ~oi testing purposes.
Before reQching the analog input of multiplier 185, the
sensor ~urrent output passes through an ~utomatic digital gain
control circuit 245. This circuit ~nsures th~t the multiplied
output of the four quudrant multiplier remains within the digitiz-
ing range of analog to digital converter 21. It automatically
decreases the level of signal applied as an analog input to multi-
plier 18S until the output of multiplier 18~ is within a prede-
termined signal range set by a window ~omparator.
Gain contr~I c;rcuit 2~5 receive~ as an input on line
231 the output of the f~ur quadrant multiplier and supplies this
~3
~LZ596~
output tc a window comparison circuit 225 consisting of ~ pair of
comparison ampli~iers 233 and 235. Window compflrMtor 225 deter-
mines if the output of the muItiplier is within a predetermined
range. If it is not, an output signal is applied through inverter
220 to gate 227 as an enable signal allowing gate 227 to pass 15
KHz clocking signals on line 749 to the clock tetminal of counter
221. These clock~ng signals originate in the controller inter-
face. As a result, the counter counts clock pulses occurring at a
15 KHz rate whenever the signal at the output of the four quadrant
multiplier exceeds a predetermined signal level rangeD Counter
221 also receives as an alternate clock input a signal SS on line
755 which is re~eived from pin 23 of system bus 13 (Fig. 3). This
signal originates from a latch 371 provided in the controller
interface which is addressed and sent data by CPU 27 as described
further below.
A reset terminal is also provided on counter a21 which
is connected to line 759 which receives the control signal SSPCL
from system bus 13 pin 26. This signal originates at a one shot
multivibrator 383 (Fig. 6A) provided in the controller interfaoe.
Reset signsl SSPCL is generated by the one-shot multivibrator flt
the leading edge of a control signal SSP supplied to R latch 373
in the controller interface by CPU ~7, Signal SSP is Qlso sup-
plied as fln enabling signal to gate 227.
The digitRl output of counter 221 is sent to a decoder
219 which supplies a digital representation of the counter 221
oontents to a programmable voltage divider 215. Progr~mmable
voltage divider 215 and amplifier 213 together determine the gsin
applied by the automatio gain control circuit 245 to an applied
input sign~l. The multipIy~ng fa~tors of ~mplifiers 213 and 211
are such that the n~ximum g~in of sutomatic gain ~ontrol eircuit
~LX59~i81
245 is 32. However, this gain f~ctor 1~ redueed by the program-
mable voltage divider 215 so that the output signal from amplifier
211 may have a gain of 32 or gains of 16, 8, 4, a, 1, .5, or .25
~ determined by the output of decoder 219. Pro~rRmmable voltage
divider 215 can be formed by a multiplying an~log to digital con-
verter similar to that used as multiplier 185.
The SSPCL reset sign~l applied to counter 221 on line
759 is received from one shot multivibrator 383 in the controller
interface ~s des~ribed earlier. The one shot multivibrator 383
supplies a pul~e to reset the ~utamatic g~in control circuit 245
to m~ximum gain when CP~ 27 instruct~ the setting of the automatic
gain control CiPCUit 245 via the SSP ~ignal applied ~o line 757,
and to one shot multivibrator 383~
As noted, the automatic digital gain control circuit 245
~ is rendered operative by the SSP signal applied to line 757 which
enables gate 227 and thus counter 221 to begin counting clock
pulses epplied to line 749. Whenever window comparator 225 de-
tects a voltage ~utside a suitable range of the analog to digital
converter 21, gate 227 is ennbled to pass the clock pulses to the
clock input of counter 221. Accordingly, counter 221 steps
through its counting states to progressively decrease the gain
~RCtor applied to the signal on line 243 until window comparator
: 225 provides an output signal indic~ting that the output of the
four quadrQnt multiplier is within a suitable conversion range.
When this occurs, the output of the window comparator passes
through inverter 229 and disables gate 227. This stops the supply
o~ clocklng signals to counter 221 which remains in its last
counting stste which decoder 219 ~pplies to the programmable volt-
~ge divider 215 leaving it in a particular voltsge dividing state.
As counter 221 cycles through its counting st~tes, de-
coder 219 may eventually ~nstruct progr~mmable volt8ge divider 215
_ ~ _
l;~S968~
to divide by its highest dividing value. This is detected by
inverter a23 which operates to inhibit gate 227 from providing ~ny
further clock pulses to counter 221. Thus, when the programmable
voltage divider is ~ycled through to its highest di~iding ~alue,
counter 221 is inhibited so thRt no further changes occur and the
programmable voltage divider remains set in its highest dividing
(lowest gain) position.
An altern~te clock input C$K2 also provided on counter
221 which is connected to line 755 which receives the control
signal SS from system bus 13 pin 23 as described previously. This
sign~l, composed of a series of pulse~, is sent by the l~tch 371
under the control of ~PU 27 to set the counter 221 to a previously
determined state which sets the automatic digital gain control
circuit 245 to a desired gain sett~ng rather th~n allo~ing the
automatic setting of the gain as described previously. This would
normally only be done for test purposes.
CPU 27 recei~es the output deta value from counter 221
via lines 707, 709 ~nd 711 ~701, 703 and 7~5 for the other half of
the section switch). Thls data is furnished through buffer 133
(Fi~. 3) to the cystem data bus 13 which in turn furnishes it to
the S-100 dat~ bus QS inputs to the CPU 27. In this manner, the
CPU 27 receives data representing the ~mount of attenuation
applled to the output signal of ~mplifier al7. This ~ttenuation
value is used by the CPU 27 when it determines actual power con-
swmed at a remote location, since the digitized value of current
multiplied by voltege provided by the four quadrant multiplier
will have been reduced by a faotor corresponding to the output of
counter 221.
An undesir~ble by-product o~ the current sensor signal
path through the automatic gain ~ontrol circuit 245 and into
multiplying AID converter 185 is a DC offset voltage produced by
1~5968~
the various ~mplifiers in the chain. To compensate for these
offset voltages, c~pacitors 205 ~nd 203 are respectively provided
in the outputs of amplifier 211 and 189. Prior to the occurrenee
of an AC power measurement, these capQcitors are allowed to charge
to the inherent offset voltages by ~onnlecting the output side of
each to ground while Rt the s~me time grounding the AC path input
243 through switch 241 using control input 747 more fully de-
scribed below The outputs o~ capacitors 205 and 203 Rre grounded
by respective switches ao7 and 201 which ~re activated by CPU 27
prior to Qn AC measurement being taken. After capa~itors 205 ~nd
203 are charged tD the DC s~fset voltages, their eonnection to
ground is removed by CPU 27 opening switches 207 and 201 ~o that
the accumulated ch~rge on capacitors 205 and 203 acts inversely to
cancel the offset voltage. Operation of switches 2~7 and 201 is
controlled by the CPU 27 which sends a signal ACGRD to the section
switches from system bus 13 pin 46 (Fig. 3). This signal is fur-
nished to latch 373 (Fig. 6A) in the controller interface by CPU
27 just prior to ~n AC measurement operation. This signal closes
switches 207 and 201 for a period sufficient to charge capacitors
ao5 and 203 to the of~set voltage, after which it ~s removed by
CPU 27. A delayed version of AOGRD, i.e. DELACGR~, is generated
by a delay circuit 137 provided in the section switches ~ig. 3)
on line 747 which is supplied to switch 241. DELACoRD controls
switch 241 to connect amplifier 217 input signal line 243 to l~ne
154 a predetermined period of time ~fter capacitors 205 ~nd 203
are released from ground by AOoRD. Accordingly, a sensor output
signal is ~pplied to the input of the automatic gsin control cir-
~uit 245 only ~fter capacitors 205 ~nd ~03 have been charged to
the DC offset voltages.
~ig. 4 also shows that the input to the multiplying A to
D converter lB5 m~y ~ome fr~n system bus 13 pins 30, 37, 87, 86,
1~5~
85, 84, 83, 82, 76, 75 and 74. These pins are ~onnected to
another tr~cking anAlog to digital converter proYided in the con-
troller interf~ce 15 which can be used if ~ tracking A to D ~on-
~erter 181 is not provided in the section switches. The tr~cking
A to D converter 181, when provided in the section switches in the
m~nner illustrated in Fig. 4, is enabled by ~ signQl Qpplied to
pin 30 of the system bus 13 which receives ~ signal SSADOFF sent
by CPU 27 to latch 371 in the controller interface.
; ~ig. 3 illustr~tes the common section switch portion
which supplies ~ontrol signals to the two section switch circuits
illustr~ted in ~ig. 4.
The bottom of ~ig. 3 shows various signal lines which
are ~pplied to Fig. 4 to control the eonfiguration of the section
switch portions. Line 761 contains ~ gated tone which is supplied
to switch 161 (Fig. 4). The tone originates in the con1;roller
interfnce which contains circuitry controlled by CPU 27 for set-
ting both the frequency and on/off period of the tone. The tone
is supplied to pin 49 of the system bus. The tone is taken from
; pin 49 ~nd ~mplified by ~mplifier 141. The remaining control
sign~ls on lines 745, 747, 749, 751, 753, 755, 757 and 759 ~nd
their origination have been described flbove and will not be re-
pe~ted.
As noted, e~ch section switch is addressed by the CPU 27
which supplies dat~ thereto Qnd tskes d~t~ therefrom. Data is
received from the section switches through buffer 133 (Fig. 3)
over lines 701, 703, 70S, 707, 709, ~nd 711 which represent the
contents of the counter 9 221 cont~ined in the two section switch
portions (Fig. 4). The output of buffer 133 is supplied to pins
43, 937 92, 91, 42, 41, ~4, and 95 of the system bus 13. From
there they ~re ~pplied through buf~er 325 of the controller inter-
face (~ig. S), bu~fer 627 of the muster controller ~Pig. ~) ~nd
~L25~3681
the S-100 bus to the data input lines to CPU 27. Buffer 133 is
enabled by ~AND gate 121 which re~eives a section switeh board
select input from ~ddress decoder 113. Address decode~ 113 is
~onnected through buffers 111 to the ~ddress lines of pins 31, 81,
80 and 79 of the system bus 13 which ~re in turn connected to t~e
address lines of the S-100 bus through lines 821 of the controller
interface (Fig. 6A) and m~ster controller (Fig. 7). Address de-
coder 113 receives ~ddressing signals fr~m CPU 27 ~nd, when
p~rticular section switch is addressed, supplies ~ board select
19 signal to gQte 121. Gate 121 also receives as enabling inputs
thereto the output of buffer 127 which is connected to system bus
13 pin 45. The controller interf~ce supplies a signal SSIO to pin-
45 (Fig. 5) which is received from inverter 776 of the m~ster ~on-
troller (Fig. 7). The signal SSIO ~ppears whenever ~ny one of the
16 section switch latches 119 or buffers 133 is being addressed ~y
; CPU 27 and is used to condition the section switches for an
input/output operation. Gate 121 also receives as an enabling
input thereto a signal PDBIN on pin 7B of system bus 13. This
signal is supplied to pin 78 by the controller interf~c~e whieh
receives its inverted form frQm the master controller (Fig. 7),
which in turn receives the signal PDBIN from pin 78 of the S-lOD
bus. The P~BIN signal is supplied by CPU 27 when it is reading
dQta from the S-100 d~ta input terminals. Thus, gate 121 is ener-
gized by a signal (BOA~D SELECT) indi~ting it is being addressed,
a signal requesting a section switch input/output operation
(SSIO), and a signal controlling the inputting of datQ to CPU 27
~PDBIN). When ~11 three signals are present, buffer 133 is en~
abled to pass the signals on lines 701, 703, 705, 707, 709 and 711
to their respective system bus 13 pin termin~ls.
Latches 119 and 131 which respectively supply various
: control signals to the section swit~h portion illustrated in Fig.
a~
_ ~ _
~l~59~
4 are respectiYely enabled by the outputs of inverters 117 and
125. Inverter 117 receives the output of NAND gate 115. NAND
gate 115 in turn reeeives enabling signals from the board select
line from address decoder 113, the SSI0 signal fr~m pin 45 and a
signal PWR from inverter 129 which receives the signal PWR from
pin 77. The signRI PWR at pin 77 is re~eived ~rom the c~ntroller
interface, which in turn receives it ~rom the S-100 bus pin 77
through the master coneroller. The PWm signal is ~ timing si~nal
generated by CPU 27 indicating thse data is on the S-100 bus ~or
reception by a remote device.
NAND gate 115 responds to the presence o~ the three
input signsls to enable latch 119 to receivé and latch data from
the CPU 27.
~ AND gate 123 enables lat~h 131 which also receives data
-from the CPU 27, supplying this to the section switch portion
Illustr~ted in Pig. 4~ NAND gate 123 receives the board select
output from address decoder 113, the PWR signsl fr~n inverter 129
and a line select (LINESEL) signal from pin 3a of the system bus
13. The LINESEL sign~l is applied to pin 3a by the controller
20interface ~Fig. 5) whieh recei~es its inverted form from the mas-
t~r controller (Fig. 7) as a decoded address si~nal ~or 16 decoded
~ddresses. Rach of the 16 ~ddresses corresponds to one of the 16
section switches. Each section switch NAND gate 123 receives
enabling inputs from the llne select slgnal PWR and Board Select
signals such that one of the section ~witches will have the output
of its NAND gate 123 enabled. This signal via inverter 125 en-
ables latch 131 on the selected section switch 17, thus allowing
the line assignment f~r that section switch to be transferred from
system bus lines 90, 40, 39, 89, 88, 35 and 36 to latch 131.
30Thus, NAND gate 123 enables latch 131 to receive line selecting
data from t~e CPU 27 which operates ~witches 143 and 145 (Fig. 4)~
~1)
- ~ _
~2596~3~
OONTR~LLER INTERFACE
Referrlng to ~igs. 5 ~nd 6, the controller inter~ace lS
(Fig. 1) will now be deseribed. As evident fr~m the discussion of
the section switches 17 above, the controller interface supplies
to syst~m bus 13 many of the control sign~ls which the section
switches use to configure them for ~ particular function, either
reoeiving sen~or outputs or supplying tone control signals to ~n
addressed information ch~nnel lO which is tempor~rily connected
through a co~munications channel to Q respective section switch
portion (Fig 4). The controller interface also gener~tes the
addressing tones which are sent to the remote stations to connect
An information ~hannel to a respective comnunications ~hannel.
Referring .first to Fig. 6, the controller inter~ace
includes an addr~ss decoder 359 which is connected to ~ddress line
A0, Al, A2 ~nd A3. These address lines, as well as sign~l line
PWR collectively identified by numeral 821 in Fig. 6, ~re output
lines from the master contr~ller 19 as is signal line 825 contain-
ing IFIO. The ~ddress decoder 3S9, when enabled by the output of
NAND gate 367, decodes four different addresses for respective
latches 369, 371, 373 and 375. NAND gate 367 is enabled by the
presence of the signal PWR whioh Is ~pplied to one input thereof
via buffer 361 and NAND gate 365 and by the signal IFIO which is
~pplied through buffer 3B3 to its other input. These signals
which come from the m~ster controller (Fig. 7), are supplied by
CPU 27 whenever the controller interf~ce is to perform an
input/output operation.
L~tch 369 re¢eives AS data inputs signals from d~ta
lines 823 via buffer 387 which originate in the master controller
(~ig. 7). These in turn are connected to respective data output
lines of the S-IOO bus to which the ~PU 27 sends ~utput data.
Accordingly, latch 369 latehes dat~ from the CPU 27 whenever
3l~5~
addressed, as determined by address decoder 35g. L~tch 369 pro-
vides output data ~ ~ . . F4, collectively indi~ated as lines
817, which are used to program Q desired tone frequency into a
programm~ble tone generator 313 (~ig. 5).
Latch 371 is likewise addressed by the CPU 27 sending an
address corresponding thereto which is decoded by address decoder
359 and which supplies an enable sign~l causing latch 371 to re-
ceive data provided by CPU a7 on its data output lines. The out-
put data of latch 371 includes the signal SSADO~F which turns the
~ 10 analog to digital converters 181 on the section switches on or
; off. This signal is applied to pin 30 of system bus 13 which is
in turn connected to the sec,tion switches as described esrlier.
Lstch 371 also applies signals SS and C~æ EL to respective pins 23
and 44 of the system bus 13 which sre also used by the section
- switches in the munner described earlier.
Another output signal CI~RDOFF appe~rs on an output data
line of lat~h 371. This signal is used to enable the buffer
amplifiers collectively identified as 379 in ~ig. 6 to gate the
output of ~ tr~cking analog to digital converter 377 to the pins
37, 87, 86, 3g, 84, 83, 82, 76, 75 and 74 of the system bus 13.
As described earlier, tracking analog to digital converter 377 is
used to provide the dig~tal representation of a voltsge at a moni-
tored electrlcal path if ~ like tracking analog to digital ~on-
verter 181 i5 not provided on the section ~witch portions (~lg.
4). When converter 377 Is used, the digital d~ta input to the A/D
multiplier 185 is taken from pins 37, 87, 86, 85, 84, 83, 82, 76
75 and 74, as described earlier with reference to Pig. 4.
Another output signal from latch 371 i~ ADTEST which is
used to control two additional gated buffer ~mplifiers in buffer
379 and the output bu~fers in latch 375 to ~llow signnls AD0
through AD9, respecti~ely taken from other output lines AD0, ADl
~25968~
of latch 371 and all the output lines AD2 . . . AD9 of latch 375,
to pass to the system bus 13 ~D0 through AD9 lines (pins 74, 75,
76, 82, 83, 84, 85, 86, 87 &nd 37). When ADTEST is present, sig-
n~ls AD0 through AD9, which ~orm a test w~rd, a~e applied to re-
spective pins o~ the system bus 13 and these ~ign~ls are used by
the A/D multiplier 185 of the section switches to ~enerate a
corresponding output which i9 digitized by A/D converter 21 and
checked by the CPU a7 for accuracy.
L~tch 375 is also enabled by a signal provided ~s an
output of ~ddress decoder 359. When it is addressed by CPU 27,
d~ta Qpplied on data lines 823 is stored by lateh 375~ When the
signal ADTEST is enabled by latch 371 the contents of latch 375
along with bits AD~ and ADl are passed to the r~spective pins 37,
87, 86, 85, 84, 83, B2, 76, 75 and 7~ of the ~ystem bus 13, as
~ described in the preceding paragraph. The purpose of latch 375 is
to store the eight most significant bits A2 through A9 of the test
word to be applied by ADTEST to the input of the A/D multiplier
185 to test its operation and ~ccurracy.
L~tch 373 is also addressed by an output of Qddress
~o decoder 3~9. When addressed by CPU 27, it latches data on lines
si~nals ~ , ACoRD ~nd SSP which are respectively supplied to
pins 97, 46, and 47 of the ~ystem bus 13~ The~e signals are used
by the section switehes in the manner describe~ e~rlier. Latch
373 also supplies output signals PHO and PHl which ~re applied to
1 of 8 analog switch 337 ~Fig. 5), the operation of which is de-
scribed below.
Latch 373 ~lso applies on respective output lines the
signals TV~, TVl and TV2 which are applied in ~ommon to the d~tn
selection inputs of 1 of 8 an~log switches 347 and 349 (Pig. 6B).
These analog switehes serve to provide a selected test volta~e of
a selected polarity to pin 24 ~ig. 6A) which is connected to one
~L259681
input of 1 of 4 an~log switch 175 and one input o~ an~log switch
161 of each of the se~tion switches (Pig. 4) for testing snd cali-
bration purposes.
A precision reference voltage generator 351 (Fig. 6B~ is
provided which supplies output volt~ges Y7, Y8 and V9 to ~ix of
the eight input lines to switch 347. The other two input lines to
; switch 347 ~re respectively connected to a 60 hz line Yoltage
input on line 813 und ground. The output line of switch 347 is
connected to amplifier 355, the output of ~hich is connected in
common to four of the input lines of switch ~49. The Outpue of
amplifier 355 ~lso passes through inverting amplifier 357 and the
inverted signal is conne~ted to the 4 remaining input lines of
switch 349. A selected one of the switches of analog switches 347
~nd 349 is closed in response to the data selection signals TV0,
TYl and TV2 ~pplied thereto, to provide at the output of switch
349 ~ precision voltage (one of V7, V8, V9, -V7, -Y8, -V9 or a 60
hz reference signal, or Q ground sign~l), the sign~l level flnd
polarity of which is determined by d~t~ sign~ls TV~, TVl and TV2.
An additional reference voltage is taken directly from the refer-
ence voltage gener~tor 351 by ~mplifier 353. This is ~pplied to
the tracking analog to dlgital converter 377 and ls used as a
reference level by the aonverter in performing its converting
oper~tion. The input voltage which is d;gitized by the tr~cking
A/D converter 377 is applied on ~n input line 804 thereto Rnd this
voltage is received from the output of ~ buffer ~mpli~ier 333
(Fig. 5) of the controller interface.
The output of ~nalog switch 349 (Fig. 6B) is Qpplied to
buffer unplifier 381 (~ig. 6A) snd from there to pin 24 of the
syst~m bus 13. The volt~ge on pin 24 is used as ~n input to An~-
log switch 175 of the section switches (~ig. 4) which m~y be used
_ ~ _
1~5968~
as an input to tra~king ~nalog to digital converter 181 for test-
lng purposes.
The precision voltage at the output of buffer ~mplifier
381 is also applied to line 824 which is an input line eO analog
switch 337 (~ig. 5) which will be described below.
The SSP output of latch 373 (Fig. 6A) is slso applied to
a one shot multivibr~tor 383 which produces a pulse signal of a
predetermined duration which appears at the output of inverter 385
as the sign~l SSPC~. This signal is applied to pin 26 of system
bus 13 which }s Qpplied to line 759 o~ the se~tion switch to reset
~ounter 221. Fig. 6A also illustrates the ~oupling of data lines
823 from the master controller through buffer 387 to the pins 90,
40, 39, 38, 89, 88,.3S and 36 of the system bus 13. This signal
path serves to couple the CPU data output lines from the S-100 bus
to the CPU data output pins of the system bus 13.
The controller interface also includes circuitry for
deriving a voltage sign~l representative of the voltage in a moni-
tored electrical path at a remote st~tion from the electrical
service entrance of fl building. Signal lines 801 collectively
represent signal lines connected to two three-phase electrical
service inputs to a building. These sign~l llnes are coupled to
the service entrance by transformers (not shown) whioh step the
high voltQge entering the buildin~ down to a low voltage level.
The lines Al-N, Bl-N, ~nd Cl-N represent three wires connected to
the neutral wire of one of the two three-phase power distribution
lines, while the signal lines Al-0, Bl-0, and Cl-a respectively
represent the three-phases of the first power line. The second
set of power distribution lines are designated as A2-~, B2-N, and
C2-N for three wires connected to the neutral wire and A2-~, B2-0
and C2-~ for the three phases of the second power line. The power
lines, collectively illustr~ted as 801, arP connected to a voltage
~25968~L
dividing network 33~ and the lines A1~0, Bl-0, Cl-~, A2-0, B~-0,
and c2-P are respectively ~oupled to different inputs of ~nalog
selection switch 337. Another ~nput to ~election switch 337 is
the test voltage input on line 824 which is tsken from the output
of buffer amplifier 381 (Fig. 6A).
Analog switch 337 ~ont~ins two switching sections ope-
rating in parallel whlch are responsive to data signals applied to
lines 807 and 809 to selectively connect one ~pplied input signal
to ~n associated buffer 2mplifier ~333 or 335) respectively con-
nected to the outputs of the two sections of switch 337. The data
: applied to lines 807 and 809 are the si~nal~ PH0 ald PHl which
appeQr on the output of latch 373. By ~ddressing latch 373 and
applying the appropriate signals PH0 and PHl thereto CPU 27 eon-
figures one half of switch 337 to pass one of the ~ignals on input
- lines 824, Al-~, Bl-0, or Cl-0 to the input of buffer amplifier
333. The output of buffer amplifier 333 is spplied to pin 33 of
; system bus 13 and to line 804 which is applied ~s an input to
tracking A to D converter 377 tFig. 6A). Likewise, in response to
PHa and PHl the other half of switch 337 couples one of the out-
: 20 puts from lines Al-N, A2-a, B2-~, or C2-0 to the input of bufferamplifier 335, the output of which i9 connected to pin 34 of the
system bus 13. The voltages of p~ns 33 and 34 appear as inputs to
~nalog 6witch 175 o~ the section switches (Fig. 4) as described
earlier. The voltage applied by buffer amplifiers 333 and 335 to
pins 33 and 34 respectively can be used by the tracking analog to
~ digital converter 337 in the controller interface ~333 only) or by
; the tracking analog to digital converters 181 in the section
switches (333 or 335) to provide a digital sign~l representative
of the volt~ge on a monitored electrical path which can be used as
the inputs to multiplier 185 for calculating power consumption.
6~
~i~. 5 also illustrates ~n oscillator 301, the output of
which is connected to the inputs of rreguency dividers 303 ~nd
305. Frequency diYider 303 provides ~n oueput signal of, e.g. 500
KHz, to pin 48 of the system bus 13 to which the elocking input of
the tracking A/D conYerters 181 of the section switches Qre con-
~ected (Pig. 4). The SOO KHz output of frequency divider 303 is
also ~pplied to sign~l line 822 which i~ used as a clocking signal
for tracking an~log to digital converter 377 (Fig. ~A). Frequency
divider 305 provides an output signal of, e.g. 15 KHz, to pin 25
of the system bus. The 15 KHz output signal of frequency divider
305 is used QS a clocking input to Q counter 317. When counter
317 is enabled by 8 signal applied to the enQble input thereof, it
continually ~ounts and the counted output appears on output lines
805 as an input to ons of eight an~Iog switch 31~. As counter 317
eontinues to count, individual switches of analog switch 319,
which have respective inputs connected to the lines Al-~, Bl-0,
Cl-0, A2-0, B2-0 and C2-0, will be successively closed. The out-
put line 321 from switch 319 is applied via diode 345 to the input
of a comp~rator 315 consisting of ~ comparison ~mplifier 343.
Comparison amplifier 343 provides an output whenever an input
voltage is applied thereto which exceeds a predetermined reference
voltage. The purpose of switch 319, counter 317, and comparator
315 ls to provide ~n automatic ~dap~ive control loop which will
continue to step switch 319 until a vol~age is found on one of the
~ power lines Al-a, Bl-O, Cl-0, A2-~, B2-~ or C2-O. When a voltage
: is found, it is sensed by comparison Rmplifier 343 which changes
: state and removes the enable input on counter 317, stopping the
counter from eounting further clock pulses received from frequency
divider 305. This causes ~nalog switch 319 to remain in its last
state effectively locking the switch closed on one o~ the power
lines whieh has ~ volt~ge ~her~on. The output line 321 from
~1 ,
~2S9~8~
an~log switch 319 is applied ~s ~n input signal to a ph~se lock
loop (PLL) frequency multiplier 3fl7, the output of which (~out) is
thirty-two (32) times the input frequency (f in) . The output of
multiplier 3~7 appears on line 310 which runs to the master con-
troller (Fig. 7). This signal is used as a sampling interrupt
~ignal ~I4 in a manner more fully described below.
The output of frequency divider 305 is also applied to
pin 25 of system bus 13 whi ch connects to NAND gate 227 of the
section swit~h portions (Figs. 3, 4) as described previously.
The controller interface also includes a programmable
frequency divider 313 (Fig. 5) which receives ~s an input an out-
put of oscillator 301. The frequency of oscillstor 301 is divided
by a value progr~mmed into the frequen~y divider 313 on data lines
817. These data lines recei~e data from latch 369 (Fig. 6A) which
is addressed by the CPU 27 to ~pply data to the latch representa-
tive of a desired tone frequency which is to be sent from the
section switches to the remote station lines connected thereto.
One tone frequency, e.g. lOOKhz, is used for sddressing the infor-
mation channels 10 at the remote stations, while other tone fre-
quencies can be used to control an operative device connected to
an addressed information channel 10 at a remote station. The out-
put of pro~rammable frequency divider 313 ls app~ied to an active
filter 311, the output of which is coupled to a buffer amplifier
309, the output of which is connected to pin 49. As discussed
earlier, the section switches are eonnected to pin 49 (Fig. 33 via
~mplifier 141 to supply a tone on input line 761 of one of eight
analog switch 161, which when appropriately configured by CPU 27,
supplies the tone to a remote station communications ehannel which
is eonne~ted to a respective section switch.
Fig. 5 also illustrates a set of buffer ~mplifiers, 325,
which are pro~ided in the ~OntrGller interface to couple data on
`~
_ ~ _
lZ59~i81
pins 43, 93, 32, 91l 42, 41, 94 ~nd 95 of the system bus 13 to
data lines 833 which run to the master controller (Fig. 7) and
: from there to the CPU 27 dsta input pins of the S-100 bus.
Fig. 5 also i}lustrstes lines 82~, 829 and 831 which
respec'ively receive the signals LINESEL, PDBIN and SS10 from the
master contro}ler (Fig. 7). These signals are ~oupled through
respective buffer ~mplifiers 327, 329 ~nd 331 to pins 32, 78 and
45 of the system bus 13 and ~re received and used by the section
switches as described earlier with reference to Fig. 3.
A line 811, also originating in the m~ster controller~
supplies a tone enable signal ~TONEN) which is inverted by in-
verter 323 and ~pplied as an ENABLE input to programmable fre-
quency divider 313.. Accordingly, the frequency emitted by pro-
: gramm~ble frequency divider 313 is controlled by data on the input
~ lines 81~ and the on/off state of the programm~ble divider is
controlled by the TONEN signfll on line 811 from the master con-
troller.
MASTER OONTROLLER
The system m~ster controller 19 (Pig. 1) is illustrated
in greater detail in Fig. 7. One of the principal functions of
the n~ster controller 19 is to provide the CPU 27 with three sepa-
rQte interrupt signals which are used by CPU 27 to execute various
interrupt programs for ~cquiring and processing d~ta from remote
station sensors.
The m~ster controller includes an oscillator 675 having
~n output signal which is connected to the input of a frequency
divider 67~. The output of freguency divider 677 is connected to
frequency divider 683 the output of which provides a master
interrupt tyiming signal MT0 on line 784. The output of frequency
divider 677 is ~lso coupled to the input of a programmable counter
illustrated as having two separate program~able counting sections
~G\
~L~59~
679 and 681. The programmable counter sections are e~ch con-
; figllred to load ~n eight bit data signsl which corresponds to a
count value which must be re~ched before ~n output signal is pro-
vided on line 783 fram the programmable counter. The two eounter
se~tions 679 and 681 are separately lo~ded in two successive eight
bit bytes of a data signal applied to lines 781 by CPU 27 through
buffer 685 whi~h is connected to the CPU dnta output pins 36, 35,
88, 89, 38, 39, 40 and 90 of the S-100 bus. Data signals from CPU
27 program the counter sections 679 and 681 to set the time period
(number of clock signals counted) which must transpire before an
output signal is placed on line 783. The counter sections 679 and
681 are respectively lo~ded by load signals FTP and CTP provided
; on lines 785 and 781. These signals are generated as sepsr&tely
dec~ded addresses by address de~oder 793 which is ~onne~ted to
: address lines A0, Al and A2 of the S-100 bus (pins 79, 80 and
: 81). Signals ~TP and CTP are applied to counter sections 679 and
681 after passing through respective buffer ~mplifiers 798 and
796. When CPU 27 programs the two sections 679 and 681 of the
programmable counter, it successively outputs the signals FTP and
CTP by providing appropriate address signals to address decoder
792, along with the data which is to be loaded into the counter
3ections 679 and 681 (applled to lines 781) by the FTP and CTP
load signals.
The output of the programmable counter (PTO) on line 783
is a programmable time duration interrupt control signal, the
purpose of which will become more evident in the discussion of the
interrupt programs executed by CPU 27.
The programmable counter is enabled by PTEN, a data
signal applied by.CPU 27 to latch 601 ViR the S-100 bus data out-
put lines through buffer B85. The signal PTEN is used to gate theprogr~mmable counter on so that after expiration of the time
4'~
~S96~1
period set therein, the signal PTO will be genersted. Other sig-
nals supplied to latch 601 by the CPU 27 are TONEN, PTIR, MTPS,
MTIR and VI4EN, the purpose of these signals will be described
below.
The tone enable signal ~TONEN) from l~tch 601 is sup-
plied as an sutput on ~ line 811 which eonnects with the con-
troller interface (Fig. 5) and provides the on/off eontrol signal
to the enable input of programnable frequency dividèr 313 as de-
scribed above.
The MTPS signal is an enable signal which is ~pplied by
the CPU (thr~ugh latch 601) to frequency divider 683 to on/off
control its operation.
The remaining three signals at latch 601, PTIR, M~IR and
YI4EN control the ~pplication of three separate interrupt sign~ls
- to the CPU interrupt lines as more fully described below.
Address decoder 786 is connected to the A4, A5, A6
; and A7 address lines respectively connected to pins 30, 29, 82 and
83 of the S-100 bus. Address decoder 786 serves to decode four
groups of sixteen addresses. For purposes of simplifying descrip-
tion, the address dec~der is illustrated as having decoded output
lines of 3X, 4X, SX, ~nd 6X (hex notation). The X represents one
of sixteen possible hexidecimel nwmbers (~ o, for exam-
ple, the address deooder provides an output on line 3X when it
decodes any one of the hex decimal addresses 30. . . 3F.
The 3X output is supplied QS an input to negative input
AND g~te 774 which receives et another input thereto the output of
NOR gate 790. Gate 774 is thus enabled whenever an ~ddress 3X is
decoded and e SINP or SOUT signal is detected at respective S-100
bus pins 46 and 45. As described earlier, SINP and SOUT are sig-
nals supplied fr~m the CPU 27 to the S-100 bus when it is getting
_ ~ _
~L259681
ready to input d~t~ (SINP) or output d~t~ (SOUT) so thQt ~ssoci-
ated devices conne~ted to the ~-100 bus can suitably ready them-
selves for the input or output operations. When gate 774 is
enabled, it supplies ~ signal to inverter 776, the output of which
is supplied to negative input OR gate 782 ~s one enabling input
thereof. The output of inverter 776 is also applied to a buffer
amplifier to generate the the signal SSI0 on line 831. This sig-
nal is applied to the controller interface (Fig. 5) which in turn
supplies it to pin 45 of the system bus 13 as previously de-
scribed.
The 5X decode output of address deeoder 786 is applied
as one input to a negative input AND gste 772, the other input of
which is connected to the output of NOR gate 790. When enabled by
the concurrent presence of the two input signals, g~te 772 pro-
- vides a sign~l LINESEL which passes through inverter 653 and
appears on line 827 as LINES~L. This signal is ~pplied to ehe
~ontroller interface (Fig. 5) which in turn supplies it to pin 32
of the system bus 13 and from there to the section switches as
described earlier.
The decoded 6X output from address decoder 786 is sup-
plied as one input to negative input AND gate 770, the other input
of which receives the output of NOR gate 790. W~en enabled by the
concurrent presence of the 6X decode addresses and a SINP or SOUT
signal from CP~ 27, gate 770 supplies, through buffer 651, a sig-
nal IFIO to line 825 which leads to the controller interface (Fig.
6A) as previously described.
The respective outputs of gates 770, 772 and 774 are
also applied through respective inverters 778, 780 and 776 as
: inputs to negative input OR gate 782. The output of gate 782
enables, through NAND gate 79a, a wait st~te generator 784 which
supplies ~ wait signal to an output PRDY line connected to pin 72
S9~1
of the S-100 bus. When a wait signal is supplied to pin 72, the
CPU stops oper~ting. The wait state generator 784 i3 a counter
which counts through a predetermined ~ounting period upon being
enabled. It receives a clock input of, for exhmple, 4 MHz which
is available at pin 24 of the S-100 bus. To ensure th~t timing
begins at an appropriate point in the instruction execution cycle
of the CPU 27, a PSYNC signal applied to pin 76 of the S-100 bus
by the CPU 27 is also npplied as an enabling input to NAND gate
792. The PSYNC signal synchronizes enablement of the wait state
generator with the CPU instruction processing.
As noted, address decoder 793 receives address signals
from the ~ddress lines A0, Al and A2. It &Iso receives ~n enable
signal P~R through inverter 77~ which recei~es the signal FW~ from
pin 77 of the S-100 bus. The signal yr~ is generated by CPU 27
during an DUtpUt operation indicating that valid data is on the S-
100 CPU data output pins. Address decoder 793 also has two nega-
tive enable inputs, one of which is connected to the 4X decoded
output from address decoder 786 end the other of which is con-
nected to the output of NAND gate 768 which in turn receives at
one input the output of NOR g~te 7g0 through inverter 788. The
net result of the enable signals ~nd ~ddress signals applied to
address decoder 793 is that it decodes addresses corresponding to
the sign~ls FTP and CTP and the en~ble signal for 1 Q tch 601
(applied through inverter 794) from the CPU 27.
The m~ster ~ontroller also provides three separate in-
terrupt signals ~, Pl~ ~nd V7~ to respective pins 10, 9 and 8 of
the S-100 data bus. These pins are in turn connected to three
interrupt lines of CPU 27. The CPU processes applied interrupts
in ~n order or priority with the M~l interrupt being of highest
priority and the VI4 interrupt being of lowest priority. Each
interrupt has one or more respective interrupt programs associ~ted
_ ~ _ .
~596~3~
therewith which CPU 27 execut*s upon being interrupted. These
progrQmS will be described in det~il below.
The three interrupts signals generated by the system ~re
a master interrupt M~I applied to pin 10 of the S-l~0 bus (Fig.
7)9 a progr~mmable interrupt PTI applied to pin ~ of the S-100
bus, and a s~mpling interrupt VI4 phuse locked to an AC power line
~nd applied to pin 8 of the S-100 bus. The latter interrupt is
gener~ted by the ph~se lock loop (PLL) frequency multiplier 307 of
the controller interfsce (Fig. 5) and is supplied as ~ signal VI4
on line 310 to the master controller. The programmable interrupt
PTI is provided on pin 9 upon the appearance of the output signal
PTO fram programm~ble counter section 679 on line 783. The master
interrupt ~Tl is provided on pin 10 upon the appearance of the M~O
signal emitted by frequency divider 683 on line 784.
~ The three interrupt control signQls V14, PTO and M~O are
each connected to respective identical latching and reset circuits
in the m~ster controller. For the purpose of simplifying descrip-
tion, only the latching and reset circuit which generates signQl
PTI will be described in detail. The PTO control signal on line
783 is ~pplied to a clock input of a ~lip-flop 603 the output of
which en~bles buffer ~mplifiers 607 and 609 to ~pply a ground
cvndition to reopective pins 73 and 9 of the S-100 bus. Ampli-
fiers 60~ and 609 respectively gener~te output signals PINT and
_
PTl. The PINT sign~l which is applied to pin 73 of the S-100 bus
goes "low" to indicate to the CPU 2~ that Rn interrupt has
occurred. The CPU a7 then examines Its interrupt lines respec-
tively connected to pins 10, 9 snd 8 of the S-100 bus to determin~
which interrupt~s) is occurring. The CPU then processes the in-
terrupt program for the highest priority interrupt then occurring.
After the interrupt PTl occurs, flip~flop 603 must be
~ reset before the occurrence of the nèxt interrupt, otherwise it
:
1~:59~
will not be detected. For this purposeJ flip-flop 603 is reset by
a signal PTIR which is provided on ~n ~utput line of latch 601.
CPU 27 supplies the signal PTIR to the latch 601 to reset flip-
fl~p 603 during processing of the interrupt program(s) associated
with the PTI interrupt. The m~ster interrupt control sign~l M~O
on line 784 likewise clocks flip-flop 605 which is reset by
signal MTIR also received from the output of latch 601. In like
manner, the interrupt control signal VI4 received on line 310
clocks flip-~lop 617 which is reset by the signal VI4EN supplied
by l~tch 601. Whenever any of the interrupt outputs to respective
pins 10, 9 or 8 is generated, the associated interrupt reguest
signal PINT is also generated to notify CPU 27 that Qn interrupt
signal is present.
Fig. 7 ~lso sh~ws a buffer 627 which is used to output
dats to the deta input pins 43, 93, 92, 91, 42, 41, 94 and 95 of
the S-100 bus which are connected to the data input lines of CPU
27. The buffer is enabled by the output of negative input AND
gate 623. One input to gate 623 is taken from the output of in-
verter 625 which has an input connected to pin 78 of the S-100
bus. This pin has a signal PDBIN applied thereto by CPU 27. As
described earlier, this signal is supplied when CPU a7 desires to
read input data. The ot~er input to gate 623 is taken from the
output of inverter 776. Thus, whenever address decoder 7B6 de-
codes a 3X address and CPU 27 supplies n SINP signal to NOR gate
790 (enabling negative input AN~ g~te 774) and the signal PDBIN to
negative input ~ND gate 623, the latter is enabled to enable
bu~fer 627 and allow data to pass to the input pins of the S-100
data bus.
A/D O~NVERTER
Figs. 8A and 8B show the details of the analog to digi-
tal converter 21. This device receives each of the output lines
1~:5968~L
from the seetion switches J0 . . . J31. These outpuS lines con-
tain an Analog sign~l representing ~ sensor output, an AC power
calculation 6ignsl or ~ test signal. The ~n~log signals on the
section switch output lines are digitized by A/D conrerter 21 ~nd
are then supplied to the data input lines of the S-100 bus for
input to the CPU 27.
The A/D converter 21 includes an address decoder 501
(Fig. 8A) which is connected to the address lines A0, Al, . . A7
of the S-100 bus. Address decoder 501 has three output lines 903,
~ 10 905 and 907. Output line 907 eontains a signal when ~ny one of 32
; different addresses, corresponding one each to the section switch
Fig. 4 portions, are received frGm the CPU 27. This line is an
~ddress line for energizing the A/D converter 21. Output lines
903 and 905 of address decoder 501 are two specific ~ddresses
which supply signals to negative input AND gates 515 and 517 re-
spectively. These g~tes respectively enable latches 5~9 and 513
which receive data from the CPU through buffer 507 ~onnected to
the data output pins 90, 40, 391 38, 89, 88, 35 and 36 of the S-
100 bus. Additional input enable signals to gates 515 and 517
arrive from the output of inverter 519 which has an input con-
nected to the output of neg~tive input ~ND gate 521. The two
inputs to g~te 5al come respectively from pin 77 of the S-100 bus
and NOR gate 523 having }ts inputs respectively connected to pins
~ 45 and 46 of the S-100 bus. NOR gate 523 determinès wh~ther the
; CP~ 27 has supplied either of the signals SOUT or SINP to the S-
100 bus, respectively indicating thet output data will be supplied
or thAt it will ~ccept input data. W~en gste 523 detects either
of these signals and the signal PWR is Qpplied to pin 77 by CPU 27
when it is re~dy to do an output operation, gate 521 will be en-
~bled ~nd either of g~tes 515 ~nd 517 will thus be enabled depend-
ing on which is ~ddressed by the CPU 27 via the signal on lines
903 and 905 of address decoder 5Dl.
$~ ~
,,
~Z5~3168~
Latch 513 receives previously stored offset data from
the CP~ 27 via buffer 507 which is representatiye of calibration
voltages obt~ined from the various sensors which ~re connected to
the inf~rmation channels at the remote stations during a calibra-
tion procedure. This digitized offset data is supplied to the
input of D/A converter 511. The calibration voltages ~re obt~ined
by sequentially sc~nning the sensors when they are under known
losd conditions snd they are stored by the CPU 27 for summation
with actu~l sensor output signsls which are to be digitized. The
output of latch 513 represents, in digital form, the upper eight
bits of the digitized offset values. The lower two bits come from
latch 509 and are lstched therein together with- the control sig-
n~ls GAIN 4X, SIGN, SUMINV, 11 BIT, TW~'S COMP and ~TE-ER, all of
which are supplied by CPU 27. The control sign~ls configure A/D
converter 21 to different operative states as described ~elow.
Digital to analog converter 511 has a control input
which selects the pol~rity (positive or negative) of the ~nalog
output. The polarity of the offset is set by the SI~N control
signal at the output of l~tch 509~
The analog offset voltage output of D/A converter 511 is
fed to a summing amplifier 512 which receives at its other input
the output of 1 of 32 line select switch 503. This device is
sim}lar to previously described analog selection switches. A
particular switch is ~losed to pass one of the input lines to the
output line 901 in eccord~nce with the ad~ressing d~ta signal
applied thereto. The selecting of an appropriate input line is
accomplished by eonnecting the data sele~t input 505 of the line
select switch 503 to the ~ddress bus lines AO . . . A4 of the S-
100 bus. The line inputs to the line select switch S03 are the
3~ respective lines J0 . . . J31 exiting from the section switches.
Two lines exit each section switch, one for e~ch of the Fig. 4
_ ~ _
1~596~31
portions. These lines represent the 32 wire pairs which are re-
spectively connected to 32 groups of remote stations.
Summing amplifier 512 sums the cRlibration offset volt-
ages applied by D/A converter 511 with the output from the section
switches which are selectively ~onnected to line 901. Summing
amplifier 512 has a swit~h~ble gain. In norm~l operation it has a
gain factor of one, but It cQn be ~witched by a eontrol signal
GAIN-4X applied from the output of latch 509 to a gain factor of
4. The output of s~nning ~mplifier 512 is applied to switch~ble
polarity, unity gain amplifier 514. The polarity of the output of
umplifier 514 is set by the ~ontrol signal SUMINV. The output of
amplifier 514 appears Qt line 914 which is ~n input line to A/D
. converter 553 ~Fig. 8B). The output of A/D converter 553 is sup-
. plied via g~ted buffers 563, 565 ~nd 567 to data lnput pins 43,
: . 93, 92, 91, 42, 41, 94 and 95 of the S-100 bus and ~re thus fed to
cPU a7.
Buffers 563, 565 ~nd 567 are used to gate the 11 bit
output lines of A/D converter 553 to the 8 bit input data lines of
CPU 27. Various outputs of the A to D converter 553 are trans-
mitted to the CPU 27 dsta input lines by operating buffers 563,
565 ~nd 567 at different times under control of ~ decoder 55l ~nd
flip-flop 548 (~ig. 8B). Decoder 551 de~odes the control signal
11 BIT to act}vate either its ~0" or nl~t output lines depending on
the level of 11 BIT. When decoder 551 ~pplies a signal to its 1'0ll
output line, g~te 563 is enabled. Decoder 55l, in turn, is en-
abled by the output of inverter 539. When enabled, buf~er 563
applies the 8 most significant bits (M~BS) of the output of A/D
~onver~er 553 to pins 43, 931 92, 91, 42, 41, 94 snd 95.
Plip flop 548 has its two outputs ~Q, Q) respe~tively
~onnected to the en~ble inputs of buffers 565 and 567 through
gated buffer ~mplif~er~ 5~0. The g~ting signal for ~mplifiers 550
~Z596~3~
originates nt the "1" output line of decoder 551. When decoder
551 enables ~mplifiers 550 either buffer 565 or 567 will be en-
abled depending on the state of flip flop 548. By toggling flip
flop 548 buffers 565 and 567 can be sequentially enabled.
Buffer 565 has five upper inputs connected to the output
of a gate 557 through inverter 568 ~nd the next input to the M~B
or m~-B output of converter 553 8S described below. The l~st two
bits of buffer 565 go to bits 9 and 8 of A/D converter 553.
Buffer 567 h~s its 8 inputs connected to the 8 least significant
bits of A/D converter 553. As c~n be seen~ by ~ppropriately con-
trolling decoder 551 with the control signal 11 BIT and operating
flip flop 548 with ehe outputs of gates 531 and 533 (respectively
spplied to the S and CL inputs) various output bits of the A/D
oonverter 553 can be gated under eontrol of CPU 27 to its data
; - inputs.
The uppermost data input line of bufer 563 is connected
to the most signific~nt bit MBB and inverted most significant bit
M~B output lines of A/D converter 553 through negative input ~R
gate 561, and NAND g~tes 557 ~nd 559. The purpose of these ga~es
and inverter 55-5 is to 8110w the upper data line of buffer 563 and
buffer 565 t~. receive either the MSB or MSB outputs of A/D con-
verter 553. This is under control of the TW~iS OOMP control sig-
nal at the output of latch 509.
The A/D converter 21 ~lso in~ludes various gati.ng cir-
cuits which are used to control operation of the A/D converter 553
8S well as to enable decoder 551 and operate flip flop 548. Nega-
tive input AND gate 529 receives the output of NOR gate 523 and
the output of en inverter 527 connected through the buffer 525 to
the pin 78 of the S-100 bus which contains the PDBIN signsl.
Accordingly, when the CPU 27 outputs either an SOUT or an SINP
signal ~nd 8 P~BIN signal, gate 529 is enabled. The output of gate
1259t68~
529 is supplied to the input of NAND gate 531 which has at its
other input the output signal on line 903 which is an address
decoded by ~ddress decoder 501. W~en the address signal and out-
put of gate 529 are present, gate 531 is enabled to supply a sig-
nal to one input of negative input OR gate 537 which receives at
its other input the output of NAND gate 533. The inputs of N~ND
g~te 533 are respectively connected to the output of gate 529 and
line g07 which is one of the ~ddress select line for the A/D con-
verter 21. A~cordingly, when the A/D converter 21 is nddressed to
make line 907 true and the CPU supplies the signals PDBIN and
either of SOUT or SINP, NAND gate 533 is enabled. When either of
gates 531 or 533 are enabled, negative input OR g~te S37 supplies
an output signal which is inverted by inverter 539. The output of
inverter 539 is passed to the decoder 551 enabling it to supply
its decoded output to the "0" or "1-- output line. The output of
gates 531 ~nd S33 also control the state of flip flop 548 and in
turn the enablement of buffers 565 and 567.
The output of NAND gate 533 is also connected through
inverter 535 to one input of NAND gate 541 which receives as its
~o other input t~e PSYNC signal on pin 76 of the S-100 bus through
bu~fer 525. When enabled by the concurrent presence of the two
input signals thereto, NAND gate 541 supplies ~n enable signal to
wait state generator 545. Wait state generator 545 is similar to
the wait state generator on the master eontroller. When enabled,
it counts a predetermined number o~ clock pulses before emitting
an output signal. The purpose of wait state generator 545 is to
; allow data to settle on the incoming section switch lines before
AID converter 553 is instructed to perform ~ conversion operation.
The output signal from wait state generator 545 is supplied to H
convert input terminal of the AID converter 553 and this starts
the A/D conversion operation.
125i96~3~
The output of NAND gate 541 which enables the wait sta$e
generator is also applied as a clear (CL,~ input to flip-flop
575. The output of flip-flop 575 passes through NOR gate 5?3 and
activates buffer S69 to pull the line ¢onnected to pln 72 of the
S-100 bus ~low". This supplies a PRDY signal to the CPU 27 plac-
ing it in a wait state. After the wait state counter counts to
its predetermined value (approximately a two micro-second delay),
the A/D converter 553 is Instructed to begin conversion. At this
time the status line STA of A/D converter 553 goes high and re-
mains high during the conversion process. This signal p~ssesthrough NOR g~te 573 and keeps buffer amplifier 56~ enab~ed to
continue application of the PRDY signal to pin 72 of the S-100
bus. After conversion is ~ompleted (approximately two micro-
seconds), A/D converter 553 removes the high signal from the
status line &nd also supplies a clock reset signal to ~lip-flop
575 so that NOR gate 573 is now disabled and removes the control
signal from buffer amplifier 569 thereby removing the wait signal
from PRDY pin 72. A set input (line 526) to flip-flop 575 is
supplied through buffer 525 from the POC line connected to pin 99
of the S-100 bus. This signal is ~ reset signal which is applied
to pin 99 whenever the system is reset and merely resets flip-flop
575 whenever a main system reset occurs.
A negative input CR gate 571 is also provided which
recei~es the ~T~-EN signal from latch sag snd the output of gate
573. It supplies An enabling signal to line select switch 503 on
line 911 whenever GATE EN is present or when gate 573 is supplying
a wait state control signal to gated buffer ~mplifier 569.
SENSORS
The system as described aboYe has the cap~bi1ity of
measuring ~ sensor output as a resistance, a preclsion resista~ce
ehange, A volt~ge, or a current. The sensor outputs are read and
~25968~
digiti~ed under control of CPU 27 during the time that the ad-
dressed information channels are connected to the central station
ov0r one of the 32 line pairs connecting the ~entral station with
the various groups of remote stations. The outputs of the sensors
can represent sensed temperature, fluid flow, BTU sonsumption,
etc. virtually without restriction.
Several representative sensors which c~n be used in the
invention and the par~meters which they measure will now be de-
scribed.
~or the purpose o~ measuring current ;n an electrical
path at a remote station, a current ~easuring transdllcer as shown
in Fig. 26 m~y be employed. It comprises a pr cision wound
toroidal current transformer 210 having a precision resistor ~08
mounted adjacent to the trQnsformer. The precision resistor 208
is connected in parallel with the secondary output of the trans-
former and with a pair of back-to-back Zener diodes ~04 and 206.
A resistor 202 is also connected in series with the coil, pre-
cision resistor and Zener diodes and the entire assembly is then
connected across the terminals of an information channel 10 at a
remote station. Since th~ precision resistor ~208 is a fixed part
of the assembly, the output of the circuit illustrated in Fig. 2
is a voltage, not a current, as with ~ standard ourrent trans-
former. The main advantage of having a voltage output for the
current sensor is that the length of wire between the transducer
and an actual measuring device is not critic~ s is the case
with a typical current transformer.
The series resistor 202 at the current transducer output
is used to provide a high output impedance which mRkes it easy to
detect tampering with the current tr~nsducer. ~or example, if
various resistiYe or reactive electrica1 components are connected
across the output of the current transducer, the resultant
S~
1~59~1
impedance change caused can be easily detected. T~mpering can
thus be detected by periodically operating CPU a7 to check the im-
pedance of the current transducer against a known reference im-
pednnce value for the transducer stored during initial cslibration
of the system. The purpose of Zener diodes 204 and 206 is to pro-
tect precision resistor 208 ~nd the remote station ll to which the
transducer is connected from very high current surges in line 212
which try to induce very high volt~ges ~cross resistor ao8.
The present invention can ~lso be used to economically
measure temperature, fluid flow and heat flow at a multiplicity of
locations. This is done by using a combination of resistance and
precision resistance change measurements in conjunction with var-
ious temperature and flow sensors which have been developed to
supply resistance an~ precision resistance outputs to the inform~-
tion channels 10.
Temperature is measured using a thermistor or other
temperature sensitive device which is connected to an information
channel 10 st a remote station. CP~ 27 operates the A/D converter
21, controller interface 15 and section switches 17 to acquire and
store the temperature sensor output as digital data.
Air flow is determined by measuring the temperature
difference between a first conventional temperature sensor e.g. a
thermistor, provided in an air stream and R second temperature
sensor provided in the air stream at a location downstream of the
first. Fig. a7 illustrates an air flow sensing system using a
thermistor 214 and a thermistor 218, the latter being thermally
bonded to a fixed resistor 216 by a thermally conductive epoxy
224, as the first and second temperature sensors. Resistor 216 is
con~ected across a voltage source 222. Also illustrated is a
convsntional humidity detector 220. The temperature difference
between thermistor 218 and thermistor 214 (each of which changes
1~59~83L
resistance with temperatures changes) dekermines the air flow
since for sny gi~en air handling system a curve of air flow rate
versus temperature differences can be experimentally derived.
Although these curves vary somewhat with absolute air temperature
~nd humidity, it is possible to construct f~milies of curves for
air flow rate versus temperature difference which are entered into
CPU 27 and used as look up t~bles for determining an air flow
knowing the sbsolute air temper~ture snd the humidity.
Humidity is measured by humidity detector 220 which
provides ~n output resistance which changes with air humidity
level. Since any one of several conventional devices can be used
as humidity detector 220 a detailed description o this device is
not provided.
The purpose of fixed resistor 216 ~nd associated voltage
source 222 is to pro~ide a heated surface in contact with ther-
mistor 218 which is maintained approximately 20 to 30C sbove the
air temperature under full flow conditions. ~xperimentation h&s
shown that the most accurate results are ~chieved when the heat
dissip~ting area of the downstream sensor comprised of resistor
216, thermistor 218 ~nd epoxy housing 2a4 is small dnd of con-
9 istent size ~nd symmetrical shape to minimiæe the effects of
orientstion of the sensor in the flow stre~m which is being
me~sured. The best configuration for the sir ilow sensor has been
found to be ~ resistor ~nd thermistor encapsulated in ~n oval
shsped housing made of a highly thermally condu~$ive snd low eleo-
tricslly conductive epoxy 224. The ovel shApe mskes it possi~le
to string the flow sensor scross Qn ~ir flow duct perpendicular to
the air flow with a minimwm of air disturbance and without concern
for its rotational posi e ion.
Heat tr~nsferred in BTU's by ~ir handling heat ex-
ch~ngers c~n be determined by using the invention with sensors
S'~
-- ~B --
lZ59~8~L
which measure the input air tempersture to an air heat exchanger
(e.g. sensor 214, ~ig. 27), the output air temperature from the
exchanger~ the sir flow rate (e.g. sensors 214 ~nd 224~ ~ig~ 27)
and the humidity (sensor 220). For each combination of these
parameters, ~ unique BTU ~alue will exist. Thus, CPU 27 can read
the values of these parQmeters fr~m sensors connected at the re-
mote station and calculate the corresponding BTU value.
Water ~r other liquid) flow is measured by the system
of the invention in much the same m~nner as air flow. In this
lQ case, however, humidity v~riations are not a consideration. To
measure water flow, a thermistorlresistor sensor, similflr to that
for the Gir flow, has been devised which is housed in a tiny metal
can. This flow sensor is illustrated in ~ig. 28A and 28B. The
sensor 226 ~omprises a chip resistor 234 whieh is connected to a
- voltage source 238 for providing a constant temper~ture adjacent a
thermistor a36 which is mounted by means of highly thermally con-
ductive epoxy 232 in thermal contact with resistor 234. The en-
tire assembly then is encased in a metal can 230 which is provided
in a h~using 228. The met~l can is then inserted into a hole in a
pipe 242 which defines a water ilow path. A saddle T or other
type of fixation device which will allow penetration of the metal
can Into the w~ter stre~m without causing a leak in the pipe is
used.
An additional thermistor 244 is mounted upstream o
sensor 226. Sensors 244 and aa6 operate essentially on the same
princip~l as the two sensors of Fig. 27 which measure air flow.
For any given water flow path, a set of curves csn be experi-
mentally obtained representing a temperature difference between
the sensors which corresponds to a particular flow rate. Thus, a
set of curves can be experimentally obtained and stored by CPU a7
rel~ting the wster flow rate to R difference in temperature sensed
~,~
~L25~9~8~
by sensors 244 ~nd 226. The cylindrical sh~pe of the metal can
makes it possible to place the flow sensor in ~ pipe perpendicular
to the water flow without having to worry about its rot&tional
position. Once the temperature difference is determined, CPU 27
c~n then calculate a water flow r~te.
For BTU me~surements of liquid flow he~t e~changer; the
sensors 244 ~nd 226 can be used on the input line to Q he~t ex-
ohanging device 231 (Fig. 29). The output line of the heat ex-
changing device csn also be connected to Qnother temperature
sensor 245 identical to sensor 244. By measuring the input flnd
output liquid temperQtures with sensors 244 and 245 and the liquid
ilow rate with sensors 244 and 226 ~s described aboYe~ the ~mount
of thermal energy emitted (or collected) by heat exchanger 231 c~n
be determined.
The charscteristics of the e,ir and fluid flow SeDSOrs
ilustrated can be varied by changing the materi~ls, component
values, he~ter power, mechanicQl configurQtion and physical size.
Consistency from one sensor to another is achieved when ~11 these
p~rameters are maintained constant. However, even if there are
variations fr~m one sensor to another9 the data processing ~nd
stor~ge cQpabilities of the CPU 27 can obtain consistency between
sensors QS it can store known flow cQlibration readings for e~h
sensor so that actu~l sensor readings can be balanced out usjng
the cnlibration data. Thus, inexpensive sensors cQn be used while
still achieving a high degree of measurement QccurQcy.
CPU OPERATION
Sensor dHta gathering and processing for the system is
handled under interrupt control of the C~U 27. Further processing
of the sensor data into more meaningful information for the dis-
play of gathered ~nd process~d dsta is handled by an operator
~'6
12S968~L
inter~ctive seguential progrQm (OIP) which runs continuously,e~cept when interrupted by the various system interrupts.
The system uses three interrupts to control the oper~-
tion of CPU 27. These have been briefly described ~bove with
reference to the system h~rdware. The highest priority interrupt
Mrl i6 generated under control of the master timer sign~l M~O
which is the output of divider 683 in the m~ster controller. MrO
is a pulse signal generated, for example, at the rate of 512
pulses per hour (one every 7.03125 seconds).
The next highest priority interrupt PTI is gener~ted
under control of the output (PTO) of the system's progr~mmable
timer formed by programmable counter sections 679 and 681 in the
master controller. This interrupt is the system's n~st actiYe
interrupt and the time between the occurrence of PTO is programmed
by the CPU a7 during execution of a program. Por purposes ~f
subsequent description the PTI interrupt will be referred to as
the sensor interrupt.
The lowest priority interrupt Y14 for the system is
generated by the ph~se lock loop IPLL) multiplier 307 on the con-
troller interfsce. The output of the phase lock loop frequencymultiplier is 32 equally sp~ced pulses for e~ch oycle of an
applied 60 Hz input signal; that is, a pulse rate of 1920 Bz.
These interrupts are used by CPU 27 to gather and process data for
AC power me~surements.
The overall program executed by CPU 27 is illustr~ted in
Pig. 9. It begins at step 401 where the CPU 27 initiQlizes the
system hardw~re. The initiali~ation program executed at step 401
is shown in Fig. 10 and described in detail below. The over~ll
program next proceeds to step 403 which contains the operator
int~ra~tive progran (OIP) whieh is illustrHted in greater detail
in ~igs. 25A . . . 25M ~nd also described in more detail below.
.
~259~8~
During initial system installation and at peri~dic times there-
after, it is desirable to calibrate the system by taking measure-
ments under known conditions o~ the outputs of v~rious sensors
which are connected to the information ~hannels 10 at the remote
stations. A~eordingly~ step 405 determines whether ~ calibrQtion
routine is desired. If s~, the progr~m proceeds to step 415 where
the CPU 27 obtains and stores initial calibr~tion data from the
sensors under control of the sensor interrupt. This datQ is that
which is supplied by CPU 2~ to D/A converter 511 through latches
: 10 509 ~nd 513. If no further sensor interrupts occur or when it
completes processing a sensor interrupt, CPU 27 returns to the
operator interactive progr~m (OIP). Since the data gathering
programs executed during system calibration ~step 415) are the
same as those executed during normal system operstion (described
below) to obtain sensor data, a separate discussion of the cali-
bration data gathering programs will not be provided.
Assuming that calibration is not desired, the CPU pro-
ceeds to start the master interrupt timer in step 407. In this
step, the CPU 27 removes the M~IR reset signal from l~tch 601
which ~llows flip flop 605 to be responsive to the M~O output of
the master interrupt timer to provide the signal ~ t the output
of buffer 613 (pin 10). CPU 27 also supplies signal MrPS to lRtch
601 which en~bles frequency divider 1383.
In the next step 409, CPU 27 begins collecting and pro-
cessing sensor output dats under ~ontrol o~ the sensor interrupt
(PTI) appearing at pin 9 of the S-100 bus. Whenever sensor inter-
rupts ~re not being processed or when the sensor interrupts stop,
the CPU returns to the operator inter~ctive program (OIP) in step
411.
3~ Whenever the high priority m~ster interrupt occurs (sig-
nal MTI on pin 1~ of the S-100 bus), the ~PU executes a master
J~
-- ~2 --
~25968~L
timer interrupt program which, ~m~ng other things, sends a reset
tone pulse to all the remote ~tations ~n the 32 communic~tions
lines and begins aguin collecting end processine sensor data by
returning to step 409.
It should be Qppreciated that the flowchart of Fig. 9 is
a macro flowch~rt and that many individual progr~ms or program
steps occur st each oper~tional block illustrated. A more oom-
plete description of CPU a7 operation follows.
The operational steps performed by CPU 27 when executing
step 401 of Fig. 9 are shown in greater detail in the flowchart of
Fig. 10.
When the system hardware is initially activated, ~t must
be initi~lized, that is preset, to a particul~r installati~n en-
vironment. The section switches must be instrueted as to which
input lines they ~ill handle, the tracking ~n610g to digit~l con-
verter in the section switches must be fed voltage from one of the
available Yoltage sources, eec. This is what is accomplished by
the initialization program.
In the first step 419 of the initialization program, the
CPU supplies the section switch line selector latch 131 with data
relating to which incoming line each section switch portion tFig.
4) will handle, whether in a "split bus" or non-"split bus" con-
figuration. Table I illustrates the line selecting bit value
assignments of latch 131 for a "split bus" configuration, while
Table II illustrates the bit value assignments ~or a non-"split
bus~ configuration.
_ ~_
12~ 6~L
TABLE I
Latch 131 1st 8 Input Lines 2nd 8 Input Lines
Letch Outputs O 1 2 3 4 5 6 7 8 9 lO 11 12 13 14 15
Ll A3 1 1 1 1 1 1 1 1 1 1
Ll A2 O O O O 1 1 1 1 O O O O
Ll Al O O 1 1 O O 1 1 O O 1 1 O O
Ll A0 O 1 O 1 O 1 O 1 O 1 O 1 O 1 O
LO A3 1 1 1 1 1 1 1 1 1 1
LO A2 O ~ O O 1 1 1 1 O O O O
LO Al O O 1 1 O O 1 1 O O 1 1 O O
LO Aa O 1 O 1 O 1 O 1 O 1 O 1 O 1 O
TABLE II
Latch 131 16 lnput Lines
atch Outputs O 1 2 3 4 5 6 7 8 9 lO 11 12 13 14 15
Ll A3 O O O O O O O O 1 1
Ll A2 O O O O 1 1 1 1 O O O O
Ll Al O O 1 1 O O 1 1 O O 1 1 O O
Ll A0 O 1 O 1 O I O 1 O 1 O 1 O 1 O
LO A3 O O O O O O O O 1 1
LO A2 O O O O 1 1 1 1 O O O O
LO Al O O 1 1 O O 1 1 O O 1 1 O O
LO A0 O 1 O 1 O 1 O 1 O 1 O 1 O 1 O
In step 421 lntch 119 is addressed by CPU a7 and sup-
plied data to configure swit~h 175 so that one of the voltages
~pplied thereto is supplied as a voltage source to the input of
~; tracking analog to digit~l converter 181.
If the configuration is a split bus configuretion the
correct voltage source is normally selected by resetting M~DESEL
and setting VSS~L-Ll and VSSEL-L2 of latch 119 on tlll the section
switches. In this configur~tion the C~GSEL signal of lat~h 371 is
~59681
set and each section switch voltage souree for the two lines Ll
and L2 it has been assigned is selected by the d~t~ at the output
of latch 119 according to Table III below.
TABLE III
First SS Portion Second BS Portion
Selected Line ~elected Line
Input to SW 161 Input to SW 161
Latch ll9
Outputs 0 1 a 3 4 S 6 7 0 1 2 3 ~ 5 6 7
L0 REFEN 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Ll REFEN
REFSELA0 0 0 0 U 0 0 0 0 ~ 0 0 0 0 0 0 O
REFS~LAI O O 0 O O O O O0 O 0 O O O O O
; REFSELA2 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0
MDDESEL 0 0 1 1 0 0 1 1~ C 1 1 0 0 1 1
~ VSSEL-L0 1 1 0 0 1 1 1 11 1 0 0 1 1 1 1
VSSEL-Ll 1 l 1 l 1 1 l l1 l 1 l 1 1 l 1
lf the configuration is a normal bus configuration with one volt-
age source the correct voltage phase is selected by choosing the
phase ViQ contr-oller interface lat~h 373 outputs PH~ and PHl which
control switch 337 according to Table lV below:
TABLE IV
Latch 373 _ Ph~se selected by SW 337
Out~ut,s Phase A Phase B Phase C
PH0 1 0
; PHl ~ 0
Norm~lly in this configuration the ~nly tracking A/D cvnverter in
the system is the one on the controller interf~ce ~nd thus signals
b@~ ~nd CI~D~FF of l~tch 371 are reset.
bl
1~5~
if the configuration is a normal bus configuration with
two voltage sources then signals SSADOFF and CIFADOFF of latch 371
are set thus ~ctivating the section ~witch tracking A/D converters
181. ln this case the proper volt~ge source is chosen first by
select ing the phase QS shown above and then the source by swi tches
175 according to Table V below:
TABLE V
Line 1 Line 2
S witch 175 Voltage Inputs Switch 175 Voltage Inputs
Source 1 Source 2 Source 1 Source 2
~i5 ~~ 5r ~ir (pin 33)
MODESEL ~ 1 1 1
VSSEL-L~ 1 0 X X
` VSSEL-LI X X 1 0
X = don' t care
In stsp 423 CPU 27 enables the controller interface 15
and section switches 17 to pass a tone signal to all remote sta-
tions connected to the line which has been selected for each sec-
tion switoh portion. This initi~l tone is designed to change the
20 powsr supplies 63 in each of the remote stations.
nEn~ble Tone" ls Qccomplished by first setting the out-
put bits F0 . . . F4 of latch 369 as shown in Table Vl below to
select a desired tone frequency:
_ ~_
12596~31
'rABLE V ~
requency ~4 P3 ~2 ~1 ~0
4 OKHz 1 1 0 0 0
62 ~ 5KE~z 0
} O O~Iz O 1 0 0
14a . 8~Iz 0 0 1 1 0
Then the IY)~aEN output of latch 601 of the master con-
troller is set and finally the output lines 719, 721, 723, 725 and
727 of latch 1}9 of all the Section Switches are set according to
the Table YII belvw 80 th~t swi$ch 161 passes a tone to the input .
: line assigned to a section switch portion:
'~ ..
,
L9REFEN
L lRE~
REFSELAp 0
R~FSELAl 0
REF~ELA2 0
In step 427 the CPU 27 ~ddresses l~tch 371 and sets the
ADTEST signal to turn off the ~pplication of test signals AD0
thr~ugh AD9 to pins 74, 75, 76, B2, 83, B4, 85, 86, 87 Qnd 37 of
the system bus 13 through gated buffer 379 and g~ted buffer 375~
In step 431 the CPU 27 configures each section switch to its DC
mensurement state by addressing latch 373 in the controller inter-
r~ce to set ACMEN ~nd reset ACGRD, which are spplied to switch 199
: (ACMEN) switches 201 and 207 (AOGRD). 8wie~h 241 receives the
signal ~Gb5;g5, which is generated by del~y 137 ~Fig. 3).
- '~T -
~ -
~LX5~
In step 433, the CPU 27 sets the controller interface
for ~ split or non-split bus configuration of the section
switches. The ~plit bus configuration is selected by setting
signal CFGSEL at latch 371. This signal is reset for normal ~non
split-bus) configuration. The split bus configur~tion is used if
voltage output from a sensor attached to an information channel
10 ~t ~ remote station is to be supplied on line 150 for use by
the tr~cking A/D converter 183. If the voltage sensing is done
off an incoming power line, a normal bus configuration would be
selected by CPU 27.
In step 437 CPU 27 ~ddresses the n~ster controller tv
inhibit the programmable timer and the generation o interrupt
signals from the m~ster controller. CPU 27 does this by addressing
latch 601 to reset the signals PTIR, M~IR, VI4EN, PTEN and MTPS.
In step 439 CPU 27 addresses latches 513 and 509 in
~nalog to digital converter 21 supplying thereto a dat~ value
represent~tive of Q zero offset voltage which is applied as an
~ input to D/A converter 511. In step 441 CPU 27 addresses latch
; 509 in the A/D converter 21 supplying thereto a signal on the GAIN4X line which instructs summing ~mplifier 512 to have a gain of 1.
In step 443, CPU 27 sets the polarity of the D/A con-
verter 511 to a positive polarity output by the signal SIGN which
is supplied as dat~ to latch 509.
~ In step 445, CPU 27 also supplies a GATE EN signal to
; latch 509 which is applied via gate 571 to line 911 as an enablingsignal to the one of 32 line sele~tor 503. In step 447, CPU 27
~upplies the 11 BIT signal to latch 509 to set the A/D converter
21 to Q mode 0 state ~set output ~0" of decoder 551 in A/D con-
verter 21 (~ig. 8B~). Finally, in step 448 CPU a7 sets ~ID con-
verter 21 for ~ standard binary output by setting the TW~'S COMP
signal on latch 509.
-- (6~} --
~5g68~
Pigs. Il and 12 illustrQte the muster timer interrupt
programs executed by CPU 27 in step 413 of ~ig. 9, when 8 master
timer interrupt ~) is receiYed. In step 451 of ~ig. 11, CPU 27
disRbles all maskable interrupts by sending its internal interrupt
controller the proper sign~l. In step 453~ CPU 27 "pushes" the
contents of various registers into a stack memory for later re-
trieval in resuming the processing of ~n interrupted program when
processing of the interrupt is finished. In step 455, CPU 2
~umps to the 'ITone reset" program illustrated in Figo 12 ~
10In the first step 457 of the tone reset program CPU 27
~pplies a tone to ~11 the communications channels (lines) inter-
connecting the section switches with the remote station groups.
The steps for enabling a tone were described earlier with refer-
ence to step ~23 of ~ig. 10.
In a subsequent step 459, CPU 27 sets the progr~mm~ble
timer in the m~ster controller with a digital value corresponding
to 99.99 miliseconds. This is accomplished by CPU 27 resetting
the signals PTEN and MTIR ~t lstch 601. CPU 27 then supplies
output d~ta via buffer 685 to the inputs of progr~mmable counter
20sections 679 and 681 in two successive eight bit lo~ds controlled
by load signals CTP ~nd PTP which the CPU also supplies through
~ddress decoder 703. Then the sign~ls PTEN and MTIR ~re set to
start the counting of sections 679 ~nd 681. At the end of the
count a sensor interrupt control signal PTO will occur which
initiates a sensor interrupt PTI ~t pin 3 of the S-100 bus (Fig.
7).
In step 461, the CPU 27 next stores the ~ddress of
program identified ~s "Sensor 0 d~ta g~thering" at NIPAD which is
pointer to the n~mory address of the first step of Q program to
30be executed next. In step 4S3, ~PU 2~ "pops" the contents of the
st~ck memory b~ck into the CPU registers thereby restoring the
_ ~ _
~259~
data which had been previously pushed onto the stack so th~t CPU
27 ~an continue to execute ~ previously interrupted program. In
the next step 465, the CPU enables the naskable interrupts by
sending its interrupt controller the proper signal.
In step 467, the CPU 27 then returns to processing of
the previously interrupted program and awQits the next sensor
interrupt. It must be remembered that at this time a t~ne is
belng applied to all communications channels through the section
switches ~nd th~t the sensor interrupt timer h~s been set for
99.99 ms which is the time period for a "reset" tone. Fig. 13
illustrates a series of programs which are entered ~t v~rious
occurances of subsequent sensor interrupts. Fig. 14 illustrRtes
the sensor interrupt program which is executed first at each sen-
sor interrupt.
When the next sensor interrupt occurs under control of
the PTO signal outputted by the programmable (sensor) interrupt
timer (after 99.99 ms), CP~ 27 first executes the sensor interrupt
program of ~ig. 14. In the first step 602 all the interrupts are
disabled in the manner described earlier with re~erence to step
451 of ~ig. 11. Then the registers are "pushed" in step 604 and
the program having its address stored ~t NIPAD is executed in step
606. After execution of the program whose address is at Nl!2AD,
CPU 27 "pops" the registers in step 608, enables the interrup'ts in
step 610 ~nd returns to the previously interrupted progr~m in step
612.
Since the address of the "Sensor ~0 data gathering"
program was previously stored at NIPAD ~Step 461 Fig. 12) this is
the first interrupt driven program run after the Fig. 12 progr~m
is executed. The "Sensor ~0 data gathering" program is shown in
Pig. 13A, l~B. As a first st~p 469 the resetting tone which was
st~rted at step 457 of the Fig. 12 progr~m is turned of~. This is
lb
1~:5~6~
accomplished by ~PU 27 addressing the m~ster controller and out-
putting data to l~tch 601 which resets the TONE ~N (tone enable)
signal on line 811. If it îs desired to turn off the reset tone
only on some lines the M~ster Controller TONE EN signal is left in
the enabling condition and the signals Ll REFEN and L2 R~FEN at
latch 119 of e~h Se~tion Switch are reset for e~ch line where no
tone is desired. At this point, the system is reset ~nd subse-
quent tones (tone bursts) sent to a group of remote stations
connected to a respective communications ch~nnel will cause the
informstion ch~nnels flt the remote stations to be sequentially
addressed and connected to the communications channel. As earlier
described, e~ch remote station of a group is enabled by a numeri-
cal r~nge of appried tones, e.g. 0-15, 16-31, 32-475 etc., while a
different information channel of a remote station is connected to
the c~mmunications channel upon the occurrence o~ e~ch tone in the
numerîcal range to which a remote station responds. For a system
having 16 remote stations each having 16 informati~n channels, 256
tones will serve to address all in~ormation channels. It should
also be remembered th~t there ~ay be, for example, up to 32 groups
of remote stations connected to the central station by respective
communications channels to whioh ~11 tones are supplied simul-
t~neously. Thus, the CPU is simultaneously addressing, gathering
~nd processing dsta for 32 sensor outputs, one for each communica-
tions ch~nnel.
Returning to the ~Sensor #0 dQts gathering" program
(~igs. 13A, 13B), in step 471 CPU 27 sets the programmable inter-
rupt timer with a time value sufficient to allow the data on the
lines from the sensor to settle. Typically, this will be 8 milli-
seconds but m~y vary depending on the type of sensor which is con-
nected to the line. Since the m~nner in whic}l the programmabletimer is ~ddressed and progr~mmed by the CPU 27 was discussed with
_ ~ _
~l~596~1
reference to step 459 of ~ig. 12 it will not be repeated herein.
In ~tep ~73, the CPU 27 performs other data gathering steps which
m~y include setting of the programmRble timer and other sensor
interrupts. These progr~ms will v~ry depending on the type of
sensor output which is being ex~mined. Different types of sensors
cAn be used in the present invention to provide measurements of
1) resistance, 2) precision resistance changes, 3) DC voltsge ~nd
4) AC power. Specific exemplary programs for the different types
of sensor output measurements will be described in detail below.
Upon completion of data gathering step 473, CPU 27 pro-
ceeds to step 475 where it stores the eddress of the 'ISensor #0
; data processing" progrRm ~t NIPAD. ~ran there~ the CPU 27 pro-
ceeds to the return step 477. At this point, the CPU has gathered
the digitized output d~ta from Sensor #0 on all communications
ch~nnels. When the next sensor interrupt is received, CPU 27
again executes the Fig. 14 routine except now N~PAD points to the
"Sensor #0 data processing" progr~m shown in ~ig. 13A which is
executed at step 606 of ~ig. 14. This program bsgins ~t step 479
where the sensor interrupt timer is set for a time sufficient to
empty the data buffer. Upon completion of step 479, CPU 27 pro-
ceeds to step 481 where it stores the ~ddress of ~ 'IStep to sensor
#l" progr~n at NIPAD. Subsequently, CPU 27 enables the interrupts
in a manner described earlier and proceeds to step 485 where it
c~lls the ~Process sensor #0 data" program. Exemplary programs
for processing various dat6 from the sensors will be described
below. After executing the "Process sensor #0 dat~" program, CPU
27 proceeds to return step 487) ~nd proceed~ from there to steps
608, 610 and 612 of the sensor interrupt progr~n of ~ig. 14.
Since NIPAD now contains the address of the program
"Step to sensor #ln, which is generally showm ~t the top of Fig.
13 ~s a "Step to next sensor" program, the next sensor interrupt
b~
1~5968~L
causes CPU 27 to execute this progr~m in step 606 of the sensor
interrupt program (Fig. 14). In the first step 514 thereof, the
tone is en~bled ~s previously described. This tone causes sensor
#l of each group o~ resnote stations to be connected to n respec-
tive cosnmunications ch~nnel. The sensor interrupt timer is then
set for 1 milliseeond in step 5}6 to define the tone duration and
the address of the "Sensor #l data gathering" program is set in
~IPAD at step 518. The CPT~ then returns at step 519. Upon occur-
; rence of the subsequent sensor interrupts, CPU 27 proceeds to
execute a "Sensor #l data gathering" program and then a "Sensor #ldatOE processing" progr~m corresponding to steps 469 through 487
described ~arlier with reference to sensor #0.
In like manner, the CPU a7 proceeds upon receipt of
successive sensor interrupt signals, to step through the progrQms
for tone addressing a sensor, and gathering and processing the
data for ~n addressed sensor. Fig. 13B illustrates the execution
of the routine for addressing the last sensor of a first addressed
remote station (e.g., sensor #15) and storing and processing out-
put data therefrom. This routine begins at step 497 where the CPU
27 executes th~ "Step to last sensor" program (same as steps 514,
51fi, 518 and 519). It then proceeds to step 499 where it executes
the programs for gnthering and processing data for the last sensor
and sets up for sensor #U of a second remote station (correspond-
ing to steps 469-487). At step 502, CPU 27 increments a unit
counter which counts the number of remote stations of a group
connected to a communications channel which have been addressed
and at step 504 the CPU determines if the unit counter equals a
maximum number or not. The purpose of the unit c~unter and the
decision step 504 is to test whether all of the sensors at all o~
the remote stations of a group have been addressed. The unit
~ounter ~ounts the number of times all sensors #0-15 have been
1259~
addressed and processed9 which represents the number of remote
stations which have been processsed. If sll remote stations of a
group have not been processed, CPU 27 proceeds to return step 508
where it awaits the next sensor interrupt at which time the "Step
to Sensor #0" program will be executed, this time ~or the ne~t
remote station. If the unit counter equals its m~ximum, indi-
catlng that the last sensor of the last remote station has been
read, the CPU resets the unit counter to ~ero in step 510 and
discontinues any further sensor interrupts and returns to the OIP
program awaiting the occurrence of Q master interrupt in step
512. When a n~ster interrupt occurs, the progr~ms ~D~ Figs. 11
through 14 are agsin executed ~s described above to be~in another
sensor addressing and data gathering and processing cycle.
When the "Step to next sensor~ progr~m is executed for
the first time following a master interrupt, the dQta stored in
NIPAD at step 518 will be the ~ddress of the "sensor #0 data
gathering" program; however, for subsequent sensor interrupts,
this address will change to correspond with the next sensor, i.e.
1, 2 . . . etc. data gathering program which must be executed.
The generalized progr~m illustrated in Fig. 13 for
sequentially tone ~ddressing the sensors and gatherinK nnd pro-
cessing sensor data will change somewhat for different types of
sensors which m~y be used. As noted, some sensors m~y change a
res;stanoe ~alue or an output voltage as a monitored parameter
changes. The system is able to perform resistance measurements,
precision resistance change measurements~ DC voltage measurements,
and AC power messurements. ~or each type of n~asurement, a
slightly different "Step to next sensorn, "Sensor data gathering"
and "Sensor data processing" progr~m will be used.
For sensor output resistance measurements, the progr~ms
of ~ig. 15, which are slightly modified versions of the general-
i~ed Fig. 13 progrsms, are executed.
-- T~ --
~59~81
The "Step to next sensor" progr~m includes step 614
where a tone is enabled, step 616 where the sensor interrupt timer
is set for 1 millisecond and step 618 where the address of a "Wait
for data to settle" program is stored at NIPAD. Steps 614 and 616
correspond directly with steps 514 ~nd 516 described above with
re2erence to Fig. 13.
The first step in the ~wait for data to settle" program
is 622 where the CPU turns off the tone. This step corresponds to
step 469 of Fig. 13. CPU 27 then proceeds to step 624 where it
sets the sensor interrupt timer for suffieient time ~X'I reguired
to allow d~t& from a monitored sensor to settle on the line. This
may vary from sensor to sensor, but is typically 8ms. In step
626, the CPU sets up the section switches for the resistance
measurement mode. Here the CPU sets the signal A~ER and resets
the signal AOGRD in latch 3~3, of the controller interface (Fig.
6A). CPU a7 then proceeds to step 628 where it selects ~ proper
resistance and voltnge so~rce to n~tch the sensor output re-
sistance range. This is accomplished by setting ~ proper sode on
the signal lines REFSE~A0, REFSE~A17 REFSELA2, Ll REFEN and ~2
RE~EN at latch 119 by the CPU. Upon completing step 628, the CPU
27 proceeds to step 630 where it stores the address of the "Take
resist~nce dRtQ" program at NIPAD ~nd then to step ~32 where it
returns and awaits the next interrupt. When the next interrupt
occurs, the CPU executes the "Take resistance d~ta" program since
this is the program whose address is presently stored at NIPAD.
The first step of this program is illustrated as step 634 where
the sensor interrupt timer is now ~et for one millisecond. Upon
completing step 634, the CPU advances to step 636 where it sequen-
tially converts analog voltage on eRch of the 32 communications
channels extending between the section switches and remote sta-
tion~ into bin~ry data and stores this in a bu~er area. Upon
_ ~5 _
i~59~83L
completing this, the CPU advances to step 638 where it stores the
~ddress of the "Step to next sensor" progrum ~t NIPAD. lt then
proceeds to step 640 where it enables the interrupts and from
there to step 642 where it calls the program used to process the
data which has been stored in the buffer area. ~pon oompleting
step 642, the CPU returns to pro~ess ~n interrupted program in
step 644 and ~w~its the next sensor interrupt. W~en the next
sensor interrupt occurs, the CPU will be instructed by the &ddress
at NIPAD to proceed to step 614 of the "Step to next sensor" pro-
gram where it enables the tone in step 614. Then in step 616, the
CPU sets the sensor interrupt timer for one millisecond. After
completing step 616, ~he CPU 27 advances to step 618 wh-ere it
stores the ~ddress of the "Wait for data to settle" progr~m at
NIPAD, which has just been described.
The programs illustrated in Fig. 15 are repeated for
each of the sensors of a remote station in the m~nner described
~bove with reference to ~igs. 13A ~nd 13B. When the l~st sensor,
e.g. ~15, of a remote st~tion is processed; that is, when step 642
of Fig. IS is executed for the l~st sensor of Q remote st~tion,
the CPU executes a routine consisting of steps 502 . . . 512 (~ig.
13B) to determine if all remote st~tions of a group have been
processed. If not, the Fig. 15 programs ere repested until al~
~ensors of all remote stations of a group have been processed at
which time the CPU will return to OIP (step 512, Fig. 13B).
The program which is used to process the data s$ored in
the buffer area which is called at step 642 by CPU 27 may take sny
one of a number of different ~orms depending upon wh~t the
me~surement represents. The v~lue m~y represent, for ex~mple
e~libration data, ~n ~ir or liquid temper~ture v~lue, or any other
measured par~meter. Depending on what the d~t~ represents, one of
the Rpplic~tions progrRms of Figs. 16 through 80 will be c~lled ~t
step 642 of Yig. l~.
_ ~ _
-
~25968~
lf the n~asurement represents communic~tion path re-
sistance ~alibration dat~, the progr~m at ~ig. 19 is called in
step 642 of Fig. 15. Acquisition of the ~ommunication path re-
sist~nce calibration data occurs when the ~libr~tion program i9
c~lled for at seep 405 of Fig. 9. At this time, ~ensor calibr~-
tion data is g~thered fron the sensors as just described. Pollow-
ing this, the calibration data is processed ~ccording to the Fig.
19 progr~m. In the first step 804 of the Fig. 19 progr~m, the CPU
27 sets a line counter N to one. It then fetches the present
sensor calibration data from the bu~fer in step B06 for line N of
the current set of remote stations tunits) (N represents one of
the 32 incoming communications channels. The 32 lines c~n be
identified by e section switch S ~0-15) and line L (0, 1) n~mbers,
but for purposes of simplicity line number N (1-32) can and will
also be used in the subsequent description.). In step 808, the
CPU fetches the previous sensor calibration data for line N. A
comparison is then m~de by CPU 27 in step 810 between the present
and previous sensor calibration data. If they differ by less than
~1% BS determined in step 810, the CPU then adds a value of 1 to N
in step 812 nnd proceeds to determine if the sensor calibration
data for all lines hQve been processed in step 814. If ~11 the
lines hnve not been processed, the CPU proceeds to step 806 where
sensor c~librQtion d~t~ for the next line is fetched. If in step
~14 CPU a7 decides that sensor dst~ for ~11 lines N (3a) of the
current set of units have been examined, it returns in step 822.
If in step 810 $he present calibration data differs from
the previous c~libration data ~or ~ given line N by more than +1%,
the line number N and the unit (remote station) number ~re all
stored in ~n error buffer in step 818 after which GPU 2q sets fln
error flag in step 820. The CPU then proceeds to step 812.
If the gsther~d dat~ represents ~n ~ir temperature, the
application program illu~trated in Fig. 21 is executed at step 642
1~
~596~
of Fig. 15. This ~pplication progr~m begins at a step 836 in
which CPU 27 sets a line counter value N to one. In step 838, a
present sensor air sample value is fetched from a buffer for line
N of the current set of units. This value is ~orrected with a
; previously stored correction value for line N of the current set
of units, and an equivalent air temperature value is determined in
step 84~. In step 842, the CPU then Qdds the temper~ture value to
an hourly accumulator and proceeds to step 844 where it increments
N. In step 846, CPU 27 determines if the data for all lines N
10have been exanined (N=33). If not, the CPU returns to step 838
where the next line sensor temperature sample is processed. If
all lines have been processed, CPU 27 pro~eeds from step 846 to
return step 852.
A sensor output n~y also be used ~D represent a temper-
ature which may be monitored for a fire condition. In such a
case, the fire process routine of Fig. 22 is used as the program
which is called in step 642 of Fig. 15. In the first step 848 of
this program CPU 27 sets a counter value N to 1. In step 851 the
CPU fetches the present sensor s~mple data for line N and compares
it with a previous sample data for line N. In step 853, a deci-
sion is made by the CPU as to whether the temperature difference
between the onmpared values exceeds a first predetermined value~
thus indicatlng a fire. If e yes condition is realized in step
853, the CPU then stores in step 856 the unit number (remote sta-
tion number) in an action buffer together with the current time.
The CPU then proceeds to step 860 where it sets an ~ction flag in
sn emergency action status word and then proceeds to step 863
where it increments N. In step 865, the CPU determines if data
for all lines have been processed (N=33). If not, the CPU returns
30to step 851; if so, thc CPU proceeds to return at step B68.
If step 853 indicates there is no fire, that is, the
change in sensor reading between two sucessive samples does not
1~
59~81
exceed the first predetermined value, the CPU advances to step 854
where it checks to see whether the di~ference exceeds a second
lower predetermined ~slue ~hich n~y indicate A potenti~l fire. If
a yes condition exists in step 864 the CPU proceeds to step 858
where it cheeks a buffer for ~ potenti~l fire indieation ~rom a
prevlous sanple. If it finds one in step 862 it proceeds to step
856 and stores inform~tion re}ating to the unit nwmber ~remote
station n~mber) ~nd ~urrent time in the ~ction buffer as described
previously. If step 862 indic~tes that there w~s no previous
potentisl fire indic~ted, the CPU proceeds to step 866 where it
stores an indication of a potential fire in a reference buffer for
the current unit for e~mp~rison with ~ subsequent s~mple of th~t
unit sensor output upon the next execution of the progrsm. From
step 866, the CPU then proceeds to step 863 where it increments
the line number N. If, in step 854, the CPU determines thQt there
is no potenti~l fire, it proceeds to step 863 to increment to the
unit number N.
If the g~thered sensor d~ta represents fluid flow condi-
tions at a remote station, then the application progr~m of Fig. 23
is executed by the CPU when it reaches step 642 of the Fig. 15
program. The first step 870 in this progrQm is the setting of a
line counter value N to 1. Then in step 872, CPU 27 fetches firs~
sensor dat~ TWI (temperature of w~ter in) (e.g. the upstre~m sen-
sor 244 in Fig. 28A) for line N. This d~t~ WAS previously ~c-
quired and stored by the CPU in a temporary buffer when processing
the d~t~ gflthering program for this sensor. ln step 873, the CPU
27 fetches second sensor (flow) data TW~ (temper~ture of w~ter
flow) (e.g. the downstre~m sensor 226 in ~ig. 28A) for line N,
which w~s obt~ined during processing of the present sensor, sub-
tr~cting ~t from the dsta ~etched in step 872 to yield (TWI-TH~).
In step 874, the value c~lculated in step 873 is further
-- ~} --
~s~
subtracted from previously acquired and stored calibration data
~TWPO ( Q TWPO-(TWI-TW~)) for line N representing the difference
between the data of the first ~nd second sensors under known flow
conditions. The result of the cslculation in step g74 is then
used in step 876 in 8 table look-up function ~or the type of sen-
sor employed to determine the actual flow rate. As noted e~rlier,
Q table of flow values ean be developed relating the outputs of
the upstre~m and downstream sensors to ~ flow rate. The data from
step 876 is then added to resultant data in an accumulator buffer
in step 878 ~nd in step 880 the CPU increments the unit counter
N. In step 882, the CPU determines whether all lines have been
processed (N=33) and if not, CPU returns to step 872 where it
begins processing data for the next line. If dat~ for all~ lines
has been processed, as determined in step 882, the CPU returns at
step 884.
If the gsthered sensor data represent BTU d~ta, the
application program of Fig. 24 is executed at step ~42 of Fig.
15. In step 885 of this program, the CPU sets a line counter
value N to 1. ln step 887, the CPU fet~hes first sensor data TWI
(temperature of water in) for line N (e.g. an upstream temperature
Rensor). This data was previously acquired and stored by the CPU
in ~ temporary buffer when processing the d~ta gathering progr~m
for this sensor. Following this in step 888, the CPU fetches
second sensor data TWF (temperature of w~ter flow) for line N
(e.g. a downstre~m temperature sensor), subtracting it from the
sensor data fetched in step 8~7 to yield TWI-TWF. The subtracted
data is then further subtracted from previously acquired and
stored calibration data ~ TWF0 for line N of the current set of
units representing the difference between the datQ of the first
~nd second sensors under known flow conditions. Pollowing this
the CPU proceeds to step 892 where it uses the v&lue calculated in
~259~8~
step 890 ( ~ TWFO-(TWI-TWF)) in a table look-up operation to de-
termine flow rate through a heat exchanger corresponding to the
v~lue calculated. The CPU then proceeds to step 894 where it
fetches third sensor datQ TW~ for line N (sensor 245, ~ig. 29),
which was a1so previously acquired ~nd stored by the CPU when
processing the data gathering program for this sensor. The third
sensor data represents a downstre~m fluid temper~ture at the out-
put of a heat exchanger. This data is corrected with previously
acquired calibration data (Q TW~), and is subtrQcted from the data
TWI obtained in step 887 to determine the difference in temper-
ature between the input ~nd output of 8 heat exch~nger. This
vQlue is then used in step 8g6 by the C~'U as a vaiue which is
; multiplied by the flow rate acquired in step 892 for ~alcul~tion
of ~ thermal energy ussge rate; thst is, the BTU r~te. In step
898, the calculated BTU rate is applied to ~n accumulating buffer
snd the CPU then increments the unit counter N in step 89~, after
; which it determines in step 902 if data from the sensors of all
lines has been processed. 1~ not, CPU returns to step 887 where
data for the next line is processed. If all units have been pro-
cessed as determined in step 902, the CPU returns at step 903.
Figs. 16A, 16B il}ustrate the programs executed by the
CPU 27 when measuring a sensor output which is in the form of a
preclsion resist~nce change. Some of this program is identical
with that illustrated in Fig. 15 and accordingly like boxes have
been numbered with the s~me reference numerals. The principal
difference between this program and that of Fig. 15 occurs in how
the resistance data which has been taken is processed and this
begins at step 904 of Fig. 16A and discussion will begin ~t this
point. When ~n ~nterrupt occurs ~fter the "take delts resistance
data" program hes been set in NIPAD by step 630 the sensor inter-
rupt timer is set ~or "X" milliseconds ~corresponding to the time
- J~r -
~ 9~8~
for execution of the "tske delta resistance data" program) in step
634 snd the CPU then proceeds to step 904 where it sets a line
~ounter L to zero ~nd to s~ep 906 where it sets a section eounter
S to zero. In step 908, the CPU sets referenee ~ata previously
acquired for the sensor into latches 513 ~nd 509 f~r section S and
line L nnd in steps 910 and 912 ths CPU configures the A/D con-
verter 21 for a delta resistance measurement. A/D converter 21 is
set for delta resistance mode in steps 910 and 912 by setting the
signals qAIN 4X, SIGN and SUMINV at the output of latch 5~9 as in
Table YIII below:
TABLE V~
Latch509 VO~VI VI-VO 4~0-VI) ~I-VO~ VO~VI ~O~VI)
GA~ 4X 0 0 l l 0
SIGN 0 0 0 0
-
SUMINV 0 1 1 0 1 0
After setting the A/D converter 21, CPU 27 proceeds to
step 914 where it converts the ~nalog delta resistance value for
the incoming line (one of the 32 incoming lines) to a binary form,
storing this in a buffer area in step 916. ~ollowing this, the
line counter is in~remented in step 918 ~nd the line counter value
is tested in step 920 to determine whether it exceeds a prede-
termined line maximum of l. If not, the CPU then proeeeds back to
step 908 where it sets the calibration resistance data for the
next line (identified by L and S) into the D/A analog converter
latches 513 and 509. If the line ~ounter is greater than a
~259~8~
maximum of I in step 92D, the line counter is set to ~ero in step
ga2 and the section ~ounter is incremented in step 324. At this
point, d~ta for two lines 0,0 and 071 (S, L) will have been
gathered. ~ollowlng this, the CPV in step ~26 tests whether the
section counter is grester th~n a m~ximum number (15). If not,
the CPU returns to step 908 to begin processing data for ~nother
line, now identified ~s 1,0. If ~ yes ~ondition is achieved in
step 926 indicating that all lines have been processed (S=lS), the
address of the rStep to next sensor" progr~m is stored at NIPAD in
step 528 following which the interrupts are enabled in step 830
and the program used to process the data currently stored in the
buffer is called step 932. This program may be one ~f the ~ppli-
cstions programs described above with reference to ~igs. 19 snd
21-24 where a chsnge in ~ precision resist~nce vQlue may represent
any one of a change in calibration dat~, ~n air temperature, a
fire condition, 8 fluid flow, or 8 BTU measurement. Step 932
selects one of these application programs for operation on the
data which h~s been gathered.
The section and line counters ~S, L~ are used to point
to one of the 32 incoming lines. The reRson for using these
counters is that previous resistance datQ for an incoming line
must be fetched in step 908 ~nd inserted into D/A converter 511
for summat}on with present resistance datQ for the same line, as
each sensor output is processed. The S and L counters enable the
CE'U to locste and fetch this previously stored data.
The sensors which may be used in the system can also
produce ~ DC voltage output and when such sensors are used, the
progr~m of ~ig. 17 is executed by the CPU to gather and process
sensor data. As was true of the precision resistance measurement
program, ~srtain steps are the same as in the progr~m illustrated
in Pig. 15 and these h~ve been labeled with the same reference
~L~5~6~l
numersls. The principal difference in n DC voltage measurement
progrnm is that a ~tep 936 sppesrs sfter the sensor interrupt
timer is set in step 624 to allow sufficient time ~or data to
settle on the lines. ~tep 936 sets the section switches ~or ~ DC
voltsge measurement n~de. The Section ~witches are set for ~ DC
voltage mode by first setting the ACMEN sign~l ~nd resetting the
ACGRD signal at the controller interface latch 373 and then re-
setting the LU and Ll REFEN signal on l~tch 119 of all the Section
Switches. Following this, the address of 8 ~Take DC voltage dat~"
program is stored at NIPAD in step 938 following which the CPU
returns in step 940 to await a next interrupt. W~en the next in-
terrupt occurs, the "take DC voltage data" program is executed
which begins ~t ste@ 634 where the sensor interrupt timer is set
~or one millisecond. If the DC voltage on the line is out of the
~ormQl operating range of A/D converter 21, the CPU can in this
step control switch 161 to select e resistor/voltage ~ombination
that will sum with the sensor voltage to bring it within the range
of A/D converter 21o ~ollowing this, the CPU proceeds to step 942
where it converts the DC voltage on each of the 32 section switch
lines into bin~ry data snd stores it in Q buffer area. Upon com-
pletion of this, the CPU then proceeds to step 944 where it stores
the address of the "step to next sensor" progr~m at NIPAD in step
944 and it then enables the interrupts in step 946 and calls the
progrnm used to process the data stored in the buffer ares in step
948. Again, this cnn be any one of the ~pplication programs de-
scribed e~rlier with references to Figs. 19 and 21-24. Following
execution of the progr~m in step 948, the DC voltage measurement
program returns at step 950.
As described nbove, a principal feature of the present
in~ention is the abllity of the ~PU to monitor power consumption
in an electricel path at one ~f the remote stations. Figs. 18A,
~2~9~
18B, 18C, 18D illustr~te the flow chart for the program executed
by CPU 27 to take the necessary AC measurements which are used to
calculate power consumption.
The "Step to next sensor" progr~m which is used for AC
power measurements is similar to the "Step to next sensor" pro-
grnms previously described for other measurements. As ~ first
step, ~ tone (addressing tone) is enQbled in step 1002 following
which the CPU 27 sets the sensor interrupt timer for one milli-
second in step 1004. After this, the address of a "Check current
transducer impedance" program is stored Qt NIPAD in step 1006
following which the CPU returns in step 1008. When the sensor
interrupt timer times out after the one millisecond time interv~
the interrupt thus generated causes the CPU to execute the '~Check
current tr~nsducer imped~nce~ progr~m which begins st step 1010.
In this step, the CPU turns off the ~ddressing tone and then pro-
ceeds to step 1012 where it sets the sensor interrupt timer for
nine milliseconds. Nine milliseconds is seiected as producing
enough time for ~ full cycle of a 60 H~ sine squAred wave~orm (120
Hz~ to occur which is s~mpled in subsequent steps of the program.
Following step' lOla, the CPU proceeds to step 1014 where lt se-
lects a current multiplied by current mode of the section
switches. The current multiplied by current mode is set by first
resetting slgn~ls VSSEL-L0, VSSEL-Ll and M~DESEL st latch 119 of
all the Sectlon Switches, Next the CFGSEL signal of 12tch 371 is
reset. The net effect of these controls signals Is to connect
section switch input llne 150 to the input of trscking A/D con-
verter 181. If the system utilizes a split bus configuration it
will ~lso be necessary to reset L0A3 and LlA3 of latch 131 on all
the Section Switches to dis6ble the external voltag~e inputs, The
third step is to set the AC path gain to a minimum. This is
accomplished by first setting the SS signal of latch 371 after
~25~6;81
which the SSP signal of l~tch 373 is ~ltern~tely reset and then
set again to set the AC path gain to maximum. Now the signal SS
at latch 371 is altern~tely reset ~nd set eight times. The AC
path g~in has now been clo~ked to minimwm g~in.
Pollowing step 1014 the CPU Qdv~nces to step 1016 where
it selects ~ proper DC test voltage which is ~pplied through Q
resistor which best m~tches the current transducer impedance.
This matching resistor is shown in Fig. 4 between pin 24 and
switch 175.
10The proper DC test volt~ge for m~suring the eurrent
tr~nsducer impedance is set by first setting signal TVO und re-
setting sign~ls TVl ~nd TY2 of latch 373 this selects ~lOV for the
: output of switch 349 ~nd syst~n bus 13 pin 24. The next snd last
step is to set the signals L~ ~EFEN, Ll REFEN, BEFSELA0, REFSELAl
and RE~SELA2 on latch 119 of Qll the section switches. This
applies the test voltage on pin 24 through 8Wi tch 161 to the in-
coming lines serviced by a ~ection switch for flpplication to
current trRnsducer connected thereto. Upon completing step 1016,
the CPU proceeds to step 1018 where it enables the AC meQsurement
path. The AC me~surement path is enflbled by setting ACGRD and
resetting ACMEN at latch 373. At this point, an incoming current
from ~ current trnnsducer (in the form of a voltQge signal) will
be ~pplied to both the A/D converter 181 ~via pQth 150) ~nd the
automatic gain control 245 (ViQ input 243) causing A/D multiplier
~181 to produce ~ current squared output.
;In the next step 1020, the CPU fills a current trsns-
ducer impedance buffer with data corresponding to hexidecimal "FF"
following which the CPU sets ~n AC measurement interrupt counter
;to ~ero in step 102~. In step IOa4, the CPU sets the maximum AC
meQsurement interrupts which ~ill o~cur to lB. Upon completion of
step 10~.4 the CPU proceeds to step 1026 where it stores the
_ . _
~259681
address of ~ program ~Set AC current gain" at NIPAD which will be
executed upon the oceurrence of the next sensor interrupt.
Following this, at step 1028, the CPU enables the AC me~surement
interrupts. The AC measurement interrupts ere enabled by setting
V14EN of the M~ster Controller latch 601. There are 32 AC
measurement interrupts genernted for each oycle o the 60 Hz main
power waYeform st the output of the phase lock loop multiplier 307
in the controller interface 15. In step 1030, the CPU en~bles the
interrupts and then returns in step 1032.
10At this point, the next sensor interrupt will cause the
; CPU to execute the ~Set AC current g~in" progr~m. However9 before
that, 16 AC measurement interrupts will occur which will cause the
AC measurement programs, identified as steps 1034 . . . 1056
~igs~ 18A, 18B~, to be executed. Although not shown in ~igs. 18A
and 18B, upon the occurrence of an AC interrupt the CPU will first
dissble nll interrupts and push its present register contents to
the stack before executing step }034. Also, prior to executing
the return steps 1039, 1049 ~nd 1056, described below, the stack
must be popped to restore the register contents and the interrupts
Qgain enabled.
The first step of the AC measurement progra~ 1034 causes
the CPU to take the current squared reading of Qll 32 lines run-
ning from the section switches to the groups of remote stations
and this data is stored in Q buffer. The CPU then proceeds to
step 1036 where it increments ~n AC meQsurement interrupt eounter
and then proceeds to step 1038 where it tests whether the AC
measurement counter is greater than 16. If not, the CPU pops the
~tack, enables the interrupts and returns and waits for the next
AC interrupt which will Qgain cause it to execute the "Check
current transducer impedance" program whieh begins at step 1034.
After this program has been executed 16 times, a yes decision will
~;~5968~L
be produced at step 1038 causing the CPU to execute step 1042
which dis~bles the AC me~sure~ent interrupts. The AC measurement
interrupts are disabled b~ resetting V14EN of the ~aster
Controller lQtch 601.
After disabling the AC measurement interrupts, the CPU
proceeds to step 1044 where it again enables the interrupts.
~ollowing thls, the CPU 27 proceeds to step 1046 where it ~ompares
the lowest value stored in the buffer for each of the 32 lines
with the d~ta stored during calibration of the system. The lowest
readings occur when the AC current is zero. Thus the lowest read-
ing representing transducer output imped~nce ~mounts to nothing
more than a DC resistance re~ding which is similar to other DC
resistance readings previously described herein. A signiSicant
change in tr~nsducer impedance may occur by someone deliberately
shorting, disconnecting or putting resistive or reactive compo-
nents in parallel or in series with the current transducer in an
sttempt to make the system read a smaller current than is actually
being consumed in the electrical path at Q remote station.
Accordingly, this portion of the program is designed to test for
t~npering or line f~ults.
If a si~nificant change jn the current transducer output
impedance is detected in step 1048, a tampering flag is set in
step 1052. This flag is periodically monitored by g f~ilure scan
program to provide an i~dication of t~mpering. After the tamper-
ing flag is ~et, the CPV proceeds to step 1054 where it stores the
section switch number, line number, unit number and voltage phase
in a tampering bu~fer. This information can then be displayed
along with location information to help identify OE remote station
which has been t~mpered with and to help in the repair process for
a faulty line condition. After step 1054, the CPU pops the stack,
enables the interrupts ~nd returns in step 1056. If there was no
~259~
; signific~nt change in the current transducer GUtpUt impedance
detected in step 1048, the CPU would also return in step 1049
after first popping ehe stack and enabling the interrupts.
The "AC current gain" program, the address of which was
set in NIPAD ~t step 1026, begins at step 1058 when ~he next sen-
sor interrupt signal is received. At this poi~t, the CPU sets the
sensor interrupt timer for nine milliseconds and then proceeds to
step 1060 to set the section switches for a voltage multiplied by
a current mode.
10The voltage multiplied by current mode is set by reset-
ting signals L0 REFEN and Ll RE~EN on lat~h 119 at all the section
switches. Following step 1060, the CPU proceeds to select a volt-
age source in step 1062 and then to seleet the automatic gain mode
at step 1064.
The procedure for selecting a Yoltage souroe was de-
scribed earlier and will not be repeated here. To select the
automatic gain, signal SSP is reset at l~tch 373 ~nd SS is reset
at latch 371. In step 1066 the AC measurement path is enabled
rollowing which the address o~ a "~ero AC pQth offset" progr~m is
~tored at NIPAD in step 1068. After this, the CPU returns in step
1070.
When tha next sensor interrupt o¢curs, the "~ero AC path
~ffset" program is executed which begins at step 107a where the
sensor interrupt timer is set for nine millseconds. ~ollowing
this, in step 1074, the AC measurement path is disabled by reset-
ting ACG~D and setting ACMEN at latch 373. In the next step 1076,
CP~ 27 stores the ~ddress of the "Take and process AC power data"
progrQm at NIPAD following which it returns in step 1078.
The "Take and process AC power data" program which is
next ~xecuted when the nex$ sensor inSerrupt occurs begins at step
108G where the sensor interrupt timer is set for 18 milliseconds.
~59~
Following thi~, the CPU enables the ~C measurement path in step
1082 and then sets the AC measurement interrupt counter to zero in
step 1084. In step 1085, the AC measurement m~ximwm interrupts is
set to 32 ~nd in step 1086 the address of the program "Step to
next sensor" is stored ~t NIPAD. In the following step 1088, the
AC measurement interrupts qre enabled and in step 1090 the CPU
intern~l interrupt controller is enabled following which the CPU
returns in step 1092.
When the next AC measurement interrupt occurs and at
each AC measurement there~fter, ~ voltage multiplied by current
reading is ta~en on ~11 32 lines and stored in a buffer by the CPU
in a step 1094. In a subsequent step 109~, the AC measurement
interrupt counter is ineremented Qnd in step 1098 the AC measure-
ment interrupt counter is tested to see if its content is gre~ter
than 3a. If not, the CPU ret~rns following step 1098. As e~rlier
noted, the process of disabling interrupts, pushing the register
contents to the stack at the beginning of the AC me~surement pro-
gr~m and popping the stack and enabling the interrupts before a
: return, are all performed by CPV 27, although not shown in Figs.18A . . . 18D. - 1~ the AC me~surement counter is greater than 3a,
BS determined In step 1098, the cæu proceeds to s~ep 1100 where it
dis~bles the AC measurement interrupts following wh;ch it executes
step llOa where it disables the AC measurement path (resets ACGRD
and sets ACMEN ~t latch 373). In a subseguent step 1104, the CPU
en~bles its interrupt controller ~nd then proceeds to step 1106
where ~t calls the "Process AC meAsurement data" program. After
execution ~f this program, the CPU returns at step 1108.
The "Process AC measur~ment data" program executed at
step 1106 in Fig. 18D is illustr~ted in grenter detail in Fig. ao.
At the time this progrAm is executed, the CP~ has stored
32 samples for each remote station on a line ~or up to 32 lines,
~2S9~i8~
1024 s~mples in all. In this progr~m, 32 power samples from a
memory buffer for each sensor are used to determine a power
measurement. In a first step of the program 1110, the CPU adds 32
sHmples from the memory buffer for a particul~r ~urrent sensor to
determine ~ power reading. The CPU then proceeds to step 1112
where the sum of the 32 shmples is m~ltiplied by a scale factor.
The scale f~ctor ~s determined by looking at the automatic gain
control setting ~or each line and using the value thereof which
was previously stored. The scaled sum is then stored in another
buffer to indicate the instantaneous power usage in a step 1114.
Following this, the CPU proceeds to 5tep 1116 where it adds the
s~aled swm to ~ peak usage buffer sum. After this, the CPU pro-
ceeds to step 1118 where it adds the s~led sum to an accumulator
buffer. In a subseguent step 1119, a line counter is incremented
~nd in a step 11~0 the CPU determines ~hether the line counter
equ~ls 33 or not indicating that all lines h~ve been processed.
lf not, it returns to step 1110 and repeats all the steps from
this point down to step 1118 for each of the lines of the sys-
tem. When step 1120 indicates that all lines heve been processed,
the CPU then proceeds to return at step 1122.
The operator Interactlve program 403 of Fig. 9 is
illustrated in det~ll in Figs. 25A . . . 25M. This program is
contlnuously executed by CPU 27 when it is not processing an in-
terrupt progrun. It is used to extract and further manipulate
processed data which has been provided by the sensor interrupt
progr~ms described above.
In the first step 1200 of the OIP ~ terminal operator is
instructed to select either a "look" mode or a "maintenance" mode.
The look mode is primarily designed to enable an operator to in-
spect the data ~cquired from individual remote StQtiOnS~ e.g.apartment units, while the m~inten~nce mode performs various
~L~S9681
housekeeping and data processing functions. ~or the purposes o~
further description, it will be assumed that each remote station
is located at an apartment unit of a building.
In the first step of the look mode~ the CPU proceeds to
step 1202 where it asks the operator whether he knows ~hat apart-
ment he is interested in. If he does, the CPU proceeds to step
1212 where it searches an apartment index with ~n operator in-
putted ap~rtment number to determine 8 section number (0-15), line
number (0~ nd unit number (0-15) which h6s been assigned to
th~t spertment. This data is stored by the CPU and is used to
identify and ~ccess datu for the apartment in question. The
~p~rtment index is R stored t~ble which contain~ the section num-
ber9 line number and unit numbers assigned to each apartment. The
m~nner in which this index is entered into the system will be
further described below. hfter completing step 1212, the CPU
pr~ceeds to step 1214 where it calculates the actual memory ad-
dresses where the ~arious data h~s been stored for the ap~rtment
number in question (for the section (S), line (L) and unit (U)
numbers assigned thereto). These addresses in~lude A temporRry
buffer address, a beginning address for psremeter data, a monthly
buffer address, and the address of an Instantaneous power buf-
far. The CPU ~lso determines from the se~tion, line and unit
numbers for ~ particular apQrtment, the configur~tion oode there-
of. The configuration oode represents the type and arrangement of
the sensors, what power line phase is being monitored, etc., which
are used at the ~partment in question. Different configurations
m~y cause the CP~ to calculate energy cons~nption differently.
If in step laO2 a determination is made thst the ope-
rRtor does not know the apartment number in question, the CPU
proceeds to step 1204 where it asks the operator to directly input
the section number, line number ~nd unit number for which data is
_
~5~368~L
sought. The CPU then proceeds to step 1206 where it determines
whether the input S, L and U data is v~lid, that is, that it
corresponds to Q section, line and unit rumber used in the system.
If the entered data is not ~alid, the CPU proceeds to step 1210
where it prints an "invalidl~ message and returns to step 1204. If
the S, L and ~ data is valid, the CPU proceeds to step 1208 where
it stores the inputted S, L and U data and looks up the npartment
number corresponding thereto in the apartment index. 'rhe CPU then
prints the apartment number for ths operator's information. Upon
concluding step 1208, the CPU then proceeds to step 1214 ~here it
performs the operations noted above for calculating the various
memory addresses ~or the d~t~ reguested corresponding to the S~ L
and U information. The configuration code for the input of S, L
and U is also determined in the manner previously described.
Upon completing step 1214, the CPU pro~eeds to step 121~
(~ig. 25~) where it prints a parameter abreviation t~ble. This
table merely lists all of the par~meters for which data has been
stored by the CPU, for example, electricity power consl~ption, air
flow, w~ter flow, BTU etc. Also in step 1216, the C~U requests
that An operator input a desired par~meter. The CPU then branches
to ~ routing corresponding to whatever parameter WQS selected by
an operator nnd inputted in ~tep 1216. Asswning for the moment
that electrlcal energy use par&meter El,C was selected, the CPU
proceeds to step 1218. Here it c~lculates an energy use rate by
first retrievin~ the energy cons~nption data for the selected
apartment. It then examines the configuration code for the apart-
ment unit under consideration to see if any additional processing
is required of the data, because of the sensor configuration. The
CPU also fetches a calibration scale f~tor previously stored for
use in calcul~ting energy consumption. The c~libration scale
factor is a factor ~hich is stored in the system by the CPU at the
_ ~ _
~2~9~81
time of installation. It is determined by using a highly accurate
calibration meter standard to determine energy consumption in a
particular electrical path in an apartment which is compared with
energy consumption as calculated and digitized by the section
switches 17 ~nd A/D converter 21. i~ there is any deviation be-
tween the standard and the power calculated by the hard,ware struc-
tures of the invention, this is stored by the CPU upon m~nual
entry of an operator as a calibration scale factor. As a result,
any measure~ent inaccur~cies inherent in the system c~n be
accounted for and balanced out.
From the power data retrieved, the eonfiguration code
and the ~alibr~tion scale factor, the CPU then calcul~tes the rate
; of energy usage for the apartment being considered. Appropriate-
const~nts ~re then applied to this rate to determine energy usage
per hour, per d~y, and per month. Summ~ry data indic~ting the
~mount ~nd cost of all ele~trical energy used to date for the
present month for this apartment is ~lso cslculated. Upon com-
; pleting Qll the electrical energy use rate calculations in step
1218, the CPU proceeds to step 1220 where the calculated energy
data is displQyed.
Upon ~ompleting step 1220 the CPU proceeds to step laa2
where it determines if an operator has inputted Q control signal
instructing the CPU to pr~ceed. If no ~ntrol signal has been
entered, the CPU proceeds to step 1223 where it w~its for the next
input s~mple of energy dQta for the apartment selected which
occurs under m~ster and sensor interrupt control ~s described
edrlier. When the next energy dat~ sample ~rrives, the CPU re-
turns to step 1218 where it recalcul~tes energy use dats u~ing the
new energy d~t~ samples. Upon reception of the control sign~l in
step 1222, the CPU proceeds to step 1224 ~Yig. 25C) where it asks
the operator if he wants to view the data for a new par~meter. If
~59~81
yes, the CPU proceeds b~ck to step 1216 ~Ind begins the seguence of
steps described earlier,
If no new paruneter is desired, the CPU proceeds from
step 1224 to step 1226 where it asks the operator if he wants to
see data for a new apartment. If yes, the CPU proceeds back to
step laO2 where it asks whether the apartment is known or not. If
the CPU determines in step 1226 th~t data for a different ~part-
ment is not desired, it proceeds to step 1228 where it asks the
oper~tor if he w~nts ~nother mode. If not the CPU proceeds to
step 1220, otherwise it returns to step 1200 and awaits a look or
malnten~n~e mode input command.
If in step 1216 the operator selects the par~meter AEL
(Average Electric~l ~nergy) the CPU proeeeds frvn there to step
1350 (Fig. 25J) where it &sks the oper~tor how m~ny samples he
wishes to include in the averaging. This is input a~ a valus N
which the CPU stores in step 1350 following which it proceeds to
step 1352 where it c~lcul~tes and prints electrieal energy use
rate data.
Following step 1352, the CPU proceeds to step 1354 where
it determines whether all of the sumples entered at step 1350 h~ve
been processed. lf not, the CPU proceeds to step 13S5 where it
waits tor the next data sunple to be collected during processing
of the sensor interrupt progr~ms. After the next s~mple h~s been
collected, the CPU cycles back to step 1352 and recalculates and
prints the electrical energy use again displaying this inform~-
tion. The s~mples oecur at the rate of 512 per hour.
When all samples have been processed as determined in
step 1354, the CPU proceeds to step 1356 where it ~sks the ope-
rator if he w~nts ~nother set of readings. lf the operator enters
a yes, this is determined in step 1358 by the ~PU which then
cy~les back to step 1350 and repeats the abo~e described pro~ess.
_ ~ _
~259g~i8~
If a no is entered by the operator in step 1356, as detected by
the CPU in step 1358, the CPU ~ycles back to the beginning of the
OIP program step 1200.
Returning to step 1216 (~ig. 25B) if the CPU determines
that an operator has inputted a request for a pQrameter W~R (Water
~low Rate) the ~PU jumps at step 1217 to a UFR routine (Pig. 25K)
; where in the first step 1360 the CPU fetches all water use data
for the selected apartment. Water use data is collected by the
CPU during execution of the sensor interrupt programs in the sume
manner as used to collect air flow data described above in refer-
ence to Fig. 23. That is, the sensed temperature difference be-
tween upstream and downstream temperature sensors m~unted in a
fluid flow path (e.g. Fig. 28A) provides ~n indic~tion of flow
rate.
The flow rste data is multiplied by a cost factor to
proYide datQ representative of total water usa~e~ The CPU then
proceeds to step 1362 where it displ~ys data eorresponding to the
rate of water usage ~s well dS cost. Upon completing the calcu-
lation and display of water use in step 1362, the CPU then pro-
ceeds to the next step whi~h is identical to step 1222 in ~ig.~5B, being labeled 1222 in ~ig. 25K. ~he WFR program oper~tion
proceeds as described above for the ELC progr~m shown in Fig. 25B,
so that description will not be repeated.
If in step 1216 (Fig. 25B) the operator enters the
parameter BTU indicRting he wishes to review data relating to BTU
consumption, the CPU branches to step 1364 (Fig. 25K) where BTU
d~ta for a selected apartment is accessed. ~ppropriate rate data
is used by the C~'U to c~lculate cost o~ BTU usa~e. The CPU then
pro~eeds to step 1366 where it calculates and di~plays thermal
energy use datQ. Upon ~ompletion of step 1366, progrRm operation
proceeds 8S described for ELC and W~R flnd this description will
not be repeated.
~59681
Assuming th~t at the output of step 1200 (~ig. 2~A), the
CPU has been instructed to enter a m~inten~nce mode, it proceeds
to step 1230 (Fig. 25D) where it prints a mainten~nce m~de command
list ~nd request an oper~tor input sele~tion. The maintenance
mode command list is illustrated in step la30 ot ~ig. 25D. In
step 1232 the CPU br~nches to a subroutine corresponding to the
maintenance mode command selected by an operator. If the ~ommand
is ALL or EGAL, the CPU proceeds to step 1234 (~ig. 25~) where it
asks the operqtor if he knows the apartment number. Steps 1234,
1236, 1238, 1240, 1242 and 1244 all corr~espond to respective steps
1202, 1204, 1206, lal0, 1208 and 1212 which have been previously
des~ribed. The purpose of these steps is to determine the ~, L
and U numbers for the aparSment under consider~tion and a detailed
description of these steps will not be repeated herein.
Upon completion Df the routine for determining the S, L
and V for the ~pQrtment nwnber in question, the CPU at step 124B
br~nches to either the ALL or ECAL routines which were previously
selected in step 1230. In the ALL routine:, the CP~ proceeds to
step 1248 where it stores all parameter d~ta for the S, L and U
which has been~selected ln a tempornry buffer and all sensor data
is printed ~rom the buffer. The CPV then proce~ds to step 1249
where It determines if An operator has input ~ control code N. If
not, the CPU proceeds to step 1250 where it waits for the next
data s~mple from the sensors which is inputted during processing
of the m~ster and sensor interrupt programs. When the next s~mple
is received, ~bout seven seconds later, the CPU proceeds bsck to
st~p 1848 where it stores the new sample d~ta for tbe S, L and U
selected in a tempor~ry buffer and prints this data fr~m the
buffer. If in ~tep 1249 the CPU determines th~t the control N
code has been re~eived, it brRnches b~ek to step 1200 (Fig. 25A)
which is the bEginning of the OIP progr~m.
~259~8~L
If during initi~l execution of step la30, the CPU de-
tects an input for EC~L, this routine will be entered at branching
step 1246 to Btep 1252.
The ECAL routine is designed to compare power calculated
by the invention with an independent calibration meter having
very high degree of aceurQcy. The purpose of this is to determine
the ealibration scale factor described earlier~ Any differences
between power ~lculated by the system of the invention ~nd power
calculated by the ~alibr~tion meter is set into the system as a
calibr~tion scale factor which is used by the system when cal~u-
; lating power consumed. In this manner, the system can be peri-
odically calibrated to a high accurQcy.
In the first step 1252 of the ECAL routine, the CPU
prompts ehe oper&tor to insert how m~ny samples he wishes the
c~libration routine to extend over. Twenty samples would be typi-
cal. The s~mples correspond to the upd~ting of the data sflmples
which occurs during processing of the sensor interrupt routines
; described earlier. The number o~ samples input by an operator is
stored as a value N. ~ollowing this, the CPU proceeds to step 1254
where it prints the apartment number, section line Qnd unit num-
bers corresponding to the sensor &nd associated line path being
c~llbrated. Also in step 1254, the CPU asks the oper~tor whether
calibration is desired for input phsses A, B or C. In many cases,
a three phase power llne runs to an ap~rtment and each m~y be
separ~tely calibrated. In some inst~llations, only a single phase
power line enters an apartment i~ which case the operator will
only select that single ph~se for calibrfltion in step 1254.
~ rom step 1254, the CPU proceeds to step la56 (~ig. 25Y)
where it prints the message to the operator to get resdy to stQrt
the calibration meter. Then in step 1257 the CPU a~tivates a tone
generator whi~h sig~ls an operator to begin operation of the
~L~S9~
calibration meter. ~rom there the CPU proceeds to step 1258 where
it calculates and di~plays corrected and uncorrected power values
for the phsse selected by the operator in step 1254. The uncor-
rected power is that stored by the CPU during ~ensor interrupt
processing which has not been corrected ~ith the calibrRtion scale
f~ctor. The corrected power ~alculation is effected by applying
calibration scale factor to the uncorr~cted power which was de-
rived during a previous execution of ~n ECAL routine. In step
1258 the CPU also prints the corrected ~nd uncorrected power for
the operator selected phase, e.g. B9 the power for this phase
after an ~X" number of samples (which will vary beSween I ~nd the
operator determined sample number N), the average uncorrected
power for the selected phase, the average corre~ted power for the
selected phase, the tot~l uncorrected energy used ~or the selected
phese and the total corrected energy used for the selected phase.
This latter value is the most important ~or calibration purposes
as it yields a watt hour energy eonsumption value which is com-
pared with a w~tt hour energy conswmption value determined by the
calibration meter.
After executing step 1258 the CPU increments the s~nple
counter in 1260 and in step 1262 determ~nes whether the sample
count is greater than the value entered by the operator in step
1252. 1~ not, the CPV proceeds to a w~it for the ne~t sample at
step 1263. In this step, the CPU determines when the next sample
of power dat~ is inputted into the system under the master and
sensor interrupt processing routines. When the next d~ta samples
for power have been ~tored in the ~ppropriate buffer registers,
the CPU proceeds back to step 1258 where it updates the uncor-
rected and csrrected power in~ormation fsr each o~ the values
described previously. Steps 1258, 1260 and 1263 are continuously
repested until in step 1262 the CPU determines that the number of
_ Q,~ _
~L259~1
samples which have occurred exceeds th~t set by the operator at
step la52. The CPU then proceeds to step 12S4 where it sounds e
tone instructing the oper~tor to stop the calibration meter. The
operator can now comp~re the contents of the c~libration meter
with the total eorrected energy for the selected phase which
~ppears on the screen from step 1258. If these respective values
di~er, the operator may instr~ct the CPU to change the c~
brQtion d~ta which is being used to correct the power. The CPU in
step 1265 prompts the oper~tor to either enter the actual sc~le
v~lue which is the reading taken from the cQlibr~tion meter, or to
manually enter a different scale factor by flrst inputting the
code "9g". If no change is desired, the CPU instructs the ope-
rator in step 1265 to enter a n 1~ .
~ ram step 1265, the CPU proceeds to step 1266 and 1268
(Fig. 25G) where it determines whether ~ ~1", a "99", or a scale
factor has been entered by the operator. If a ~1" has been en-
tered, the CPU proceeds from step 1256 to step 1272 where it
prints the present cAlibration value. From there it proceeds to
; step 1276 where it ~sks the oper~tor if he wishes to e~librate
~nother phase. If the ~nswer is yes, the CPU proceeds to step
la64 a~d repeats the ~CAL routin0 for a different ph~se. 1~ the
operAtor does not deslre to calibr~te ~nother phase, the CPU pro-
ceeds from step 1276 to ~tep 1278 where it inquiras if the ope-
r~tor wishes to calibrQte the power lines for another apartment.
lf yes, the CPU proceeds ~rom step 1278 to step 1234 (Fig. 25E)
but if not, the CPU then proceeds directly to step 128~ where it
Qsks the operator if he wishes to have the new cAlibration data
stored on disk. Y~ yes, the CP~ proceeds to step 128a where it
stores the new calibr~tion d~ta on a disk and from there returns
to the beginning of the OIP progr~m ~t step 1200 (~ig. 25A). 1~
the new ealibrAtion data is not to be stored on disk, the CPU
_ ~ _
~1259~
proceeds from step 1280 to the beginning of the OIP progr~m at
step 1200 (Fig. 25Al.
If in step 1266 the CPU determines that the operator
~nput at step 1265 was not a "1", it proceeds to step 1268 where
it determines if it was ~ "99-1. If not it proceeds to step 1270
where a scale fa~tor calculated from the ~alibration meter reading
which was entered by the operator in step 1265 is stored as a new
scale factor to be used for subsequent c~libration of incoming
power data. ~rom there the CPU proceeds to step 1272 where it
executes steps 1272, 1276, 12789 1280 and 1282 (~ig. 25G) in the
manner described above.
If in step læs8 the ~PU determines that the operator
entered a ~991t ~ode It pro~eeds to step 1274 where it prompts the
~ operator to input A desired binary scale value QS the calibration
;~ scale fa~tor. From there the CPU proceeds to step 1272 ~Fig. 25G)
snd where it executes the subsequent steps in the m~nner previous-
, ly described.
; If in the m~intenance mode co~m~nd input step la30 (Fig.
2SD), the CPU determines that the command APT NO. was entered, it
proceeds to a routine ~r finding an apartment number from a sec-
tion, line and unit number input by the oper~tor. This routine
begins at step 1284 (~ig. 25H) where the operator Is prompted to
enter the S, L and U information in sequence. In step 1286 the
CPU consult 9 the ~partment index and identifies the apartment
number associated with the input S, L and U inform~tion following
which in step la88 ehe CP~ asks the operator if he wants another
spartment nu~ber fr~m available S, L nnd U iniormation. If not,
this routine returns to the en$ry point ~Itep 1200 ~ig. 2SA) of
the OIP program. If in step 1288 the operator }ndicates that ~n
additionQl apartment number is desired, the CPU proceeds back to
step 1284 where it requests new ~, L and U information.
~2596~31
If when in the m~inten~nce mode ~ommand input step 1~30
(Pig. 25D) the operator inputs the 5LU comm~nd, the CPU branches
to a routine for determining the S, L and U inform~tion fr~m an
inputted ~partment number. This routine is also illustr~ted in
~ig. 25H and has as a first step 1290 an input inguiry to the
operator requesting an apartment number. Following this, the CPU
se~rches the apartment index to determine the S, L and U d~ta
corresponding to this spartment. FrGm there the CPU proceeds to
step 1294 where it prints the ~, ~ snd U inform~tion ~nd then
returns to the input o~ the OIP program step 1200 ~Fig. 25A).
af in the maintenance mode ~ommand input step 1230 (Fig.
25D) the operstor selects the ~NT input, the CPU proe~e~s to ~n
initiali~ation routine illustrated in Fig. 25H. The first step
1296 of this routine is to request th0 operator to input his
initiali~ation code. The CPU then ~ompares this initislization
code with previously st~red initiali~ation ~odes representing
suthorized users of the system. lf the initialization code is
proper, as checked in step la9B, the CPU proceeds to initiali~e
the system in step 1300. To initialize the system, the CPU
executes the sensor interrupt routines to gather Qnd Qcquire cali-
br~tion offset dat~ for the sensors operating under known condi-
t~ons. Also in step 1300 the CPU prints on a display screen that
the system was initialized and the date Qnd time of initiali~a-
tion.
Upon completion of step 1300, the CPU proceeds to step
1302 where it ~sks the operator i~ he wishes to input an apartment
index at this time. If an apartment index input is not desired,
the CPU determines this in step 1304 and proceeds to a start rou-
tine which begins at step 1305 (~ig. 25H) If in step 1304 the
CPU determines that ~n apartment index is to be inputted it pro-
~eeds to an apartment index input routine which begins at step
1310 (Fig. 25I).
_ ~ _
~X591~8~L
The first step of the start routine 1305 prompts the
operator to input a control ch&racter "S" to start operation of
the ~ystem. In step 1306, the CPU determines whether the start
code for an "S" has been input. If 80~ it starts the system and
prints the time the system was started. If no input command "S"
is received, the CPU at step 1306 br~nches b~ck to the beginning
o~ the OIP program at step 1200 (Fi~. a5A).
If as a result of step 1304 it is determined that an
apartment index is to be input, the CPU proceeds to step 1310
(~ig. 251) of the apartment index input routine. There it pr~mpts
; the operator to input an "I" if an apartment index is to be input
or a "C" if a previously stored apartment index is to be cor-
rected. ~ollowing step 1310, the CPU proceeds to steps 1312 an-d
1314 where it determines whether the operator has input sn "I" or
a "C". If an "I" was input, the CPU proceeds from step 1312 to
step 1326 where it instructs the operator that he may exit the
apartment index routine by typing an n ~ code, or that he can exit
a present apartment line by entering a "space bar~ oode or that he
mRy enter an ap~rtment input by entering ~ "carriage return~ code.
After instructlng the operator in step 1326 the CPU proceeds to
step 1328. In this step t~e CPV first sets a s~ction counter, a
line counter and a unit counter to nn initlal zero state. It then
displ~ys the states of these counters on the scre~n as S
L _ , and U _ , where the blanks represent the present contents
of the various counter~. The CPU then WQitS for the operator to
enter an Mpartment number sfter which he will execute a "carriage
returnn. At this point the CPU then assigns the inputted apArt-
ment number to the S, L and U numbers which were printed on the
screen prior to the operRtor entered apartment number. The CPU
then steps the se~tion counter to a new v~lus and displays new S,
L and U numbers on the screen following which it awaits a new
3L~5~681
apartment number entry by the oper~tor. The CPU then cycles
through the section counter until it reaches its m~ximun value
after which 16 S, L and U numbers will have been assigned to 16
entered ap~rtment numbers by the operator. ~ollowing this, the
CPU inerements the line eounter and resets the section ~ounter to
~ero and repests the process for the next 16 ~p~rtment entries
until the section counter again reaches its maximum. After this
the unit counter is incremented and the section and line counters
reset to ~ero. After the next 32 entries, the unit counter is
again incremented. Eventually, dll the counters reach their maxi-
mum states ~nd the CPU exits at step 1328 to step 1330 where it
prints "index full'l message to the operator. At this point, the
CPU has stored corresponding S, L and U numbers for each entered
apartment number. Pr~m step 1330, the CPU pro~eeds to step 1332
where it asks the operstor if he wishes to store the new apartment
index on a disk. I~ a yes response is entered, the CPU proceeds to
step 1324 where the apartment index is stored on disk and then to
the OIP progrun step 1200. If the answer at step 1322 is no, the
CPU proceeds back to input step 1200 of the OIP program.
Returning to step 1310, if the oper~tor input a "C"
indicatlng he wished correction of an existing ~partment index,
the CPU pro¢eeds to step 1316 where it requests the operator to
input S, L and U codes for which an assigned apartment number
needs correction. The CPU then proceeds to step 1318 where it
; se~rches the apArtment index and prints the apartment for S, L and
U information. It then prompts the oper~tor to enter a corrected
; apartment number and then stores the corrected apartment number in
the ap~rtment index in correspondence to the entered S, L and U
codes. Pollowing the step 1318, the CP~ proceeds to step 1320
where it asks the operator i~ he wishes to correct another apQrt-
me~t number and if the answer is yes ~he CPU br~nces back to step
1316.
l ob
~L2~9~8~L
Returning to the m~intenance de ~ommand input step
1230 (Fig. 25D) ~nother operator selected input mode is TIM~.. If
this is selected, at step la32 the CPU branches to a TIME routine
where in step 1332 SFig. 25L) it readq a real time clock ~nd
prints the present time after which it returns to the beginning of
the OIP progr~m, step 1200 (Fig. 25A). Another maintenance mode
input ~omnand is TIME SET ~nd if this is selected in step 1230 by
~n operator the CPU proceeds to a TIME SET routine ~Fig, 25L)
where it prompts an oper~tor to enter the present time which the
CPU then sets into the system real time clock. After this, the
CPU returns to step 12Q0 of the OIP program.
Another input mode ~omm~nd which an operQtor can select
at step 1230 is D~TE. In the first step 1336 of this routine
(Fig. 25L), the CPU reads the present month, day and yeQr fram the
; system clock and displays it to the oper~tor. After this,, the CPU
returns to step 1200 of the OIP program,
Another m~intenan~e mode input comm~nd is DATE SET and
if this is selected by the operator in step 1230, the CPU branches
to a DATE SET routine illustrated in step 1338 (Fig, 25L). In
step 1338 the CPU prompts the operator to enter the present date
which the CPU sets into the system clock. Upon completing step
1338, the CPU returns to the beginning of the OIP program at step
1200 (Fig. 25A).
Another ma~ntenance mode input command is APT INDEX. If
this command is selected by an operator a~ step la30, the CPU
enters the APT INDEX routine described earlier which begins at
step 1310 (Fig. 25I).
Additional inpu$ commands in the m~intenance m~de are
EC, ER, ~C, and TR. ~he EC routine (Fig. 25M) which ~sn be se-
lected has a step 1340 in which the CPU prompts an operator toinput an electri~ity eonversion ~onstant which the CPU uses to
~;~5~
cQlculate energy consumption. In the routine ER (~ig. 25M), the
CPU proceeds to step 1342 where it prompts an operator to input an
electrieity rQte cost factor. If the routine TC is selected, the
~PU proceeds to step l344 ~ig. 25M) where it prompts the operator
to input a therm~l conversion constant which }s used for BTU cal-
culations. Finally, if the operator selects the input routine TR,
the CPU proceeds to step l346 (~ig. 25M) where it prompts the
oper~tor to input a thermal rste cost figure which is stored and
used for thermal energy (BTU) cost calculdtions. Upon completion
of any of the four foregoing routines, the program pro~eeds to
step 1200 (Fig. 25A) of the OIP progr~m.
It should be ~ppreci~ted from the foregoing description
that the present invention provides a unique data gathering and
transmitting system in which a central station is capable of easi-
ly addressing each of the remote st~tions and each of the informa-
tion channels thereat by a simple sequential tone pulsing scheme.
~arious types of sensors m~y be connected to the information
channels at the remote stations, but the invention finds particu-
lar utility in measuring power consumption through an electrical
path at the remote station by having ~t least one of the lines at
each remote station connected to a current sensor which provides
ourrent data to the central station. This current data i5 multi-
plied by Q voltage data which represents the voltage in the elec-
trical path which is monitored by the current sensor to provide a
consumed power value ~t the central st~tion which can be stored
and accumulated ~or information or billing purposes.
Although the invention has been described with reference
to a specific embodiment, it should be understood that various
modifications can be m~de to the disclosed invention without de-
parting from its spirit or scope. Accordingly, the invention isnot tc be considered as limited by the foregoing description, but
1~
- ~6 -
:~L259~
is only to be considered ~s limi ted by the ~ldims which ~re
~ppended hereto.
