Note: Descriptions are shown in the official language in which they were submitted.
1 70128-89
BACKGROUND OF THE INVENTION
Field of tke Invention
This inventlon relates to configurable electrical
cireuits and in particular, to a method and means for providing
on-chip programming of each of a plurality of logic elements
formed on a chip of semiconductor material to configure each logic
element to carry out certain desired functions, and to configure
interconnects between the logic elements.
Prior Art
Gate arrays are well known in the prior art. Typically
a gate array is produced by interconnecting a plurality of active
devices in a base array in any one of number of ways to achieve a
desired logic function. As gate arrays beeome more complex, the
simulation of the logic to be achieved from a given
interconnection of the aetive devices in the base array beeomes
more diffieult and is typieally carried out using a eomputer
program. The layout of the actual interconnections for the active
deviees in the base array to yield a finished gate array is then
derived using a eomputer aided design program of a type well known
~0 in the art. The process of designing such a structure is complex
and reasonably expensive requiring the use of logic simulation and
verification programs and semiconductor device layout programs.
Aeeordingly, a need exists for an alternative approach which
signifieantly simplifies the obtaining of a given logic function
from a base array.
SUMMARY
~ In accordance with this invention, I provide a structure
which I denote as a configurable logic array which allows changing
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the configuration of the finlshed integrated circuit from time-to-
time (even when the integrated circuit is installed in a system)
to provide any one of a plurality of logical functions from the
same integrated circuit. In accordance with my invention, by
providing a number of "configurable logical elements" (also
re~erred to herein as "logic elements") in the base array, a new
type of integrated circuit is achieved which is capable of being
configured to provide any one of a plurality of logic functions
depending upon the tasks which the system of which it is a part is
called upon to perform. By "configurable logical element" I mean
a combination of devices which are capable of being electrically
interconnected by switches operated in response to control bits to
perform any one of a plurality of logical functions.
A configurable logic array of my invention is comprised
of a multiplicity of configurable logic elements each of which can
include all the circuit elements necessary to provide one or more
of the functions provided by an AND gate, flip flop, inverter, NOR
gate, exclusive OR gate, and combinations of these functions to
form more complex functions. In accordance with my invention, the
~0 particular function to be carried out by a configurable logic
element is determined by control signals applied to the
configurable logic element from control logic. Depending on the
control signals, the configurable logic element of one embodiment
of my invention can function as an AND gate, an OR gate, a NOR
gate, a NAND gate or an exclusive OR gate or any one of a number
of other logic elements without any change in physical structure.
In accordance wi~h my invention, structure is provided to allow
any one of a plurality of functions to be performed by each
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configurable logic element. Selecting a desired function is done
by providing control logic to store and generate control signals
which control the configuratlon of each configurable logic
element.
In one embodiment of my invention, the control signals
are stored and transmitted by control logic formed integrally with
and as part of the integrated circuit chip containing the
configurable logic element. However, if desired the control
information can be stored and/or ganerated outside this integrated
circuit and transmitted through pins to the configurable logic
element.
In general, in accordance with my invention, a given set
of control signals is transmitted to one configurable logic
element to control the configuration of that configurable logic
element. The control logic is thus arranged to provide any one
set of a plurality of sets of control bits to each configurable
logic element on the chip. The actual set of control bits
provided to each configurable logic element on the integrated
circuit chip depends on the function to be carried out by the
~0 integrated circuit chip or by each configurable logic element on
the chip. The configuration of each logic element on the chip is
determined by the intended function of the total chip and by the
intended function of that configurable logic element as part of
the chip. Thus the resulting structure is known as a
"Configurable Logic Array" or "CLA" and each logic element in the
array is known as a "Configurable Logic Element" or "CLE".
- In general, each integrated circuit chip has in addition
to and associated with the control logic certain on-chip data
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routing circuitry including configurable interconnects. In one
embodiment the on-chip data rou~ing is achieved by using a memory
to store ~he particular data used to configure the configurable
logic elements and by then transferring the data from the memory
to a novel combination of a dynamic shift register and static
latch element wi~hin or associated with each configurable logic
element on the chip.
The particular structure of this invention is versatile
in that it can be implemented particularly easily using P channel,
N channel, or CMOS technologies in the embodiment shown. Of
course, structure incorporating the principles oE this invention
can, if desired, be implemented using any other appropriate
semiconductor technology. The novel dynamic shift register-static
latch element of this invention is particularly useful in that the
structural "overhead" (i.e., access circuitry and routing
circuitry) is kept to a minimum relative to the useful logic
functions on the total chip~ Of particular importance, no
addressing, data selection, or decoding in each configurable logic
element is necessary when this novel combination of a dynamic
~0 shift register and static latch element is used to implement the
con~igurable logic array of my invention.
In accordance with a broad aspect of the invention there
is provided a programmable circuit comprising,
a plurality of configurable logic elements, each configurable
logic element having a plurality of input leads and at least one
output lead and having a programming means to cause said
configurable logic element to perform a selected logic function;
a plurality of inputtoutput ports;
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a group of interconnect lines;
means for programmably connecting each of said input leads of
each of said configurable logic elements to at least one of said
interconnect lines;
means for programmably connecting said at least one output
lead of each of said configurable logic elements to at least one
of said interconnect lines;
means for programmably connecting each of said input/output
ports to at least one of said interconnect lines; and
means for programmably connecting each one of said
interconnect lines to at least one other of said interconnect
lines;
whereby each of said input leads and each of said at least
one output lead of each of said configurable logic elements can be
connected dixectly or indirectly to each of said input/output
ports and to each other, and whereby each of said conf.igurable
logic elements can be programmed to perform a selected one of a
plurality of logic functions, and said configurable logic elements
can be connected to each other and to said input/output ports in a
~0 selectable manner.
In accordance with another broad aspect of the inventlon
there is provided an interconnect structure for programmably
interconnecting lines within an integrated circuit comprising:
at least three sets of interconnect lines including a first
set, a second set, and a thlrd set;
programmable means, not including said sets of interconnect
lines, for connecting at least one of said lines in said first set
to at least one of said lines in said second set, for connecting
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at least one of said lines in said first se~ ~,o at least one of
said lines in said third set, and for connec~ing a~ least one of
said lines in said second set to at least one of said lines in
said third set.
In accordance with another broad aspect of the invention
there is provided a configurable system comprising:
one master configurable logic array;
a plurality of slave configurable logic arrays;
at least one memory;
said master configurable logic array having means for
retxieving data from said at least one memory;
means for firs~ using said data for configuring itself, and
means for passing some of said da~a to said plurality of
slave configurable logic arrays.
In accordance with another broad aspect of the invention
there is provided a configurable system comprising:
a master configurable logic array;
a plurality of slave configurable logic arrays; and
a controller including means for addressing said configurable
0 logic arrays and
means for sending data to said configurable logic arrays;
wherein said master configurable logic array includes means
for being configured by said data from said controller and
means ~or configuring said slave configurable logic arrays.
This invention will be more fully understood in
conjunction with the following detailed description taken together
with the drawings.
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Descrietion o~ the Drawinqs
Figure 1 illustrates some of the various logic functions
capable of being provided by each logic ele~ent in a configurable
logic array;
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Figure 2 illustrates the internal logic structure of one
possible logic element capable of implementing a number of useful
functions with two variables A, B and certain configuration
control bits, C0 through C5;
Figure 3A illustrates a 16 bit RAM select circuit
wherein any one of sixteen possible input states is capable of
being identified and 216 functions are capable of being
implemented;
Figure 3s illustrates a selection structure for
selecting any one of sixteen bits capable of implementing 215
functions, for transmittal to an output lead;
Figure 3C illustrates one possible Karnaugh plot for the
structure of Figure 3A;
Figure 3D illustrates the logic gates represented by
placing a binary one in the Karnaugh map of E'igure 3C at the
intersections of the first and second rows and the first column;
Figure 4A illustrates one embodiment of my configurable
electrical circuit wherein a plurality of configurable logic
elements (shown as nine logic elements) are formed on an
~0 integrated circuit chip together with an array of leads including
leads from the logic elements and from input/output pads, and
programmable interconnects formed between selected leads to yield
desired logic functions;
Figure 4B shows the key to the cross-connections between
crossing conductive leads in Figure 4B;
Figure 5 represents a portion of the circuitry of a
novel combination static and dynamic shift register appropriate
for use with the configurable logic array of this invention;
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Figure 6A through 6H represent wave ~orms of use in
explaining the operation of the novel structure o~ Figure 5;
Figure 7A represents a schematic diagram of a
configurable logic array showing nine of N configurable logic
elements where N is a selected integer greater than 9 and selected
interconnections between conductive leads;
Figure 7B-l through 7B-7 are the key showing the types
of interconnections made by the symbo]s shown in Figure 7A;
Figure 8A illustrates a system with a microprocessor
controller and four configurable logic arrays;
Figure 8s illustrates a combination of four configurable
logic arrays together with a nonvolatile memory;
Figures 9A through 9G illustrate various topologies for
forming interconnections such as those shown in Figures 7B-l
through 7B-7 between two or more leads in a configurable logic
array;
Figures 10A and 10B show a circuit for implementing the
bidirectional buffer/amplifier represented by an "X" in a box in
Figures 4A and 4B; and
Figure ll shows a single board microcomputer using the
Configurable Logic Array of this invention.
DETAILED DESCRIPTION
The following detailed description of this invention is
meant to be illustrative only and not limiting. Other embodiments
of this invention will be obvious to those skilled in the art in
view of the following disclosure.
--6--
1 Turning now to Figure 1, Figure 1 illustr~tes certain
2 logic functions capable of being in~egrated into a configur-
3 able logic element. The 28 functions shown in Figure 1
4 are merely illustrative and other elements not shown can,
if desired, be included in a configurable logic element.
6 The following elements are sho~m:
8 Element Function
9 1 AND gate
2 NAND gate
11 3 AND gate with inverted input
12 4 NAND gate with inverted input
13 5 OR gate
14 6 NOR gate
1~ 7 exclusive OR gate
16 8 exclusive NOR gate
17 9 3 input AND gate
18 10 3 input NAND gate
19 11 3 input OR gate
12 3 input NOR gate
21 13 OR gate with one input comprising AND gate
~ 14 NOR gate with one input comprising AND gate
23 15 AND gate with one input comprising OR gate
~4 16 NAND gate with one input comprising OR gate
17 3 input AND gate with one input inverted
~6 18 3 input NAND gate with one inverted input
27 19 3 input OR gate with one inverted input
~8 20 3 lead NOR gate with one inverted input
29 21 one of two inputs multiplexer
22 inverting one of two inputs multiplexer
31 23 "D" flip flop with reset
32 24 Set-Reset latch
33 25 "D" flip-flop with reset and inverted
34 output
26 Set-reset latch with reset and inverted
36 output
37
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27 "D" flip-flop with set
28 "D" flip-flop with set and i~verted output
Of course, other logic elements can also be implemented
in accordance with this invention.
Figure 2 illustrates the internal logic structure of one
possible ~ogic element which is capable of implementing all useful
functions of the two variables A and B, with the functions being
selected by configuration control signals C0, C0, Cl, Cl...
through C5, as shown in Figure 2. For example, to implement an
AND gate function using the structure shown in Figura 2, the input
leads labelled A and B are shunted past inverters 21 and 22,
respectively, by high level signals on the C1 and C0 configuration
control leads. Leads Cl and C0 are connected to well-known pass
transistors 29c and 29d. (Throughout this specification a pass
transistor will be represented by the symbol shown within the
circles 29c and 29d). Low level signals are applied to the
configuration control leads C0 , Cl C4. Assuming that C0, Cl and
all of the other leads are connected to N channel MOS pass
~0 transistors, the control signals, C2, C2, C3 and C3 are "don't
cares". That is these signals can be high or low without
affecting the output signal. In addition, a high level signal on
C5 is applied to enable AND gate 25. Thus AND gate 25 serves as a
two input AND gate providing to NOR gate 26 the logical AND of
input variables A and B. The signal from AND gate 25 is passed
through NOR gate 26. NOR gate 26 converts the high level signal
from gate 25 to a low level signal to turn off MOS transistor 29a
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(the source of which is grounded and the drain of which is
connected to the output lead 28) and to turn on through NOR gate
27 N channel transistor 29b (the drain of which is connected to a
power supply and the source of which is connected to both the
output lead 28 and the drain of N channel transistor 29a). Thus
the structure of Figure 2 configured as described above is an AND
gate. Other logic functions can also be produced by appropriate
selection of the control signals to be supplied to the
configuration control leads C0 through C5 to activate the
ln appropriate pass transistors and gates within the structure.
Figure 3A illustrates a 16 bit RAM capable of producing one
of sixteen output signals in response to any one of sixteen
possible combinations of input signals. Thus input signals A and
B control the X decoder to select any one OL the four columns in
the 16 bit RAM. Input signals C and D control the Y decoder to
select any one of the four rows in the 16 bit RAM. The 16 bit RAM
produces an output signal representative of the bit at the
intersection of the selected row and column. There are 16 such
intersections and thus sixteen such bits. There are 216 possible
`20 combinations of functions capable of being represented by the set
of 16 bits present in the 16 bit RAM. Thus, if a NOR gate is to
be simulated by the 16 bits in the RAM, the Karnaugh map for the
RAM would be as shown in Figure 3C. In Figure 3C all bits are "0"
except the bit at the intersection of the first row ~representing
A=0, B=0) and the first column (representing C=0, D=0). Should a
less frequently used function be desired to be generated by the 16
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bit RAM, (for example, should a "1" output signal be desired for
~=1, B=0, C=0 and D=0) then a binary "1" is stored at the
intersection of the second row and the first column. Should a
binary "1" be desired both when A=0, s=o, C=0 and D=0 and also
when A=l, s=0, C=0 and D=0, then a binary "1" is stored at each of
the intersections of the first column with the first row and the
second row. The logic circuit represented by this loading of the
RA~1 is as shown in Figure 3D. Thus the RAM of Figure 3A
represents an elegant and simple implementation of any one of 216
logic functions~
Figure 3B shows another structure for yielding any one
of sixteen select bits in a 16-bit RAM. Each of registers 0-15 in
the vertical column to the left labelled "16 Select Bits",
contains a selected signal, either a binary 1 or 0. By selecting
the proper combination of A, B, C and D, a particular bit stored
in a particular one of the sixteen locations in the 16 Select Bits
register is transmitted to the output lead. Thus, for example, to
transmit the bit in the "1" register to the output lead, the
signal A, B, C, D is applied to the leads so labelled. To
~0 transmit the signal labelled "15" in the sixteenth location in the
16 Select Bits register to the output lead, the signal A, B, C,
and D is applied to the appropriate columns. Again, any one of
216 logic functions can be implemented using this structure.
Figure 4A illustrates an embodiment of a configurable
logic array of this invention containing nine configurable logical
elements. As shown in Figure 4A, nine logical elements are placed
~ on an integrated circuit chip together with interconnects and
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variable switches for connecting various leads to other leads.
Each of logic elements 40-1 through 40-9 represents a collection
of circuitry such as that shown in Figure 2 or some similar
structure capable of being configured as described above with
respect to Figure 2 to perform any one of a number of logic
functions. To program the circuitry of a logic element such as
shown in Figure 2, selected signals are applied to input leads of
the configurable logic element identified as con~iguration control
input leads thereby from a source such as the RAM of Figure 3A or
3B described above to generate a desired logical function in each
of the logic elements. In Figure 4A, no specific I/O pad has been
identified as an input lead for applying the configuration control
signals to the logic elements. However, any particular I/O pad
can be selected for this purpose. The configuration control bits
can be input into the configurable logic array of Figure 4A either
in series or in parallel depending upon design considerations.
Input of configuration control bits is described later in
conjunction with Figures 5, 8A, and 8B. In addition, another I/O
pad will be used on input clock signals to clock the logic
~0 elements both for the shifting in of the configuration control
signals to each configurable logic element and for controlling the
operation of each logic element during the functioning of the
integrated circuit chip in its intended manner. The combination
of logic elements 40-1 through 40-9 as configured by the
configuration control bits plus the interconnect structure of
Figure 4-A yields the desired logical output for the Configurable
Logic Array. Figure 4B illustrates the meaning of the
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interconnect symbols used in Figure ~A.
To configure a logic element such as logic element 40-1
(Figure 4A) a number of bits must be applied to the confiyuration
control leads such as leads C0 through C5, as shown, for example,
in Figure 2. To do this, a shift regis~er is utilized, in the
preferred embodiment as part of each configurable logic element.
Figure 5 illustrates a novel shift register of use in this
invention. The shift register of Figure 5 is illustrated showing
two basic storage cells. Each storage cell is capable of storing
one bit of information. Of course, an actual shi~t register will
contain as many storage cells as required to configure the logic
element of which the shift register is a part, to its desired
configuration. In operation, an input signal provided on one of
the I/O pads shown in Figure 4A is applied to input lead 58 of
Figure 5, which in Figure 4A would be one of the logic element
input lines. This input signal (shown in Figure 6D) contains -the
pulses to be stored in the shift register as configuration control
bits to configure the configurable logic element tc perform a
desired logic function or to conflgure an interconnection between
~0 leads in a manner to be described shortly. Thus the sequence of
pulses applied to input lead 58 of Figure 5 represents those
pulses which when stored in the storage cells of the shift
register will activate the configuration control bits in the
proper manner to achieve the desired functional and/or
interconnection result. For example, if the circuit of Figure 2
is to be configured to form an AND gate, the pulses C0, Cl, C2,
~ C3, C4 and C5 would be represented by l,l,X,X, 0,1.
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The sequence of pulses applied to input lead 58 is
synchronized with clocking pulses ~1 and ~2 applied to leads 57
and 59 respectively. Thus in the Eirst period of operation
clocking pulse ~1 goes high (Figure 6A), clocking pulse ~2 is low
(Figure 6B), the hold signal (Figure 6C) is low during shifting
thereby facilitating the passage of data through sequentially
connected cells 5-1, 5-2 et al. of the shift register of Figure 5.
To shift the pattern 01010 into the shift register, the following
operations occur: The input signal (Figure 6D) on lead 58 ~Figure
5) is low during approximately the first half cycle of the
clocking period tl. The output signal Ql of the inverter 51-1
goes to a high level in response to the low level input signal on
lead 58 and ~1 high to enable PASS transistor 53-1. During the
first clocking period tl, the clock signal ~1 goes low (Figure 6A)
and the clock signal ~2 shortly thereafter goes high (Figure 6B)
to enable PASS transistor 55-1. Consequently, the high level
output signal Ql is transmitted to the input lead of inverter 52-1
by enabled pass transistor 55 1 and thereby produces a low level
~0 output signal Ql on the output lead of inverter 52-1. Thus at the
end of period tl, the output signal Ql (Figure 6F) from inverter
52-1 is low level. The output signals Q2 and Q2 (Figures 6G, 6H)
from inverters 51-2 and 52-2 in the second cell are still
indeterminate because no known signal has yet propagated to the
second storage cell 5-2 to change the signals of these inverters
to a known state.
At the beginning of the second period (labelled "t2" in
~ Figures 6A through 6H), ~1 goes high (Figure 6A) and ~2 is low
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(Figure 6B) having gone low before period tl ended. The input
signal (Figure 6D) now has risen to a high level representing a
binary 1 and thus the output signal Ql of inverter 51-1 has gone
low. The output signal Ql of inverter 52-1 remains low because
pass transistor 55-1 is held off by the low level ~2 signal. Some
time through the second period ~1 goes low followed a fraction of
time later by ~2 going high. At this time, the output signal Ql
is transmitted through pass transistor 55-1 to inverter 52-1
thereby driving the output signal Ql from inverter 52-1 to high
level. Meanwhile, during period t2 the previous low level signal
Ql from inverter 52-1 has driven the output signal Q2 of inverter
51-2 to a high level when ~1 was at a high level to enable PASS
tra-nsistor 53-2. Also the change in ~2 from a low level to a high
level in the second half of period t2 to enable PASS transistor
55-2 drives the output signal Q2 from inverter 52-2 to a low
level. In this manner, the input signal on lead 58 (Figure 6D) is
trans~itted through each of the cells 5-1, 5-2, 5-3 et al. in the
shift register. Upon the transfer into the shift register of the
desired information, the hold signal (Figure 6C) is enabled (i.e.,
driven to a high level) thereby to connect the feedback leads 50-
1, 50-2, and 50-3 et al. from the output leads of inverters of one
stage to input leads of inverters of the same stage so as to hold
the information then in each cell indeEinitely. In operation, the
signal stored in a given cell of Figure 5 is connected to a
configuration control portion of a logic element or to an
interconnect pass device.
g Ql' Ql' Q2l Q2' etc. from the shift register
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of Figure 5 are directly connected to the (configuration) control
inputs of a logic element such as shown in Figure 4A or the pass
devices of the configurable interconnect (to be explained later in
conjunction wi-th Figure 9A).
When ~1 is low, ~2 and hold may be brought high, thus
holding the data indefinitely. The entire shift register may be
set or cleared by setting or clearing the input with ~1 and ~2
both high and HOLD low. Enough set/reset time must be allowed for
the signal to propagate the entire length of the shift register to
clear the shift register in this manner. Naturally this time is
dependent upon the length of the shift register.
The shift register operates in its dynamic phase by
storing the information being shifted as charge on the gates of
the pass transistors (not shown in Figure 5 but shown in Figure 2
and well-known) comprising inverters 51-1, 52-1, 51-2, 52-2 et al.
of the shift register. These inverters are of well-known design
and will not be described in detail. The use of the dynamic shift
register is an important feature of the invention because each
cell of a dynamic shift register uses six transistors and thus
~0 takes up very little area. Uniquely, the dynamic shift register
is converted to a static latch by adding only one transistor to
each cell. Thus the novel dynamic shift register-static latch can
be easily fabricated as part of a configurable logic element
without adding significant complexity to the circuit or consuming
significant semiconductor area. Because of the "hold" signal, the
dynamic shift register can be driven a-t a very low frequency
because placing the shift register on hold automatically refreshes
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the data. Thus a separate refresh circuit is not needed.
It will be apparent from the above description that the
novel, dynamic shift register static latch circuit is unique in
that it does not need refreshing once it has been latched into a
hold posi-tion. This is accomplished by use of the feedback
circuit comprising lead 50-l and pass transistor 54-1 in cell 5-l,
for example.
Figure 7~ shows an additional configurable logic array
containing a plurality of configurable logic elements. In
particular, configurable logic elements 70-1, 70-2, 70-4 and 70-5
are shown in their entirety while configurable logic elements 70-
3, 70-6 and 70-7 through 70-9 are shown partially. The complete
interconnections of these last five logical elements are not
shown. The structure shown in Figure 7A is merely illustrative of
the types of configurations and connections which can be
implemented using the configurable logic array of this invention
and does not depict an actual circuit configured to carry out an
intended function.
As shown in Figure 7A, given leads can be interconnected
by any one of a plurality of different means (i.e.,
interconnection structures). The symbols representing the
interconnections shown in Figure 7A are illustrated in Figure 7B.
In particular, while the schematics depicting various
interconnections are to some extent self-explanatory, the
conventions used in these schematics are explained in Figures 9A
through 9G.
Figure 9A is the schematic of a circuit for making a
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number of different interconnections between two cross-over leads
such as shown in Figure 7s-3, horizontal lead 90-1 and vertical
lead 90-2. Thus, in Figure 9A, pass transistor 2, when activated
into the conducting state, connects lead 90-3 to lead 90-1. Pass
transistor 1, when conducting, connects lead 90-3 to lead 90-4.
Pass transistor 4, when conducting, connects lead 90-4 to lead 90-
2 and pass transistor 3, when conducting, connects lead 90-1 to
lead 90-2. Pass transistors 6 and 5, when off, separate lead 90-2
from lead 90-3 and separate lead 90-1 from lead 90-4 respectively.
Thus, should it be desired to connect vertical lead 90-2 to
vertical lead 90-3, pass transistor 6 is activated. Likewise,
should it be desired to connect horizontal lead 90-1 to horizontal
lead 90-4, pass transistor 5 is activated. The -terminology used
to represent the possible connections between a plurality of leads
can become quite complex. Thus, a simplified notation system as
shown in Figures 9B to 9E has been adopted.
In Figure 9B, a plurality of pass transistors 92-1
through 92-13 are shown. The convention adopted in Figure 9B is
to have a given pass transistor represented by a single short
line. Thus, the line labelled 92-1 represents a pass transistor.
Pass transistor 92-1 is drawn so that its two ends point to the
ends of the leads 91-5 and 91-6 being interconnected by pass
transistor 92-1. Thus, the right end 93a of pass transistor 92-1
is aimed to the end 94a of lead 91-5. The left end 93b of pass
transistor 92-1 is aimed to the end 94b of lead 91-6. For
simplicity and to avoid cluttering the drawing in Figure 9B, the
- other ends of the transistors are not labelled. However, by
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visually aligning the line representing a given pass transistor
with the ends of the leads 91-1 through 91-6 the particular two
leads interconnected by that pass transistor can be determined.
Thus, pass transistor 92-7 interconnects horizontal lead 91-4 with
vertical lead 92-8. Pass transistor 92-13 interconnects
hori20ntal lead 91-4 with hori~ontal lead 91-2. Pass transistor
92-12 interconnects lead 91-3 with lead 91-5. Similar connections
can be made between the other pass transistors and the other
leads.
The above description assumes that only two leads are to
be interconnected. If more than two leads are to be
interconnected, the structure of Figure 9B can also be used for
this purpose. Thus, lead 91-3 can be connected to lead 91-2 by
turning on pass transistor 92-10. Simultaneously, lead 91-3 can
be connected to lead 91-4 by turning on pass transistor 92-13.
Alternatively, lead 91-3 could be connected to lead 91-4 by
turning on pass transistor 92-11. Of course, this would also
connect lead 91-4 through lead 91-3 and pass transistor 92-10 to
lead 91-2. In addition, lead 91-6, for example, could be
connected to the three leads 91-2, 91-3, 91-4 by turning on pass
transistor 92-8. Clearly, a large number of permutations of
interconnections can be made using this structure. In the case
where all the pass transistors are turned on, all the leads 91-1
to 91-6 are interconnected. The resulting structure has a large
capacitance which can actually be used in circuits as a component.
Of course, all leads in Figure 9B can be interconnected by turning
on as few as five pass transistors. Note that in Figure 9B leads
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91-1 and 91-2 cannot be direc-tly connected to each other nor can
lead 91-4 be directly connected to lead 91-5 without involvlng
another lead. However, this omission is not of importance because
in an ;ntegrated circuit there is in general no need for two
parallel leads to carry the same signal. OE course, two
additional pass transistors could be added to the structure of
Figure 9B Figure 9B is considered to be merely a symbolic
representation of intersecting leads and leads 91-1 and 91-2 are
merely shown for convenience as being parallel but in fact can
1~ represent non-parallel leads on an integrated circuit.
With reference to Figures 9C and 9D two other possible
representations are illustrated. In Figure 9D leads 1 to 8 are
shown coming together at a complicated intersection. Leads 1 and
8 are parallel horizontal to the left, leads 4 and 5 are parallel
horizontal to the right, leads 2 and 3 are parallel vertical up
and leads 6 and 7 are parallel vertical down. Looking for a
moment at lead 6, the end 6a of lead 6 can be connected sensibly
to the ends "a" of leads 1, 2, 3, 4, 5 and 8. It is not sensible
to connect lead 6 to lead 7 because theoretically the two leads
~0 are going in one direction and only one lead is required to carry
the necessary information in that direction. Since lead 6 has six
possible connections and there are eight leads, a total of forty-
eight possible connections are offered by the structure of Figure
9D. Since a given pass transistor connects two ends, twenty-four
pass transistors are required to make the required forty-eight
connections. The particular pass transistors have their ends
~ labelled in Figure 9D to illustrate the leads which are connected
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by a given pass transistor. Thus, pass transistor 6-8
interconnects the end 6a of lead 6 to the end 8a of lead 8. Pass
transistors 7-5 interconnects the end of lead 7 to the end of lead
5. Because of the complexity of the structure of Figure 9D a
slightly different convention (a line with numbers on both ends)
has been adopted for representing the pass transistor than that
which was described above in conjunctlon with Figure 9B.
Figure 9E illustrates types of interconnections possible
using the method of this invention. The leads interconnected are
illustrated by howing continuous lines are broken lines depending
on whether a given lead is connected to another lead or left
unconnected. These interconnections are self-explanatory.
Figure 9F illustrates the connections that would be
possible if the four pass transistors 1~6, 2-5, 3-8, 4-7 omitted
from Figure 9D were in fact included. The dashed lines show the
interconnections possible be these omitted transistors. Thus,
Figure 9D shows only twenty pass transistors whereas twenty-four
pass transistors are necessary to make all possible connections
between the leads. Figure 9G illustrates the way in which it is
?0 possible to interconnect leads 4 and 7 without the four transistor
connections shown in Figure 9F being present. Thus, to connect
lead 4 to lead 7, lead ~ is connected directly to lead 8 by means
of transistor 4-8 while lead 8 is connected to lead 7 by pass
transistor 8-7.
Figure 9C illustrates the configuration of Figure 9D
with the full twenty-four interconnection transistors shown rather
than merely the twenty shown in Figure 9D. As shown in Figure 9C
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pass transistors 1-6, 7-4, 2-5 and 8-3 have been added to the
transistors shown in Figure 9D. For convenience and to avoid
cluttering the drawing, the other pass transistors shown in Figure
9D have not been numbered in Figure 9C except for pass transistor
6-8.
Note that each of the interconnections shown above in
Figures 9A through 9G requires only one gate in order to connect
one lead to another except for the particular configuration
illustrated in Figure 9G wherein two gates are required. This
means that the speed of circuits formed using the interconnections
of this invention is greater than the speed of circuits using
prior art interconnections.
The symbology used in Figures 7s-l through 7s-7 is
identical to the symbology just explained in conjunction with
Figures 9A through 9G. Thus, for example, Figure 7B-7 illustrates
on the left the symbol for a 2D transistor interchange and on the
right the locations of the 2D transistors and corresponds
precisely to the interchange explained above in conjunction with
Figure 9D.
Figure 7B-l illustrates three transistors capable of
making a T connection, a cross-connection or a four-way connection
but not a vertical only connection and therefore not a full
interconnection. By full interconnection is meant the ability to
connect each of the leads (in Figure 7B-l, four leads) coming into
a node to a given node or to each of the other leads coming into
the node in any combination.
~ Figure 7B-2 shows a one transistor interconnection to
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connect a row with a column. Figure 7B-3 shows a six transistor
full cross interconnection wherein any one of four leads coming
into a node can be connected to any one of the other three leads.
figure 7B-~ shows six leads coming into an intersection wherein
ten pass transistors are used to interconnect any one of the six
input leads to any one of the five other leads input to the node.
Figure 7B-5 illustrates a four-lead node where two horizontal
continuous leads are interconnected with two separate vertical
leads using five pass transistors.
1~ Figure 7B-6 illustrates a three-transistor
interconnection wherein any one of three leads coming into a node
can be interconnected with any one of the other two leads. Figure
7B-7 illustrates the twenty-transistor interchange for
interconnecting any one of eight input leads to any one of the
other eight input leads except that lead parallel and adjacent to
the lead being interconnected as illustrated in Figure 9D and
except for the four interconnections shown in Figure 9F.
Figures 8A and 8B illustrate two possible systems
capable of using the configurable logic arrays of this invention.
2~ In Figure 8A, a microprocessor microcontroller produces address
signals, control signals and data signals which are transmitted to
a master configurable logic array. Also shown are N slave CLAs.
As shown in Figure 8A, the control bits to control each of the
configurable logic elements in each slave configurable logic array
are transmitted on the data leads from the microcontroller to the
master configurable logic array. From the master configurable
~ logic array, this data is transmitted in series to each one of N
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22 70128-89
configurable logic arrays where N is a selected integer. The
control bits for controlling the configuration of each
configurable logic element in each of the configurable logic
arrays are ~ransmitted in series through slave configurable logic
array l, slave configurable loyic array 2 through to the Nth
configurable array. The data is stored in serial shift registers
as described above in conjunction with Figure 5O When the proper
bits are located in the proper storage cells in each shift
register, the hold signal shown in Figure 6C is raised to a high
level thereby locking each data bit into the proper location in
the corresponding shift register thus con-figuring each
configurable logic element in each configurable logic array. The
data clock signals are applied on a separate lead to each
configurable logic array, as shown to clock in the control data.
The address arrow pointing to CLA (master) in Figure 8A
merely indicates that the microprocessor has the ability to select
a particular master configurable logic array for receipt of data
from the microprocessor. In Figure 8B the master configurable
logic array is capable of going into the nonvolatile memory with
addresses to select particular data to be retrieved from the
memory to be used to configure each of the slave configurable
logic arrays. In Figure 8A the microprocessor produces address
signals which will go to off chip memory or to other circuitry
tnot shown).
In Figure 8B the structure is similar to that shown in
Figure 8A except that a nonvolatile memory such as a ROM, EPROM,
~ or E2PROM is used as the source for the configuration control bits
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to be transmitted into each of the configurable loyic arrays. The
structure of Figure 8B is unique in -that when power is turned on
or when a reset signal is applied to the master CLA, the master
CLA initiates the transfer of the information for controlling or
configuring the Configurable Logic Array from the non-volatile
memory to the master CLA and to -~he slave CLAs 1 to N. In this
sense, the structure of Figure 8B is self configuring in response
to power on or a reset signal.
A single board microcomputer using a Configurable Logic
Array of this invention is shown in Figure 11. Configurable Logic
Array 110 performs the chip decode functions, the latching
functions and the various special logic that is necessary to
implement a single board microcomputer. The CLA has an output
lead ("DONE") which is low from the time the power is turned on
until the single board microcomputer is fully functional.
The first event that occurs when power is turned on is
that Configurable Logic Array 110 forces the Z8002 CPU 111 into
the reset state. Reset forces the outputs of the CPU to be tri-
stated (i.e., to go to high impedance level) which makes it
possible for the Configurable Logic Array to use the control lines
from the CPU 111 while it is being configured. The Configurable
Logic Array 110 through a set of address lines (LAl - LA12)
addresses the EPROMS 113 which are also used for the bootstrap of
the Z8002 CPU 111. In addition, the EPROMS 113 have available in
them configuration information for the CLA 110. The CLA 110 has
signals which, during the self-loading time, are fixed so that
particular bi-directional buffers 112 can be set in the correct
24 70128-89
direction for loading data from the EPROMS 113 to the Configurable
Logic Array 110. Configurable Logic Array 110 then sequentialLy
addresses locations in the EPROMS 113 which are read into the
Configurable Logic ~rray 110 to configure the CLA 110. When array
110 is totally configured it then takes on its new functions and
unlatches the DONE output which releases the reset line to the CPU
111. CPU 111 is then in control of the entire system. The decode
used herein decodes the addresses from the CPU to create chip
enables and chip selects for the various RAMS and EPROMS in the
system and for the I/O devices as well.
The bi-directional selectable buffer 112 shown in Figure
11 is illustrated in more detail in Figures 10A and 10B. Figure
10A shows the bi-directional buffer as comprising an inverter 101
connected into a CMOS inverter comprising p-channel transistor 103
and n-channel transistor 104, the output lead of which is ga-ted by
pass transistor 108. In the other direction, inverter 102 feeds
an input signal onto the gates of p-channel pass transistor 105
connected in series with n-channel transistor 106. The output
from the node between the p- and n-channel transistors is
~0 controlled by pass transistor 107. The pass transistors 107 and
108 are activated by the Q, Q signals from the storage element
which can comprise a standard flip-flop. Thus, the buffer passes
a signal in one direction or the other on leads 109a or 109b,
depending upon whether or not pass transistor 107 or pass
transistor 108 is turned on.
Figure 10B illustrates schematically the circuit of
~ Figure 10A. In Figure 10B, the series connected p-channel and n-
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channel transistors 103 and 104 have been represented by inverter
103' and series connected p-channel pass transistor 105 and n-
channel pass transistor 106 have been represented by inverter
105'. Of course, in operation, the two circuits are identical.
With reference to Figures 4A and 4s directional
amplifiers (shown by an X in a box) are used to amplify signals
which have been attenuated by a number of pass transistors. This
speeds up considerably the operation of the circuit~ The delay of
a signal increases approximately in proportion to the square of
the number of pass transistors through which a signal must pass.
The amplifier brings the signal voltage back to its normal level.
In view of the above description, it will be obvious to those
skilled in the art that a configurable logic element in a
Configurable Logic Array is capable of being reconfigured even
after the Configurable Logic Array has been installed in a
circuit. Indeed, this is one of the key advantages of the
Configurable Logic Array of this invention. Thus, a Configurable
Logic Array can be reconfigured to provide a new logical function
as part of its normal operation in the system of which it is a
~0 part.
Another advantage of this invention is that the I/O pads
can be used as either input or output pads and can be controlled
by any internal signal using pass transistors.
While one embodiment of this invention has been
described, other embodiments of this invention will be obvious in
view of the above disclosure.
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