Note: Descriptions are shown in the official language in which they were submitted.
~2go~66
TITLE OF THE INV~NTION
MET~OD AND APPARATUS FOR DATA TRhNSF~R
~ACKGROUND OF THE INV~NTION
The present invention reiate~ a methDd and an
apparatus for data trans~er.
~n information processing apparatus so far
propo~ed, for exa~ple, a video imcge proceSBing system .-
(such as that disclosed iD Treati8eq of In3titute of -
Electronics and Communic~tion EngiDeers of Japar 85/4
! Vol. J6~-D No. 4 and Japanese Patent Laid-oPen No. ~8-
215813) is provided with a plurality of proce~sors, and
the microprograms as the content~ of the ~icroprogram
memories therein are adapted to be exchanged when 3cope
of processi~g i~ enlarged. In such a case, the
~icroprogram~ are supplied from a progra~ supplying
portion which in general is for~ed of a host computer to
each of the processors, and it i8 adapted, for example,
uch that ~icroprograms are exchanged on regue t of a
user effected by hi~ turniDg OD ~ ~witch.
When a plurality of ~hort programs are to be
sequentially executed by a processor9 for exa~ple, it is
a geDersl practice that the programs are ~ent one by one
to the proces~or each ti~e one progra~ has been
lZ91~
executed.
If there are a plurality of dsta proce~sors
and different programs are to be tran~ferrsd to the
plurality of proce~sor~, it i~ gen~rally practiced that
the processor to which a program is to be transferred i~
selectsd for each program to be transferred.
When such a transfer sy~tem wa~ ~dopted that a
plurality of ~hort progra~s were to be ~equentially 6ent
to a processor for execution, the transfers had to be
repeated the same number of times as the number of the
programs there were and a large portion of the
processing time was taken for the transferring, and so,
there was such a defect that the processing speed as a
whole was reduced considerably.
And, when the sy~tem was such that a plurality
of different programs were to be transferred to a
plurality of processors and the processors were to be
~elected for each program to be transferred thereto, it
was recessary to provide an arrangement for ~election
control of the proce~or~, ~nd ~o, there Wa5 such a
defect that the circuit became rather complex and large
in scale to meet such transferriDg requirement.
OBJ~CT OF THE INVENTION
A primary object of the present invention is
the provision of a data transfer Ppparatus cap~ble of ~D
effective dQta transfer.
BRIEF DESCRIPTION OF TH~ DRAWINGS
Fig. 1 i~ a conceptual drawing showing the
whole of an image proce~sing apparatus to which the data
transfer app&ratu of tbe preclent invention is a~plie~;
Fig. 2 i~ a block diagra~ ~howing 8~ exa~ple ..
of the main portion of the i~age processiDg apparatus of
Fig- l;
Fig. 3.is a circuit diagram showi~g an example
of structure of a portion of Fig. 2;
Fig. 4 is a flow chart of ~ode control;
Figs. 5 and 6 are block diagrams showing
examples of the ~ain portion of the i~age proce~sing
apparatus of Fig. l;
Fig. 7 i8 a blook diagram ~howiDg another
exRmple of the main portion of the image proce~ g
apparatus of Fig. l;
Fig. 8 i~ a timing chart showing operatioDS of
the arrangemeDk of Fig. 7;
Fig. 9 is ~ flow chart ahowing a iagno~i~
~ircuit a~ indioat~d in Fig. 6;
Fig. 10 is a circuit diagram ~howing another
example of the main portion of the image proces~ing
apparatuR of Fig. l;
Fig. 11 i6 8 drawing indicating coDtents of a
~emory shown in Fig. 10;
Fig~. 12 Rnd 13 cre block diagrams showiDg
other exa~ples of the main pot ion o~ the image
proces~ing apparatus of ~ig. 1;
Fig. 14 is a drQWiDg 8hoWiDg QD example of a
program to be transferred by the arraDgement of Fig. 13;
and
Figs. 16 and 16 are block diagra3s ~howing
other examples of the main portion of the image
processing apparatus of Fig. 1.
D~TAILED DESCRIPTION OF TH~ PR8~RRED ~MBODIMENTS
An embodiment of the present invention applied
to ~ video image proces3ing ~ystem will be described in
the following with reference to the accompanyi~g
drawings .
The example of ~ video i~age proce~sing
app~ratu~ as shown in Fig. 1 i8 provided for achieving
high-speed data proce~sing, and the Bame comprises an
input/output portion 1 (hereinafter to be cnlled an
0~:)66~
IOC), a ~emory portion 2 (hereinafter to be called a
VIM) consisti~g of aD input i~age ~e~ory 2A ~hereina~ter
to be called a VIMIN) and an output imPge memory 2B
(hereiDafter to be called a VIMOUT), a data proce~ing
portion 3 coDsisting of a po3itioD 3tationary processor
~yste~ 3A (hereinafter to be called a PIP) for chiefly
calculating picture element ~alue~ a~d a po~ition
variart prvce~sor sy~tem 3B (hereinafter to be calied a
PVP) ~or controlling data ~low~ such a~ coDtrolling of
addres~e~ and for adjusting proce~se~ to coincide in
timi~g, aDd a proces~or 4 (hereiDafter to be called a
TC) a~ a total controller ~or cootrolling execution and
stoppiDg of processes ahd exchange of programs. The TC
4 i~ provided with a host computer 5 (hereinafter to be
called an HC) for controlling the eDtire video image
processing apparatu.~.
The IOC 1 nakes A/D coDversion of video
signals coming from a video camera or YTR, for example,
to provide digitRl image data and writes the ~ame in the
VIMIN 2A, and also, reads out proces~ed i~age data from
the VIMOUT 2~ and make~ D/A conversion of the same to
restore analog video ~ignals, 80 that they ~ay, for
exa~ple, be recorded in a VTR 7 or 3upplied to a ~onitor
receiver 8 for erabli~g ~onitori~g of the video image to
~2~31V~i~
be made.
In the pre~ent case, the ~ignal~ en~bled to be
input and ~utput are the video 9ignal3 of the NTSC
8y8tem or the R-G-B sy~tem, and either of these y~tems
i~ ~pecified by the TC 4. ADd, a picture ele~ent i~
provided, for exa~ple, by B-bit d~ta.
¦ The writing and reading i~ge dsta in and out
o~ the VIM 2 i8 performed iD o~e lump of the i~age dats,
~a~ely, in block~ of a field or a frame. Therefore,
each of the VIMIN 2A and the VIMOUT 2B is ~ade up of a
plurality ~heets of ~emories, each having capscity for
the i~age dat~ of a ~ield or a fra~e of, for example, 12
sheets of 768 x 512 byte~ of ~rame memories. In the
ca~e of the pre3ent example, the use of these 12 sheets
of ~rame memories is not fixed but adapted to be
~lexibly allotted to either of the VIMIN ZA and the
VIMOUT 2B according to the purpo~e of the processiDg or
the picture image as the object of the processing. And,
the ~emory is adapted such that two sheets are used ag
one ~et, namely, when one sheet is eDabled to be
written, the other ~heet is enabled to be read, whereby
it i^~ ~ade possible that the processin from outside the
VIM 2 by the IOC 1 and the processing within the VIM 2
by the PIP 3A and the PVP 3B are performed iD parallel.
~g~
I~ the present case, the control ~ode sigDal
determiniDg whether the plurality sheets of ~ra~e
~emories Df VIM 2 should come under the control of the
IOC 1 or under the control of the PVP 3B is issuad from
the IOC 1 and ~upplied to the VIM 2.
~ he data proces~ing portion 3 comprises a
processor, reads image data stored in the YIMIN 2A
according to it3 program, proce~ses the data iarious
w8y3, and writes the processed data in VIMOUT ZB.
The data processing portion 3 i8 made up of
separated sy.~tems o~ the PIP 3A and the PVP 3B, and by
virtue of ~uch ~eparated arrangement, the processing
time to be coDsumed in the data processiDg portion iq
determined only by whichever i3 longer of the processing
times taksn by both the systems, while it was determined
by the sum of the proceqsing times iD the prior art data
proce3sing portion. Therefore, in the caqe of the
present example, such high-spesd proce~sing is
achievable as the processing of video data can be
performed on a real time basis.
The processor of the data proces~ing portion 3
is made up of one sheet or a plural sheets of proceqsors
aDd the microprograms as the contents of their
microprogram memories are adapted to be exchanged when
~0~6~
the scope of the processing i5 enlarged.
The program exchange i3 csrried out in this
way: the microprograms are ~upplied from the HC 5 to the
TC 4 in advance and ~tored? for example, in a RAM
provided therein, and theresfter, when, for example, the
user has ~ade a request for exchanging 30me programs (by
turning a switch on), the TC 4 ~upplic9 the programs to
each of the processors.
. , . , :, ,,
The PIP 3A ~nd the PVP 3B are basically of the
~ame architecture being ~n independent proces~or
. comprising a control UDit, arithmetic unit, memory u~it,
and input/output port. Ea~h thereof i9 arranged in a
multiprocessor structure made up of a plurality of unit
proc~ssors and it i9 adapted such that high-~peed
processing is achieved chiefly by adoption of a parallel
processiDg 3y~tem.
The PIP 3A comprise , for example, 60 sheets
of PIP processors and several qheets of subprocessor~
and processes image data coming from the VIM 2 or
gererates i~age data within the PIP 3A itself.
The PVP 3~ comprise~, for example, 30 ~heets
or ~o of processors and controls flowR of i~age data
inward of the VIM Z such 8S allotment of the picture
element data to the PIP 3A or collectioo.
~2~ 6~
Namely, the PVP 3B generate3 addre~ data and
co~trol signal~ ~or the VIM 2 and ~upplie~ these to the
VIM Z, and also, generates input/output control sigDals
~nd other control ~igDal~ ~or the PIP 3A and supplies
these to the PIP 3A.
The image data proce~si~g i8 not always
co~ducted in such a manner that the data fro~ a ~heet of
~rame of the VIMIN 2A are proce~sed and the proce~sed
data are written iD the VIMOUT 2B, but so~etimes such
data coming fro~ a plural ~heets of frame me~orie~ and
extending over a plural ~heet~ of frames are proc~ssed.
The ~umber of digits for ~rithmetic processing
in the PIP 3A and PVP 3B is 16-bit as a 3tandard and
such a proc~ssiDg speed is achievable in the arithmetic
processing of i~age data that will process i~age dsta of
oDe frame within one fra~e, namely, that will enable
real-time processiDg. As a ~atter of course, there are
also ~uch processes thst require longer processing ti~e
thaD ODe ~ra~e.
I~ the present c~3e, the ima~e data processi~g
by the PIP 3A Pnd PYP 3B is per~ormed in synchronism
with the fra~e. Therefore, a process start ti~ing
signal PS iD synchroni~ with the frame is supplied from
IOC 1 to the PYP 3B. The signal PS is ordinarily at a
~2~ 6~
high level and it is brought to a low level at the
proce~siDg ~tart timiDg. OD the other hand, a sigDal OK
indicatiDg that a proce~ has been fini~hed is supplied
from the PVP 3B to the IOC 1. This ignal OK is output
from a processor at the core of the PVP 3B, the
proces~or performing timing control o~ the proce~sors of
the processing system in the proce cor~ of the PVP 38,
~hen a proce~s has been ~inlshed. The process st~rt
timing signal PS i~ generated in the IOC 1 bRsed on a
fr~me start signal indicating the first line of each
~rame and the process end Qignal OK.
When the processing i perfor~ed on a real
ti~e ba~is, ~ince the signal OK is always obtained at
the end of each frame, the signal PS becomes the ~ame
signal as the frame start signal FL.
~ n the other hand, when the processing time is
longer th~n one frame, the signal PS does not concur
with the frame period but is obtained at the start of a
frame after a signal OR has been output.
And, when it is detected by the processor at
the core of the PVP 3B dependent o~ a progra~ that the
process start timing signal PS frGm the IOC l has been
brought to the low level, this proce~or ~tarts to run,
and output~, according to the program, timing ~ignals to
129~6~
other proce~Ror~ (inclu3i~e of the PIP 3A), 8upplic8
sddres~es to the VIM ~, reads the i~age data from the
VIM 2 and allowq the s,ame to be proce~sed in the PIP 3A
And, the same; when the processing h~s been finished,
outputs the signal 0~ and ~tops, waiting for isquance of
the ~ext process ~tart timing signal PS.
In this ca~e, only the i~age signal portion,
excluding the synchroniziDg rign~l or hurst signal, lS
taken Q~ the object o~ proce3siDg a~d the dat~ read out
from the VIM 2 dose not iDclude the synchronizing 3ignal
and burst signal. Therefore, the IOC 1 is provided with
a ROM generating the ~ynchroDi~ing 3ign81, burst sigDal,
and the vertical blanking signal, and in thç case of the
NTSC signal, the data from the YI~OUT 2B (after being
rearranged, if nece-,~ary) are tranqferred to the D/A
converter together with such ~ynchronizing ~ignal, burst
signal, and vertical blanking ~ignal.
Also in the c~se of the three primary color
signal, an outer synchronizing ignal becomes necessary.
Tki~ sigDal is generated also in the IOC 1 aDd supplied
to the monitor and other~.
In the above parallel proce~siDg sy~tem by the
u~e of ~ultiprocessors, the ~C 4 ~akec synthetic control
according to the below mentioned three ~odes, and
11
~9~
thereby, execution of processes, atopping, and program
transfer (exchaDge) are carried out consistently, ~nd
also, the tran.~fer and execution are effectively
conducted by using a 810W clock and a fast clock Ht the
time3 o~ the program tranRfer and the program execution,
respectively.
Fig. 2 is 8 dr~wing showiDg coDDection8
betweeD the co~trol unit of one of the plurality of
proces80rs which constitute the PIP 3A or YVP 3B and the
TC 4 and the structure i9 co~mon to all of the
processors of which programs are exchanged.
That i8, the portioo in the drawing other than
the TC 4 show~ an example of the structure of the
control unit of the processor. A microprogram
eoDtroller 10 gererate~ addresses of microprogram
memorie~ 14 for~ed of RAMs.
The ~icroprogr~m memory ll provides an
i~struction bit, for exa~ple, of 4-bit for selecting one
fro~ a plurality of iDstruction in the ~icroprogram
controller 10 snd the sa~e is ~upplied to the
instruction terminal I of the co~troller 10 through a
register 15.
ID the pre~ent case, the controller 10 has 16
kinds o~ in3truction~.
~9~
A selector 16 is aupplied with a plural piece~
of desired one-bit in~ormstion and one of which i~
elected according to information read out from the
~icroprogram ~emory 12. The one-bit information from
the selector 16 is ~upplied to the terminal CC o~ the
~icroprogra~ controller 10 ~ u co~ditio~ code~ which i~
combiDed with the lDstructioD bit sDd serves as
information for enabling next addres~ to be decided on
the ona advanced with o~e increment, or o~ the addreRs
supplied ~t the direct input terminal D, or on another
address.
The microprogram ~emory 13 provides, for
example, information about the addreqs of the
destination of a "~0 TO state~ent", the ~umber of timeq
of repetition of a DO loop, or the like, and the sa~e is
latched by a register 17a.
The ~icroprogram ~e~ory 14 provides
informetion about the microin~tructions and the ~ame iq
supplied to the arith~etic unit of thi~ proceq~or
through a register 18.
There is al30 provided a predetermiDed code
generator Z5 for outputting a predeter~ined code which
has been properly e~tabli hed by the desigDer aDd the
predetermined code from thi~ predeter~ined code
13
~x~oo~;~
generator 25 is supplied through a register 26 to the
arithmetic unit by way of the bus common with the
microin~truction from the ~icroprogram memory 14.
The microprogram controller 10 i8 adapted to
enable one of three eDable signals, PL, VECT, snd MAP,
scccrding to the irstructioD bit. ~ence, one of the
registers 17a to 17c i8 eDabled according to the
iDStrUCtion bit and the addre~s which has been latched
by thst register becomes the direct input. The sigDal
PL i8 enabled by ~o~t o~ the in tructioDs, while the
sigDal~ VECT and MAP are enabled only by ~pecial
instruction~. And that, ir a ~tate o~ that instruction
bit, whether the direct input is choseD or ~ot is
dependent on the condition code from the selector 16.
.The microprogram controller 10 is 90 arranged
. that, when the 4-bit iDstruction bit ~rom the regi~ter
1~ is (0000) , which represents an lnstruction ~JUMP
ZERO~ , the address zero a.~ the start address i9 always
output from the microprogram controller 10 regardles~ o~
tbe co~dition code.
The TC 4 includes a R~M 41 in which the
programs to be ~upplied to the ~icroprogram ~e~ories 11
- 14 are stored a~d an address generator 42 for the
same.
14
~2~
There is al~o provided a mode sig~sl generator
43 for generating 2-bit ~ode signal~ MA aDd MB to
effectuat~ three modea -- execution mode, re~et (stop)
mode, and program exchange mode --, a~ well a3 a write
signal generatsr 44 for geDerating a program write
signal for the ~icroprogram memories 11 - 14 in the
program excha~ge mode.
The ~ode signal generator 43 i3 formed, for
exa~ple, as shown in Fig. 3.
. That is, the switches SWA and SWB are ~witches
i to be changed by the user, one terminal A being applied
with a positive D.C. ~oltage a~d the other terminsl B
. being grounded. And, a signal a obtained at the switch
SWA is supplied to one iDpUt terminal of the OR gate 45.
And, a signal b obtained at the switch SWB is, on one
hand, led out as the mode signal MB aDd, OD the other
hand, supplied to the other input termiDal of the OR
gate 45. ~nd, the mode signal MA is led out ~rom the OR
gate 45.
ID this case, the modes are eistablished as
~hown below fro~ the 2-bit mode signals MA and MB:
~z~0~6~
Tuble 1
MA = O MB = O program transfer mode
__
MA = 1 MB ~ O reset (stop) mode
. MA = 1 mb - 1 eXeCUtiOD mode
That i8, when the switch SWB iR turned to the
~ide of the ter~inal A, the ~ode is ~et to the execut1on
~ode regardless o~ the state of the switch ~WA, when the
switch SWA is tur~ed to the ~id~ of the terminal A ~nd
the ~witch SWB i9 turned to the side of the ter~inal B,
the mode i8 set to the reset mode, ~nd when the switch
SWB is turned to the side of the terminal B and the
switoh SWA i9 also turned to the side of the terminal B,
the mode is set to the program exchange mode.
As apparent from the above ~entioned T~ble 1,
execution of the progra~ i9 stopped when the ~ignal MB
is turned to "O" and the program becomes executabl~ when
the ~ignal i3 turned to "1" , and 30 the mode signal MB
iR uDderstood to mean a reC~et (stop) signal.
When the sigDal MA i8 turned to "O", exchange
of program beco~es possible. Therefore, the mode sigDal
is understood to mean a change ~ignal.
By these two ~ode signals MA Qnd MB, each~of
18
lZ9(~(:366
the ~odes are effccted in the following manner.
That i~, the selector 20 ~elects the addres~
for the microprogram 3e~0ries 11 - 14 from the address
from the microprogram controller 10 aDd the addre~s from
the TC 4. As the ~elect ~ignal therefor, the ~ignal Mh
i8 ~pplied and the addrecs from She microprogra~
CoDtrOller 10 i9 ~elPcted when the ~ignal MA i~ "1", aDd
the address from the TC 4 i8 selected when the slgnal MA
ig "O".
A g~te circuit 21 gates a write 8ignal WR
according to the ~ignal MA as the gate signal. Na~ely,
the gate is open when the gate signal MA i5 ~0~ and the
signal WR i3 3upplied to each of the write enable
terminals WE of the microprogram memories 11 - 14.
The microprogram memories 11 - 14 are brought
to a write enabled state when ~0" i8 ~upplied to their
write enable terminals WE.
Further, the ~ignal MB i8 supplied to the
reset terminal o~ the regi~ter 15, snd when the ~a~e is
~0", the register 1~ i8 reset.
And, The TC 4 i~ provided with a clock
generator 46 of a ~ast clock C~F at 7.16 MHz (two times
as high a~ the color ~ubcarrier freque~cy.of NTSC color
~igDal) a~ well as a clock-generator 47 of a 810w clock
~2~ )6~i
CKS at 2 MHz.
The fast clock C~F used at the time of program
execution is supplied to the microprogram controller 10
and the registers 1~ and 18, and further to the clock
termiDals of the registers lia snd 17b.
And, the clock C~F i~ ~1 o ~upplied to the
clock ter~inal of a regi~ter 19 through a bu~fer 22.
The slow clock CBS used at the time of program
transfer i~ supplied as the clock to a lo~d control unit
48 within tbe TC 4 as well as tD the addre~3 generator
42 and other~, and the ~ame i8 al~o 3upplied to the
clock termiDal of the register 19 via a buffer 23.
The mode sigDal MA i8 supplied as it i3 to the
output enable terminal of the buffer 23 and al80
supplied through an inverter 24 to the output enable
terminal o~ the buffer 22, whereby9 as also discuRsed
later, the output of the buffer 22 i9 made effecti~e at
the ti~e of execution of a program and the fa3t clock
CXF is ~upplied to the register 19, while the output of
the buffer 23 is made ef~ective ut the ti~e of traDsger
of a progra~ and the ~low elock C~S i8 3upplied to the
regi~ter 19.
The load control unit 48 ~ithin the TC 4
supervi~e~ the 3tate~ of the mode ~i~nals MA and M~ and
18
lX~0~)66
control~ the proces~iDg in the TC 4 accordirg to each
~ode.
In the progrsm execution mode, the mode ~ignal
MA is "1", and o, the 3elector 20 provide3 the
ddres~e~ changin~ with the fast clock C~F from the
~icroprogrsm controller 10 and the~e addresses ure
aupplied to ~ach of the microprogram memsrie~ 14
t~rough the regist~r 19 at the timing delsyed by one
clock. At this time, ~iDCe the ~ode signal MA is "ln,
the bu~er 22 i9 e~fective a~d the clock of the register
19 is the fast clock CXF.
And, ~irce the signal MA i~ "1", the output of
the OR gate 21 i9 kept on at the "1" level and the
~emories 11 - 14 do not become write enabled.
Further, ~ince the mode ~ignal MB ia "1/', the
register 16 i~ not re~et, and so, th~ data read out from
the microprogram memory 11 i9 delayed by one clock of
the clock CKF iD this register 15 aDd supplied to the
in~truction terminal o~ the ~icroprogram controller lQ
whereby the progra~ is executed.
At this ti~e, ~ince the ~ode 3ignal MA is "1",
the regi~ter 18 to which the ~i~nal MA i~ supplied
through an inverter 27 i9 rend~red output enabled, while
the register Z6 is disabled, and ~o, the
19
lZ~O~
~icroinstruction read out fro~ the micropro~raD ~emory
14 is delayed by one clock of the clsck CXF in the
regi~ter 18 and ~upplied to the arithmetic unit.
ID the pre~ent executioD mode, ~hile the
program i~ executed with the fast clock CXF, there ~re
provided pipeline registers, ~amely, the register 19
between the ~icroprogra~ controller 10 and the
~icroprogram memories 11 - 14, as well as th~ regi3ter~
15 and 17a and- a register (not ~hown) at the input of
the ~elector 16 between their respective output ~ides of
the microprogram memorie~ 11, 13, and 12 and the
~icroprogram controller 10. ~nd thereby, the c10ck
cycle can be ~horte~ed.
Thst is, in the image proce~sing spp~ratus of
the pre~eDt example, a parallel proces~ing system by the
u~e of ~ultiprocessors i3 primarily employed, but a
pipeline processing system is Rlso e~ployed in ~ome
portion 83 mentioned above to ~chieve higher speed
processing.
In the program traDsfer mode, the ~ode ~ignal
MB i~ NO~ ~ aDd AO, th~ r~ ter 16 i~ re~et s~d ~0000)
i3 BUppli~d to the iDstruction ter~in~l of the
~icroprogram co~troller 10. BeDce, the ~icroprogra~
coDtroller 10 output~ the ~ero addrea~ continuou~ly aDd
,.- I
~ O
~LZ9~06~
is ~topped. That is, the program address~s for all the
processing sy~tems proces~ors, the PIP 3A and PVP 3B,
are ~0" and they are in the program stopped state.
Since the mode signal MA i3 also "0", the
selector 20 i8 brought to the coDditioD to select the
addre~s ~rom the addres~ generator 42 oP the TC 4. And,
since the output of the buffer 22 i~ made invalid and
that of the buffer 23 i9 ~ade valid, the clock of the
regiRter 19 becomes the 310W clock CKS.
Namely, in this program traDsfer mode, all the
microprogram ~emorie~ of all the processor~ are
completely co~trolled by the TC 4, and hence, the clock
become~ the slow clock CKS.
Since the mode signal MA i9 "0", the register
26 is rendered enabled and the register 18 is rendered
disabled, and so, the predetermined code from the
predetermined code generator 25 becomes to be supplied
to the arithmetic UDit.
ID the pre~ent case, it i~ al~o practicable to
arrange such that the signal MA i6 3upplied to the
output enable terminal OE of the ~icroprogra~ controller
10 and the output bu~fer of the microprogram controller
10 i~ thereby tur~sd of~.
In this program trarsfer mode, sddresses are
supplied from the addre3s generator 42 to the RAM 41
under instruction from the load coDtrol unit 48 in
accordaoce with the program for program tran~fer of the
TC 4, a~d the program data to be ~ent to the
microprogram memories 11 - 14 are read out from the RAM
41 at the rate of the clock C~S. At-the same time, the
write sag~al WR from the write signal generator 44
become~ ~-on,. Qnd since the mode ~lgnal MA iB ~0~ the
output of the OR gate 21 ~130 beco~es "O", and
therefore, the ~icroprogram memorie~ 14 are brought
to a write enabled ~tate.
Thus~ according to the addresses from the
addre~s gener~tor 42, the program data from the RAM 41
are sequentially written iD the microprogram memories 11
- 14 and the program transfer i9 carried out.
In the prese~t example, the program tra~sfer
i9 made to each, at a time, of the plurality of
proce~sors,
That i8, the TC 4 i8 provided with a ROM 49 in
which a proces~or select sig~al i9 stored. At the time
o~ program transfer, the proce~or ~elect 9ignal i9 read
out from the ROM 49 under instruction from the load
~ontrol unit 480 The proce~sor select signal i decoded
in a decoder 50, whereby only select ~ignal SEL for the
~Z~0~66
~elected processor becomes "O" aDd others become "1".
Thi~ select ~ignal SE i~ ~upplied to the OR g~te 21, and
only the microprogra~ memories 11 - 14 of the processor
in which the select ~ignal SEL is "O" are rerdsred write
enabled a~d the program is rewritten thereiD.
When rewritirg in the microprogram ~emories of
ODe processor is fi~ished, the ROM 49 delivers the
proces~or s21ect signal of the DeXt proce~or, whereby
the select signal SEL to that processors becomes ~0" and
the program traDsfer to this proces~or is carried out iD
the ~a~e way as described above. If the programs of all
of the proce~Rors have to be exchanged, the above
procedure i8 repeated the same number of time~ as the
aumber of the processors.
Now, it is possible to arraDge such that
specific data other than the processor select signals
are stored at a specific address in the ROM 49, aDd in
the ca3e where the program i8 Dot to be tran~ferred to
all of the processors but to be tra~sferred to a few of
them, the ~pecific data Bt the specific address are read
out under instruction from the load contral unit 48 to
be given when the tra~sfer to the few proce~sor~ have
beeD finished, namely, when the program transfer to the
sequentially designsted processors covering all of them
~ z9~66
to ~hich the program had to be transferred ha~ been
finished. And, thi~ output from the ROM 49 ~ay be
supplied to a detector circuit ~2 for detecting the
specific data. And thus, it can be arranged 3uch that,
when the specific dsta are read out from the ~OM 49, the
ame i8 detected by the detector circuit 52, and the
detection si~nal is supplied to the load control u~it 48
to ~top the program load.
~ the specific data, ~uch data of the
proce3sor select signal of which all bits are "1" ~ay be
used, in which c~se, the ~peci~ic detector circuit 52
~ay be formed of an AND gate.
It ~ay also be practicable to put signals
other than those to be essentially sent to each of the
processors, such as program content~, addre~s thereof,
aDd di~ferent p~rameter~ for each of the processors, in
the ~pecific data and mske use of such specific data.
Then, if the programs to be Bent to each of
the proce~sors are more thar o~e, or the progra~s to be
~ent to each of the procsssors are more than one and
di~erent from each other, the~e programs together may
be considered to be one program and written in each
proce~sor. And, desigDatioD of the program to be
exeeuted in the next place by each processor ~ay be
24
12~)()6~
giYen by providing each proce~or with the relevant
execution ~tsrt.addre~.
The execution start addres~es are ~upplied
from the RAM 51 to the regi~ter 17c of each prsce~sor.
And, as the latch signal for this register 17c, the
~bove ~enti~ned ~elect signal SEL i8 supplied thereto,
and at the ti~ing the Relect ~ignal SEL i5 turned from
"O" to "1", the then appearing execution tart addrePs
is latched.
The register 17c iB e~abled by aD enable
~ignal MAP fro~ the ~icroprogram controller 10, and
thereby, the latched data are supplied to the direct
irput terminsl D. When the program i~ started iu the
previously di~cussed execution ~ode, it i~ adapted ~uch
that the addre3s from the register 17c is taken in by
the microprogram controller 10, and therefrom, the
addre~s from the ~icroprogram coDtroller 10 is
geDersted.
ID the de~cribed ~anner9 the program and th~
execution start addres~es thereo~ are ~ent to each
proce880r i~ ~equence.
Incidentally, the executioD ~tart addres~es
for sach processor in the RAM 51 are previou~ly ~upplied
thereto from the host computer ~.
129(~
In this program traDsfer mode, as al80
described before, the micro~rogram controller 10 keeps
on outputting the zero addre~s and is in a stopped
state.
Now, it is not known what ~icroi~struction i~
stored in the register 18. HoweYer, since the register
18 iB di~abled as described before, the microin~truction
is not supplied to the Qrith~et c unit but a
predeter3ined code from the predetermiDed code generator
25 i9 suppliad through the register 26 to the arithmetic
unit as a microiDstructioD.
I~ the present ca~e, the predetermined code is
what is freely decided by the hardware design~r in
advance. If it i8 ~ade to be an opportune code at the
time of the program transfer such as, for example, to
forbid writing in the RAM in the processiDg arithmetic
unit, the contents in the RAM will never be destructed
during the program transfer.
If, as the predetermined code, such an
instructioD is prepared as to allow the iritial value of
the sum-of-products calculating circuit or accumulating
circuit to become "0", the~ it will become pos~ible,
when the program transfer is fiQished and the next
progra~ is to be executed, to i~mediately ~tart the
26
~2~0C)6~
execution without taking the ~tep of initializing the
au~-of-product~ or accumulQting calculation.
In the reset (stop) ~ode, the mode sigDals MA
= 1 and MB = 0, ~nd 80, the address from the
microprogram controller 10 i~ selected by the selector
20 o-f each proce~sor, and the clock C~F is ~elected a~
the clock of the register 19. 8ut, 3ince the regi~ter
15 i3 pUt iD the re~et ~tate by the signal MB, the zero
addre38 i9 continuou~ly output from the ~icroprogram
coDtroller 10 and all the proce~sor~ are brought into a
program execution ~topped state.
Si~ce the ~ignal MA is ~ ny write sigDal
becoming "0" i~ not given to the ~icroprogram memories
14.
And, iD this reset mode, the start addres~ of
the specific program desired to be executed in the next
place out o$ the plurality of programs which are
previously written in the ~icroprogram ~emory of each of
the proces30rs is respecified.
That i~ the ~me w~y ~.~ in the program
tran~fer ~ode, whil~ the processor select ~ignals are
output in ~equence ~rom the ROM 49, the execution start
addresses are ~equentially output from the RAM ~0 for
each of the proce~sorsS and the execution start
lX900~;~
addre~ses are latched in 3equeDce by the sigDal SEL in
the regi~ter 17c of each processor.
Therefore, when entering the execution mode in
the next place, execution in each proce~or will be
started with the program for which the execution start
addre~ hQs been respecified. Thu~, diffçrent progra~
ca~ be executed by each of the processor~ without new
programs tran~ferred there*o.
The above de~cribed three modes are controlled
by the program of the proces30r in the TC 4.
~ ig. 4 is a flow chart showiDg the relative
procedure in the TC 4.
That i5, at first, the state of the reset
sign~l MB is detected in the step (101). If the 9ignal
MB = 1, when the signal MA = 1 Q9 apparent from Fig. 3,
the mode i9 judged to be the progra~ execution ~ode and
the TC 4 continues to take the ~tep (101).
If the sign~l MB become~ MB = 0, the program
proceeds from the step (101) to the ~tep (102), wherein
the ~tate of the signal MA i8 detected.
I~ the ~ignal M~ = 1, the mode i~ the re~et
~ode, and, as described previou~ly, the ~icroprogram
controller~ 10 of ~11 of the processors coDtinuously
output the zero addr@s~ ~nd the program execution i8
28
1~90(~6
stopped. The program then proceed~ to the 3tep (lD3),
whereir the start addresR is giVeD to each of the
processorq in sequence, and returns to the 3tep
(101).
ID the step (102), if the signal MA = O, siDce
the ~ignal MB = l the ~ode beco~e~ the program exchange
mode. The progra~ proceed~ to the otep (104), wherein O
i8 loaded in the ROM 49 o~ the TC 4 whereby the ~irst
prOCe930r i8 specified, s~d in the step (105), the
program is tranRferred to that proce~sor. I~ the next
step (106), the addres~ in the ROM 49 is advance by oDe
increment. In the next step (107), it i~ judged whether
the program has been trsDsferred to all the processorq,
or to all of the proces~ors to which the program had to
be tra~erred, aDd i~ it has not been finished, the
program returns to the ~tep (105) and the program is
tran~erred to the next proc~ssor iD the step (lD6).
The steps (lD5) to (107) ~re repeated $he same
number of times as the total number of the relative
processors .
If it i3 judged that the transfer of the
program ha~ been fini~hed in the step (107), the program
proceeds to the qtep (10~), wherein the ~t~te of the
Aignal MA is detected. If the 3ign~1 MA = O, thi~ s$ep
~Z~
(109) is repeatedly tsken and the program exchange mode
i8 held on. If the signQl MA is turned to MA = 1, then
the program i5 released from the program exchange ~ode
and return~ to the step (101).
In the case where the program tran~fer i~ to
; be decided to have been ~inished by dstection of ~ome
~pecific data, the address in the ROM 49 i8, although
advanced by one iDcrement in an ordinary case, changed
to the addres~ at whioh the apecific data are w~itten in
the step (106), ~nd the same is read out.
In the next ~tep (107), judgment whether or
not the read output from the ROM 49 iB the specific data
iQ made in the specific data detector circuit 6Z.
If the read output from the ROM 49 is the
specific data, program transfer stopping is effected by
the load control UDit 48 in the ~tep ~108).
If the read output ~r~m the ROM 49 is Dot the
speci~ic data, the program retur~ to the ~tep (105) and
the program traD~er i~ made for the DeXt processDr.
~ When the program tran~er is ~topped in the
~tep (108), the 3tate of the signal MA is detected in
the ~ext step (109).
~ lthough the above descript iQD has been ~ade
taking a nultiprocesaor ~ystem as an example, it ia a
~:90066
~atter of course that the present in~eDtion i3 al80
applicable to mode controlling of one proces~or.
In the case of the above example, a plurality
of processors coD~tituting a parallel processing
apparatus are adapted to be totally controlled i~ three
~ode~ by the TC 4, and ~o, each of the procesAors can be
controlled without having conflicts with each other.
That i8, if a plurality of proce3~0r~ are contro1led
individuslly, some ~ay execute a program, some may
exchaDge a program, and 80~e may be re~et, and thu~,
there i~ possibility of erroDeous execution to be made.
According to the sbove described example, such a fault
can be prevented.
I~ the case of the present example, it i~
po~sible to shift from the program exchange mode or the
executioD mode to the re~et ~ode i~stantly by adoption
of the switches SWB and SWA. Therefore, in the middle
of program execution or in the stage where progra~
exchange has not bee~ ~inished for all the processors,
the mode can be changed to the re3et mode as required.
According to the present inventio~l process
executioD - stopping and program tra~sfer caD be clearly
and coD~istently coDtrolled by virtue of the total
controlling of the data processors iD the three ~odes.
According to the pre~ent invention, ~he
program execution and trQnsfer can be performed
effectively without reducing the execution speed or
without increasing the hardware by virtue of the proper
u~e of dif~erent clocks according to whether the mode i8
the program transfer mode or the program execution mode.
, AccordiDg to the present i~vention, at the
I time of program trans~er, supply o~ any i~struction from, the mieroprogram memory to the arithmetic u~it i8
i ~orbidden, and i~tead, a predetermined code ~o~t
opportune at the time of program transfer is ~upplied to
the arithmetic unit as an instruction. And therefore,
~uch insecurity that it i9 ~ot known what in~truction is
now supplied to the arithmetic UDit can be removed, and,
for example, the contents of the memory in the
arithmetic unit can be protscted.
According to the pre~ent invention, since it
is arrsnged therein such that, when a signal to be sent
to a processor to which a program is to be transferred
bec~mes a specific ooe, it i~ detected and the program
transfer is thereby ~topped, the program tran~er can be
easily ~inished st any time point. Thus, the total
loading time for the program trans~er can be reduced.
- Fig. ~ shows a concrete structure of the PIP
32
~96~0~
~ystem 3A. Although the PIP ~ystem 3A ha~, in reality,
a large number (60 3ets, ~or example) o~ proceqsor3
arranged in parsl1el, only two sets of them are qhown iD
the drawin~, In thi~ drawing, digital data from the YIM
syste~ 2 are ~upplied to input regi~ters 31-1 to 31-n
~herein~ter to be called the FRA) provided ~or each of
the processors 3-1 to 3-n, and the~e registerg are
controlIed by the PVP ~yste~ 3B iD accordaDce with the
~ddress read out of the VIM sy~tem 2 and stored with a
predetermi~ed amount of data ~ecessary ~or each
processor.
The data written i~ the~e register~ 31-1 to
3l-n are supplied to arith~etic unitc 32-1, 33-l to 3Z-
n, 33-n9 respectively. Each of the arithmetic units i5
provided with an adder/subtractor, multiplier,
coefficient ~emory, data memory, etc. and make~ linear
and non-linear data coDversion cal-culations according to
coDtrol signal from the control UDit9 34-l to 34-
~Results o~ the calculation6 are obtained at the
srithmetic units 33-l to 33-D, a~d further, the
arithmetic UDit 33-1 to 33-n are controlled by the PVP
~ystem 3B according to write addresses of the VIM sy~tem
Z, whereby the results o~ the calculations are written
i~ ~ece~sary portions in the VIM system 2.
33
1~90066
ID the present case, the control sigDals from
the control unit~ 34-1 to 34-n are for~ed accordiDg to
the micropr~gram written in the microprogram memories
(MPM) denoted by 11 - 14 iD Fig. 2 (denoted
represeDtatively by 3~-1 to 3~-n iD Fig. 6). The
microprogram is written from outside through program
change controls 36-1 to 36-~.
~ owever, in the above ca~e, ~f the above
mentioned ~icroprogra~ i~ formed by the exi~tiDg host
computer (~C) 5 etc., the traDs~er rate from the HC 5 to
each MPM 3~-1 to 3~-~ is limited by the capacity of the
line, and therefore, it is only possible to transfer the
progra~ at the rate, for example, of 600 ~byte~/sec or
~o, and therefore, it take~ much time for the rewriting
in all of the MPMs 3~-1 to 3~-n. Due to the fact that
proceQ~ing i~ the PIP syRtem 3A etc. become3 i~possible
during that time, many inconveniences have been
experienced. ADd, ~ince the transfer cannot be
performed until the processing in the PIP system 3A etc.
has been finished, the ~C side has had to wait until it
is fini3hed, and therefore, there has been such a
dif~iculty that the efficiency of usage of the HC is
considerably lowered.
In Fig. 6, khe microprogram transferred in 16-
34
9~o~i~
bit structure from the host computer ~C) ~ is suppliedto the previously de~cribed 64 Kbytes memory 41 in the
TC 4. Further, a write control signal from the HC 5 i3
supplied to the coDtrol unit 4B, the signal from the
control unit 48 i8 ~upplied to the memory 41 and the
~emory addre~# generator circuit 42a in the address
generator circuit 42, and the genersted addr~ss is
supplied to the ~emory 41, whereby the ~icroprogram is
WritteD iD the ~e~ory 41 at an arbitrary ~ddres3. At
this time, a ~tatus sigDal showi~g that the ~emory 41 i8
write enabled i~ ~upplied from the control unit ~8 to
the ~C 5.
Further, a stQtus signal showing that the
~icroprogram memories are rewrite enabled iq supplied
from the PIP system 3A to the control unit 48. ADd
thereby, the signal from the control unit 48 i~ supplied
to the memory addres~ ge~erator circuit 42a and the MPM
address generator circuit 4Zb. And, while the addresses
to sequentially read the memory 41 are generated by the
circuit 42a, a chip select signal for WritiDg the read
microprogram iD the ~pecified MPM and addre ~2S for
writi~g the program in ~equence iD the MPM are generated
by the circuit 42b.
Thus,-while the ~icroprogram read out from the
66
~e~ory 41 iD, for ex~ple, 16-bit structure i~ 3upplied
to the PIP sy~tem 3A through a ~ultiplexer (MUX) 63, the
addre3~es etc. from the circuit 42b-are Rupplied to the
PIP ~yste~ 3A. ~urther, the write control ~ignal ~rom
the control unit 48 i3 ~upplied to the PIP ay~te~ 3A.
~ ccordiDg to the nbove de~cribed arrangemeDt,
the ~e~ory 41 and the PIP 8y8te~ 3A can be coDnected
through a dedicated line and, further, tran3fer in
~ultibit structure, ~uch as 16-bit ~tructure, can be
practiced. Therefore, assuming thst the transfer rate
i~ 8 Mbytes/sec, for exa~ple, the tran~er c~n be made
at the rate 16 ti~e~ as high as that in the ca~e of the
convention~l direct transfer from the ~C, ~00
~bytes/sec, for example,
Further, in the ca~e where the same
~icroprogra~ is to be transferred to the plurality oi~
proce~or~ in the PIP ~yste~ 3A, the program can. be se~t
to them simulta~eously by Brranging 8 plurality of chip
select ~ignals to be geDerated by the MPM address
generstor eircuit 42b. And thereby, the program can be
tr~nsferred, for exa~ple, within the verticsl blankiDg
period of the video Yignal, and thus, real-ti~e ~ignal
processlDg csn be per~or~ed without producing aDy
disturbaDce in the im~ge.
36
1~900~
The described tran~fer process has been made
po~,sible by ~tructuriDg the control unit 48 etc. with a
so-called ~icroprocessor.
IDcideDtally, the above described program
tran~fer can be applied not only to the PIP ~ystem 3A as
de~cribed above but also to the IOC system 1, PYP system
3B, etc.
~ ven in ~,uch ca~es, however, ths tranRferring
time between the HC 5.and the ~e~ory i9 the ame as
be~ore and the ~C 5 aDd the line are occupied during the
tran~ferring ti~e, and so, there i~ the possibility of a
lowering of efficiency in the usage o~ the ~C ~ a~d the
liD~!.
In the above described example, when the
program is to be transferred to in~ide the TC 4, it has
been ~rra~ged such that the program only i~ ~ent thereto
and the.address in the RAM 41 i9 produced in~ide the TC
4. In the next example, the addres~ in the RAM 41 is
also transferred from the HC 5 together with the
program.
Th~t is, in Fig. 7, the data trans~erred, ~or
example, in 16-bit structure from the host computer (HC)
~ are ~upplied to regi~ter~ 9a, 9b, 9c, aDd 9d, each
being of 16-bit structure. And, a control ~ignal ~rom
the ~C 5 i~ ~upplied to the control unit 48a ~nd the
produced write signal is supplied to the registers 9a -
9d.
_ ~ere, a~ the data from the ~C ~, as showD in
Fig. 8A, for example, data identification informatioD
(ID) is tr~nsferred at the timi~g in ~ynchroni~m with
the control ~ignQl (the start ~ignal: Fig. BB)
iDdicating the start of the traD~fer from the ~C 5, sDd
thereafter, data (D) are transferred at intervals of a
predetermined clock (Fig. 8C). Then, the above
identification informatioD (ID) from the control unit
48a i3 written i~ the register 9a by means, for example,
of the write signal output to the register 9a at the
timing of the above mentioned start signal, and this
information i3 detected in the control unit 48a. Then,
the data D are written in sequence in the regi~ter 9b by
means of the write ~ignal output to the register 9b at
~ the timing of the çlock. The data (D) are supplied
i through a regi~ter 9e to the IOC sy~tem 2, etc. In the
~ data (D), there are provided, for example, the kind of
processing cystem (NTSC, RGB, etc.) and information for
~ode ~etting (real time, waiting for processing to be
finished, still picture~ etc.).
When the above mentioned microprogram is to be
3~
0~i6
rewritten, informatio~ (L) showing the length o~ the
program to be transferred followiDg the ideDtification
information (ID) i5 trao3ferred from the HC 5, in
successioD to the identificatioD infor~atioD (ID) as
~hown iD Fig. 8 (D). Thereafter, later di~cu~sed
addresses (A) of the ~emory 41 and data forming the
program (PD) are transferred alternately. MeaDwhile,
from the control unit 48a, as ~hown in Fig. 8E, a ~rite
~ign~ again output to the register 9a at the ti~ing
of the next clock to that for the ~tart ~igDal -- in
re~ponse thereto the ideDtification information (ID)
indicatiDg the program ha3 been written in the regi~ter
9a --, and thereby, the information (L) about the length
is written in the regi~ter 9Q. Then, ag showD in Figs.
8F and 8G, write ~igaals are alternately output to the
registers 9c and 9d every other clock, whereby the
address A i8 written in the re~ister 9c and the program
data PD i~ written in the register 9d, separately.
The addres~ A from the register 9c i9 ~upplied
through a multiplexer (MUX) ~3a to the memory 41 aDd the
progr~m d~ta (PD) ~rom the register 9d are written at
that address. Meanwhile, a write control ~ignal is
~upplied ~ro~ the control unit 4B to the me~ory ~1.
And, the writi~g i9 made to the extent specified by the
39
12~ i6
length infor~ctisn (L).
~ he~ the ~riting i8 fiDi~hed, the MUX 53a is
~witched by a ~ignal from th~ control uni~ 48a. And, a
signal ~rom a 3econd control u~it 48 i5 supplaed to the
me~ory addre~s generator circuit ~Za and MPM address
geDerator circuit 42b. While addresses to read in
3equencs the ~emory 41 are output from the circuit 42a,
chip ~elect signals *or writi~g the read ~icroprogra~s
in a speci~ic MPM and ~ddre~es ~or ~equentially writing
the ~ame in the ~PM are output from the circuit 42b.
Thus, the microprograms read from the ~e~ory
41 are ~upplied through the ~ultiplexer (MU~) 53 to the
PIP system 3A, PVP system 3B, etc. and the addre~ses
etc. from the circuit 42b are qupplied to the PIP sy~tem
3A aDd otherc.
In the above de~cribed apparatus, since it i5
adapted ~uch that the program data (PD) aDd the addreYs
data (A) are separated and writing iD the me~ory 41 is
~ade according to thc~e ~ddresse~, it 13 ~ade POS3 1b1e
to chaDge a portion of the progra~ while keeping all the
re~t of the program as it is. That i3, in a filtering
process, a ~ew filtering can be perfor~ed ~ith tbe
progra~ for arithmetic proces3i~g not changed but only
the coef~icient data therein changed. ID cUch a case,
1~9~06~;
with the above deRcribed apparatu~, first, the entire
arithmetic program i~ transferred, a~d then, accordiDg
to the need, only the coefficient data are exchanged,
and thereby, various processes can be performed.
With the above described apparatu~, it take~
I twice as lorg time a~ that in the coDventional case for
tran~erring the ~irst program, but the d~ta for
changi~g the coefficient data etc. iD the-filtering
'I , . . . ...................... . . ...... .. . ...
I proce~s only account3 ~or lX or le~s of the entire data.
I~ Therefore, suppo~i~g 5 time5 0~ exchaDges are made, if
the entire portion i8 expressed by 1, the time taken by
the pre~e~t apparatus becomes
1 x 2 ~ 0.01 x 2 x 6 = 2.1,
which is le58 than half that in the conventional case,
i.e.,
1 x ~ = 6.0 .
Further, with the above described apparatus,
it become~ un~ece~sary to provide a circuit for
generating the write ~ddre~s within the apparatus.
Accortin~ to the pre~ent invention, siDce
addre3ses are attached to the data forming the
microprogram tran3ferred from the host computer and the
writing is made according to these addre3se3, it i8
po~sible to rewrite any portio~ of the program once
41
- ;
.
30~6~
written in the memory by specifying the addre~s for that
portion. Thu~, in such 8 case to rewrite a ~ortioo of a
long program, it is only required to transfer oDly that
portion, and therefore, it has become po~sible to finish
the rewritiDg in a very short time.
It ometimes occur~ that the result of the
proce. siDg performed according to a tran~ferred
~icroprogram i3 found incorrect. Various causes are
¦ considered gor occurre~ce of ~uch aD incorrect result,
such a~ malfunction of the processor etc. within the
proce~sing apparatus, failure in the line between the HC
and the processing apparatus, and others. And, there
have been such problems that the cau~e i~ difficult to
i determine.
Therefore, 3uch a practice has been taken up
so far as t-o inspect the proces~ors with a probe one by
one, after having each of the proce3~0rs provided with a
te~tiDg termi~al, or to inspect the line with the
operation of the ~C halted. ~owever, in tha case of the
appcratus including a lar~e number of processors as
described above, it has t~ken ~ch time aDd labor only
for checking tho~e proces~or~ one by one. And, since
the li~e has been iDspected first for the rea~on that
such a failure in general i~ attributable to the line,
42
~X~0~Ç;6
the ~C ha~ had to be frequeDtly halted ard it ha3 been a
problem th~t the efficiency of the usage of the ~C i8
thereby lowered.
Therefo~e, the TC 4 i9 provided, as ~hown in
Fi~. 6, with a ROM 54 with a program for diagDosis
written thereiD. In the program for the diagnostic
purpose, ~uch a 3ystem i3 adopted that arithmetic
operations are made with all the functions of the
. .. . .... ..
processor employed ther~iD and the results are compared
with previously calculsted right a~ wers. Further, by
properly arranging a program, it iq enabled to detect,
from each rcgister iDcorporated iD the processor,
whether the processor i9 in good order or not.
~ hile the address from the memory address
generator circuit 42a is supplied to the ROM 54 and the
program from the ROM 64 is supplied to the N~X ~3, ~
control signal from the control unit 48 i9 ~upplied to
the MUX 63, aDd thereby, the program ~rom the RAM 41 is
supplied to the PIP syste~ 3A. Further, the addres~es
etc. fro~ the circuit 42b are ~upplied to the PIP system
3A. And, the write control ~ignal ~rom the control unit
48 is supplied tG the PIP 3y~tem 3A.
Therefore, iD the above described arrangement,
by ~upplying a command ~ignal from outside to the
43
~LZ~0~i6
control unit 48 when incorrectnes~ or such a thin~ i8
~ound iD the result of the prOCesSiDg~ the progrsm
written in the ROM 54 i~ supplied to the PIP ~ystem 3A
a~d the processor-~ etc. of the PIP syste~ 3A sre
diagnosed. If there i3 found oothing wrong iD the
result of the diagnosis, it i~ under~tood that no
proces~or is out of order and the line between the HC
a~d the apparatus is then in3pected, but if ~omething i8
found to be wrong in the result of.the diagnosis, the - -
processor i6 subjected to ~ore closer exa~inQtion.
Shown in Fig. 9 is a flow chart for the
diagnosis, wherein, first, in the step (201), the MUX ~3
1S switched to the side of the ~OM 54. In the next step
(202), the address generator circuits 42a and 42b are
driven and the ROM 54 is read, whereby the program for
diQgnosis is transferred to the PIP ~ystem 3A. Further,
in the atep (203), ~rith~etic oper~tions are ~ade by the
processor according to the program for diagnosis.
In the step (204), deci~io~ (diagnosis) by the
result of the operatious i8 ~ade, and if it is found to
be inoorrect (NG) 9 a closer exami~atioD i8 made in the
step (Z05) sDd the result thereof is di~played iD the
Btep (206). When the operatioD re~ult is correct (OK)
in the 3tep (204), the line between the ~C ~nd the
44
1290~6
apparatus i~ inspected in the step (207) and the result
thereof i8 displayed in the ~tep (208).
When the di3play i8 made iD the st~ps (206) or
(208), the MUX 53 i8 re~et tc the ~ide of the memory 41
and the diagno~tic operation i~ ended.
According to the above de~cribed arrangemeDt,
in which the diagnostic operation i~ performed in the
de~cribed manner, the ROM 54 with the program for-
disg~osis written therein i~ incorporated in the
transferring arrangement, and 80, the transfer of the
program i~ not af~ected by the line ~hether it i8 good
or not and correct diagnosis i8 en~ured, and that, by
the re~ult of the diagnosi~, it can be decided whether
¦ the line is good or not.
Further, ~ince the program for diagnosis can
be transferred in a ~horter time than in the ca~e where
the program is tran~ferred from the HC, the diagDosis
can be fiDished quickly ond~ further, without disturbing
the opersticn of the HC, whereby the reliability on the
overall ~pparHtus can be improved.
The proce~ g to diagDo~e the proce~or with
o built-in ROM ha3 been made possible by formiDg the
control unit 48 etc. of so-called ~icroproce~orQ.
~; The diagnosi~ o~ the proces or i~ applicable
~2900~i
not only to the PIP sy~tem 3A a~ de~cribed above but
al~o to the IOC system 1, PVP 8y8tem 3B, etc.
And, the above described ROM 54 can be loaded
with programs etc. which are repeatedly used for
ordi~ary proces~ing in addition to the progrsm for
diagnosis.
. According to the present invention, aince the
ROM with the 2rogram for diagnosi3 written therein is
provided in the apparatu~ aD~ it i8 adapted 6uch that -
this program is tr~n~ferred, in the event of need~ to
each microprogram ~emory 80 that the processor may be
diag~osed, it is.enabled to easily diagnose the
. processor being out of order, while keeping the
operation of the host computer unaffected during the
. diagnosis.
In the TC 4 of the embodiment in Fig. ~, it is
. required to provide ~any memory units and peripheral
circuits such as the RAM 41 for ~tori~g the ~rogram, the
address generator circuit 42 for generatiDg the
addresse~ thereinr the ROM 49 for ~toring the select
aignal o~ each of the processors ~ and the RAM ~1 ~or
storing the execution start addres6es for each
processor, but it i3 po~sible to e~body these in ~ large
~cale ~emory. .
: 46
;
- 1~9(3(~
That i3, the load coDtrol UDit 48 and a memory
419 can be srranged a~ ~hown in Fig. 10, and the ~emory
41~ i8 stored at its ~equential addre~3e3 with the
execution start addre~ses and ~uch parameters, proces~or
~elect signal~, Addres~es, program content~, and write
~ignals.
The~e ~ignal5 to be supplied to the proce8~0r~
, are ~equentially read out from the me~ory ~1' according
I to the addres3e~ ~ro~ ~he load control.unit 48, whereby
the processors selected by the proce~sor sel~ct signal~
are supplied with the parameters and the ~icroprogram
~e~ories thereof .are written in with the program
contents.
With Fig. 11 takeD as an example, when the
addres~es 0 to 7 of the memory 41' are read out, the
prsgram contents are written in the microprogram memory
of the proces~or No. 10 at i.ts addresse3 0 to 7, and
when, in succession thereto, the addresses 8 to 23 of
the memory 41' ~re read out, the program contents are
written in the microprogram ~emory of the proces~or No.
2~ at its addrs~ es 0 to 15.
Now, out of the 3ignal~ to be sent to th~
proces~ors ~hown in Fig. 11, only one kiDd of the
proces~or 3elect ~ig~al aDd the p~rameter are ~ivsa to
47
~Z~6~
one proces~or, i.e., the ~cme sigDals are repeatedly
output for each of the addres6es from the memory 41' to
0~8 PrOCeS80r.
On the other hand, the program contents and
their memory addresse~ as well as the write sign~ls mu~t
be output differently for each ~ddres~, not ~or each
processor .
ID the case where the~e data are read out from
...
one memory 41' and transferred to each of the proce~ors
a~ ~hown iD Fig. 10, it is required as i~dicsted iD Fig.
ll that not oDly the data nece~ary ~or each addre~ of
the memory 41' but also the ~ata uDchanged ~or each
proceC~or must be stored at the addre~es in ~quence,
ard therefore, the efficiency o~ usage of the Demory is
lowered very much,
Then, in another embodiDent of the present
invention as shown in Fig. 12, the TC 4 i~ provided with
the load control u~it 48 end a ~emory for ~toring the
signals to be supplied to the ~icroprogram memories ll -
14. As the ~e~ory, in the pre~nt ca~e, a proce~or-
wise memory 41'a a~d aa addre~-wi~e ~emory 41'b are
provided.
In the proce3sor-wi~e ~emory 41'a ~re stored
ODe ki~d o~ data for each of the proce~or~, i.e., the
4 8 !-
lX~06~
parameter and proce~sor select ~ignal a3 well a~ n
program identification signal IDP.
In the address-wise memory 41'b are ~tored the
program content~ aDd address data thereof QS well as the
write aigDals WR written ~or each of the addre3~es.
As the program identi~ication signal IDP in
the preseDt ex~mple, the address in the front of the
~ddress-wise memory 41' for the program to be sent to
each o~ the proces~ors i~ used. For exa~ple, according
to the example of Fig. 11, when the processor 10 i8
selected, the addres~ in the front, "0", for its
program, and when t~e processor No. 2~ is ~elected, the
address in the front, "8", for its program are u3ed as
the program idertificatio~ ~ignals IDP, re~pectively.
`Reference numeral 42' deDotes a counter for
generating tpe address for the addre~s-wise memory 41'b.
The program identificatioD ~ignal IDP from the memory
41'a is preset by a preset signal in ynchroDism with
~election of each processor fro~ the load control unit
48, ard it~ value i5 ~equentially cDuDted up ~rom the
preQet value.
Reference ~umeral 44' i9 a comparator circuit
for detecting aD ~nd of the progra~-traDsfer to OD2
proces~or through co~parison of a ~roce980r-wi8e prograD
49
~Z9~
end address ~ND output from the proce~sor-wiae ~emory
41'a and the address for the ~emory 41'b from the
counter 42'. The comparison output i8 supplied to the
load control u~it 48.
In the present progra~ tran~fer mode, the
program transfer to each proces~or i8 carried out
accordiDg to the program ~ransfer program ~rom the TC 4
and under in~truction ~rom the load control unit 48 iD
the ~ollowiDg way.
~ . . . . . . . .
ThQt i9, in the first place, the first address
is 3upplied ~rom the load control unit 48 to the
processor-wise memory 41'a. Then, the select signal for
~electing the proce3sor to which the trsnsfer is to be
made at first, the parameter for the processor, the
front addre~s as the identification signal IDP of the
program for the processor, and the end addre~s END for
the program are read out from the ~emory 41'a.
The proce~sor select signal read out from the
~emory 41'a is decoded by the tecoder ~0, ~hereby only
the select signal SEL for the processor to be selected
becomes NOl~ and others become "1". The ~elect ~ignal
S~L is ~upplied to the OR gate 21. Since the ~ode
signal MA i~ "O" at this time, this OR gate functions 80
that the microprogram ~emories 11 - 14 of the processor
~0
for which the select signal S~L i8 1-0" iB rendered write
ensbled wheD the write signal WR beco~e~ "O", and then,
the program becomes rewritable.
On the other hand, the ~ro~t addre~s as the
identification sig~al IDP i~ prese~ in the counter 42'
by the pre~et 8;gnal fro~ the load control unit 4~, and
the counter 42' i8 al~owed to count up from the pre~et
front addres~ value.
A~ previously described, ~heD the selected
processor i~ the procee~or NO. 10 a~ shown ir Fig. 11,
the ~ame is allowed to count up from the address 0.
~nd, according to the address fro~ the counter 42'9 the
program contents, the address therefor, and the write
sinal WR becoming "O" are sequentially read out from
the address-wise me~ory 41'b.
Therefors, the microprogram me~ories 11 - 14
of the selected processor is written in with the program
content~ in sequence at the addre~es ~ent from the
address-wise ~emory 41'b.
~ nd, when there appears the eDd address ~ND
(for example, the addre~ No. 7 ~or the proces~or No.
10) of the progra~ being transferred to the same
proce~sor, agreement between the output address value
fro~ the COUDter 42' and the eDd vslue ~ND ia detected
~1
-
129~06~
in the comparator circuit 44', and responding to the
dstection signal, the lo~d control unit 48 ~uppli83 next
addres~ which has been advanced by one increment to the
processor-wise ~emory 41'a.
Then, the proces~or ~elect ~ignal for
selectiDg the Dext proce~sor i~ generated by the
processor-wi~e ~smory 41'a, the ~elect signal S~L
6electing the processor becomes "0", and thus, in like
~anner, the program exchange i carried out for this
processor. I~ the progra~s of ~11 of the processors sre
to be exchanged, like operations are repeated the same
number of times as that of the processors.
And, in the present example~ if a plurality of
programs are to be sent to each of the proceasors or a
plurality of programs which are different fro~ each
other are to be sent thereto, these plurality of
programs are consideret to be one program and this
progrsm iB arranged to be written in each processor.
And, it i9 further arranged such that the programs
required by each processor c~n be 6pecified by providing
each proces~or with an eXeCUtiQn stQrt addre3~ a8 the
para~eter.
The executioD ~tart addres~e~ are obtai~ed
irom the memory 41' Q a~ described above and ~upplied to
52
~29~ 6
the register 17c of esch processor. And, the sigDal S2L
is ~upplied to the register 17c a~ the latch sign~1
therefor, and at tbe timing this select ~ignal S~L turn~
from "0" to '!1", the then appearing execution addres~ i~
latched.
Incidentally, the contents o~ the memorie
41' 8 and 41'h have been given from tbe h3st co~puter
in advance.
ID the re~et ~ode., the tart addres~ o~ th~
program desired to be executed in the next place out of
the plurality of programs previously written in the
microprogram memory of each proceRsor are re~pecified.
That i~, the sam~ as in the ca~e of the program
transfer, the proces~or select sigDal~ and the execution
st~rt addresses are sequentially output from the memory
41'a for each of the proces~or~, whereby the execution
start addres~es are sequeDtially latched in the
registers 17c of each o~ the processor~ by the signal
SEL.
Si~ce the ~ode signal MA = 1 at thi~ time, the
output of the OR gate 21 doe3 not beco~e ~", and
there~ore the progra~ i8 not rewritten.
The flow chart of the proce~sing in the TC 4
i~ simil~r to that of Fig. 4, but in the ~tep ~104), the
53
9~i6
address 0 i~ output from the load control unit 48 of the
TC 4 thereby to specify the first processor, and in the
step (105), the progra~ is tranQferred to the proces~or.
I~ the next step (106), the addre~3 ~or the me~ory 41'a
is advanced by one increme~t. In the next step (1073,
it is judged whether the programs have been traDsferred
to all of the processors, or have been transferred to
the procescors to which the programs had to be
transferred, and if it is judged ~ot to have been
fiDished~ the proce~s flow returns to the step (105) and
the program transfer to the next proce sor is per~ormed
in the step (106).
According to the prese~t invention, the
app~rstus is provided ~ith two memories, i.e., the
memory ~toring processor-wise information and the ~emory
~toring address-wise information of the progrsm to be
transferred, and thereby, the program supplying portion
haq been arranged in a hierarchical ~tructure.
Therefore, as compared with the case where information
for each proce~sor iB stored at each of the addresses
~or the transferred progra~, the memory area can be
saved and effective u~sge of the memory can be achieved.
Fig. 13 i~ ~or illustrating a~ e~bodied
circuit of ~he program tr~sfer-syate~ according to the
54
9~)6~;
preseDt invention, whereiD the case where a plurality o~
program3 are trsnsferred to a plurality of proces~ors i~
iDdicated.
The pre~ent progra~ supplyiDg portion formed
of the TC 4 i~cludes a program RAM or ROM 41 storing the
plurality of programs to be traDsferred, an ~ddress RAM
or ROM 51 storing t~e execution start addres~e~ for each
of the proces ors, an address counter 42 for the program
RAM ~1, and a write signal generstor 44 formed o~ a
comparator, and supplies the programs to D 8ets 0
proce~sors 3-1, 3-2 , -- , 3-n.
ID the present csse, it i~ adapted such that
only a plurality of programs which have to be ~eDt can
be sent out of the plurality of progra~s stored in the
progr~m RAM 41.
Th~t is, the losd sontrol unit 48 i9 provided
with a ~tart v~lue ge~erator ~Ba for generating the
start address of the progrsm with lower-Dumbered
addresses of the plurality o~ progra~s to be sent out of
the plurality of the programs stored iD the program R~M
41 and ~n end value gener~tor 48b for generating the end
QddresY of the program with higher-numbered addre~ses of
the plur~lity o~ progra~3 to be ~e~t out of th~ . I
plurality of the programs stored i~ the program RAM 41.
~9~0~6
That is, in the ca~e, for e~ample, where contents of the
first to third programs are stored in the program ~M 41
~t the addresse~ from "0" to "28" as shown in Fig. 14
and the first to third programs are to be tran~erred to
the proces~ors 3-1 to 3-n, the start ~alue generator 48a
provides the data for the address value "0" and the end
value generator 48b provide~ the data for the address
value "28".
- And, the start value fro~ the start value
generator 48a i~ ~uppli~d to the addre~s COUDter 42 and
the addre~s counter 42 start3 counting from thi~ start
value. And the couDted-value output is supplied to the
program RAM 41 a~ re~d addresses and also supplied to
the ~icroprogram ~emories of each of the processors 3-1
to 3-n as write addresses ADRS. The program data DATA
read out from the RAM 41 are al~o ~upplied to the
microprogram memorie of each of the processor~ 3-1 to
3-n.
ID this case, the microprogra~ memories of
each processor is provided with virtually equal capacity
to th~t of the program RAM 41.
The addre3s data ADRS from the address counter
42 is al~o supplied to a co~parator 44 and therein
compared with the end value ~rom the end v~lue generator
66
0~6~i
48b. From the comparator 44 i~ output a write aignal
WR, which i8 held, for example, at "O" until the addresY
data ADRS sequentially ~hanging fro~ the start value
reaches the end v~lue. The write ~ignRl i8 ~upplied to
the write e~able terminal~ o~ the ~icroprogram ~emories
~f each of the pr~cessor& 3-1 to 3-n, and writiDg of the
progra~ in the memorie~ i8 ensbled while the write
erable ~ignal.is kept at "O". - .
In the ~e~cribed manner, the write si~Dal WR
is held at "O" while the Qddress dsta ADRS from the
addre~q counter ~2 cha~ges from ~O" to ~28", aod during
thi~ period of time, the first to third program~ written
in the program RAM 41 at the addre~ses "O" to ~28",
regarded os one program, are ~equentially read out from
the program RAM 41 and written in the microprogra~
memories at the addres~s according to the addre~s dat~
ADRS.
While the progra~ are transferred to e ch of
the processors 3-1 to 3-n, executior ~tart Qddre~e~ CSl
to CSr, i.e., the start addres es of the progrQms out of
the ~irst to third program~ to be execuged i~ the next
place by each of the proce~ors are supplied from the
addre~s RAM ~1 indiYidually to each thereof a~d latched
by the register~ o~ e~ch o~ the prose~sors 3-1 to 3-D.
57
1290~66
If the exsmple of Fig. 14 i~ taken up, the execution
start addres~ of the first program is "0", the execution
~tart address of tbe second program is "6", and the
execution start addre~ of the third program is "19".
In the event of the program execution to be
~tarted by e~ch proces~or after the transfer has been
fiDished, the program i8 stsrted at $he execution start
address, and thus, desired progra~s can be executed.
If the program3 to be executed in the next . .-
i place are included in the plural progra~s which have
i already been tran~ferred, the execution ~ddresses only
j will be retransferred, and thereby, different progr~s
.
are enabled to be executed by each of the processors.
By the way, it is possible to individually
transfer a plurality of progr~s, as a lump of program,
to each processor, but the trRnsfer can be finished at
one time if the programs are ~imultaneously transgerred
in the manner as illustrated in Fig. 13.
Acsording to the pre~ent invention as
described above, a plurality of programs are rearded as
one program and transferred at one time and the
execution start signals of each of the programs are
separately sent, aDd therefore the programs requiring
plur~l ti~e~ of transfer caD be traDOEferred at one ti~e
58
lZ90(1~
and the transferring time can be reduced.
And, ~ince a plurality of different program
can be transferred to a plurality of proce~sors without
requiring a ~election control arrangement, the eircuit
for the tran~fer becomes ~maller i~ ~cale.
~ owever, in the case where çach of a plurality
o~ processors are ~upplied wit~ different programs, the
Dumber of th~ program~ to be seDt in a lump will become
the ~ame a~ the total Dumber of the proce~sors and the
trs~sferring time will accordingly become loDger. Then,
in some case where there are a large ~umber of
proce~sors, the transferring time as a whole may be
reduced if arranged such that the progr~ms of the same
number as the number of the processors to which program
transfer is to be ~ade are arranged in n lump and this
lump of programs is individuaily transferred to esch of
the procesaor~ in question.
Fig. 15 shows another embodiment of the
apparatus of the pre~ent invention. Thi~ inventioD i3
characterized by the portion in the traD~ferring
proce~sor outputting ~elect signal~ to a plurality o~
processors.
The plurality o~ proces~or~ are divided in
~o~e groups iD 3uch a way, ~or example, that tho~e
59
~ 290~)~6
processors which are possible to perform the ~sme work
are put in a group. In the pre~ent caqe, they are
divided in k groups, each thereof being formed of i
processors, pamely, the first group o~ proces30r~ 3-11,
3-12, -- , 3-li, the ~econd group of processors ~-21, 3-
22, ... , 3-2i, -- , and the k-th yroup of proces~ors 3-
kl, 3-k2, -- , 3-~i.
The tran~ferring proçe~sor 4 is provided with .
decoders 55-1, 55-2, -- , 55-k for ~upplying- each of the ..
proce~sors o~ each of the group~ with a select signal.
These decoders 55-l, 55-2, .- , 55-k are, similar to the
decoder ~0 iD Fig. 2, such that only one ~elect ~ignal
therefro~ become~ "0" and all the others become "1"
according to the input bit thereto, aDd, as the input
data, the lower l-bit portion of a m-bit ~elect signal
i5 supplied. The higher (~-l)-bit portio~ of t~e m-bi~
select ~ignal i~ input to a decoder.56. This decQder 56
generates select signals Sl, S2, -- , Sk for selecting
one out of the decoders 55-1, 55-2, ..- , ~-k for each
of the groups, and each of the select sigDals Sl,
S2, -- , Sk ~re ~upplied to enable ter~inal~ EN of the
decoders 5~-1, 55-2, ... , 55-k.
In the pre ent ca~e, ~, 1, k, and i are ~o
~elected a~ to Ruffice 2~ 2 i aDd 2m-1 2 k .
129~6~
The ~elect sigDal is provided with oDe extra
bit 80 that group-wise selectioD i8 ~ade possible. The
one-bit signal GS i~ supplied to one of the iDpUt
ter~inals of each of the VR gates 57-1, 67-2, ~ , 57-k.
The other input terminal of the OR gate 57-1 i8 supplied
with the ~elect signal Sl, the oth~r input terminul of
the OR gate 67-2 is ~upplied with the ~elect ~igDal ~2,
... , and the other i~put tsrminal of the OR gate 5?-k i5
~upplied with the select signal Sk.
From each of the decoder~ 55-1, 55-2, ~
56-k, i pieces of processor ~elect signals are supplied
through each of i piece~ of ~ND gates 58-11 to 58-li,
58~21 to 58-2i, ... ; 58~kl to 68-ki, respectively, to
- each group of processors 3-11 to 3~1i, 3-21 to 3-2i,
o- , 3-kl tc 3-ki, respective~y. ~Dd, the output of the
OR gate 57-l~i~ co~only supplied to the fir~t group o~
~ND gates ~8-11 to ~8-li, the output of the OR gate 67-2
is com~only ~upplied to the second group o~ AND gates
58-21 to 58-2i, -~ , snd the output of the OR gate 67-k
i9 commonly ~upplied to the k-th group of ~ND gates 58-
kl to ~8-ki, respectively.
With ths ahove de~cribed 6tructure,
~equeDtially transferring dif~ereDt program~ to each of
the proces~Drs one by one and writiDg the programs in
. 61
-
~ .
their respective memories aa has hitherto been practiced
i8 carried out in the following m~nner.
Firstly, the signal GS is brought into the
~tste of "1". ~ence, all of the outputs of the OR gates
~7-1 to 57-k become "1", ar,d the AND gates 58-11 to ~8-
ki sre all brought into the ~tate of gating the outputs
of the decoders ~6-1 to ~5-k a~ they ~re.
U~der these coDditions, the input aelect
sigDal is ~equentially advanced with one incr~ment esch
time of the tran~fer.
In the present case, the input to the decoder
56 i5 held in an uncha~ged state until the program
trsDsfer to one processor has been finished, namely,
held in a state of selecting the decoder of one group.
That is, ~ccording to the input select signal,
only the select signal Sl first becomes "O", whereby the
decoder 5~ rendered operative as a decoder, while
the processor select signals output from all of the
others become "1" regardless of the inputs thereto.
Thus, the first group i~ selected and the
program is sequentially written through a bus iD the
memorie~ of the processors 3-11 to 3-li of the first
: group i~ accordance with the l-bit select ~i~Dal of the
decoder 56-1.
62
. ... .
3 ~9~
When i times of the program transfers to the
processors 3-11 to 3-li of the fir~t group have been
fini~hed~ the lowest bit of the higher (m~ bit input
~elect ~ignal is inverted, whereby only the ~elect
- signQl S2 of the output of the decoder 56 beco~es "O" to
render the decoder 55-2 operutive as a decoder and
output~ of all o~ other decoders 55-1, ~5-3 to 55-k
become "1". Thus, in like manner, the program is.
sequentially t~ansferred to the proce~sor~ of the secoDd
group according to the lower l-bit select sign~l.
There~fter, one of the decoders ~-1 to ~5-k
i~ likewise rendered operstive a~ ~ decoder according to
the select ~ign~l output from the decoder 56, and
progr~m transfers are sequentially ~de i times to i
pieces of proces~ors of the group of that decoder, aDd
thereby, the program trsnsfer~ to ~11 of the proce~or~
are carried out in ~equence.
Next~ at the ti~e of group-wise program
transfer, the signal GS is turned to "0". Then, the
outputs o~ the OR gate~, to which the ~elect ~igral~
being ~lOll DUt of the select sigDals Sl to Sk output from
the decoder 56 are supplied, ~eco~e "0". For example,
i~ the ~ignal Sl is "0", the output o~ the O~ ate 57-1
beco~e~ "0", whereby outputs of all of the i pieces of
~3
~.2~
AND gates 58-11 to 58-lc of its group become "0"
regardless of the select ~ignal output from the decoder
~5-1. Thus, the memories of the proces~ors 3-11 to 3-li
of the first group are rendered write enabled, ond 80,
the same program is written in the proce~sor~ 3-11 to 3-
li of the first group at o~e time of transfer.
Then, in like manDer, identical progra~ i8
simultaneously written in i pieces of proces~or~ of the
group ~elected by one of the select signals Sl to Sk
from the decoder 5~9 ~t one time of tran~fer.
Therefore, in the present ca~e, program
transfer to all o~ the ~ x i piece~ o~ processors can be
carried out by i times of transfers and the transferring
ti~e can thereby be reduced.
Incidentally, instead of traD~ferring programs
to all proces30rs in 3equence, it i~ of course pos~ible
to transfer the program to a~y processor or to any group
of proce~ors at any desired time by arranging the input
Eelect signal to become the data to elect that
processor or group.
In dividirg the proce~sors into so~e groups,
each o~ the group~ need not be for~ed of the same
~u~ber6 of proces~ors but may be iormed of ~ny nu~ber of
procesaors which will use the same program. In such a
64
case, by storing the Dumber of processor~ belonging to
each of the group~ iD ~ ~emory, the lo~ of ti~e
produced when the tranqfer i~ ~equentially made to each
group can be elimiDated.
Fig. 16 show~ another example of the apparatus
o~ the present inYention, which i8 ~n improved ex~mple
of that iD Fig. 15 and parts thereof corresponding to
the example in Fig. 16 ~re denoted by the ~me rsference
numerals. . : .
In the pre~eDt example, ~ pieces of proces~orq
are divided into a fir~t group i~cluding i pieces of
processors and a ~econd group includiDg (D - i) pieces
of proce~sors.
In the ca~e of the pre3ent exQmple, n pieces
of ~elect signals from a decoder 55 for selecting n
processors ~re supplied through AND gates 58-1 to ~8-D,
re pectively, to each of the proce~sors 3-1 to 3-n.
There i~ also provided a group Relector
circuit ~9, to which a two-bit select signal is
supplied.
And, a first group select signal GSl is
~upplied to the AND gate~ 58-1 to 58-j -- to which the
~elect signals from the decoder ~5 for gelectiDg the
proce~sors 3-1 to 3-j of the fir~t group are supplied at
~ ~9~066
o~e input terminal~ -- at the other input terminals.
~nd, the ~econd group select signals GS2 i8 supplied to
the AND gates ~-j+l to 58-n -- to which the ~elect
sin~1s from the decoder 55 for ~electing the proces~ors
3-j+l to 3-D of the second group ure supplied at oDe
iDpUt terminals -- at the other input terminals.
In the case where differeDt programs are
~equentially tr~n~fe~red to each o~ the processors one
by oDe the same as hitherto iD prQ~tice, the ~roup
eelector circuit 59 is supplied with signal3 c~using
both the 3ignals GSl and GS2 to beco~e "1". ~ence, the
AND gates ~8-1 to 58-n are brought to the state allowing
the outputs of the decoder 5~ as they are, and
thereafter, the ~equential transfers to all of the
processors are c~rried out just iD the ~ame way a~
previously described.
Next, if the ~elector circuit 59 i8 supplied
with such signQl~ that will turn oniy the signal CSl to
~0", then all of the outputs of the ~ND gate~ ~8-1 to
SB-j become "0" regardless of the output select ~ign~ls
from the decoder ~5, aDd thereby, the same program is
~imultaneously written in the proces~or~ 3-1 to 3-j of
the fir~t group at one time of transfer.
And, in the ca3e where only the signal GS2 i~
66
12~
turned to "O", the outputs of the AND gates 68-j~l to
58-n ~11 become "O" regardl2ss of the output ~slect
~ign~ls from the decoder ~5, whereby identical program
imultaneously written in the proceqRor~ 3-j+l to 3-n
of the ~econd group at one time of transfer.
If both of the 3ignal~ GSl and ~S2 are turned
to ~0", the output~ of the ~ND gate~ ~8-1 to 68-D all
become "O", in which caYe identical program can be
simultaneou~ly tran ferred to all of the proce ~or~ 3-1
to 3-~.
In the pre3ent invention, when tran~ferriD
information to a plurality of prooe~ors, infor~ation
can not only be traDsferred individually to each of the
proce~qors but also ~i~ultaneously tran~ferred, at one
time of tran~fer, to a plur~lity of processora which
will u~e the~same information, and 80, a reduction in
the transferriDg time can be achieved.
Although the case where t~e apparatus of the
preseDt invention was applied to the video 3ignal
proces3ing has been de~cribed above, it i8 a ~atter of
course that the pre~ent invention i8 applicable to
digital proces~ing of other infor~ation signal than the
video signal such ~ the audio ~ign~l becau~e a portion
o~ ~uoh ~ signal for the durQtion of a unit time can be
0~6
~tored in a memory and the signal csn be ~equentially
processed for each of uch a unit-time portion.
While the above de6cription ha~ been ~ade ~ith
a multiprocessor system takeD 8~ ~n example, the present
invention can of course be applied to the ca~e where a
~ingle proce~sor i~ ~ods controlled.
¦. Further, the above described exa~ple hss been
of the ca~e of traD~ferring microprograms, but ~s a ~
~atter of cour~e the transferable data ~r~ not li~ited
to the microprograms.
~8
