Note: Descriptions are shown in the official language in which they were submitted.
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FREQUENCY SYNTHESIZER
This invention relates to frequency synthesis and is
especially, but not exclusively, applicable to frequency
synthesizers such as are used in radio systems, for example
cellular radio systems.
Generally, such frequency synthesizers use a reference
frequency as a source and synthesize from it a desired output
frequency as a multiple (in the case of an indirect synthesizer)
or quotient (in the case of a direct synthesizer) of the
reference frequency. The ratio between the output frequency and
the reference frequency is determined by a control signal which
may be analog or digital depending upon the implementation
preferred.
In a typical direct frequency synthesizer, the input
reference frequency is much higher than the frequency to be
synthesized and is divided directly to provide an output signal
of the required frequency. A low pass filter reduces
quantization noise in this output signal. One disadvantage of
the direct frequency synthesizer is that the reference has to be
at a much higher frequency than the output, which makes it
unsuitable for applications such as cellular radio, where the
output frequency is near the limits of the fabrication
technology. Another disadvantage is that in some cases a high
resolution digital-to-analog converter is required, which
presents a substantial technical problem if the frequency
synthesizer is to be fabricated as an integrated circuit.
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In a typical indirect frequency synthesizer, the
division takes place in a feedback path. The frequency of the
input reference signal is approximately equal to that of the
divided signal. The signal which is actually divided is the
required output signal, which is thus the highest signal which
needs to be generated in the circuit. Hence, the indirect
frequency synthesizer is preferred for applications such as
cellular radio.
In both direct and indirect frequency synthesizers,
quantization produces spurious frequencies and/or phase noise
which may appear in the output signal and present a problem.
In synthesizers which employ a sine look-up table, the analog
to-digital converter generates spectral peaks at several
p red i ctab 1 a f requenc i es , the ene rgy 1 eve 1 of these spectra 1 peaks
being dependent upon the resolution of the digital-to-analog
converter. The greater the number of input bits to the digital-
to-analog converter, the greater the difference between the
spurious frequencies and/or phase noise and the output at the
fundamental frequency.
Increasing the resolution of the digital-to-analog
converter will decrease the spurious frequencies and/or phase
noise but this technique is not preferred since the concomitant
increase in complexity of the digital-to-analog converter results
in slower operating speed, increased power consumption, lower
reliability and higher implementation costs.
Anothe r approach , exemp 1 i f i ed by Canad i an patent No .
1,173,515, to which the reader is directed for reference, is to
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cancel phase error each cycle. Unfortunately, this approach
still requires a digital-to-analog converter and also involves
precise matching between the digital value of the phase error
stored in a phase register and a time delay at the output of a
voltage-control pulse delay.
Various other techniques have been employed to reduce
the quantization noise in frequency synthesizers. For example,
U.S. patent number 4,652,832, issued to Steven C. Jasper, to
which the reader is directed for reference, discloses a frequency
synthesizer in which a digital dither signal is applied to the
output of a phase accumulator before conversion into sine and
cosine data through look-up tables. Although this may give an
increase in resolution at the intermediate stage, it does not
eliminate the effects of quantization error at the digital-to
analog conversion stage.
U.S. patent number 4,410,954, issued to Charles
Wheatley III, to which the reader is directed for reference,
discloses a frequency synthesizer in which a phase accumulator
is used as a direct digital integrator, eliminating the usual
sine amplitude look-up table and the digital-to-analog converter.
A dither signal applied to either the input or the output of the
accumu 1 ator vari es the phase vectors i n smal 1 steps that are 1 ess
than the minimum phase step. This approach increases frequency
resolution and reduces noise but unfortunately is not entirely
satisfactory because the dither signal introduces random or
pseudorandom noise throughout the spectrum and hence at the
desired output frequency and its multiples. Also, its ability
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to achieve high frequency resolution through the use of advanced
sine amplitude conversion techniques is limited.
WIPO patent application number 89/06009, published
June 29, 1989, discusses direct frequency synthesizers (DDS) for
frequency hopping and multi-channel systems which comprise a
digital phase accumulator, a periodic wave function conversion
el ement i n the form of a read-on 1 y memory ( ROM ) devi ce, and a
digital-to-analog converter. The phase accumulator increments
a phase ang 1 a wh i ch i s conve rted i nto an anal og waveform by a
conversion element. The instantaneous amplitudes at given points
during the period of the sine function are computed as digital
values from the accumulated phase then transferred to the
digital-to-analog converter for conversion to an analog signal
having the same frequency as the phase angle data. The digital-
to-analog conversion introduces spurious frequencies and/or phase
noise due to quantization. These spurious frequencies and/or
phase noise are distributed throughout the frequency spectrum by
generating a series of randomly- or pseudorandomly-varying
numbers, adding one to each of the sine amplitude numbers,
truncating the addend, and applying it to the digital-to-analog
converter. The random or pseudorandom numbers are generally
scaled to a predetermined amplitude before being added to the
sine amplitude numbers. This approach is not entirely
satisfactory for cellular radio systems because an unacceptable
level of noise is still present in the vicinity of the operating
frequency unless many bits are employed in the digital-to-analog
converter, with disadvantages as discussed above.
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As the number of users in a cellular radio system
increases, a larger number of communications channels are needed
within an allotted bandwidth, so the separation between channels
must be less. This results in a need for finer frequency
resolution, so the reference or mixing frequency for each channel
must be derived more accurately and spurious frequencies and/or
phase noise must be minimized.
WIPO patent applications Nos. WO 86/05045 and WO
86/05046, published August 1986, disclose fractional-N frequency
synthesizers which use a sigma delta modulator to control the
division ratio.
According to one aspect of the present invention, there
is provided a frequency synthesizer comprising:
detector means (110) responsive to a reference signal
and a phase control signal (fa) for generating a control signal
that varies in dependence upon the phase difference between said
reference signal and said phase control signal;
means (118) responsive to said control signal far
generating an output signal (fo) whose frequency varies in
dependence upon said control signal;
means (106) for dividing said output signal (fo) to
provide said phase control signal (fd), said dividing means
having a control input and being operable to vary its division
ratio in dependence upon a ratio control signal (b{t}) applied
to said control input; and
second or higher order sigma-delta modulator means
(102) responsive to a frequency control signal (6~) and to said
phase control signal ( fd) to provide said ratio control signal
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(bit}), the sigma-delta modulator means (102) being arranged to
displace any quantization noise in said ratio control signal
(bit}) away from the frequency of said phase control signal (fd)
and multiples thereof.
Consequently, the mixing action of the detector means
heterodynes (frequency-translates) the phase control signal (fd)
and its multiples to d.c. Substantially all of the quantization
noise remaining after the heterodyning will then be at
frequencies above the cut-off point of the low pass filter means.
According to another aspect of the invention, a direct
frequency synthesizer comprises:
variable modulus divider means (106) for dividing a
signal having a reference frequency (f~) to provide an output
signal of a desired frequency (f~), the ratio of such division
being variable in dependence upon a ratio control signal (b{t}),
and;
second or higher order sigma-delta modulator means
(102) responsive to a frequency control signal (d~) and to the
output (f~) of said divider means (106) for supplying a said
ratio control signal (b{t}) in which any quantization noise is
displaced away from the frequency of said output signal and
multiples thereof.
According to a third aspect of the invention, there is
provided a frequency synthesizer comprising divider means (106)
for dividing a first signal (fo; fo' ) of a first frequency to
provide a second signal (f~;f~) of a second frequency, the ratio
of such division being variable in dependence upon a ratio
control signal (b{t}), and second or higher order sigma-delta
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modulator means (102) responsive to a control signal (s~) for
supplying said ratio control signal (b{t}), such that any
quantization noise in said ratio control signal (b{t}) is
displaced away from the second frequency and multiples thereof,
characterized in that said sigma-delta modulator means comprises
a plurality of sigma-delta modulators connected in cascade, one
of said modulators (102) being controlled by a second frequency
control signal (8~0) to provide an output {b(t)'}, the other of
said modulators ( 102' ) being controlled by the sum of said output
(b{t}') and a third frequency control signal (dal) to provide
said ratio control signal (b{t}) to said divider (106).
According to a fourth aspect of the invention, there is
provided a frequency synthesizer comprising divider means (106)
for dividing a first signal (f~; fo' ) of a first frequency to
provide a second signal (f~;fd) of a second frequency, the ratio
of such division being variable in dependence upon a ratio
control signal (b{t}), and second or higher order sigma-delta
modulator means (102) responsive to a control signal (s~) for
supplying said ratio control signal (b{t}), such that any
quantization noise in said ratio control signal (b{t}) is
displaced away from the first and second frequencies and
multiples thereof, characterized in that said divider means
comprises a first divider (312) for dividing said first signal
by either of two ratios to provide an intermediate signal (fm),
second divider means (316) for dividing said intermediate signal
(f",) by a third ratio to provide said second signal (fd) , and
control means (302, 318) clocked by the intermediate signal (f~,)
and responsive to the instantaneous state of said second divider
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means (316), a second frequency control signal (Id), and the
output from the sigma-delta modulator means (102), for
controlling the division ratio of said first divider (312) to
select one of said two ratios.
According to a fifth aspect of the invention, there is
provided a frequency synthesizer comprising divider means (106)
for dividing a first signal (fo; fo' ) of a first frequency to
provide a second signal (f~;fd) of a second frequency, the ratio
of such division being variable in dependence upon a ratio
control signal (b{t}), and second or higher order sigma-delta
modulator means (102) responsive to a control signal (d~) for
supplying said ratio control signal (b{t}), such that any
quantization noise in said ratio control signal (b{t}) is
displaced away from the second frequency and multiples thereof,
characterized in that said modulator means (102) comprises means
(208, 210) for providing two reference signals (+REF, -REF),
means (214, 216) responsive to the sum of said frequency control
signal (a~) and a said reference signal (+REF, -REF) for
providing said ratio control signal (b{t}), and means (202,
204,206) for summing either of said reference signals (+REF, -
REF) and said frequency control signal (8~) in dependence upon
said ratio control signal (b{t}).
Embodiments of the invention will now be described by
way of example only and with reference to the accompanying
drawings, in which;
Figure 1 is a block schematic diagram of a first
embodiment of the invention comprising an indirect frequency
synthesizer employing a sigma-delta modulator;
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Figure 2 is a detail diagram of a fractional-N divider
of the synthesizer showing the sigma-delta modulator in more
detail;
Figure 3 is a detail diagram showing a variable modulus
divider portion of the fractional-N divider of Figure 1 in more
detail;
Figure 4 is a block schematic diagram of a direct
frequency synthesizer embodying the invention; and
Figure 5 illustrates a modification applicable to both
the indirect synthesizer and the direct frequency synthesizer.
Figure 1 shows an indirect frequency synthesizer for
synthesizing an output signal fo, having a frequency of 89.1 MHz,
from an input reference signal f;, having a frequency of 2.2 MHz.
The synthesizer comprises a feedback loop which includes a
fractional-N divider 100 for dividing the first or output signal
fo to provide a second signal, the phase control signal fd, which
also is about 2.2 MHz., for comparison with the reference signal
f;. The fractional-N divider 100 comprises a sigma-delta
modulator 102 which provides, on line 104, a ratio control signal
b(t) which controls the ratio of a variable modulus divider 106.
The output of the variable modulus divider 106, the phase control
signal fd, is applied on line 108 to a phase detector 110 which
compares it with the input reference signal f;.
The control signal provided at the output of phase
detector 110, on line 112, is a nominally d.c. voltage which is
proportional to the phase difference between the input signal f;
and the phase control signal fd. This control signal is filtered
by means of a low pass filter 114 and applied on line 116 to
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control a voltage controlled oscillator 118 which generates the
output frequency fo on line 120.
The output of the sigma-delta modulator 102, which
controls the variable modulus divider 106 to determine the
division ratio between the output frequency fo and the phase
control signal fd, (and indirectly reference frequency f;) , is
itself determined by a control signal s~ applied to the sigma-
delta modulator 102 on line 122. The sigma-delta modulator 102
uses, as a clock, the phase control signal fd from the output of
variable modulus divider 106.
The sigma-delta modulator 102 is conveniently of the
kind described by James C. Candy in a paper entitled "Use of
Double Integration in Sigma Delta Modulation", IEEE Trans. on
Communications, Vol. COM-33, No.3, March 1985, to which the
reader is directed for reference. The characteristics of a
sigma-delta modulator are such that the quantization noise at its
output tends to be towards the high end of the spectrum and hence
away from both the DC level of the control voltage 8~ and the
frequency of phase control signal fd and its multiples. The way
in which the discrete time filtering of the quantization noise
occurs is evident from equation 3 on page 251 of the
aforementioned paper by Candy.
The sigma-delta modulator 102 acts as a discrete time
filter in that its output signal changes at discrete time
intervals rather than continuously. In effect, the sigma-delta
modulator 102 is an "all pass" filter to the substantially
constant control signal 8~p and a "high pass" filter to
quantization noise. This noise is inherent in the sigma-delta
to
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modulator 102. Where an analog sigma-delta modulator is used,
the noise will have reduced power spectral density in the
vicinity of phase control signal fd and its multiples. Where a
digital sigma-delta modulator is used, reduced spurious frequency
components in the vicinity of fo and its multiples will result
from the placement of the zeros of the high pass filter function
at d.c., the frequency of phase control signal fd, and its
multiples.
Figure 2 shows the fractional-N divider 100, comprising
the variable modulus divider 106 and a second order sigma-delta
modulator 102, the latter being shown in more detail. In a
practical embodiment of the invention, the variable modulus
divider 106 was implemented using a two modulus programmable
divider, part number SP8716, by Plessey Semiconductors Limited.
The two modulus programmable divider 106 divides the frequency
fo alternately by "40" and "41", respectively, in dependence upon
the state, 1 or 0, of the control signal 8~ received on line 104
from the sigma-delta modulator 102. The output of the two
modulus programmable divider 106 is thus the phase control signal
frequency fd which is applied via line 108 to the phase detector
110 (Figure 1).
In the sigma-delta modulator 102, the two's
complement control signal 8~ is applied to an adder 202. A
positive reference signal (+REF) or a negative reference signal
(-REF) is applied, on line 204, to a second input of the adder
202 by a selector switch 206. This selector switch 206 selects
the positive reference +REF, from source 208, or the negative
reference -REF, from source 210, in dependence upon the state of
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the ratio control signal b(t) from the sigma-delta modulator 102,
which is applied to the switch 206 on line 104.
The adder 202 combines the reference signal +REF or the
reference signal -REF with the control signal 8~ and applies the
aggregate on line 212 to an accumulator 214.
It should be noted that, for satisfactory operation,
the signal 8~ should be greater then -REF/2 and less than +REF/2.
For a 16 bit implementation, REF may, for example, be the number
8192. The frequency control signal 6~ has a constant or slowly
varying level and the reference signal applied to adder 202
alternates between two constant or slowly varying levels. The
input to accumulator 214 is a signed two's complement signal and
its output, an unsigned binary number, can go either up or down.
In a second accumulator, 216, this unsigned binary number is
added to the previously stored value, causing the value stored
in accumulator 216 to increase. The overflow output of
accumulator 216, comprising a single bit, is stored by delay
means or latch 218 until the next cycle of the clock (signal fd),
then supplied as the output of the sigma-delta modulator 102 on
line 104. (The latch 218 and accumulators 214 and 216, are all
clocked by the signal fd.)
Quantization noise is inherent within the sigma-delta
modulator 102 since its output is low resolution, i.e. one bit,
and its input is high resolution i.e. the signal 8~. As
discussed earlier, however, the noise is shifted away from d.c.,
the frequency of the phase control signal fd and its multiples,
thus ameliorating the problem of spurious frequencies and/or
phase noise. Increasing the number of bits in the sigma-delta
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modulator, or cascading the sigma-delta modulators, permits
arbitrarily fine resolution, even though the one-bit output
itself constitutes coarse resolution. Whereas a basic phase
locked loop, i.e. without the sigma-delta modulator, can only
synthesize two frequencies, vis. f; x n or f; x (n + 1) , the
sigma-delta modulator permits synthesis of substantially any
frequency between f; x ( n + 0 . 2 5 ) and f; x ( n + 0 . 7 5 ) providing
the sigma-delta modulator has enough bits. Increasing the number
of bits increases the resolution of the frequencies which can be
synthesized.
Figure 3 shows an alternative fractional-N divider
comprising a sigma-delta modulator 102 which is the same as in
Figure 1, but with a two stage variable modulus divider. As
before, the sigma-delta modulator 102 is controlled by a
frequency control signal d~. A second control signal, Id, which
comprises a sequence of single bits, is applied to a selector in
the form of 3-to-1 multiplexes 302, together with the instant
output of the sigma-delta modulator 102 on line 304 and, on line
308, the output of the modulator 102 from the preceding clock
period via a one bit delay 306.
The output of the 3-to-1 multiplexes 302, on line 310,
controls a divide-by-3 or 4 divider 312 , which divides the output
signal fo and applies the resulting signal f", on line 314 to a
divide-by-16 divider 316 which divides it to give the phase
control signal fd. The divide-by-16 divider 316 has 16 states,
typically represented by 4 bits or 8 bits depending upon how the
counter was implemented.
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The instantaneous state of divider 316 is applied to
control logic 318 which controls the multiplexes 302. The
control logic 318 and multiplexes 302, which together comprise
selection means, are clocked by the output f,~ of divider 312. In
a specific practical case, Id comprised 14 ones or zeros,
representing the integer portion of the division ratio, and two
zeros.
The control logic 318 causes the multiplexes 302 to
select one of (i) the second control signal Id; (ii) the direct
output of the sigma-delta modulator 102; and (iii) the delayed
output of the sigma-delta modulator 102. For the first 14
cycles, signal Ia controls the divide-by-3 or 4 divider 312. On
the 15'i' cycle, the divide-by-3 or 4 divider 312 is controlled by
the direct output of the sigma-delta modulator 102 and on the 16'~
cycle by the output of delay 306. As a result, the variable
modulus divider 106 can divide by any number between 49 and 63,
with Id representing the integer portion of the division ratio
and 8~ representing the fractional portion of the division ratio.
The output of divide-by-16 counter 316, the phase control signal
fd, serves as a clock for the delay 306.
Although the foregoing specific description is of an
indirect frequency synthesizer, the invention is also applicable
to direct synthesizers. Such a direct frequency synthesizer is
illustrated in Figure 4 and comprises a sigma-delta modulator 102
and a variable modulus divider 106 which may be of similar
construction to those described with reference to Figures 1, 2 and
3. A first signal fo' is applied to the input of variable
modulus divider 106, the output of which is the output signal f~,
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at the desired frequency. The frequency of the first signal fo'
is much higher than that of the output signal f~. The division
ratio is controlled, as before, by a control signal a~ applied
to the sigma-delta modulator 102.
Alternatively, the division ratio may be controlled by
changing the values +REF and -REF in the sigma-delta modulator
102. Since the division ratio is proportional to 8~/REF, the
frequency of the output signal f~, varies linearly with REF.
Consequently, changing the reference by fixed increments will
change the output frequency f~ in linear increments.
In essence, the direct frequency synthesizer
corresponds to the fractional-N divider 100 i.e. the frequency
synthesizer of Figure 1 without the phase detector 110, filter
114 and voltage controlled oscillator 118.
It should be appreciated that the fractional-N divider
described with reference to Figure 3 could be used for either the
direct synthesizer or the indirect synthesizer.
To act as a good pseudo-random number generator (PN),
an all-digital sigma-delta modulator must be capable of producing
long bit sequences. The length of the sequence is one of several
figures of merit for a PN generator and all PN generators have
a finite sequence length. However, under certain conditions the
second order all digital sigma-delta modulator may not produce
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a sequence long enough to be of practical use. This condition
may be caused by the p resence at the i nput to the s i gma-de 1 to
modulator of a static signal s~ which has many zeros in the less
significant bits of the binary representation of a~. For
example, in sigma-delta modulator 102, if 8~ were a "round"
binary number, such as 2048 which has a binary representation of
0000 1000 0000 0000, the sequence length could be as short as 4
depending on the initial state of the accumulator 214. When the
initial state of accumulator 214 also is a "round" binary number,
+/-REF the initial state and the frequency control signal b~ are
all "round", the input to the second accumulator 216 is "round"
also, so neither accumulator can cycle through many states.
A simple solution is to adapt the sigma-delta modulator
102 to ensure that either the accumulator 214 powers up with an
"odd" binary number, or the accumulator 214 powers up with a
val ue of 0 and then i nput an "odd" number on 1 i ne 122 for one
cycle. The desired frequency control signal s~ can then be
inputted in subsequent cycles as described for normal operation.
An appropriate value for this "odd" number has been found to be
17.
Alternatively, the problem of short sequences may be
overcome by modifying the sigma-delta modulator 102, namely by
providing three or more integrators with two or three feedback
paths. One of the feedback paths then uses a reference that is
not "round" while the main input reference remains "round".
In Figure 5, which illustrates a modification
applicable to both the indirect frequency synthesizer of Figure
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1 and the direct frequency synthesizer of Figure 4, two sigma-
delta modulators 102' and 102", respectively, are connected in
cascade by means of an adder 502. The output of sigma-delta
modulator 102' is applied to one input of adder 502 and the
output of the adder 502 is applied to the second sigma-delta
modulator 102". A second frequency control signal 8~0, which is
a multi-bit (16-bit) signal, is applied to the input of sigma-
delta modulator 102'. The output of sigma-delta modulator 102'
is a single bit which adder 502 adds to the second least
significant bit of a third frequency control signal 8~~. Second
frequency control signal 8~o is offset relative to third
frequency control signal s~l. Conveniently third frequency
control signal 8~1 represents a coarse adjustment to the
fractional part of the total division quotient and second
frequency control signal s~o represents a fine adjustment to the
total division quotient. In essence, the combined signals 8~1
and duo effectively correspond to a higher resolution version of
frequency control signal s~ of Figure 1. Since the input signal
to sigma-delta modulator 102" is now active, the problem of short
sequence lengths does not arise.
Various other modifications and substitutions will be
apparent to one skilled in the art. For example, the sigma-delta
modulator could be implemented in analog manner, for example as
disclosed by Candy in the aforementioned paper. The output of
the delay or latch 218 could be multi-bit and the variable
modulus divider 106 could be a multi-bit multi-fraction divider.
Another modification concerns the way in which the
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various additions are performed by adder 202 and accumulators 214
and 216, respectively. Instead of being performed
simultaneously, as described, they could be performed serially,
for example by using the intermediate clock fm or the input
signal fo in the embodiment of Figure 3.
Sigma-delta modulators are available which will produce
a multi-bit output and it is envisaged that they could be used
with a suitable modification of the programmable divider to
respond to such a multi-bit signal.
Although frequency synthesizers embodying the invention
are particularly suitable for cellular radio systems, their
application is not limited to them. It is envisaged tr,at- ~tho,-
applications will include synthesized frequency modulation and
mixed analog and digital sigma-delta modulators for providing
linearized and frequency-stabilized on-chip voltage controlled
oscillators.
For example, the embodiment shown in Figure 5 could be
used for synthesized frequency modulation if third frequency
control signal S~1 were used for channel selection. Then second
frequency control signal 8øo would be used to modulate the
instantaneous output frequency fo about the channel frequency.
The embodiment of Figure 5 could also be modified to
serve as a voltage-controlled oscillator by providing an analog
sigma-delta modulator 102' and a digital sigma-delta modulator
102". Third frequency control signal d~~ would be a fixed
digital signal serving for channel selection. Second frequency
control signal 8~o would be analog, namely a variable voltage
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which would control the output frequency. In the context of the
embodiment of Figure 1, the variable output frequency would be
fo. In the context of the embodiment of Figure 4, the variable
output frequency would be f~,. In both cases, improved stability
would result from the fact that the output frequency is referred
to the input reference signal.
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