Note: Descriptions are shown in the official language in which they were submitted.
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PARALLEL SYNC DETECTION
Field of the Invention
This invention relates in general to digital signal
receivers, and more particularly to a parallel sync
detector for detecting sync words in a serial data
signal.
Backqround of the Invention
Format synchronization in serial data links is
generally obtained through the periodic insertion of
sync words in the data format. Recognition of the sync
word at the output of the data receiver is required in
order to obtain bit level synchronization for
synchronous decoding of the data.
Brief Description of the Drawings
A brief description of prior art sync detectors
will be provided herein below along with a description
of the preferred embodiment of the present invention,
with reference to the following drawings, in which:
Figure 1 is a schematic block diagram of a
conventional sync detector in accordance with the prior
art;
Figure 2 is a block schematic diagram of a parallel
sync detector in accordance with the preferred
embodiment of the present invention; and
Figure 3 is a block schematic diagram of an
alternative design of correlator for use in the sync
detector of the present invention.
Discussion of the Prior Art
Turning to Figure 1, a conventional sync detector
is shown for detecting an M-bit sync word within a
serial input signal.
A serial data signal is clocked into an M-bit shift
register 1 under control of a serial clock signal
synchronized to the data signal. Successive bits
appearing on the ou~uLs of shift register l are
compared within a correlator 2 to corresponding bits
2 ~ 7 3
(Sl, S2...SM) of the M-bit sync word stored within
template register 3.
The correlator 2 performs a multiplication of
respective pairs of signals output from the shift
register 1 and sync word template 3 via multipliers X1,
X2...Xm. Respective outputs of the multipliers X1,
X2...Xm are applied to the inputs of a summer 4. The
ou~u~ of summer 4 is applied to one input of a
comparator 5, and a second input of a comparator
receives a threshold signal having a value of M-T, where
T designates a threshold number of acceptable errors in
the received sync word.
In operation, comparator 5 generates a one bit
output signal having a logic high value when the output
value from summer 4 exceeds M-T, and a logic low value
otherwise. In other words, if the number of agreements
between the stored input data signal within shift
register 1 and the sync word generated from template 3
P~cee~e the aforementioned threshold M-T, the sync word
is considered to have been detected.
The correlator 2 may be implemented in either
analog or digital form (e.g. multipliers Xl, X2...Xm,
summer 4, and comparator 5 may be either analog or
digital circuits). However, the o~u~ of comparator 5
should be a binary value.
The primary limitation of the above discussed prior
art sync detector is that the input data signal is
processe~ serially, which for high data rates results in
a requirement for high speed, high power and complexity
of circuitry.
Summary of the Invention
In accordance with the present invention, a sync
detector is provided which operates on an input signal
at a fraction of the data rate of the input signal
itself, resulting in low power and complexity of
implementation.
2 ~ 7 ~
In accordance with an aspect of the present
invention, there is provided a parallel sync detection
circuit comprising means for converting an input serial
signal into a parallel signal, means for detecting
possible phase of a sync word in said parallel signal
and generating a phase signal responsive thereto, means
for receiving said phase signal and in response
generating a stored version of said sync word phase
shifted in accordance with said phase signal, and a
correlator for comparing said parallel signal to said
phase shifted stored version of said sync word and in
the event of substantial identity therebetween
generating an output signal for indicating detection of
said sync word.
In accordance with another aspect of the present
invention, there is provided a circuit for detecting a
digital sync word of M bits in a serial signal,
comprising:
a) means for receiving and converting said serial
~ignal into a parallel signal having N bits;
where M=KN, and K i8 an integer:
b) means for storing K+1 successive N-bit
sequences of said parallel signal;
c) means for detecting phase location of said
digital sync word in said K+l successive
N-bit sequences, and generating a digital
phase signal responsive thereto;
d) means for receiving said digital phase signal
and in response generating a phase shifted
correct version of said digital sync word, and
e) means for receiving and comparing KN of said
K+l successive N-bit sequences in parallel to
said phase shifted correct version of said
. digital sync word, and in the event said N-bit
sequences of said parallel signal correlate
with said correct version of said digital sync
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word then generating an output signal
indicative of detection of said sync word in
said serial signal.
Detailed Descri~tion of the Preferred Embodiment
Turning to Figure 2, a parallel sync detector is
shown in accordance with the preferred embodiment
comprising a serial-to-parallel converter 10 having a
clock input connected to a clock divider 12.
In operation, the input serial clock signal is
divided by N in divider 12 for clocking out respective
N-bit parallel segments of the digital serial input
signal from converter 10.
The number of bits N in the parallel signal is
chosen such that M=KN, where M is the number of bits in
the sync word to be detected, and X is an integer.
Successive N-bit segments of the parallel signal
are loaded into respective N-bit registers Rl,
R2...RK+1. As shown in Figure 2, the inputs of
register Rl are connected to the serial-to-parallel
converter 10 for receiving s~tccessive N-bit parallel
signal segments of the digital serial input signal. The
N-bit ~u~u~s of register Rl are connected to
corresponding inputs of register R2, and the outputs of
register R2 are connected to corresponding inputs of a
subsequent register (e.g. R3), etc. Respective N-bit
segments are loaded into the registers Rl, R2...RK+l
under control of the divided clock signal ou~u~ from
divider 12.
In accordance with the present invention, for an
M-bit sync word, a predeter ine~ ;n; number of bits
~J(min)) are required to identify the phase of the sync
word at the receiver. In this regard, a phase detector
14 is connected to predetermined outputs of various one
or more of the registers Rl, R2...RK+1 for receiving J
bits of the (K+l)N-bit parallel signal segment.
Although the J bits are depicted in Figure 1 as being
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received from register R1, the J bits can, in fact, be
selected from any one or plurality of individual outputs
of the registerS R1, R2---RK+l-
Upon deciding on the bits J and which of the
register ou~uLs these bits are to be obtained from, aconstraint is placed on the sync word such that there
are N unique sequences of J bits for identifying the
phase. Thus, for a J-bit "snap shot" of the (K+l)N-bit
segment of incoming signal, a minimum of J(min) bits are
required to positively identify the phase of the sync
word within the input signal. Of course, in normal
usage, various J-bit patterns appear in the serial data
signal which do not form part of the sync word. Thus,
phase detector 14 functions as a necessary but not
sufficient means for detecting the presence of a sync
word, while the correlator 16 performs the ultimate
determination.
The minimum number of bits required to identify the
phase of the sync word within K+l N-bit consecutive
segments of input data may be represented by P, where
2P=N and J(min) > = P (assuming T=O, where T is the
number of errors allowed in the received sync word).
In general, the minimum number of bits required to
identify the phase of a sync word in the presence of up
to T errors is J(min) = P+2T. This follows from the
principles of digital information theory which dictate
that the actual minimum number of bits J(min) is
determined by the requirement that there must be N
consecutive segments of J bits in the sync word, each
segment having a Hamming distance of P+2T from each
other segment.
For example, if a 16 bit sync word is used (M=16),
and if N=8 (byte wide detection), then a minimum number
of 3 bits (e.g. J(min) = 3) are required to determine
the location of the sync word in (K+1) = 3 consecutive
bytes of data. If one error is to be allowed in the
2 ~
detection of the sync word (e.g T=1), then at least
J(min)=P+2T=3+2xl=5 bits are re~uired to identify the
phase of the sync word.
Phase detector 14 can be in the form of a look-up
table for comparing the input J bits with a
predetermined template, or can be in the form of a
digital mapping (e.g. programmable logic array) for
generating the P-bit phase signal upon receipt of the
appropriate bit pattern within the input signal.
The P-bit designation of sync word phase is output
from phase detector 14 and applied to a sync word
generator 18 which, according to the preferred
embodiment, is implemented as a PROM. In response, sync
word generator 18 generates a (K+l)N-bit digital signal
in ~hich the phase location of the M bit sync word is
determined by the value of P.
Respective N-bit se~ -nts of the phase shifted sync
word are compared to successive N-bit segments of the
parallel input signals ou~p~L from registers R1,
R2...RK+l. The P-bit phase signal output from detector
14 is also applied to correlator 16 such that correlator
effectively masks the bits surrolln~ing the phase shifted
sync word o~u~ from generator 18, as well as the
corresponding data bits o~ from registers R1 and
RK+l-
In all other respects, the correlator 16 operates
in an identical manner to the correlator 2 discussed
above with reference to the prior art detector of Figure
1.
Thus, in operation, correlator 16 receives a
threshold input signal (M-T) and generates a logic high
correlator o~uL signal in the event that the received
parallel converted input signal from registers R1,
R2...RK+l is substantially identical to the stored sync
word output from generator 18 (exception being made for
up to T errors).
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In addition to the one bit output signal from
correlator 16, the parallel sync detector of the
present invention also provides an indication of the P-
bit phase signal.
Thus, as discussed above, the circuit of the
present invention generates an accurate detection of
sync words at a fraction 1/N of the input serial data
rate. Accordingly, substantial savings are effected in
complexity, cost and power implementation requirements
over prior art serial sync detectors.
Figure 3 illustrates an alternative means of
correlating the (K+l)N bits from the register ouL~u~s
(here labelled X(1), X(2),...X((K+l)N)) as determined by
the P bits of phase detector 14 (Figure 2).
More particularly, logical circuit elements or
blocks 20, 22...24 are provided for effecting respective
arbitrary mappings of P+1 bits to 1 bit. The mappings
are represented by fl(xl~o)~ f2(X2~ 0O)---f(K+l)N
(X(K+1)N,0O). The logical circuit blocks 20, 22...24
may be implemented by programmable logic devices such as
PLA's, etc.
In operation, the P bits of phase detector o~u~
identify X(i) as one of KN possible sync bits or one or
N maskable data bits. If X(i) is a possible sync bit
and is the same value as the sync bit identified, the
ouL~uL of the logical block (e.g. block 20, 22...24) is
C(i) = 1. Otherwise, C(i) = 0 if X(i) is a possible
sync bit and is not the same value as the sync bit
identified, or X(i) is a -sk~hle data bit.
The (K+l)N ou~uLs of logical blocks 20, 22..... 24
are summed via summer 26 for comparison against the
correlator threshold in comparator 28, as occurs in the
above-discussed prior art.
~he alternative embodiment of Figure 3 is
functionally the same as the preferred embodiment
illustrated in Figure 2, but does not include the
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explicit formation of sync and mask bits for input to a
conventional correlator.
Variations and modifications of the present
invention are possible within the sphere and scope of
the invention as defined by the claims appended hereto.
