Note: Descriptions are shown in the official language in which they were submitted.
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TITLE OF THE INVENTION
2"Radio Pager Tone Alarm Circuit For Generating Variable Duty Constant
3Audio Frequency Pulses Modulated With Unique Tone Pattern"
4BACKGROUND OF THE INVENTION
sThe present invention relates generally to radio pagers, and more
6specifically to a sound alarm circuit for such radio pagers which generates
7an alert tone of escalating sound levels.
8A radio pager having the capability of successively escalating the
gsound level of an alert tone is described in Japanese Patent Publication 63-
10252030 (Tokkaisho). According to the prior art technique, constant audio
11 frequency pulses are modulated with a variable duty tone pattern that
12 identifies particular incoming pages. The duty ratio of the tone pattern is
13 successively increased to increase the sound level of the tone.
14 One serious disadvantage of the prior art technique is that since the
, 15 sound level is controlled by the duty ratio of a tone pattern, the alert tone
~ 16 patterns as standardized by the Post Office Code Standardization
`i 17 Advisory Group (POCSAG) cannot be employed for escalating alert tones.
18 SUMMARY OF THE INVENTION
19 It is therefore an object of the present invention to provide a radio
20 pager that enables internationally standardized alert tone patterns to be
21 employed for alerting users with an escalating sound level.
22 According to the present invention, the radio pager comprises a
23 receiver for receiving a paging signal containing a unique identifier
24 identifying the own radio pager and an alert tone pattern. A pulse
2S generating clrcuit generates audio-frequency pulses having a duty ratio
2 6 increasing as a function of time in response to receipt of the paging signal.
: 27 A modulating means is provided for modulating the variable duty pulses
2 8 with the alert tone pattern for applying the modulated pulses to a
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2 9 loudspeaker.
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BRIEF DESCR!PTION OF THE DRAWINGS
2 The present invention will be described in further detail with reference
3 to the accompanying drawings, in which:
4 Fig. 1 is a block diagram of a radio pager of the present invention;
s Fig. 2 is a block diagram of a sound alarm circuit of this invention;
6 Fig. 3 is a waveform diagram associated with the sound alarm circuit
7 of Fig. 2;
8 Fig. 4 is a waveform diagram of the tone pulses modulated with a
9 POCSAG A-code tone pattern;
Fig. 5 is a block diagram of a modified form of the sound alarm
1 1 circuit;
12 Fig. 6 is a waveform diagram associated with the sound alarm circuit
13 of Fig. 5;
14 Fig. 7 is a block diagram of an alternative form of the sound alarm
circuit; and
16 Fig. 8 is a waveform diagram associated with the sound alarm circuit
17 of Fig. 7.
1 8 DETAILED DESCRIPTIQN
19 A radio pager of the present invention as represented in Fig. 1
20 comprises a front end 2 for converting paging signals received by antenna
21 1 to baseband signals for coupling to a waveshaper 3. The output of
22 waveshaper 3 is applied to a decoder 4 in which the received signal is
23 checked for a coincidence between a pager identifier contained in it and
24 the one stored in a PROM (programmable read only memory) 5. On
2 5 detecting a coincidence, decoder 4 alerts a sound alarm circuit 6 with a
26 POCSAG (Post Office Code Standardization Advisory Group) alert tone
27 signal having one of predetermined tone patterns or cadences. For
28 example, one such cadence is a cyclic sequence of 7/8-second ~N and
29 1/8-second OFF. Sound alarm circuit 6 modulates the tone signal with a
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variable duty pulse sequence and activates a loudspeaker 7. A reset
2 switch 8 is connected to the decoder 4 to be operated when the user
3 answers an incoming page.
4 As shown in Fig. 2, sound aiarm clrcuit 6 comprises an AND gate 10
s that is responsive to an enable signal from decoder 4 to pass high-
6 frequency clock pulses from a clock source 9 to frequency dividers 11 and
7 12, and further to an up-counter 13 during the time the pager is being
8 alerted. As shown in Fig. 3, frequency divider 11 divides the frequency of
9 the clock to produce an output whose frequency determines the pitch of
the alert tone, typically at 2.6 kHz, and frequency divider 12 divides that
11 clock frequency so that its output determines the rate at which the duty
12 ratio of the 2.6-kHz pulse sequence is varied. Typicatly, the duty ratio is
13 stepwisely varied at 6-second intervals. The output of frequency divider
14 11 is applied to the up-counter 13 as a reset pulse so that its output
15 represents a digital count value which continuously increments in response
16 to the clock pulse until it rapidly drops to zero in response to the reset
17 pulse. On the other hand, the output of frequency divider 12 is applied to
18 a down-counter 15 to produce a decremental binary count value which
19 represents the varying rate of the duty ratio. A monostable multivibrator
2 0 14 iS provided for producing a pulse for clearing the contents of down-
21 counter 15 as soon as the pager is alerted.
22 The digital output of down~counter 15 is applied to a binary-to-duty
2 3 converter 16 which converts it to a digital value representing the duty ratio
24 of the 2.6-kHz pulse sequence for each 6-second interval. In a typical
25 example, binary-to-duty converter 16 successively generates outputs
2 6 representing duty ratios of 12.5 %, 25 %, 33 % and 50 %. The outputs of
27 binary-to-duty converter 16 and up-counter 13 are applied to a digital
28 comparator 17 in which they are compared with each other to produce a
29 high-level output when the digital value of counter 13 is greater than the
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output of bina~-to-duty converter 16. It is seen therefore that the output
2 of comparator 17 is a sequence of constant-frequency pulses of a variable
3 duty ratio which increases stepwisely at 6-second intervals as shown in
4 Fig. 3. From the tone quality standpoint, the maximum duty ratio is set 50
s % as described above.
6 The output of cornparator 17 is applied to an AND gate 18 to which a
7 POCSAG tone pattem, say A-code pattern, is also applied. In this way,
8 the variable duty 2.6 kHz pulse sequence is modulated by the POCSAG
9 A-code pattern as shown in Fig. 4 and applied through an amplifier 19 to
10 the speaker 7. Loudspeaker 7 has a narrow band of frequency response
11 characteristic. This characteristic is sufficient to suppress the harmonic
12 components of the modulated alert tone pulse which may otherwise
3 cause changes in tone quality with variations of the duty ratio.
14 Therefore, the POCSAG tone pattern can be used for generating an
S alert tone with successively escalating sound levels.
16 A modified form of the sound alarm circuit 6 is shown in Fig. 5. In this
7 modificationt a programmable counter 20 is used instead of the up-
8 counter 13 and comparator 17. Programmable counter 20 is clocked by
19 the output of AND gate 10 and reset by the output of frequency divider
11. The output of binary-to-duty converter 16 is applied to
21 programmable counter 20 as a preset count value which decrements at 6
22 second intervals in response to the output of frequency divider 12 (Fig. 6),23 and hence the duty ratio of the tone pulses generated by programmable
24 counter 20 increases with the decrease in the preset count value.
2S Alternatively, the present invention can be further modified as shown
26 in Fig. 7 in which the down-counter is replaced with an up-counter 31 and
27 binary-to-duty converter 32 transforms the stepwisely incremental value
28 of the output of counter 31 to a stepwisely incremental duty ratio. A flip-
29 flop 30 is provided having a set input terminal connected to the output of
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frequency divider 11 and a reset input terminal connected to the output of
2 programmable counter 34 whose program input is connected to the
3 output of binary-to-duty converter 32. An AND gate 33 is responsive to
4 the output of flip-flop 30 to pass the output of AND gate 10 to the clock
s input of programmable counter 34. The output of flip-flop 30 is further
6 applied to the reset input of programmable counter 34 and one input of
7 AND gate 18.
8 As shown in Fig. 8, flip-flop 30 is triggered into a high-level, set
9 condition in response to each output pulse from frequency divider 11 to
allow clock pulses from AND gate 10 to pass through AND gate 33 to the
11 programmable counter 34. The latter produces a high-level output when
12 the duty representing count value is reached and resets the flip-flop 30 to
13 a low-level condition, producing a tone pulse having a stepwisely
14 incremental duty ratio.
15 The foregoing description shows only one preferred embodiment of
16 the present invention. Various modifications are apparent to those skilled
17 in the art without departing from the scope of the present invention which
18 is only limited by the appended claims. Therefore, the embodiment
19 shown and described is only illustrative, not restrictive.
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