Note: Descriptions are shown in the official language in which they were submitted.
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STAR-WIRED RING LAN
BACKGROUND OF THE INV~TIOM
m is invention relates to data transfer netwDrks, especially
local area netwDrks (L~Ns), and is concerned E~rticularly, but not
exclusi~ely, with integrated voice a~ data LANs - rvD LANs.
Many different types of L~Ns exist or have been propose~, and
many have been standardised u~der the aegis of I~ 03mmittee 802. :
L~Ns typically. comprise a nL~tRr of termlnals linked by one of a
number of network arrangements, inc~uding point-to-point, ring and
bus networks. Each of these geametries has its advantages Ar~
drawbacks however.
In the proposed IEEE 802.9 star L~N, connected using point-to-
point wiring, each term m al (1~ is linked directly to a port of a
multi-port access unit AU and each TE ~unctions substantially
independently. This arrang~ment is particularly advantageous in
terms of fault or errDr handling. Each TE link is independent
and so failure of one does not affect the remainder of the LAN. It
is disad~antageous hGwever in that a large amount o~ hardware is
required within the AU. In order to permit oommunication ~ een ~ ;
indepe~dent TEs in a framed tim~ division multipl-ex (T~M) system the
data transfer to and from each has to be contrDlled and krought into
alignnent. In a point to point ~ this r ~ es as many parallel
sets of data-handling hardware as there are TEs ~nd so i~ expensive.
In ring and bus k~sed L~Ns all the TEs and any ring or bU5 :
master are linked by a single loop or ~us. Any master unit
therefore requLres only one port inFut and one port output.
Various forms~of ring and bus LaNs exist. For example token rings
allow only one TE to write data int4~the ring at a time, which~data
then circLlates the ring anl is read by the addressed lE. Only a
TE h31ding the;token lS Eermitted t~ writ~ data, after which ~he
token is passed on around the rmg. Much less ha~dwzre is
requi~d overall Ln this case than ~n a mlllt1-port poi~t~ po~n~
~ 5ta~ IAN~ e~en;though r peater un~ts are required to repeat tha
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signal at intervals around the ring. The proposed 802.9 point-
to-point star-wired LA~ requires~approx~mately double the higher
level hardware (e.g. multiplexers, channel and pac~et hardware)
since an instance of this hardware is needed at both ends of each
point to point l m k. A ring or bus network therefore costs less
than an equivalent point-to-point netw~rk, but leads to serious
disadvantages regarding error or fault tolerance. In a ring, if
one termunal or link fails, then unlike a point-to-point star the
whole L~N fails, affecting all the TEs, and the LAN has ~o be
reconfigured.
A star-wired LAN may be implemented as a hybrid between a
poi~t-to-point and a ring LAN. As in a ring L~N all TEs are linked
in a continuous loop extending ~rom an access unit (AU) ou~put back
to an AU input but the loop also returns to the AU between each pair
of TEs. This ~eans that the AU requires less hardware than for a
point-to-point LAN since data signals are transmitted around a ring
linked to all TEs. Cost is therefore low. A hybrid star LAN can
also have sume of the fault tolerance of a poLnt-to-poLnt LAN. If
a single terminal or the link to it fails, then it may be ~ypassed
within the AU with a simple link to replace the TE. Continuity of
the star is thus mainta m ed. It is known to do this in hybrid
token star-rings. However, such replacement of a TE may require
reconfiguration of the IAN to allow for the changed delay in the
star.
SUMM~RY OF IHE INVENTION
The invention is defined in the appended claims to which
reference should now be made.
In a first aspect the invention relates to hybrid star networks
and provides a data transfer netw~rk oomprising an access umt
ha~ing a port for a terminal, the port ocmprising a port input an~ a
port output for respectively sending signals to and receiving
signals from the terminal, the terminal being link~d to the access
unit by da~a transmission m~ans forming a terminal li~ e~tending
from the port input via ~ send data line to the termhnal and f m m
the tenninal via a receive data line back to the port output, a
bypass link between the port input and the port output Ln parallel
wi~h ~he term mal link, ani a switch m~ans for m uting data to the
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t.erminal port output via either the terminal link or the bypass
link, in which the time delays between the port input and the port
output via the terminal link and via the bypass link are matched.
Provision of a bypass link of the same del~y time as the
corresponding TE link in a hybrid star network considerably enhances
fault or error tolerance, since a faulty TE link can be bypassed by
means of the switch without a~y effect on the configuration of the
rest of the LAN. The timing of the LAN d~es not change and all
other TEs are unafected.
The bypass link preferably has a fIxed time delay which may be
the same for all termunals, and the terminal link preferably
comprises an adjustable time delay ele~ent for matching to this
fixed delay.
If the adjustable delay element, which may be a FIFO with an
adjustable fill level, is controlled by the AU, the delays of the TE
link and its bypass may be matched autamatically. In a preferred
embo1inent the AU ccmprises an initialisation controller at the port
to enable automatic matching of the delay elements to be carried
out.
Although the switch means oould act at the port input it is
much preferred that .it shall act on the port output side.
According to the invention the data transfer network preferably
further oomprises a control means responsive to a co~parator for
co~trolling the switch means. Data from the port input enters
both the termlnal link and the bypass link and the comparator
oompares the data signals after transmission along each link.
The ad~ition of a oamparator can enhance the fault or error
tolerance of the hybrid star IAN. Within the AU, at each TE link
the incoming data 8ignal iS fed to both the TE link and its bypass
link. The signals are oomçared before they reach the switch at
the port output, whence they pass on to the remainder of the star, !~
and the switch is controlled acoordingly. The bypass link is
highly unlikely to introduce aniy errors into the data and so its
- output ma~ be considered error free. If the TE has no access to
write data into ~he network and no errors have ocaurred, a signal
returning to the AU from the TE link should be the same as that Ln
the bypass and thus a ccmparison should show no differences.
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The control means responsive to the comparator can thus count
the bit error rate (BER) of its TE link. It can therefore
iàentify certain error or fault conditions (such as disconnection or
non-operation of the TE) and act accordingly. At some threshold
BER the control means may for example permanently connect the bypass
link. It will still scan the TE link signal however, and if the TE
reco~,mences correct operation, the control n~ ; can reconnect it
automatically.
The comparator may in a preferred ~mbodime~t cQmpare the
signals in the T_ loop and bypass link at a small time deiay before
those signals reach the switch oontrolled by the comparator. This
would allow more relaxed timing for the control of the switch.
The AU may advantageously be implemented for a plurality o-f TEs
using a single VLSI device. In this case the delay elements, the
shift register and the FrFO, w~uld require signific~nt areas of the
device and so the time delays required would be adva~tageously
reduced as far as possible. A 4-octet delay for each bypass link
should be sufficient to allow for the m2xim~m transmission time via
a terminal link in a typical LAN. The FIFO should be long enough
to allow for the maxlm~m variation in TE link delays of the LAN.
A greater number of AU ports for connection to TEs could then ba
implemented on a single VISI device.
If a small delay time at each port is used however, then the
total time of transit of a physic 1 fra~e (PF) around all the ports
in the L~N may be shorter than the length of each PF. T3 maintain
PF alignment, the data transit time around the LAN m~st be equal to
the length of a PF. A further separate shift regis-ter may
therefore be inserted into the ring of the L~N in order to increase
the total data transmission time around the L~N.
Further, the IEs req~ired by the L~N of the invantion may be so
designed that they are no different from those requircd for point to
point LANs currently under consideration hy lL~ 802. Each TE
communicates directly only wi~h the AU and is independent of all
other TEs. For each TE therefore, the L~N of the invention appears
identical to a point to point LAN.
The invention also provides a system of data transmission which ~ -
is particularly advantageous when us~d in combination with the
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network described above. ~his data transmission system is based on
the kno~n transmission system of time division multiplexed physical
frames (PF). These are blocks of data of fixed length and defined
structure which in existing systems are generated by a PF Generator
(PFG) within the AU, are passed around the net~ork and recovered and
terminated in the AU by a PF Aligner (PFA) and an associated PF
store (PFS). If however a LAN has a fixed ~elay time for a
complete circuit, in particular a delay whicl~ is an integral
mLltiple of the frame period, then there is nD requirement for a PFA
and a PFS to maintain align¢ent of a reoovered PF with a subsequent
generated PF. However, a PFA may still be required to align PFs
in a LAN with PFs in a seco~d IVD-LAN or other transmission system -
such as an ISDN. TW~ or more LANs ~rking on oompatible systems
(for example ISDN systems) ~ay be linked, but PFs sent from one to
the other will not necessarily be aligned. A PFA and an
associated PF Store (PFS) will therefore be required. It should
be noted that only one PFG, PFA and PFS are therefore re~1ired in an
AU using the hybrid star-wired L~N of the invention. An
equivalent point-to-point star-wired L~N using PFs would require a
PFG, a PFA and a PFS for each TE and would therefore be considerably
more costly.
The organisation of each Physical Frame (PF) oomprises a n~mber
of heirarchical layers. In the lowest physical layer, information
bits and a clock are transferred. On the next higher heirarchical
layer, the infor~ation within the PF ~s subdivided into a number of
TDM sl~ts, each typically oomprising an octet of 8 bits. The
slots may then be group0d in a higher layer into a series of
channels. Each channel may contain any number of slots and
therefore be of any data capacity.
In any TDM network it is necessary to manage allocation of
these slots and channels to network devices. This is o~nventionally
d3ne on a call-by-call basis by includLng slot allocation data in
one or more slots of each frame, re~erred to as the D channel in
ISDN telephon~. In a oonventional system a managem~nt unit which in
a LAN may be the AU or one of the tarminals, supervises slot -
allocation and hence the data in the D channel, by neans of which
the terminals are granted access to slots.
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It is frequently necessary to utilize channels composed of more
than one time slot. Thus in an rVD L~N and using I~ 802.9
terminology, in addition to single slot channels for voice or data
(B channels) there may be e.g. six or twelve slot channels for video
~C channels) which can be allocated to devices on a call-by-call
basis and a broadband packet channel (p channe]) that -takes up all
otherwise unallocated slots. Various proposals have been made to
detall the manner in which allocation of slots to channels should be
managed.
In the PAC point to point LAN scheme as proposed to r~ 802.9,
there is a semi-permanent ~i.e. not call-by-call) allocation of
slots to channels controlled by slot allocation data carried within
each frame. This provides some flexibility because the allocation
can be changed from frame to frame to meet changing demands, in
p2rticular by adjusting the size of the C channel allocation
relative to the size of the P ch~nnel allocation. The D channel and
a PF boundary control octet then control the apportionment of these
slots to P and C channels. One disadvantage of this system is its
susceptibility to transmission errors s m ce it relies upon channel
allocation data carried by each frame. Furthermore the rigid
slot to channel relationship is rather inflexible.
The present inventor has proposed a more flexible and robust
system to L~kL 802.9 whereby the slot ~o channel allocation is
maintained within a template stored at each network device. Since
it is stored, this allocation is substantially unaffected by
transmission errors. In order to allow ~he template to be updated
to adapt to chang m g demands, each davice stores not only an active
template but a background template which can be changed by data sant -
over the LAN to all devices by the access unit. A protoool
operating on a bit in the framung time slot used as a "swap" flag
may then be used to cause all devices to swap over the stored active
and bac~ground templates, thus bringing a new active template into
operation. ~his mech2nism ensures that all devices always use the
same template; disaster is m~re or less inevitable if they do not.
The storad templates avoid the xisks inherent in oontlnual
transmission of slot to channel allocation by the access unit.
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It is a further object of ~he invention to reduce as far as
possible the processing that each TE is required to perform and to
reduce the storage required at each TE. This reduces the total
cost OI a LAN and reduces any TE modification required to connect a
TE to a L~N.
Accordingly the invention further provides in a further aspect
a data transfer network oamprising a plurality of termunals and a
multiport access unit connected via a data tra~smission ring, and
communicating with each other via channels co~stituted by varying
nu~bers of ti~e division multiplexed slots, wherein each termLnal
comprises means for storing indefinite~y at least the part of a
template relevant thereto, and the access unit cQmprises means for
storing the entire template, which template allocates slots to
channels and further allocates at least scme cha~nels to specific
terminals.
In conjunction with the hybrid star network system with bypa~s i
links described earlier, it will be seen that the use of this
template system is advantageous. The template stored by the AU and
control~ing channel allocation o~ the PF contains information as to
whether a termlna} has access to write to any channel of the PF.
The control means used Ln the AU to control the switch connecting
either a TE link or its bypass link to the output port of that
section of the L~N can then advantageously use the tem@late stored
by the AU.
Data corruption during transmission is most likely to occur in
the TE link during transmission from an A~ port to a TE and back.
By contrastr the corresponding bypass link may be considered error
free. Since the control means controlling the switch to connect
either the TE link or the bypass link to the port output is
responsive to the AU template, it may advantageously connect the
error free bypass link to the port output as much as possible. It
is only necessary to pass those slots of a PF to which a TE has
write access frGm the TE link to the port output. All other slots
may be passed to the port output via the kypass link. The control
means ma~ thus use data from the AU template, which defines those
slots of a PF to which a TE has write access, to control the switch
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accordingly. In this way, errors introduced in a rrE lLnk may be
substantially removed frcm the signal passed fm m that r~E port on
around the L~N.
Further error resilience is provided by the CQmDarator. By
comparing data in the TE link and bypass link near the pcrt output
in TDM slots to which the TE has no write access, and assuming that
the bypass link is error free, the switch control me2ns in response
to the comparator may determune the bit error rate (BER) introduced
by data corruption in transmission around the 'E link. Using BER
threshold techniques the control means can thus identify certaln
categories of TE link faults and oontrol the part output switch
accordingly. Further, if the c~mparator detects signal
corruption in the rE link of a channel to which that 'E has read
access, then it may assume that the corruption might have occurred
before the signal reached the TE and thus that the TE may not have
received the information correctly. The AU can then act
accordingly.
The cc~bination of PFs, channel allocation and stored templates
with automatic term mal bypass links thus provides a system that is
particularly robust and resilient in the face of both hard and soft
line errors.
In the prior art, a number of physical layer systens for
heirarchical organisation of synchronous time division multiplexed
physical frames have been employed or proposed. In template based
systems, the template ccmprises information allocating groups of
slots in a PF to channels and ide~tifying each channel by a chL~nnel
number for example. Each type of channel requires a certain number
of slots to provide the required data transfer capacity. In an
IVD-LAN as described here, channels may ke designated for purposes
including, for example ~following certain rEEE 802 proposals):
Channel ID ~ el Function
F Framing
P Packet transfer
B Voice or Data (single slot)
C Video Conference ~si~ slot channel)
D ISDN Signalling
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In an emkodiment of the invention, the PFG generates PFs and
8kHz and operates at a data rate of 8.192 Mbps. Each PF then
c~ntains 128 octet wide slots. In the embcdiment a B channel for
voice of data would then require one slot per PF, and a C channel
for video 6 slot.
It is preferable that a data rate of at least 4 M~ps is used in
order to enable rvD networking of a number of termlnals, although
higher data rates such as 8 or 16 Mbps would be advantageous,
allowing greater bandwidth and networking of a larger number of
terminals.
The template scher~e of the invention for dynamic channel
allocation provides substantial resilience in the face of errors.
The channel allocation for a PF is stored in the AU and at least the
relevant part thereof is stored in each TE. The TEs therefore
store information as to which slots in a PF each may use, and for
what purpose. The stored active template thereby determunes
channel allocation for all PFs until a new template is brought into
operation. This is achieved by a template swap operation, as
explained above. The backgrou~d template may be determined
before being brought into operation by the AU according to a higher
level call request mechanism in response to data sent to the AU by
TEs requesting channel allocation changes according to their
forthcoming requirements. The invention is t concerned with
this higher level mechanism. The background template is then
transmitted around the LAN in PFs in a dedicated channel. In
practice this channel may be only a single slot, and only a part of
a templa~e may be transmitted in each PF. If the LAN bit rate is
8Mbps and the PF rate is 8kHz, then there are 128 slots per frame.
If a single te~plate transfer slot is allocated in each PF, then 128
PFs will be required to transmit the full t~mplate. The series of
128 PFs is termed a multiframe. Clearly the template
transmQssion channel ma~ oomprise two or more slots, in which case
each m~Itiframe will be proportionately shorter.
As the multiframe is transmitted, the background template data
may thus be received and stored by each TE. In a preferred
emkodiment, to reduce the storage capacity required at the TEs, each
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TE may store only those sections of the template relevant to itself,
that is the channel numbers of, and the slots allocated to, those
channels to which it has access. It should be noted that the
te~plate stored at the AU and at each TE may not then be of the same
form. The filtering of the AU template information required to
achieve this may be perform~d either at the AU or at the TE.
A number of schemes are possible for reducing the memory and TE
processing capability required to store templates at TEs. For
e~ample, if all the slots of a template are stored in a TE, it is
not necessary to store slot numbers. These are determ med
un2mbiguously by memory location. Furthermore TE identifiers for
unshared channels may t be stored. If a TE only needs to s~ore
the template information relevant to itself, these TE identifiers
may be replaced by 'me/ t me' bits.
If only a partial template is stored, then slot numbers may be
stored as well as channel n~mbers. Only the template information
for t~ose slots to which the TE has access need then be stored and
so neither TE numbers nor 'me/not me' bits need be stored. Only a
set of the relevant matched slot and ch2nnel numbers need be stored.
In this way, from a multiframe se~uence of PFs, each TE can
acquire appropriate definitions of a background template, which is
- to become the new active template, by use of a dedicated template
transfer channel of a relatively small data capacity. Tne useful
information carrying data capacity of the LAN is thus maximised.
When required, the background template is then s~apped wlth the
active temp~ate. This may only require each TE to read a swap
control bit a~ the beginning of the first PF to initiate use of the
new template as each TE would already contain the new te~plate in
memory, having read it as the background ~emplate in previous PFs.
~ore sophisticated signalling of a swap may be used however to
reduce the chance d errors. In this way/ a new t~,wlate may be
implemented rapidly and ~ransparently, prcvid1Dg in a single
mLltiframe operation a new template at all TEs.
Using this scheme, template information for the control of time
division multiplexing of slots within physical frames can be
transmitted to TEs of a LAN with a very high level of integrity and
entirely within the physical layer.
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BRIEF DESCRIPTION OF THE DRA~INGS
En~xxl~nents of the invention will now be described by way of
ex2mple with reference to the accGmp2nying drawings in which;
Figure 1 is a schematic diagram of a hybrid star-wired LAN;
Figure 2 is a schematic diagra~ of a terminal and its bypass
li~k and associated control system;
Figure 2A is a schematic diagram of the ir~tialisation control
of an AU port;
Figure 3 shows the structure of a single empty physical frame;
Figure 4 shows the position of the physical sub-layer within an
OSI layer heirarchy;
- Figure 5 is a schematic diagram of a L~N interface of a
termin~l; and
Figure 6 shows an example of the time division multiplexing of
the slots of a PF into channels and the corres~onding template.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
1. Bypass link system
An emboYim:nt of a L~N according to the invention constitutes
an implementation of the channel multiplexer and physical framing
sub-layer of layer 1 of the OSI model, as illustrated in Figure 4.
It comprises a multi-port access unit (AU) 1 and eight IVD terminals
2, denoted TEO to TE7 and each connected to its own port, Figure 1. ~ -~
However, the number of termlnals in such a L~N may cIearly be more
or less than eight. The ~U 1 and the terminals 2 are linked b~ a
hybrid star network 3. The netw~rk thus forms a continuous ring,
but the ring returns via the AU~between each TE to form a hybrid
star. The AU 1 oomprises a physical frame generator (PFG) 5 for
injecting the physical frame struc~ure and a physical frame aligner
(PF~) 6 for efecting frame alignment with an eKternal ISDN link 4
and acting as a bridge between the ~N and the ISDN link.
In the embod~m~nt, the time taken for a PF to pass around the
star is 125 microseoonds, and the PFs are generated at a fre~ency
of 8 kH2. The data transfer speed is 8.I92 Mbps. The PFs thus each
contain 1024 bits, coxresponding to 128 octet-wide TDM slots. The
delay per terminal may be only 4 octets, or 32 octe~s for all eight
terminals. A shift regis~er delay 7 (whose position in the loop is
arbitrary) is included to make up the total delay of 1~8 octets.
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Other delays per terminal may be used. In general the smallest
feasible value should be selected. The shift register delay 7
realigns each PF received at the AU to the same phase as the next
transmitted PF.
Each terminal 2 of the L~N is connected to the AU 1 by TIP
(telephone tt~isted pair) cables 3 or optical ~ibres. A 'send' data
line 3S (Fig.2) extends to the terminal 2 from a port in~Dut 8 in
the AU l. A 'receive' data line 3R returns from thP terminal and
can be connected to a port output 9 by a switch 12. Each port 30
is provided with a parallel bypass link extending from the port
input 8 and through a shift register ll whose output can be
connected to the port output 9 by the switch 12. When a signal is
transmitted around the ring it enters the section of the netw~rk
shown in Figure 2 at the port input 8. It is then split into two
and passes via the send line 3S to the IVD terminal 2 and also along
the bypass link directly into the shift register ll. The signal
sent to the rVD terminal 2 returns to the AU 1 via the receive line
3R and enters a FIFO variable length buffer 13. Either the signal
output from the FIFO (F0) or the signal output from the shift
register (SO) may then be connected by means of the ~witch 12 to the
port output 9 to be transmitted from this section of the network on
around the ring 3. The way in which the switch 12 is controlled
is explained below.
The data transmission times through the rVD terminal link and
through the bypass are e~ual. The transmission time around the
netw~rk is se~ first by the lengths - which are preferably equal -
of the bypass shift registers l} on each port of the AU. These may
be say 4 octets, i.e. 4 slots each and the delay 7 ~Fig. l) has a
delay o~ 128 - (4 x 8) = 96 slots. Alternatively, for an AU with
eight ports using frames of 128 octet-wide slots for data, the delay
evenly divided at each port will be ~6 slots. The bypass shift
registers ll must then provide this delay and the delay 7 is not
ne~ ssary.
There will be a delay in transmitting ~he PF from the send line
3S around ~he IVD terminaL loop to the receive line 3R, depeDding on
the type of Iine code encoder/deooder used, the line propagation
dela~, and the delay wi ~ the rVD termunal itself. The total -
W O 90/15492 ~5~si PCT/GB90/00886
delay can then be matched to the 4 or 16 5Iots delay of the bypass
shift register 11 by adjustment of the FIFO elastic ~uffer 13 which
is an asynchronous fall-through FIFO with clocked output. Such a
FIFO automatically re-establishes bit synchronisation of the sic;nal
at its output while being tolerant of jitter on its input.
The FIFO 13 is set during an initialisation mode of a port.
~his m~de is c~ntrolled by an initialiser 15 (s~wn in detail in
Figure 2A) which may be shared by a plurali~y of ports. The
initialiser 15 sends an mitialisation ~ode claq (IM) to a port to
start initialisation of that port. In the initialising mDde the
port switch 16 directs "Idle" slots ~A5 hex) from the initialiser 15
out to the I~D-TE, except at framing slot (slot 0) time when a -
framung patten~ (~3 hex) is sent. The 'icUe' and 'framing'
patterns are chosen so that misalignme~t by any number of bits is
detectable and identifiable. When the raming pattern is detected
at the input to the FIFO 13 by fram m g detector 40, the ~and~ ~ate
41 outputs a clear (CLR) signal to clear the FIFO 13 to an empty
state. The 'idle' slots following the framing slot then
progressively fill the FIFO 13 since the FIFO output clock is
disabled (edge reset) when the initialisation mode is entered.
The FrFO output (FO) is not clocked until the framing slot (slot 0)
is clocked out of the shift register 11 and detected by framing
detector 42. The framing detector 42 output then operates a latch
43 via a gate 44 to re-enable the FIF0 output clock via gate 45.
Clock pulses (CLK) are then passed to the FIFO 13 to clock data FO
out of the FIF0 13 in synchronisation with the shift register output
SO. The detector 42 may be replaced by a counter which counts off
th~ kncwn number of clock pulses corresponding to the delay of the `
shift register 11.
In a preferred embcd1ment, a more rigorous test for
synchronisation may be employed, which verifies that 3 consecutive
framing patterns are o~rrectly received at the input to the FrFO 13 ~ ,
(FI) at the oorrect times, one PF ~part, before the port is
considered to have ~een properly initialised. The outFuts from the
IYD termi~al link and~the bypass link are then synchronised so that
signals from ei~her may be transmitted on around the network via the
switch 12 with identical delays. -;
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The switching by the switch 12 of either the signal so or the
signal FO to the port output 9 is performed under the control of the
port control 17 wnich is sensitive to the te~plate 18 and to a
com~rator 14 which com~ares the sisnals F0 and S0.
2. TemDlate System
The operation of the switch 12 is related to the structure of
the transmitted data, which will be considerecd before reverting to
description of operation of the control 17 etc. In the en~xxl~ment,
the data is transmitted as a series of 125 microsecond physical
frames generated at 8 kHz. With a bit rate of 8.192 Mbps each PF
contains 128 byte-wide slots. A typical arrangement of a PF is
shown in Figure 3. The first two slots are reqlired to contain
framing and control/status information, essentially in accordance
with oonventional TDM practice. The third a~d fourth slots contain
at least a portion of a template, for updating the background
template. The template describes koth the channel to slot
association and also the terminals which may use each channel. It
also identifies any unused channels, and defines overhead channels
such as framing control, states and template channels. In an
alternative example, the first three slots contain framung and
control/status information, and the fourth slot contains a portion
of the te~plate.
The allocation of slots tc, carry framlng, control, status and
template updating information may vary according to the re~irements
of a given LAN. In particular the template channel, allocated one
or two slots per PF as described above, ~a~ comprise more slots
especially if the L~N comprises a large number of TEs. As
described below, a smgle slot channel an~ 128 PF m~ltiframes are
adequate for the ~ TE LAN of the embodlment but in a larger LAN, the
in~ormation required in a full template will be greater and
correspondingly a w.ider template update transmission cnannel or
longer multiframes ~ould be required.
A full template defines for each slot of a PF the channel to
whi d that slot is allocated and the IE5 which may write to that
slot. A channel n~y camprise a nLmber of slots depending on the
da~a transfer capacity required. In the L~N of the embod~ment for
example, several types of chann~l may be allocated to TE~.
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According to I~ 802.9 proposals these may include:
Channel Channel Channel No.slots
Numcer Type Function required
0 P Packet Traffic *
1 D TE specific ISDN 64kbps signalling
2 B Voice channel 1 `
3 B BRI - Rate Adapted Data
4 B Okher X.25 channel
C Video Conference 1 6 --
6 C Video Conference 2 6
7 S Spare Channel
*All slots otherwise unallocated
In additionj shared channels can be supported. These are ~ :
shared between two TEs and either TE may write to or re~d from that
channel at any time. Since a PF always travels in the same ~;
dlrection around the ring of the L~N, two-way comn~nication, such as
a voice link for e~ample, may thus be effected in a single channel
which may be a single slot.
In ~he embodm ent, each PF contains 128 byte-wide slots. Each
slot may be allocated a channel nu~ber and a TE number. Since there
are 8 TEs and a channel numbers, 6 bits are r~qulr0d to describe a
TE and a channel type for each slot. If one slot per PF is used to
transmit template inform2tion then, as described below, each PF may
carry the template information for 1 slot. 128 PFs are therefore
required to transmit a full template, which takes 16 ms. These
m~lti-frames comprising 128 8 kHz P~s, repeating 64 times pex
seoond, may be flagged in the oontrollstatus slot. Alterna~ively
they may be flagged by, for example, inverting the framing pattern
at the end of each multiframe. A full template may thus be
transferred in a multi~rame entirely within the physical layer. ~ :
An example of a template ~ransmission and sborege system will
now be described. In the ertxx~h1#nt, a one slot channel in each PF
is dedicated to template tran~mission. A multiframe of 128 ~rames
is therefore required to transmi~ a camplete back4rw nd template,
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~` but the bandwidth remainLng for data tra~smission is max~mised.
Eight bits are~therefore available for template transmission in
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each PF. Since sequential PFs can describe sequential template
slots it is unnecessary to transmit the slot number as long as the
first ~F of each multiframe is identified. Each PF can therefore
carry 8 bits of template data to descri~e one slot. In the
embcdiment, three bits indicate by number the TE. w~ich owns the
slot. A further tw~ bits indicate an ownership descriptor which
is coded as follows:
Bit 6 Bit 7
0 0 Shared P channel slot
0 1 Slot uniquely allocated to one TE.
1 0 Slot is shared by 2 TEs on this AU.
1 1 Framing, Control, Status, Template slot.
The use of the remaining three bits depends on the ownership
descriptor. If the slot forms part of a channel sh.~red with a
second T~, then these three bits indicate the number of that TE.
If the slot is a part of a channel uniquely owned by the TE
described in the first three bits, then the remalning three bits are
used to indicate the number of the channel the slot belongs to.
When a template is transmitted by the AU, the relevant parts of
it must be stored in each TE. In order to reduce the memDry
requirement, a filtered or reduced form of the template is stored at
each TE..... The only ~emplate information each TE requires is a ~ -
definltion of the channels to which it may write data or read data.
It is only the AU which is required to store a complete template.
The filtering of the template for each T2 may be per~ormed at
the TE itself but is preferably performed at the AU by the template
update processor 19 and the port control 17 so that only the
required template data is transmitted to each TE. The processing
capability required of each q~ is thus reduced.
It should be noted that the stored form of the template at each
TE and at the AU will ~e different.
A simple example of a ~ull template will now be described ~Fig.
6), Ln which ~he following channels are allocated:
. :
IVD-TE O has a conventional 2B + D BRI-ISDN organisation.
IVD-TE 1 has B ~ C + D channels
rvD-TE 7 has two B channels
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Thi~teen slots are re~uired to allocate these channels. For
example, slots 0-3 always carry control and t~lace infor~ation and
so slots 4-6 may carry two B channels and a D channel for TE O,
slots 7 and 8 may carry a B and a D channel for TE l, slots 9-14 may
carry a C channel for TE l and slots 15 and ]6 may carry two B
channels for TE 7. The remaining 108 slots wi:Ll be for packet
transfer and accessible at any time by any TE, in accordance with
kno~n requestfgrant and priority arbitra~ion procedlres.
With the template syslem it is thus easily possible to provide
certain TEs with dedicated or at least semi-pe:nmanent channels of
any type while designating other slots of each PF for general packet
use by an~ TE on the LAN. It is also possible to provide TEs with
further ch2nnels on request. For example, if an IVD-TE requests a
voice channel for a certain period, then it can be allocated one by
the AU via a new template as long as sufficient data transfer
capacity is available.
3. Comparator operation '~
During operation of the network with a T~M tran~fer system
described by such a template therefore, and when in addition a ,-
oomparator 14 compares signals SO and FO from a TE link and its
bypass link, a considerable degree of error checking can be -
performed. Since it can be assumgd that ~he data signal SO is error
free, then any errors which arise durLng the passage of the signal
around the IVD termunal loop can be detected by oomparison in
comparator 14 of FO with SO, providing that the data has not b~en
changed by the IVD terminal by a 'write' operation. It should be
ted however that such writ mg will be infrequent and so most data
passed on arou~d the LAN will pass through the bypass link with
associated low bit eDr rates.
At the AU, the foreground template completely identifies those
slots ~lhich each IVD terminal has the right to m3di~y by writ mg to ;
th~m. This information can then be oombined with that from the ;
oompara~or 14 in order to control the switch 12 via the port control
17 so th~ only the data in the slots allocated to the IVD terminal
on that port for writing are swit~hed through to the next port, the
remainder of the slots be1ng switched through from SO. This ensures
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that ~error-free~ data from the hypass shift register is passed on
as much as possible.
In practice, although a TE receives each PF, unless the TE has
write access to a slot then all slots passed on by its ~U port to
the next AU port will have been carried by the bypass linX.
~herefore the signals received by each TE, wherever a TE is placed
in the L~N, will have been carried around the L~N in substantially
error free bypass links. This is p2rticularly true for the error-
sensitive framing and control/status slots.
Using this system each IVD terminal on the L~N is there~ore
substantially isolated from the effects of any co~Iupt links to
other IVD terminals or of faults in other terminals.
Since the number of bit errors at each port can be detected by
the camparators, the LAN of the embodlment also allows fau~ts
resulting in unacceptably high bit error rates to be recognised and
appropriate action to be taken automatically. For example if some
level of bit error rate (BER) is c~nsidered unacceptable and is
exceeded, the appropriate bypass link can be permanently connected
Lnto the network to shut down the corrupted TE loop and to avoid any
risk of disruption to other terminals. In such a shut down
condition the PF signal is still however sent to the IVD terminal
and the comparator can still operate.
In addition, 3ER thresholding techniques can distinguish
various conditions such as disconnection or switching off of the IVD
terminal. If either of these occur for example, the comçarator can
determine reconnection or switching on and thus reconnect the IVD
term~nal link automatically.
Thus the port control means 17 responds to the AU foreground
template 18 to select SO via the switch 12 in all slots to which the
TE 2 does not have write access. Normally the switch 12 selects
FO in slots to which the TE2 does have write access but the control
means 17 will respond to certain error states signalled by the
oomparator 14 to select SO perman~ently.
When the TE link is reconnected it will be necessary to
reinitialise the port. While the bypass link is perm2nently
linked Lnto the network, the AU port is in an initialisation state
and ettenpts to reinitialise itself by matching the T~ link delay to
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the bypass link delay as described earlier. When the TE is
reconnectecl or any TE link fault is corrected, the AU port will
reinitialise automatically and transparen~ly, thus reconnecting the
TE to the L~N with no clisruption at all to any other part of the LAN.
4. Terminal ten~71ate storaqe and data control system
An embod1me~t of the template storage and clata control system :
of a TE is shown in Figure 5. The data is input to the TE via an
ir47ut line fram the send line 35 of the netw~7rkO Initially the
Physical Frame Sync~roniser (PFS) 26 locates slot 0 and aligns the
tIming of the TE with the incc~ng PF at the i~7ut. When
synchronised, the PFS enables normal TE Control and Status L~3ic 21,
which controls all aspects of physical layer logic according to data
receivecl in PF slots 1 and 2, the control and status slots.
Su~7séquently all user data for the TE in each PF is dem~ltiplexed by
a demultiplexer 20 and the framung, control, status, and data for
other TEs are routed directly throuc3h the repeat and loop logic 27
by the control unit 21 to the AU receive line 3R. The data biks 0-3
carried in the slot 3 dedicated to template information, and
containing a channel number ahd a 'me/not me' bit, are sent to a
background template store 25. Each PF carries a portion of a
template, and so a succession of PFs making up a multiframe allows a
whole template to be built up in the backgr~und template store 25.
The te~plate so formed is a background template which may be brought
into the foreground by a template swap command carried by one or
more control slots in subsequent PFs. ;
The template store 22 stores the for~ground template which is
used by the control unit 21 to determine to which slots of each PF
the TE may write.
The TE itself may read and write data received and sent from
its data oontrol system via the octet-wide data cha~nels 23 under
the direction of the foreground template in template store 22.
The data received and sent are timed ~y the control logic 21
respectively through a PF slot demultiplexer 20 and a PF slot
multiplexer 24.
. The repeat and loop logic 27 passes ~ontrol slots and user
slo~s t allocated ~o the TE directly fr~m the L~put lIne 3S to the
output line 3R for return to the AU.
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