Note: Descriptions are shown in the official language in which they were submitted.
W092/~783' PCT/GB~/00~9
Local Time ~enerator ~or a computer
This invention relates to a local time generator for
a computer, to make the local time available when required by
a central processing unit of the computer.
Varlous difficulties have been encountered in the past
in making the local time available to a computer's central
processing unit when re~uired by the latter, without occupying
processiny time.
A particular application where local time is needed
accurately is in a loosely coupled distributed computer system,
where the individual node computers operate in their own
time~rames, but where correction of the time generators of the
nodes is carried out to synchronise these timeframes. In this
case it is desirable for each node to record the time of
receipt of each message over the communications medium from
other nodes, and to apply a timestamp to each transmitted
message so that the receiving node computer can compare the
time of transmission, according to the timeframe of the
transmitting node, with the time of receipt as measured in its
own time frame.
We have now devised a local time generator for a
computer, which makes the local time available when required
by any element or unit of the computer, e.g. a central
' processing unit of the computer.
In accordance with this invention there is provided a
local time generator for a computer, comprising means for
continuously generating signals representing local time, and
a time bus to which said time signals are continuously applied.
In use, the local time is continuously available on the
timebus, and may be used by any unit connected onto the
timebus.
Preferably the local time generator includes at least
one register connected to the timebus. The processor of the
computer, into which the local time generator is fitted, may
at any instant command the register to latch its contents,
, ~35 which then represent the local time at that instant. After
;
W~92/1783' PCT/GB9~/0()~9~
sending thl~s command to the register (referred to herein as the
snap-shot register), the processor can proceed with other
operations and retrieve the recorded time or timestamp from the
register when free to do so. Alternatively, the processor may
command the snap-shot register to indicate when a predetermined
local time is reached: for this purpose the processor loads
the snap-shot register with data representing the set time,
after which the register continuously compares that set time
with the local time appearing on the time bus, until the set
.O time is reached.
The snap-shot register may be arranged to respond to
an input signal for example received via an input interface of
the computer into which the time generator is fitted, to
trigger the snap-shot register to latch into itself the local
time at that instant. The processor can retrieve this record
or timestamp later on.
Any number of snap shot registers may be provided in
the computer so that a number of events may be recorded and
retrieved later by the processor, before the registers are
reset.
The computer into which the time generator is fitted
may comprise a plurality of processors, each with its own data
bus, memory and optionally an input/output interface, plus a
snap-shot register connected to the timebus.
The computer into which the time generator is fitted
may comprise a node computer for a loosely coupled distributed
computer system, in which case it further comprises a
communications unit for coupling the data bus to a
communications medium common to a plurality of such node
computers. Preferably the communications medium has a snap~
shot register associated with it, for the purpose of recording
the time of receipt of each message received over the
communications medium, and for applying a timestamp to each
message which the node computer transmits.
Preferably the node computer compares the time of
receipt of each message according to its own time frame, with
the timestamp carried by that message and representing the time
of transmission, measured according to the timeframe of the
transmitting node computer. If any discrepancy is found
W092/17832 3 ~1~ 7 3~.L
(allowing for transmission time), the time generator of the
node computex can be adjusted automatically to synchronise with
the other node computer(s).
Preferably the adjustment of the time generator is
carried out by altering the rate of change of time for a period
(e.g. changing the rate at which pulses are applied to a
counter), so that no instant of time is missed nor generated
twice.
' PreEerably the time generator is formed as a unit
j lO together with at least one snap-shot register (pre~erably two
snap-shot registers) and preferably as an integrated circuit.
An embodiment of this invention will now be described
by way of example only and with reference to thP accompanying
drawings, in which:
Figure l is a schematic block diagram of a node
computer fitted with a local time generator in accordance with
this invention, the computer being shown in a loosely coupled
distributed computer system; and
Figure 2 is a schematic block dlagram of the local time
generator.
Referring to the example shown in Figure ~, there is
, shown one node computer in a loosely coupled distributed
i computer system. The overall system comprises a plurality of
such node computers connected to a common communication medium
~ 25 MED. Each node computer may comprise a single processor, or
,, as shown it may comprise a plurality of processors one of which
may act as a master supervising the others. In the example
shown, each processor comprises a bus to which is connected
the CPU, memory MEM, an input/output interface I/O, and a snap-
shot register SSR (the function of which will be described).
; The computer bus CBI for one of the CPU's may extend to a
communications unit COMMS which is coupled to the
co~munications medium MED. The bus for each of the other
processors may also be connected to the bus CBI by respective
communications units e.g. CM. This is one of many possible
architectures.
The node computer is fitted with a local time generator
whi~h comprises a time generator TIME GEN, a timebu~ TB and two
snap-shot registers SSRl, SSR2. The snap-shot registers SSRl
WO92/17832 PCT/GB92/00~9~
4 ,_
and SS~ r~o~nected to the timebus: register SSRl is
triggered from the communications unit COMMS and register SSR2
is connected to the databus CBl of the master processor. The
snapshot register e.g. SSR of each of the other processors is
S also connected to the time bus TB.
The time generator continuously generates
signals defining the local time and applies these signals to
the timebus TB: the signals may be updated typically every
l ~s. The timebus TB therefore always carries the current
local time and this is available to all processors and to the
communications unit COMMS via the respective snap-shot
registers. Thus, if during the course of processing any
processor requires the local time, it sends a command to its
snap-shot register: this register latches its contents,
corresponding to the data currently on the timebus; the
register now holds data representing the local time at the
instant the processor made the command; the processor need not
retrieve this data from the snap-shot register immediately, but
, may carry on with further processing and then retrieve the data
! 20 or timestamp when free to do so.
` Alternatively for example, a processor may command its
snap-shot register to indicate when a predetermined local time
has been reached: in this case the register holds data
representing the time set by the processor and continuously
compares this data with the local time data appearing on the
timebus TB: when these two correspond, the register sends an
indicating signal to its processor.
The snap-shot register SSRl is for use solely by the
main communications unit COMMS. In the case of messages
received by the node computer over the communicating medium
MED, the communications unit COMMS can instruct the register
SSRl to record the time of xeceipt of the message, for
retrieval later by one of the processors over the data bus.
In the case of messages sent out over the communications medium
MED from the nod~ computer, the communications unit COMMS can
instruct the register SSRl to record the time of transmission,
so that this can be added as a timestamp to the outgoing
message and also recorded by the transmitting processor.
In the example shown, the time generator TIME GEN and
WO92/17832 5 2
two snap-shot registers SSR1 and SSR2 are formed as a unit o~
a single chip and Figure 2 shows further details. Thus, in
this example the time generator compr.ises a data bus
connectable externally to the data bus CBI of the node
computer: also the timebus may be extended via an external
interface. Snap-shot registers SSR1 and SSR2 are connected
to the data bus and timebus of the chip. A timing system TS
is driven by an external 16 MHz crystal and in turn drives a
52 bit counter COUNT. In essence the timing system comprises
a divider ~. 16) but is adjustable as will be described. The
timebus preferably includes 16 data lines, 4 strobe lines and
a status line and the time signals are applied to the timebus
in multiplex manner: thus the complete data to define the
local time consists of too many bits to be carried
simultaneously on the timebus, so the contents of the counter
(defining the local time) are applied to the time-bus data
lines in four parts in succession, the strobe lines defining
each of the four parts in turn. Each snap-shot register has
a command unit CU which acts to latch the register contents
upon receipt of a signal from an external trigger input TRIG
1 or TRIG 2.
~ he local time held by the counter COUNT may be set or
updated by data written into it from the data bus. The timing
system can be adjusted by an adjustment register AR, f~r
example to synchronize with the timing systems of other node
computers coupled to the same communications medium MED. An
address decode circuit DECODE receives external address and
strobe inputs via a buffer, to drive the adjustment register
AR under the command of a control register CR. The master
processor of the node is able to compare the time of receipt
of any message, against a timestamp contained in that message
and indicating the time of transmission according to the
timeframe of the transmitting node computer. An allowance is
made for transmission time but if any discrepancy is found
between the time frames of the different node computers, the
master processor of the appropriate node runs a known algorithm
to calculate a correction needed to adjust its own timing
generator The correction is applied via the data bus to the
adjustment register AR and thence to the timing system TS.
