Note: Descriptions are shown in the official language in which they were submitted.
.~2 ~ ) 72235-10
BACKGROUND
The subject matter of this invention is related to the
subject ma~ters of inventions of Canadian Patent Application
Serial No. 2,008,589 entitled "Switch Components and Multiple
Data Rate Non-Blocking Switch Network Utilizing the Same" and
Canadian Patent Application Serial No. 2,004,840 entitled
"Virtual Tributary Cross-Connect Switch and Switch Matrix
Utilizing the Same", both of which are assigned to the assignee
hereof.
This invention relates generally to cross-connect
systems for cross-connecting high speed digital signals. The
invention more particularly relates to a modular, non-blocking,
expandable, digital cross-connect system capable of cross-
connecting high-rate digital signals such as DS-3 and SONET
(acronym for "synchronous optical network") and lower-rate
signals such as DS-l, CEPT32, etc., where the lower-rate signals
may be components of the high-rate signals, or may terminate on
low speed lines.
The telecommunications network servicing the United
States and the rest of the world is presently evolving from
analog transmission to digital transmission with ever-increasing
bandwidth requirements. Fiber optic cable has proved to be a
--1--
~1135~0
valuable tool o~ such evolution, replacing copper cable in nearly
every application ~rom large trunks to subscriber distribution
plants. Fiber optic cable is capable of carrying much more
information than copper with lower attenuation.
While fiber optic cable represents the ~uture in
telecommunications, presently there remains an entire
telecommunication network comprised o~ various cable types,
served by equipment o~ di~erent vintages, and run according to
various coexisting transmission standards. While older
standards, cables, and equipment will be eventually phased out,
~or the time being it is necessary that all the old and new
standards, equipment and transmission lines be as compatible as
possible. For example, in a wire plant, every signal should be
connectable to every other signal. To achieve this, it is not
enough to simply multiplex siqnals from lower to high orders and
vice-versa. In addition to a mux/demux/ function, signal format
conversion operations must be per~ormed before connectibility can
be achieved. For instance, a DS-3 signal cannot simply be
connected to an STS-l signal as these signals are at di~ferent
rates and use different multiplexing ~ormats.
The present devices for cross-connection and switchlng
require rate and format conversion means and are typically
incapable of passing the b~ndwidth which ~iber optic cables can
carry. Where wideband switching is attempted, the utilized
devices are often not compatible with each other as they
~.113~ '10
typically employ proprietary signaling schemes. Furthermore, the
equipment conducting the wideband switching is typically limited
in its range o~ sizes and ~ea~ures, thereby making network
expansion di~icult and costly.
In attempting to accommodate the protocols, equipment, and
cables o~ the past while providinq ~or the direction o~ the
~uture, various standards and system requirements relating to
~iber optic cables have been adopted. In particular, the Tl
Standards Committees o~ ANSI hav~ provided a dra~t document ANSI
Tl.105-1988 dated March 10, 1988 which sets ~orth speci~ications
~or a rate and ~ormat of signals which are to be used in optical
inter~aces. Additional details and requirements are set forth in
Technical Advisory publications SR-TSY-000202, -00a233, 000253,
-00~303 Issue 3 o~ Bell Communicatio-n Research (BellCore). The
provided speci~ications detail the SONET (synchronous optical
network) standard. SONEl de~ines a hierarchy o~ mutiplexing
levels and standard protocols which allow e~icient use of the
wide bandwidth o~ ~iber optic cable, while providing a means to
merge lower level DS0 and DSl signals in a common medium. In
essence, SONET establishes a uni~orm, standardized transmission
and signaling scheme which provides a synchronous transmission
~ormat that is compatible with all current and anticipated signal
hierarchies. Because o~ the nature o~ ~iber optics, expansion o~
bandwidth is easily accomplished.
--3--
~i~13~
While the SONET specifications provide standards which in
theory permit cross-connection of high rate digital carrier
signals with other high-rate diqital carrier signals (e.g. DS-3
and SONET), lower-rate digital signals with other lower-rate
signals both carried by the high rate siqnals (e.g. DS-2, DS-l,
CEPT32, ~S-0), and lower-rate signals carried by high~rate
signals with lower-rate signals carried on lower-rate digital
carriers (e.g. add-drop a DS-l from a SONET or DS-3 carrier),
systems for accomplishing the same are not known in the art.
Clearly, then such systems are needed.
SUMMARY OF T~E INVENTION
It is therefore an object of the invention to provide a
crossiconnect system capable of cross-connecting high rate
digital carrier signals, and lower-rate components thereof.
It is a further object o~ the invention to provide a
modular, non-blocking, expandable, SONET compatible cross-connect
system.
It is another object of the invention to provide a modular
SONET-compatible cross-connect system capable of add/drop and
multiplexing functions.
At the outset, it should be stated for purposes herein, that
the term "substantially SO~JET formatted signals" shall be
21 13540
,
understood to be a signal ln SONET form having its vlrtual
tributaries as well as at least the Al, A2, Hl, H2, and H4
overhead bytes defined. In all except the synchronous locked
mode of the SONET signal, the Vl and V2 bytes must also be
defined for the signal to be in substantially SONET format.
The other overhead bytes need not be defined.
In accordance wlth the present invention there is
provided a modular, expandable cross-connect system for high
speed SONET digital signals, comprising: receiving means for
receiving at least one signal formatted in a substantially
SONET format; transmitting means for transmitting at least one
cross-connected substantially SONET formatted signal; cross-
connection means coupled to said receiving means and said
transmitting means for cross-connecting said substantlally
SONET formatted signal from said receiving means to said
transmitting means; said cross-connection means comprising at
least virtual tributary cross-connectlon means, sald vlrtual
tributary cross-connection means comprising, SONET signal
receiving means for receiving a plurality of substantially
SONET formatted signals, including means for disassembling
said substantially SONET formatted slgnals into vlrtual
tributary payloads of tracked phase, and means for cross-
connectlng sald vlrtual trlbutary payloads in space, tlme, and
phase to generate new substantially SONET formatted signals.
In accordance wlth the present lnventlon there ls
further provided a modular, expandable cross-connect system
for hlgh speed SONET dlgital signals, comprising: a plurality
of receiving/transmitting means each for receiving at least
r 72235-lOD
~1 l3J40
one slgnal formatted ln a substantlally SONET format and for
transmltting at least one cross-connected substantially SONET
formatted signal; cross-connection means coupled to at least
two of said receivlng transmitting means for cross-connectlng
said substantlally SONET formatted signal from a first of said
receiving/transmitting means to a second of said receiving/
transmitting means; said cross-connection means comprising at
least a virtual tributary cross-connection means, said virtual
tributary cross-connection means comprising, SONET signal
receiving means for receiving a plurality of substantially
SONET formatted signals, includlng means for disassembllng
said substantially SONET formatted signals into virtual
tributary payloads of tracked phase, and means for cross-
connecting sald vlrtual tributary payloads in space, tlme, and
phase to generate new substantially SONET formatted signals.
Preferably the system also lncludes at a
transmltting means for taking the substantlally SONET
formatted signal and transmittlng lt over one of a DSn, CEPTn
or STSn compatlble llne. Where the slgnal is to be
transmltted over a line other than a STSn compatible llne, the
substantlally SONET formatted slgnal must be approprlately
converted by a converslon means lnto an approprlate format.
In one embodlment, the switched, converted
substantlally SONET formatted slgnal is included as part of an
outgolng SONET
72235-lOD
~ ~ ~ 35'~ 72235-10
_,
signal, and a SONET transmitting means is provided to properly
format the entire signal including the converted, switched
signal, in~o a SONET signal for transmission. In another
embodiment, an add/drop means is utilized to at least partially
disassemble the substantially SONET formatted signal so as to
obtain therefrom a virtual tributary or a portion of a virtual
tributary and to couple the obtained signal to an external
transmission medium.
The switching means for cross-connecting the
substantially SONET formatted signal may comprise either the
wide-band cross-connect (WBX) component disclosed and claimed in
copending Canadian Patent Application Serial No. 2,008,589 or
the virtual tributary cross-connect component (VTX) disclosed
and claimed in copending Canadian Patent Application Serial No.
2,004,840, or both.
Among the various components that may be utilized in
the system are the WBX, the VTX, a DS-3/SONET converter, a
SONET bus interface, add/drop multiplexers, a SONET path
terminator/originator, a SONET3/1 mux/demux, a scrambler/-
descrambler and SONET24/3 mux/demux, a SONET line interface,and a DS-3 line interface. All components except for the VTX
are capable of working in "forward" and "reverse" modes. The
DS-3/SONET converter can take a DS-3 signal, break it into
twenty-eight DS-l signals, and stuff each DS-l into a virtual
tributary of a substantially SONET formatted signal, as well as
accomplishing the inverse, or take the entire DS-3 signal and map
~il3~
it as speci~ied into a substantially SONET ~ormatted signal. The
SONET bus inter~ace is a serial/parallel converter which takes a
serial SONET siqnal and produces a byte parallel SONET signal
with a byte and mu'ti~rame clock on a parallel bus. The add/drop
multiplexers basically drop o~ the contents o~ virtual
tributaries to an ~xternal transmission line in one direction and
add in~ormation ~rom external transmission lines by converting
them into VTs in the other direction. A ~irst add/drop mux is an
async add/drop mux which permits DS-l signals to be coupled into
SONET asynchronous mode VTs which can then be cross~connected
into SONET or DS-3 signals. A second add/drop mux is a sync
add/drop mux which permits adding and dropping DS-l signals to
and ~rom byte synchronous VTs. A third add/drop mux permits
add/drop o~ individual DS-0 channels ~rom byte synchronous mode
VTs. Additional add/drop multiplexers can be utilized to
add/drop data to/~rom CEPT channels, etc.
A typical SONET line inter~ace receives a 1.2 gigabit bit
serial STS-24 signal and provides a hyte parallel output with a
STS-3 rate byte and ~rame clock. The scrambler/descrambler and
SONET24/3 mux/demux provides scrambling and parity check
~unctions a.s well as taking the SONET STS:24 signal and clocks
~rom the line inter~ace and providinq eight constituent SONET
STS-3 signals there~rom. The eight STS-3 signals are sent to the
SONET3/1 mux/demux which takes a STS=3 signal and provides the
three constituent SONET STS-l signals there~rom. The SONET STS-l
signal is sent to the SONET path terminator/originator which
~ --7--
t~ ~13~~
interprets some o~ the path and transport overhead, zeroes out
most o~ the overhead bytes, and sends the remaining signal to the
cross-connect matrix stages. On the outgoinq side, the
terminator/originator accepts a signal ~rom the matrix stages,
inserts the path and transport overhead bytes and recalculates
the pointer ~or the SONET payload envelope. The DS-3 line
inter~ace inter~aces the system components with a DS3 channel by
pe~r~emin-3 clock recovery, bipolar/unipolar conversions, B3ZS
encoding/decoding, automatic gain control, equalization control,
and bipolar violation counting.
The modularity of the system components permits a mixing and
matching o~ components in order to obtain systems o~ various
complexities and capabilities. For example, a rather .simple use
o~ the system would be to convert a DS-3 signal into a SONET
signal. To accomplish the same, the ~ollowing components would
be utilized: a DS-3 line inter~ace; the WBX (i~ desired); a
DS3/SONET converter; and the ~ront end components (typically the
SONET path terminator/originator, SONET 3/1 mux/demux,
scrambler/descrambler and SONET24/3 mux/demux, and SONET line
inter~ace) as required. The DS-3 signal would be received by the
DS-3 line inter~ace and be properly processed. The processed
signal is connected (via the WBX, i~ desired) to the DS3/SONET
converter where it would he stu~ed into a substantially SONET
formatted signal. The substantally SO~ET ~ormatted signal would
then be connected (again via the WBX, i~ desired) to the SONET
path terminator/originator ~or ~ront end processing.
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21~3~0
Another simple use o~ the system would be to cross connect
DS-l signals. To accomplish the same the ~ollowing components
would be utilized: an async add/drop mux, a SONET bus inter~ace,
and the VTX. ~rhe async add/drop mux would take the DS-l signal,
convert it to substantially SONET ~ormat (i.e. virtual tributary)
and ~orward it to the bus inter~ace. The bus interface would
re~ormat the signal and ~orward it in its virtual tributary ~orm
to the VTX which would switch the converted DS-l signal into a
~ull-sized substantially SONET signal. The SONET signal would
then he sent back through the SONET bus inter~ace to an add/drop
mux at a desired location. The add/drop mux would cause the
virtual tributary to be dropped and reconverted into a DS~l
siqnal.
A more complex use o~ the system might be to take a SONET
signal, cause some virtual tributaries to be used as part o~ a
DS~3 signal, others to be used as part o~ a SONET signal, and yet
others to be used as individual DS-l signals. To accomplish the
same, all o~ the components would be utilized. The front end
components would receive the SONET signal and eventually ~orward
it either directly to the VTX or to the ~X. I~ used, the WBX
would ~orward the signal appropriately to the VTX where various
new SONET signals would be generated. A ~irst new SONET signal
carrying some o~ the original VTs would be sent via the WBX (i~
used) to the ~ront end circuitry and sent as a SONET signal. A
second new SONET siynal containing other original VTs would be
2~135~0
sent to the DS3/SONET converter where a DS3 signal would be
generated. The DS3 signal would be sent out over a DS-3 line via
the WBX (i~ used) and the DS3 line inter~ace. Yet other virtual
tributaries co~ld be included in a third new SONET signal which
would be ~orwarded to a desired add/drop mux via the SONET bus
inter~ace. At the add/drop mux, one or more virtual tributaries
would be dropped and converted into DS-l signals.
Additional objects and advantaqes o~ the invention will
become apparent to those skilled in the art upon re~erence to the
detailed description in conjunction with the provided Figures.
BRIEF DESCRIPTION OF THE DRAWINGS
~ igure 1 is a block diagram o~ a modular, non-blocking,
expandable, digital cross~connect system o~ the invention
permitting the cross-connecting o~ high-rate digital signals such
as DS-3 and SONET and lower:rate siqnals such as DS-l, C~PT32,
etc., regardless o~ whether or not the lower-rate signals are
components o~ the high-rate signals;
Figure 2a is a block diaqram o~ the transmit side of the
scrambler/descrambler SONET~4/3 mux/demux component o~ the
invention;
Figure 2b is a block diagram o~ the receive side o~ the
--10-
3~0
scrambler/descramber SONET24/3 mux/demux component o~ the
invention;
Figure 3a is a block diagram o~ the transmit side o~ the
SONET3/1 mux/demux component o~ the invention;
Figure 3b is a block diagram o~ the receive side o~ the
SONET3/1 mux/demux component o~ the invention;
Figure 4 is a block diagram o~ the SONET path
terminator/originator component of the invention;
Figure 5 is a block diagram o~ the DS3 line inter~ace
component o~ the invention;
Figure 6 is a block diagram o~ the SONET bus inter~ace
component o~ the invention;
Eligure 7 is a block diagram o~ the add/drop mux/demux o~ the
invention;
Figure 8a is a block diagram diagram o~ the architecture o~
the basic component o~ the wide band cross~connect (WBX)
switching component o~ the invention;
Figure 8b is a logic diagram o~ a section o~ a switching
matLix for use in the basic component o~ Figure 5a;
~113~0
Figure 8c is a block diagram of an eighty port two stage
non-blocking WBX switching network indicative of the utilization
of twenty_six basic switching components;
Figure 9a is a block diagram o~ the architecture o~ the
basic component o~ the virtual tributary cross-connect (VTX)
switching module of the invention;
Figure 9b is ~ block diagram o~ the pointer calculation
means, the memory means and the comprison means o~ the basic
switching module o~ Figure 9a;
Figure 9c is a block diagram o~ a VTX switch network column
utilizing a plurality of identical basic virtual tributary
cross-connect switching components; and
Figure 10 is a block diagram o~ the DS3/SONET converter
component of the invention.
nETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
- Turning to Figure 1, a block diagram containing all o~ the
primary components o~ the modular, non-blocking, expandable,
digital cross~connect system 1~ of the invention is seen. At the
outset, it should be appreciated that all the components need not
be present in order to practice the invention. The invention
3~
.~
envisions using various subsets o~ the provided components in
order to provide various ~unctions. It is the modularity and
expandability o~ the components which provides the practitioner
with the power~ul ability to increase both ~unctionality and
throughput as desired. It should also be recognized that while a
controller 20 is required to act as the "brains" o~ the system
10, the controller 20 is not considered part o~ the invention.
Indeed, various controllers are known in the art, and it is
considered within the capabilities o~ one skilled in the art to
provide or adapt a controller ~or use with the system invention.
In essence, there are ten ~unctional components o~ the
invention, with one of the ten (the add/drop mux) taking many
embodiments. Four o~ the ~unctional components, the SONET line
inter~ace 100, the scrambler/descrambler SONET24/3 mux/demux 200
(hereina~ter "scrambler"), the SONET3/1 mux/demux 300
(hereina~ter "3/1 mux"), and the SONET path terminator/originator
400 (hereinafter "SPT") are considered SO~ET "~ront end"
components. Pre~erably, each, except the scrambler, is capable
of interfacing with particular SONET lines as well as conducting
all o~ the ~nctions o~ the ~ront end components which are in
~ront o~ it. For example, the 3/1 mux 300 is capable o~
inter~acing with a SONET-3 line and o~ conducting the ~unctions
o~ the scrambler 200 and SO~'ET line inter~ace 100 ~or a SONET-3
line.
-13
CA 02113~40 1998-04-06
The SONET line interface 100 is preferably an
integrated circuit chip manufactured by Vitesse Company of
Camarillo, California under the designation *Vitesse 8010.
The basic function of the SONET line interface 100 is to
interface with the 1.2Gbit STS-24 line, find the framing
pattern governing the line, and provide a SONET formatted byte
parallel output at an STS-3 rate. In conjunction with the
byte parallel output, the Vitesse 8010 provides a byte and
frame clock.
The basic functions of the scrambler 200 on the
receive side is to descramble the received byte-parallel STS-
24 signal, conduct a parity check on the Bl byte of the SONET
frame, and demultiplex of the STS-24 signal into eight STS-3
signals. On the transmit side, the scrambler 200 multiplexes
up to eight STS-3 signals and scrambles the signals. As
preferably implemented, the scrambler 200 is capable of
processing both STS-24 and STS-12 signals. The scrambler can
also facilitate an N+l fault recovery mechanism by providing a
ninth STS-3 signal input/output to which one of the STS-3
signals can be routed in the event of internal component
failure of a 3/1 mux 300 or an SPT 400.
The 3/1 mux 300 basically demultiplexes an STS-3
signal into three STS-1 signals on the receive side, and
multiplexes three STS-l signals into an STS-3 signal on the
transmit side. However, additional capacity is preferably
built into the 3/1 mux so that it can conduct parity checking
and scrambling and
* Trade-mark
- 14 -
72235-lOD
~ 3~U
descrambling so that the 3/1 mux 300 can act as a line inter~ace
to an OC3 (SONET STS-3) line via a parallel to serial conversion
such as that conducted by the Vitesses 8010.
The SPT 400 takes incoming SONET STS-l signals and routes
most o~ the path overhead and transport overhead to a
microprocessor ~or processing while zeroing out that overhead ~or
purposes o~ the data stream. Where the tra~fic on the two data
communication channels is small, the SPT 4~0 provides some HDLC
processing. On the transmit s;de, the SPT 400 inserts path and
transport overhead into the substantially SONET ~ormatted signals
it receives. It also recalculates a SONET payload envelope
pointer, as the SPT basically inter~aces the time ~rame o~ the
internal system 10 to the time ~rame o~ the external
telecommunications network. Pre~erably, the SPT 400 also has the
capabilities o~ scrambling/descrambling, parity checking and line
inter~ace, so that it can be used as a line inter~ace to an STS-l
line.
Another ~ront end component o~ system 10, is the DS*3 line
transmitter/receiver S0~ (hereina~ter "DS3RT"). The DS3RT 500
serves as an inter~ace between the system 10 and a DS:3 line o~
the telecommunications networ~. The DS3RT 5~0 receives a bipolar
B3ZS line signal at 44. 736 MHZ, decodes the signal, conducts a
bipolar to unipolar conversion, and provides automatic gain
control and error rate counting. On the transmit side, the DS3RT
conducts a B3ZS encoding and a unipolar to bipolar conversion.
-15-
~3~'10
The l~st "front end" components ~or the systeln 10 are the
SONET bus inter~ace 600 (hereinafter "SBI") and the various
add/drop multiplexers 700a, 700b,... (hereina~ter "ADMs") which
may also be considered "rear end" components. The SBI 600
provides essentially the same ~unctions as the Vitesse 8010
component 100 except it inter~aces with an STS-l signal instead
of an STS-24 signal. Thus, on the transmit side (out o~ the
system), the SBI 600 takes a serial SONET signal and produces a
byte parallel SONET signal with byte and multi~rame clocks on a
parallel bus, while on the receive side (into the system), the
SBI 600 produces a bit serial SONET signal ~rom the byte parallel
signal. In addition, it extracts certain channels of the
recovered signal that are used in data transmission and teleohony
signalling applications and inserts this in~ormation into the
substantially SONET ~ormatted signal.
The ~unction o~ the ADI~s 700 is to inter~ace the system 10
which utilizes substantially SONET ~ormatted signals with various
lower rate lines, including DS-0, T-l, T-lc, T-2, CEPT, etc.
Thus, each ADM i~s particular to the type o~ line with which it
inter~aces. ADM 700a inter~aces with a DS-0 line. Hence, ADM
700a must inter~ace with a synchronous virtual tributary, and
must be capable o~ adding or dropping a DS-0 channel ~rom such a
synchronous virtual tributary. ADM 700b inter~aces with an
asynchronous T-l line. Hence ADM 700b is capable o~ adding or
dropping an asyn~hronous virtual trib~tary ~rom a SONET signal.
-16
~-13J~
In a similar manner ADM 700c can add or drop a locked mode
virtual trihutary into or ~rom a SONET signal, while ADM 700d can
add or drop a CEPT signal into or ~rom a SONET signal.
The switching components in the system 10 include the wide
band cross connect switching network 800 (hereinafter "WBX") and
the virtual tributary cross-connect switching network 900
(hereinafter "VTX"). The WBX is a non-blocking folded Clos
switching network constructed out of a plurality of identical
.switch components. The switching network permits simultaneous
switching of digital signals having different data rates,
provided, of course, that signals of like composition are
cross-connected. Expansion of the WBX 800 is accomplished by
adding additional stages of the identical switch components.
Clock skew and signal error due to the multiple stage switch
network are eliminated by regenerating a clock signal associated
with the data at each stage of the network.
The VTX 900 is also a non blocking switching network
comprised of a plurality of identical switch components. The VTX
receives substantially SONET formatted signals, and switches the
VTs of the SONET signal in space, time, and phase to create new
substantially SONET formatted signals. Expansion of the
switching network 900 is accomplished by adding additional
identical switch components.
-17-
~ll3~4~
The last primary component o~ the entire system 10, is the
DS3/SONET converter 1200. The DS3/SONET converter 1200 serves in
either o~ two capacities. In a first mode, the DS3/SONET
converter 12~0 receives a DS-3 signal (as processed by the DS3
line interface 500) and stuffs the signal into a substantially
SONET formatted signal. In a second mode, the DS3/SONET
converter 1200 receives the processed DS-3 signal, breaks the
signal into its component parts (typically ~S-l signals), and
stuffs the component parts into SON~T ~ormatted virtual
tributaries. In either mode, the DS3/SONET converter 1200 also
accomplishes the inverse functions. Also, in either mode, it
accomplishes error and bit parity monitoring functions.
As will be discussed hereinafter, various subcombinations of
the various components o~ system 10 provide different
capabilities. The modularity of the system 10 permits a user to
determine which components are pertinent to the user's particular
requirements and to arrange those components in a desired
arrangement. However, the modularity also permits the user to
add identical or different components should the required
throughput or capabilities change over time.
Turning to Figures 2a and 2b, the details of the transmit
and receive sides of the scrambler 200 are respectively seen. As
seen in Figure 2a, scrambler 2Q0 is substantially divided into
two nearly identical sections 201a and 201b, each of which is
capable o~ multiplexing four STS-3's at 38.88 M~ibble/sec into a
-18-
CA 02113~40 1998-04-06
single STS-12 at 77.76 Mbytes/sec. The Mux8 control line 205
is utilized to control whether two STS-12 signals. are then
multiplexed together as a single STS-24 signal at 155.52
Mbytes/sec.
The STS-3 input blocks 210a - 210e of scrambler
section 201a accepts four bit nibbles of data with the most
significant nibble being received first. The blocks form the
nibbles into bytes which are placed onto a transmit byte bus
212 under timing control of 4:1 controller 214 which
sequentially enables each block. The input blocks 210 of
section 201b are identically controlled, except that section
201b includes only four input blocks. Thus, section 201a is
seen to have a spare input block 210e which provides
redundancy in case any of the other eight input blocks 210 are
not properly functioning. The spare is told via the spare
code control line 214, which of the eight input blocks it is
replacing. This information is required, as each of the input
blocks encodes SONET C1 bytes indicative of the STS01 signals
it is processing (values of one to twenty-four).
The 4:1 controller 214 utilizes the muxframe* 221
and a 77.76 MHz clock 223 in controlling the input blocks 210
of section 201a. The muxframe signal is used to set the
frame of the resulting generated SONET-12 and is a delayed
version of the muxframe signal 222 which is generated by the
receive section of the scrambler 200. The 77.76 MHz signal
223 is derived from a 155.52 MHz clock 225 which is divided by
divider 227. The 77.76
*Trade-mark
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72235-10D
21~35~
, .
MHz signal is used as the scanning rate of the input blocks 210
by 4:1 controller 214. Where the spare input block 210e is being
utilized, the controller 214 switches the control leads ~rom the
replaced input to the spare block 210e. I~ the spare is to
replace a block in section 201b, spare block 210e is connected to
the byte bus o~ section 201b. Also, i~ the spare block 210e is
to replace block 210a in section 201a, the spare hlock 210e must
be connected to bus 229 which sends bit interleaved parity
information from output driver 240 to the input block generating
the SONET l B2 byte. The B2 byte, which is located in STS-l #1,
contains the bit interleaved parity o~ the previous ~rame. The
bit interleaved parity information is deterrnined in the output
driver block 240 after scrambling is accomplished by scrambling
means 250.
The purpose o~ the scrambler means 250 is to improve the
statistics of the output signal. Scrambler means 250 receives
the muxframe* control 221, the 77.76 ~1Hz clock 223, disable
scramble control 253, mux8 control 205, and the S12 control 257
which indicates when the twelfth STS-l signal has been scanned by
controller 214. Scrambler 250 also receives all the data from
the input blocks 210, and based on the various control signals,
properly scrambles them and ~orwards them to output bu~Eer 260.
Output buf~er 260, under control of 8:1 controller 262
accommodates the multiplexing of the two STS 12 signals, as a
silnilar ~utput buE~er is lo~ate in section 2Ulb.
-20-
113~
As is indicated in Figure 2a, the output driver 240 and 8:1
controller 262 are common to both sections 201a and 201b of the
transmit side of scrambler 200. As aforementioned, the output
driver calculates the value of the BIP-8 byte over the entire
frame of the STS-12 or STS 24 signal. The output driver also
provides proper timing and waveforms to the output which will
either assume a 77.76 or 155.52 MByte/sec signal depending on the
mux8 control signal (i.e. whether a STS-12 or STS-24 signal is
being generated).
Turning to Figure 2b, the receive side o~ scrambler 200 is
seen in some detail. The recelve side, in a manner similar to
the transmit side, is substantially divided into two sections
270a and 270b. Common to both sections 270 is an input retiming
block 272 and 8:1 demux control 273. The demux control 273 is
active only when the mux8 control 205 is true. Otherwise, demux
control 273 and section 270b are powered down. Demux control 273
demultiplexes the incoming STS-24 signal into two STS-12 signals
which are then demultiplexed into two sets of four STS-3 signals
under control o~ the 4:1 controllers 278. Controllers 278
utilize a ~raming signal received ~rom the input retiming block
272 in accomplishing the same.
The retiming block 272 receives an STS-24 signal as eight
STS-3 signals with eight bit bytes on up to eight leads (DINs
1-8) 274a - 274h. It also receives a byte clock 275 at 77.76 or
155.52 MHz depending vn the mux8 si(3nal 205, an~ a ~raming pulse
72235-lO
signal 276 coincident with byte A2 of STS-l #7 (i.e. the third
byte after the start of the frame). The output of retiming
block 272 ~re clock signals to the 4:1 demux 278, and data to
input buffer 280. Buffer 280 stores the incoming data and
retransmits it to a descrambling means 282.
Data from the descrambler is forwarded to STS-3 output
blocks 290 which receive the STS-3 signals at 19.44 Mbytes/second
and output signals at 38.88 MNibbles/second. When scrambling is
enabled, the STS-3 output block 290a performs parity error
calculations from the Bl byte and from the BIP-8 signal received
from the input retiming block 272. As with the transmit side,
the receive side of scrambler 200 includes a spare block 290e
for allowing possible failure on one of the other blocks. If
the spare block replaces output block 290a, it must perform the
parity check and error insertion for STS-l #1. If the spare
block replaces an output block in section 270b, the byte bus
of the spare output is connected to the byte bus of the lower
4:1 demux control.
A block diagram of the transmit side 301a of the 3/1
mux component 300 is seen in Figure 3a. On the transmit side,
data is received by three serial/parallel converters 310a - 310c
from three SPTs (see Figure 4~ as bit serial data clocked at
51.84
-22-
CA 02113~40 1998-04-06
MHz. The serial/parallel converters 310 convert the STS-1 bit
serial signals into STS-1 byte parallel signals and place the
bytes on byte bus 314 under the control of STS byte number
generator 318. The STS byte number generator 318 is able to
control the serial/parallel converters 310 because it receives
a delayed system frame clock 321 and a 51.84 MHz clock 323 and
generates therefrom the timing for the bytes from the three
serial/parallel converters. The 51.84 MHz clock 323 is
received from a clock generator 327 which divides an available
155.52 MHz clock by three. The system frame clock (SYS
FRAME), on the other hand may either be generated internally
from a frame indication input (MUXFRAME), or may be directly
available.
In controlling the signal flow, the STS byte number
generator 323 enables each serial/parallel converter 310
cyclically. Because the three STS-1 signals arrive in sync,
serial/parallel converters 310b and 310c are provided with
associated storage means 311b and 311c which prevent overflow
while permitting the converters 310b and 310c to wait their
turns. The STS byte number generator 323 also sends its byte
clock and system frame to the output driver block 325. The
byte clock is set at 19.44 MHz (three-eighths the 51.84 MHz
clock) except when the Nibble control input 329 is at ground;
then the byte clock is set at 38.88 MHz (three-quarters the
51.84 MHz clock). The output driver block 325 retimes as
necessary and provides TTL outputs. The output driver 325,
the byte clock and frame as inputs (via STS byte number
generator 318), as well as the data byte bus 314 and nibble
control 329.
- 23 -
72235-lOD
CA 02113~40 1998-04-06
When the nibble control 329 is at ground, only three output
pins of the driver 325 are utilized and bytes are transmitted
as two four-bit nibbles at 38.88 MNibbles/sec which is twice
the byte rate. A second control 337 is set when scrambling is
required (i.e. the component 300 is to interface directly with
an STS-3 line). In such situations, BIP-8 is calculated and
passed to the STS-1 number one block 310a, scrambling is
enabled, and all eight output pins of driver 325 are utilized
for transmission of eight-bit bytes at 19.44 Mbytes/sec.
As previously indicated, the 3/1 mux component 300
also has the capability of scrambling the signal which is to
be transmitted so that the component can interface with a STS-
3 line. Thus, scrambler controller 330 is provided, along
with ROM 332 and an XOR block 334. The scrambler controller
330 controls the ROM addressing so that framing bytes and STS
identification bytes do not get scrambled. The ROM 332
provides a look-up table for byte-wide scramble values and
provides an output to the XOR block 334 at the falling edge of
the byte clock. The XOR block basically adds in module two
the data coming from byte bus 314 with the eight bits of data
from the scrambler ROM 332. Where scrambling is not required
(i.e. where the output of 3/1 mux component 300 is to the
scrambler 200), the ROM outputs only zeroes. In this matter,
the XOR block 334 passes the data bytes to output driver 325
unaltered.
- 24 -
72235-lOD
~1135~~
Turning to Figure 3b, the receive side o~ the 3/1 mux
component is seen. The incoming signal, when received ~rom a
STS 3 line, is r~ceived ~s a scramiled ~i~ht-bit par~llel ST~'3
si~nal, with a mux ~rame clock indicating the ~irst byte o~ the
~rame. Where the incoming signal is received ~rom scrambler
component 200, the received signal is an unscrambled fourebit
nibble signal. Reg~rdless, the input retiming block 350 receives
th~ ~at~ si(3nal, c~ntroLs signals and clocks, ~nd ~Jenerates its
own controls and clocks while outputting the data signal to XOR
block 352. In particular, where descrambling must be
accomplished, a BIP~8 value is calculated and sent to the STS~l
#1 transmit block 370a ~or a parity check. Likewise, a scrambler
enable control siqnal 353 is sent to the scrambler control 355 o~
descrambler 360, which is comrised o~ scrambler control 355, ROM
357 and XOR block 352. The scrambler control 355, ROM 357 and
XOR block 352 all ~unction in manners similar to their
counterparts on the transmit side o~ the 3/1 mux compoent 200.
Thus, where descrambling is required, XOR block 352 per~orms its
modulo two ~uncti(~n on the incomin~ d~ta on d~ta bus 375 (nihble
signals heing converted to byte ~ormat) and values provided by
ROM 357 under control o~ scrambler control 355. Where
descrambling is not required, zeroes are provided by ROM 357 to
XOR block 352 and the data passes unprocessed to the
parallel/serial converters 370. The parallel/serial converters
370a, 370b, and 370c are essentially identical, and convert the
parallel signals on bus 353 into serial 51.84 MHz data and clock
signals which are sent to SPT components 400.
-25-
~ 5 40 72235-10
The SONET path terminator (SPT) component 400 of the
invention lS seen in block diagram form in Figure 4. On the
receiving end, a bit-serial SONET STS-l signal at 51.84 Mb/s
and a clock are received on lines 401 and 403 by the line-sync
block 404 which searches for and tracks framing bytes Al and A2
of the SONET frame. Line sync block 404 sends the transport
overhead bytes of the SONET signal along with their byte number
to the transport overhead receive control 406 (TOH RX). Line
sync block 404 also monitors for loss of signal, loss of frame,
loss of pointer, and receives the STS-line Alarm Indication
Signal (AIS). The detection of loss of signal, frame, or pointer
causes a bit to be set in the status register of the exception
report handler block 412 which results in later action, as well
as causing immediate insertion of STS-path AIS forward, as
required. AIS is cleared when the condition clears. Where the
SPT is used as a direct interface to an STS-l (OC-l) line, the
line sync block also conducts BIP-8 Bl parity generation and
checking and line descrambling.
The transport overhead bytes received by the TOH RX
406 are preprocessed by conducting simple functional tasks, and
routing signals to other modules for further processing. The path
overhead relating to the virtual tributaries in the STS-l signal
CA 02113~40 1998-04-06
is forwarded to the path overhead receive control (POH RX)
408, while other signals are delivered to the datacom receiver
410 and the report handler 412. The TOH RX 406 also generates
signals for the orderwire and exitdata ports 411 and 413, and
returns some data signals into the data path via TOH RX mux
415. The POH RX 408 module functions in much the same way as
the TOH RX 406 in that it extracts information from incoming
bytes, routes the information to appropriate support modules
and back into the data stream (via POH RX mux 417), and passes
most of the data onto the next stage. In particular, the data
stream is sent to the network parallel/serial converter 420
which takes the byte data stream signal and converts it into a
bit serial 51.84 Mbit/sec signal for transmission to a
switching (cross-connect) component.
The transmit side of the SPT 400 is basically the
same as the receive side except that instead of stripping and
analyzing the overhead, the transmit side inserts overhead
into a substantially SONET formatted signal. The SPT 400
receives at its network frame sync (NFS) module 430 a bit
serial 51.84 Mbit/sec data signal 431 typically from the WBX
800 or VTX 900 along with a synchronized clock signal 433.
The NFS module searches for and locks to the synchronization
dictated by SONET bytes A1 and A2, and uses the SONET byte
locations to extract the SONET payload envelope as well as to
keep track of the frame byte numbers of the incoming data.
The NFS also monitors for loss of signal, frame, and pointer,
and for the network STS-path AIS, any of which causes
specified condition bits to be set. The data bytes of the
- 27 -
72235-lOD
CA 02113~40 1998-04-06
received signal are then passed to the next stage of the
transmit side via the path overhead transmit mux (POH TX) 445.
However, the byte location information is sent to the path
overhead transmit control 436 so that bytes J1, C2, G1, F2,
Z3, Z4, and Z5 can be added to the substantially SONET
formatted signal via POH TX mux 445. In addition, the POH
transmit control 436 calculates BIP-8 B3 for the received
signal so that any errors can be reported to the exception
report handler 412 and further recalculates a new BIP-8 B3 for
insertion into the SONET signal.
In addition, the POH TX control 436 conducts pointer
calculations to permit the envelope of the outgoing line STS-1
signal to be formed. The SONET payload envelope signal
received must be retimed to the selected line output clock by
the recalculating of a new STS-1 pointer value. Bit and frame
clocks for the new output STS-1 signal may come from external
or internal sources. Thus, new values for the STS-1 pointer
bytes H1, H2, and H3 are provided, and a small FIFO is
included to allow for stuff operations on the outgoing signal.
The resulting signal exiting the POH TX mux 445 is an STS-1
signal properly timed to the line output clock, with a proper
SPE, proper path overhead information, and with "old" transmit
overhead information. The TOH information, however, is
replaced at the TOH TX mux 447 by the TOH TX control 438.
The TOH transmit control module 438 conducts the
final signal processing needed for the generation of an output
STS-1 signal. Its sole required calculation is of the BIP-8
B2 parity, although it can insert new TOH overhead bytes as
- 28 -
72235-10D
CA 02113~40 1998-04-06
desired. The new bytes are inserted into the STS-1 signal at
TOH transmit mux 447, and the STS-1 byte signal is sent to the
line parallel to serial converter 450 which converts the
signal into a bit serial 51.84 Mbit/sec STS-1 signal with an
accompanying clock signal.
As previously indicated, the exception report
handler (ERH) 412 is provided to detect specified changes in
system information. Upon detection of changes, the ERH flags
the control system via processor interface 455 and provides
the status information (contained in associated RAM 452) to
the control system. Contained within the ERH RAM space are:
a status byte including a test bit for test mode, an error bit
and a parity bit; RX and TX control and routing bits; current
TX values for TOH/POH control bytes; RX last and current
values of the TOH/POH control bytes; 64 bytes of a J1 buffer;
192 bytes of TX frame buffer; and 192 bytes of RX frame
buffer.
Also provided in the SPT module 400 are the datacom
RX module 410 and the datacom TX module 440 which provide for
both receiving and generating a single packet at a time on
either the Section or Line datacom channels (found within the
SONET TOH). For applications where small volumes of message
traffic are anticipated, these internal modules are adequate,
while for
- 29 -
72235-lOD
~ 0 72235-10
applications requiring larger message volumes, ports to external
datacom receive and transmit circuits are provided.
~ s described above, the DS-3 line interface component
500 generally transmits and receives a bipolar B3ZS line signal
at 44. 736 MlHz. On the receive end, component 500 conducts a
bipolar to unipolar conversion, decodes the line signal, and
provides automatic gain control and error rate counting. On
the transmit side, the DS3RT conducts a B3ZS encoding and a
unipolar to bipolar conversion. In order to accomplish these
tasks, the received signal is fed to threshold detectors 505
which detect and report the presence of positive and negative
pulses as well as reporting loss of signal if no threshold is
exceeded for about ten milliseconds. When a threshold is
exceeded, the detectors send the data and a positive or negative
indication to B3ZS receiver 410. The B3ZS receiver 510 detects
bipolar violations and notifies the bipolar violation counter
515 of the same, and conducts the bipolar-unipolar conversion.
The unipolar data is then sent to data/clock alignment means 520
which associates a clock with the unipolar data, and sends the
clocked data to output select circuit 525. The output select
circuit 525 switches the DS-3 signal and clock to one of two
outputs to provide alternate paths for the signals should that
be necessary. Of course, instead of sending the DS-3 data out
via the output select 525, the data may be looped back via
loopback circuit 5 30.
-30-
~,~,"113~40 72235-10
On the transmit side, DS-3 data being received by
interface component 500 is received at input select 540 and is
forwarded Ito AIS generator 545. AIS generator 545 generates the
AIS alarm when the received data meets certain criteria. The
AIS alarm is also generated when a lo-ss of signal is recognized
by the threshold detectors 505. Data leaving AIS generator 545
is forwarded to the B3ZS transmit block 550 which examines the
clocked data and determines which zeroes must be changed to ones,
and what the polarity of each binary one should be. That
information is forwarded to line driver 555 which generates the
bipolar B3ZS coded DS-3 signal.
Turning to the "back end" components of system 10, one
embodiment of the SONET bus interface 600 of the system is seen
in Figure 6. In essence, the SONET bus interface 600 is a
serial/parallel converter which converts a bit serial
substantially SONET formatted STS-l signal into a byte parallel
substantially SONET formatted STS-l signal. The SONET bus
interface 600 receives the SONET data signal and block signal at
the frame sync block 605 which searches for the framing bytes Al
and A2, as well as monitoring for loss of frame. The received
data is buffered and presented in byte format, along with a byte
CA 02113~40 1998-04-06
number and byte clock to the parity error circuit 610. Parity
error circuit 610 performs a continuous B3 error count. When
the control signal OUTPUTENA is active, the current error
count of parity error circuit 610 is presented to a system
controller (not shown) via eight bit line ERRORCT. When the
control signal RESET is active, the current error count is
reset to zero.
The bytes of the SONET signal, along with the byte
clock and receiver 51.84 Mb/s clock are then sent to the
receive section of parallel bus interface 620. The receive
section outputs the data bytes on the output bus 622, and
generates a byte clock and a multiframe clock which are
respectively output on buses 626 and 630. The period of the
multiframe clock is that of the received multiframe signal H4
and the multiframe clock is synchronous with the H4 signal.
If the multiframe signal is absent, the parallel bus interface
620 generates a four-frame multiframe on its own.
On the transmit side of parallel bus interface 620,
information from add/drop multiplexers 700 is received via the
byte parallel input bus 634. The byte informatio,n is passed
to the B3 parity generator 636 which calculates a value for
the B3 byte. The byte parallel data is then sent to STS-1
transmitter 640 which generates a bit serial STS-1 signal
therefrom along with an associated clock.
Turning to Figure,7, a block diagram of a preferred
asynchronous add/drop mux 700b is provided which is capable of
interfacing to the two STS-1 embodiment of the SONET bus
interface. It should be appreciated that, from the teachings
- 32 -
72235-lOD
CA 02113~40 1998-04-06
associated with Figure 7, those skilled in the art should be
capable of providing additional add/drop multiplexers such as
a sychronous add/drop mux 700c, a DS=0 add/drop mux 700a,
synchronous and asynchronous CEPTn add/drop multiplexers,
etc , and should further be capable of providing add/drop
multiplexers which are capable of interfacing with the SONET
bus interface 600 shown in Figure 6.
The asynchronous add/drop mux 700b is capable of
logically connecting two selected asynchronous VT1.5 signals
of a SONET signal to two external T-1 lines, and whether zero,
one or two signals are so-connected is under control of
control interface 705. Where a SONET bus interface 600 such
as shown in Fig. 6 is utilized, VT1.5 signals may be read from
the receive bus (E) 622 and written to the transmit bus (W)
634. However, where the SONET bus interface has the
previously described duplicating circuitry, both the east 622
and west 634 buses may be carrying data to be dropped, and
either VT1.5 signal may be connected to add or drop in either
direction. The VT1.5 signals are received by the receive
circuitry 710a and 710b via east and west buses such as bus
622 of Figure 6 which terminates at the SONET bus interface
600. Receive circuitry 710 also receives associated
multiframe and byte clocks (such as clocks 626 and 630) and
thus
72235-lOD
1.354(~
is able to provide a byte count along with the data bytes to the
virtual tributary SONET payload envelope extract circuitry 712a
and 712b (hereina~ter "VT SPE extract"). The VT SPE extract
circuitry 712 uses the pointers in the SONET signal to r~ad the
relevant transport and path overhead bytes, to discard the
negative stu~, and to extract the payloads o~ the desired
virtual tributaries which are then ~orwarded in bit serial ~orm
into either o~ two FIFOs 720a or 720b via either o~ two
multiplexers 716a or 716b.
Because the virtual tributaries o~ SONET siqnals are
arranged to encompass a DS-l signal, the signals received by bit
FIFOs 720 are DS-l signals in content. However, because the DS-l
signals were travelling in SONET ~ormat, the clocking of the DS~l
signal is not smooth; i.e. occasional phase steps or gaps are
located therein due to pointer movement and the SONET signal
structure. Still, the average ~requency o~ the DS-l signal
contained in the virtual tributary may be extracted by digital
phase locked loops (DPLL) 725a and 725b each having the data ~rom
its associated FIFOs 720 as an input. Each DPLL then sends the
data ~rom its associated FIFO 720 along with the associated
extracted clock to respective line output circuits 728a and 728b
so that a non-jittered DS-l clocked signal may be provided at the
average actual DS-l rate o~ the outgoing line. The line output
circuits 728 encode the received data according to either AMI or
B8ZS rules and pass the encoded DS:l signals to wave shapers (not
shown) and then out to the DS-l (Tl) lines.
-34~
5 ~ ~
-
Turninq to the transmit side o~ the add/drop mux 700, each
o~ the two incoming signals will be received by the line input-
circuits 738a and 738b on two incoming data lines which are
accompanied by clock signals. The line input circuits 738 decode
the AMI or B8ZS encoded data signals, monitor and report bipolar
violations, and output a DS-l bit serial stream along with the
received clock to twenty ~our bit FIFOs 74~a and 740b. The FIFOs
accommodate the unevenness o~ the SONET clock relative to a
particular DS~l siqnal. The bits in the FI~Os are pulled by
either of the SONET VT assembly circuits 745a and 745b.
The SONET VT assembly circuits 745 assemble the DS-l signals
into asynchronous mode VTl.5s by appropriately using the data
signal ~rom the FIFO 740 and the byte and multi~rame clock
signals o~ the bus to which it is associated. These clock
signals define the byte, ~rame, and multi~rame boundaries so that
all the in~ormation required for constructing a proper virtual
tri~utary is availa~le to the V'l' asselnlly circuits 7~5. 'I'he
resulting VT's are tllen ~orwar~e~ to the east or west SONET data
buses via the SONIBUS transmit circuits 748a and 748b. The
SONIBUS transmit circuits 748 not only couple the assembly
circuits 745 to the SONET buses, but, where loop operation is
utilized, the SONIBUS transmit circuits 748 cause signals which
were dropped at the add/drop mux 700 to be zeroed on the
appropriate SO~ET bus. For example, when a VT signal is dropped
~rom the east bus, the byte positions o~ that signal needs to be
~.113~û 72235 l0
zeroed on the transmit east bus. Hence, the SONIBUS transmit
circuit 748 activates the ZE bus line to cause the transmitted
signal to be zeroed.
Turning to Figure 8a, a block diagram of the preferred
switching component of the WBX switching system module 800 of
the invention is seen. The switching component 810 is preferably
a CMOS integrated circuit device which includes thirty-two data
ports (for sixteen bidirectional lines) 820a-1, 820a-2, 820b-1,
820b-2, ..., 820p-1, 820p-2, thirty-two clock ports 830a-1,
830a-2, 830b-1, 830b-2, ... , 830p-1, 830p-2 (one for each data
port), sixteen clock regenerators 840a, 840b, ..., 840p (one
for each outgoing or outlet data port), sixteen flip-flops
850a, 850b, ..., 850p (once for each clock generator), and a
logical switching matrix 860 for connecting ports in a desired
fashion. Each switching component 810 also preferably includes
a control interface 862 which controls switching matrix 860 in
accord with instructions received over a control bus 864 from a
system controller 2Q (séen in Figure l).
Inputs into switching component 810 are from control
bus 864 as well as from sixteen inlet (input) data lines 872a-1,
872b-1, ..., 872p-1 which carry data, and sixteen inlet clock
lines 874a-1, 874b-1, ..., 874p-1 which carry clock signals
-36-
~1~3~
associated with the data signals. The inp~t data signals are
pre~erably digital signals which were generateA after clock
recovery, bit decision and decoding of an analog signal, and the
associated input clock signals are the clock signals obtained
~rom that clock recovery.
Outputs from switching component 810 are onto sixteen outlet
(output) data lines 872a-2, 872b-2,...,872p-2 which carry
outgoing data, and ~rom sixteen outlet (output) clock lines
874a-2, 874b_2,..., 87~p-2 which carry clock signals associated
with the data signals. The output data si~nals are digital
signals which have been appropriately switched, while the output
clock signals are clock signals which have been regenerated by
the clock regenerators 840.
Switching matrix 860 is preferably comprised of duplicate
matrices denoted by 860a and 860b; a first matrix 860a utilized
for switching data signals, and the second matrix 860b utilized
~or switching clock signals associated with the data signals.
Both matrices 86~a and 860b may be comprised according to the
teachings o~ the art. For example, as seen in Figure 8b, a
plurality of AND gates 865a-a, 865a-b, 865a-c..., 865a-p, 865b-a,
865b-b,..., 865b-p, ..., 865p-a,..., 865p:p are used to
cross-connect any of the data inlet lines 872a~1,..., 872p~1, to
any o~ the data outlet lines 872a-2,..., 872p-2. Whether A~D
t ~ S ~ J ~ L Ill i t t ~ L ~l l L () III ~ I I L~ t ~ L I I L U U Y
the outlet lines is under control of- the address registers
~3 ~3~40
869a,..., 869p which comprise the control inter~ace 862. The
address registers enable an AND gate by sending a ~our bit
address code simultaneously to the sixteen AND gates in a column.
The AND gates are arranged with dif~erent input inverters so that
a particular code will enable only a single AND gate in the
matrix column. The data input to the enabled AND gate is passed
to the OR gate 867 ~or that column (OR gates 867 are coupled to
all AND gate outputs in a column) an the OR gate oasses the data
signal ~rom the enabled AND gate to the output.
With the provid~d switch matrix, a single input signal may
be broadcast on all output lines (multicasting) by simultaneously
enabling all sixteen AND gates o~ a single row. A "loopback" may
be accomplished by enabling an AND gate along a diagonal o~ the
matrix (e.g. 865a-a or 865b~b, etc.) which causes the signal o~
an input line to be sent back out over its related output line.
O~ course, standard crossiconnections may be arranged by
con~iguring switch matrix 860a as desired. With sixteen duplex
ports, up to eight simultaneous duplex paths may be set up within
the switching component 810. Simplex paths may also be
established. However, regardless o~ the manner in which the
switch matrix 860a is configured, the clock matrix 860b should be
configured identically so that the clock associated with
particular data travels with that data through the switching
38-
~ll3~0
As indicated in Figure 8a, the output of the clock
regeneration circuit 840 is seen to the desired clock output port
830-2. In addition, the output oE the clock regeneration circuit
is ~ed to the clocking input o~ a D-type flip-~lop 850 which is
arranged to receive at its D input the data Erom data matrix
860a. Thus, the regenerated clock output Erom the regenerator
840 not only acts as the regenerated clock output for the
switching component 810, but also acts to cause the data to be
clocked out oE the switching component synchronously with its
associated clock.
A plurality oE the preferred switching components 81~
detailed in Figure 8a may be used to provide a multiple stage
non-blocking switchig network. For example, a two-stage eighty
(~our line; data/clock duplex) port folded Clos network 800
utilizing twenty-six switching components 810a - 810z is seen in
Figure 8c. As arranged, each switching component oE the ~irst
stage has Eive duplex ports acting as input/outputs to the
network, and sixteen switching components 810a _ 810p are
required to provide the eighty terminal duplex ports. With ~ive
input ports in each switching component, the Eolded Clos network
requires at least nine outputs to the next stage in order to be
non~blocking. In ~act, ten are typically provided. Thus,
EiEteen o~ the sixteen available ports are utilized in each ~irst
stage switching component. Also, with sixteen switching
componets having ten duplex otputs each, the second re~lecting
stage must provide one hundred sixty duplex ports. With sixteen
-39-
~.'f 1 13~ ~ 72235-lo
ports available per switching component, ten additional switching
components 810q - 810z are utilized to act as the reflecting
stage of t~e folded Clos network. Lines between the various
ports of the various switching components as seen in Figure 8c
are indicative of typical paths through the network. Of course,
with the provided structure, any of the provided eighty input
ports can be connected to any (or all) of the eighty output
ports. Alsor if properly programmed, eighty different sets of
connections each having its own clock and hence its own bit rate
may be arranged with the provided switching network of Figure 8c.
While Figure 8c illustrates an eighty duplex port
non-blocking switching network, those skilled in the art will
recognize that a network as large as desired may be constructed
by utilizing additional stages of WBX components.
Additional details regarding the WBX system module 800
may be had with reference to previously referred to Canadian
Patent Application Serial No. 2,008,589.
Turning to Figure 9, a block diagram of a single
switching component 900-1 of the virtual tributary cross-connect
(VTX) module 900 of the system is seen with particular detail to
the receiving means of the component. Background information
regarding details of a SONET signal, as well as additional
detail regarding the VTX system module 900 may be seen in
previously referred to Canadian Patent Application Serial No.
2,004,840.
-40-
21~3~0
-
In component 900 1, SONET signals are received by SONET
frame synchronization circuitry 904a and 904b which find the Al
and A2 bytes of the SONET signals. In this manner, the SONET
frames may be deciphered to determine the location of the SPEs
within the frame. (From hereon, for purposes o~ brevity, the
circuitry relating to a single SONET si~nal will be described).
The synchronization circuitry 904a outputs the received data
along with a ~yte number which indicates to which byte within the
SONET ~rame the data belongs. The VT SPE read circuitry 906a
receives the hytes of data and byte numbers, ~inds bytes Hl and
H2, and locates the start of the SPE within the received signal.
With knowledge of the SPE location, the VT SPE read circuitry
906a locates the path overhead, and in particular byte H4, so
that a determination of the phase of the virtual tributaries
within the SPE (as defined by the H4 byte) may be had. Then,
with knowledge of H4, the Vl and V2 bytes of the virtual
tributaries are ~ound so that the starting time (i.e. V5 byte
location within the payload ~rame) o~ each o~ the virtual
tributary payloads can be found and tagged. The VT SPE read
circuitry 906a in a hyte serial manner, based on the format of
the incoming SON~T signal essentially demultiplexes the SONET
signal into its component virtual tributaries and forwards the
payload (data) o~ each virtual tributary to its appopriate VT
section or slice 910a 1 through 910a 28. In sending the data to
its VT slice, the SONET transport overhead, path overhead and VT
pointer bytes are discarded, leavinq only the VT SPEs. The V5
-41-
35q~
byte o~ each virtual tributary payload is tagged, however, as it
is sent into the VT section slice 91Ga:l throuqh 910a-28 in order
to preserve the phase in~ormation o~ the VT payload.
Depending on the format of the incoming SONET siqnal as
known to the VT mode control 975, different numbers of the
twenty~eight available VT slices might be utilized ~or a single
SONET signal. Thus, if the SONET signal is comprised of
twenty-eight VTl.5 virtual tributaries, all twenty eight slices
910a~1 through 910a-28 are utilized. However, if some of the
virtual tributaries are VT2, VT3, or VT6 virtual tributaries,
~ewer slices are utilized. Of course, with fewer virtual
tributaries, the rates o~ data ~lowing into and out of the slices
will be greater.
With the virtual tributary data having been demultiplexed
out o~ the SONET frame by the receiving circuitry, the switch
component 900-1 must then perform the functions o~ switching the
VTs in space and time, and reassemble the VTs into new SONET
signals. A block diagram for accomplishing the same is seen in
Figure 9b where three o~ twenty eight slices (twenty-eight slices
representing one hal~ o~ component 900-1) are seen in more
detail. In essence, each slice 910 may be broken down into four
components: buffer means 920 for storing the incoming data on a
FIFO basis and ~or storing the V5 tags; pointer calculation means
930 for determining the phase offset between the incoming virtual
tributaries and the SONET signals which are being generated (i.e.
-42-
L3~0
~or calculating the pointer contained in Vl and V2 so that it
will properly point to the position o~ V5 in the generated SO~JET
signals); read/write means 940 including memory means 942 for
storing the virtual tributary destination o~ the data stored in
the bu~er, comparison means 944 ~or comparing the stored virtual
tributary destination to a clocked signal indicative o~ the
virtual tributary of the to-be generated SONET signal requiring
data, and memory means 946 ~or storing the output SONET link
destination number ~or the stored VT; and non:blocking switch
matrix means 950 including AND gate means 951a-1 throu~h 951a 28
and OR gate means 952~1 through 952-32 ~or connecting virtual
tributary data contained in any o~ the bu~er means 920 to any o~
thirty-two data buses 960-1, ..., 960-32 (seen in Figure 9a) on
which the new SONET signals are generated. System inputs into
slices 910 include a 51.84 MB/s system bit clock 964 and a 2 kHz
multi~rame clock 966 which de~ines ~or the slices which quarter
o~ the virtual tributary multiframe is located in the particular
SONET SPE. Master counter 968 produces an output multi~rame
clock signal 967 advanced in time by one system bit clock ~rom
the input multi~rame clock 966, such that the component at the
top o~ an array o~ n components is n-l system bit clocks ahead o~
the component at t~e bottom o~ the array. Control in~ormation
~rom a processor (not shown) is also input into the slices via
processor bus 971 and microprocessor inter~ace 973. The control
in~ormation is used to set the memory means 942 and 946 o~
read/write means 940 (seen in Fig. 9b) such that particular
incomln~ virtual tributaries o~ disassembled SONET signals can be
-43
4 ~
,
inserted via switch matrix means 950 onto a desired SONET
generation bus 960 at a desired time (i.e. corresponding to a
desired VT).
Turning back to Figure 9b, more details o~ the component
900-1 are seen. In particular, it is seen that the virtual
tributary data assigned to slice 910a-1 is received in a buf~er
920a-1. Buffer 920a-1, as preferably configured, includes a FIFO
register o~ three eight-bit words which stores the bytes o~ the
VT SPE, three V5 one-bit ~lags which track the eight-bit words, a
set of three one bit "read" flags, a set o~ three one-bit "write"
~lags, and three additional flags. The V5 flags are used to
indicate whether the byte (eight bit word) contained in a
particular register o~ the FIFO is the V5 byte. The read and
write flags are basically recirculating pointers which indicate
from where the next word should be read for output onto the SONET
generating buses, and to where the next word should be written
for storage in the FIFO. O~ the three remaining ~lags, one
indicates a positive stu~ operation, one indicates ~ negative
stu~ operation, and one indicates circuit initialization which
is discussed hereinafter.
Pointer calculation means 930a-1 serves the multiple
functions o~ calculating the pointer ~or the virtual tributary
~rame, tracking the positive and negative stu~s and adjustinq
the virtual tributary ~rame pointer accordingly, and generating
and causing the insertion o~ the pointer bytes (i.e. Vl, V2,
:44-
CA 02113~40 1998-04-06
etc.) in the VT data stream. In order to properly insert
pointer bytes into the VT data stream, the calculation means
930 receives multiframe timing information such that it can
determine when VT overhead bytes Vl, V2, V3 and V4 are to be
inserted into the VT data stream through the use of
multiplexer 93la-1. In this regard, it should be noted that
the pointer calculation means 930a-1 preferably assumes byte
values for the H1 and H2 SONET overhead bytes such that the
pointer contained therein has a value equal to five hundred
twenty-two. In this manner the SONET signals generated by the
component 900-1 has its VT columns aligned with the STS-1 SPE
columns (such that each SONET payload is totally contained
within a single SONET frame; see Fig. 5).
The virtual tributary pointer calculations conducted
by the pointer calculation means 930 are primarily conducted
during an initialization procedure which occurs at startup or
following a reconfiguration of the system. The purpose of the
virtual tributary pointer which is contained in bytes V1 and
V2 is to point to the byte V5 which is the first byte in the
VT frame. The value contained in the pointer bit locations of
bytes V1 and V2 indicates the distance (byte offset) between
byte V3 and byte V5 for that virtual tributary. Thus, during
initialization (for each VT) a counter is set to zero at the
V3 byte location which is located as a result of the virtual
tributary frame clock 966. As each byte contained in the
buffer is pulled from the buffer onto the SONET generation bus
(in a manner to be described hereinafter, the counter is
incremented by one. When the byte
- 45 -
72235-lOD
3 ~ ~ ~
pulled ~rom the bu~er is identi~ied as the V5 byte o~ the
received virtual tributary as indicated by the ~lag bit tagging
the sa~e, the counter value is indicative of the desired pointer
value which is then stored. The pointer value is then maintained
and used to set bytes Vl and V2 o~ the succeeding virtual
tributary ~rames. The only time the pointer value is changed is
when a positive or negative stu~ occurs, such that the pointer
value is incremented when a positive stu~ is indicated, and the
pointer value is decremented when a negative stu~ is indicated.
In sum, the pointer calculation means 930a-1 is seen to switch a
virtual tributary in "phase", as the location o~ the beginning o~
the virtual tributary frame in the incoming SONET signal will
typically di~er ~rom the ~rame location in the generated SONET
signal.
The switching o~ the virtual tributaries in "time" and
"space" is carried out together by the read/write means 940 and
the switch matrix means 950. In particular, the read/write means
940a'1 is comprise~ oE three re~isters: virtual tributary
destination register 942a-1, a comparison register 944a-1, and a
destination SONET bus number register 946a 1. The virtual
tributary destination register 942a-1 stores the virtual
tributary number into which the data in the bu~ers 920a-1 are to
be inserted. ~ecause the SONET generation buses are synchronized
in time, the occurrence o~ the virtual tributaries in the SONET
~rame are distinctly set in time. Thus, as the master counter
968 proceeds, its value may be equated to the sequence o~ byte
-45-
~113S40
times in the overall SONET frame. For a given mix o~ VT sizes as
stored in VT mode control 975, there is an exact mapping between
the count o~ master counter 968 and the virtual tributary
timeslot available ~or data insertion on the SONET generating
bus. This map~ing is done by VT number selector means 977 which
provides a current VT number value to the comparison registers
~44. 'l'he current VT nu~ er value is t~len colnpdred in comparison
registers 9~ to the virtual tributary distination register.s 942
of the read/write means 940 . I~ the two match, it is time for
the data contained in the bu~er to be written onto a SONET
generation bus 960. In essence, then, the switching o~ virtual
tributary number one o~ the received SONET signal whose data is
bu~ered in bu~er 920a-1 into a virtual tributary number n o~
the generated SONET signal constitutes a switching o~ the virtual
tributary in time.
The switching o~ the virtual tributary in space is
accomplished by means o~ the destination SONET bus number
registers 946 of the read/write means in conjunction with a
switch matrix 950 which can connect each o~ the ~i~ty-six
(twenty-eight virtual tributaries times two) data bu~ers 920 o~
the switch component 900-1 to each o~ thirty-two SONET generating
buses 960. SONET bus destination register 946a-1 is activated
upon an output o~ comparator 944a-1 which causes a byte to be
"pulled" from the FIFO 920a-1. The contents o~ register 946a-1
(which were loaded into the register by the system microprocessor
via processor bus 971 and microprocessor inter~ace 973)
-47-
~lt3~0
..~
corresp~nds to the num~e~ oE the SON~T bus onto which th~ data
from the FIFO is to be switched. Thus, the SONET bus destination
register 946 1 acts to control some o~ the logic circuitry of the
switch matrix 950.
Switch matrix 950 o~ component 900-1 is logically composed
of fi~ty-six sections 951a 1 through 951a-28 and 951b-1 through
951b-28 of thirty-two AND gates each with each AND gate connected
to one o~ thirty-two OR gates 952~1 through 952 32. The contents
of register 946-al (in a non_broadcasting mode) are used to
activate exactly one o~ the thirty-two AND gates o~ section
951a-1, thereby permitting a byte from bu~fer 920a~1 to be
inserted in bit-serial form via multiplexer 931a-1 onto one
destination bus 960 which comprises the output of one OR gate
952. Thus, at the appropriate time as dictated by comparator
944a-1, data contained in bu~er 920a-1 is pulled out o~ the
buffer and written onto the hus 960 dictated by register 946a-1.
In essence, then, switch matrix 950 as controlled by the
destination bus number registers 946 switch the virtual
tributaries in space.
The thirty-two outputs 960-1 through 950 32 of the
thirty-two OR gate structures 952-1 through 952-32 contain all of
the space and time switched VTs of the two SONET signals
originally received by the component 1~0. However, in switching
network as will be described with re~erence to Figure 9c, these
outputs must be combined with the outputs 961~1 through 961-32 of
-48-
~tl 3~40
the switch component above it in the switch network. OR gates
965-1 through 965-32 are provided ~or that reason. The outputs
o~ OR gates 965 are then combined with SONET overhead byt2s Al,
A2, Bl, Hl, H2, H3, and H4 which ar~ generated and inserted by
overhead generation mean~ 980. The outputs o~ overhead
generAtion means 980 are reclocked according to the system bit
clock 964 by an array of D ~lip-flops 990 to produce outputs
992~1 through 992-32.
Signals 961-l through 961-32 ~rom the previous switch
component are bit and multi~rame synchronous with
locally-generated signals 96041 through 960 32 by virtue o~ the
established one cycle bit clock o~set between switch components.
Hence, the combination of signals 961 and 960 may be accomplished
directly by OR~ing. The outputs o~ OR gates 965 thus contain all
o~ the VTs arriving on all o~ the components above the local
component in the network as well as those arriving on the local
component.
In the overhead generation means 980, the SONET signal
~raming bytes Al and A2, the STS-l pointer bytes Hl, H2, and H3,
the multi~rame indicator byte H4, and the SONET B3 parity check
bytes are inserted. To insert them at proper times, the system
bit clock 964 and the multi~rame clock 966 are provided. The
values o~ Al, A2, and H3 are ~ixed by design. Likewise, the
values o~ Hl, H2, as a~orementioned are set to provide a pointer
having a value equal to ~ive hundred twenty-two so that the SONET
-49
~113~40
p lcad is totally contained within a SONET ~rame. The val~ of
byte H4 is determined by the m~ltiframe signal 966, while the
value of B3 is calculated over each of the outputs of OR gates
965il through 965~32. In calculating B3, any value received from
outputs 965 in the s2 byte position is ignored.
Turning to Figure 9c, it is seen that a typical switching
network 900 may be comprised o~ sixteen switch components 900-1
900~16. By vertically aligning the sixteen components, up to
thirty~two incoming SONET signals 1001 through 1032 can be
handled with up to eight hundred and ninety-six virtual
tributaries being switched to produce thirty-two new SONET
signals 1101 through 1132 which are output on the thirty~two
SONET generating buses 992 1, ..., 992 32. If additional SONET
siqnals are to be processed, the switching network is expanded
both vertically and horizontally so that four sets o~ sixteen
switch components are utilized. Vertical expansion permits
additional incoming SONET si~nals to be received, whlle
horizontal expansion provides additional SONET generating buses
so that additional SONET output si~nals can be generated. With
sixty~four VTX switch components, the virtual tributaries of up
to sixty~four SONET signals may be processed and switched to
create sixty~our new SONET signals. It should be appreciated
that as large a network as desired may be created.
In order for the switching components and switching network
to properly ~unction such that the virtual tributaries may be
~50-
~113~0
.
switched in time, phase, and space, the entire virtual tributary
switching network (VTX nodule 900) is synchronized. Each o~ the
SONET generating buses (thirty~two per component) are in phase
with each other and are timed by the system bit clock 964. In
addition, as a~orementioned, each switching component in a
vertical column is arranged to be one system bit clock cycle time
advanced from its lower-adjacent component. In particular, the
multi~rame clock is passed through ~rom the bottom most colnponent
to the top component in the co~umn (as seen by the output o~
master counter 968 of Fig. 9a) such that in passing the clock,
each higher co~.nponent is advanced in time by one system bit clock
cycle relative to the the adjacent lower component. As a result,
as the generated SONET signal on the SONET generating buses 960
is passed down through a component, it is in time phase with the
local signals o~ that component.
In generating new SONET signals, as a~orementioned, the
SONET envelope signal (overhead) is pre~erably generated at the
overhead generating means 980 by providing values ~or ~raming
bytes Al and A2, multi~rame byte H4, and the SONET SPE pointer
bytes Hl and H2. At the start o~ each new SON~T ~rame, the bits
o~ the Al and A2 ~raming bytes are serially placed on each bus by
means 980. Because each succeecing component is displaced in
time, the succeeding components continually overwrite the ~1 and
A2 in~ormation. However, the Al and A2 in~ormation is
overwritten (due to OR gates 965) with identical in~ormation
stored in the overhead generation means o~ the succeeding
-51-
L 3 ~ ~ ~
.
components. Hence, proper bytes are generated. After thirty~two
clock cycles, the virtual tributary payload is reached, with the
master counter indicating that byte one of virtual tributary one
should be placed on the respective buses over the next eight
clock cycles. Thus, those slices having virtual tributary
destination registers equal to a value one pull a byte out o~
their bu~ers and in bit serial ~ashion place that byte on the
~us to which the bu~er is switched by switch matrix 950 (as
indicated by the destination bus number register). At th~ end o~
those eight cloc~ cycles, the slices o~ the component highest in
the column could have placed at least one byte on at least one
bus, while the slice o~ the ninth component in the column has not
reached its thirty-third clock cycle. ~or the highest component,
the next eight clock cycles would require the placement o~ byte
one o~ virtual tributary two on respective buses, while ~or the
ninth component in the column, byte one o~ virtu~l tributary one
is being placed on the buses. The procedure continues ~or all o~
the components in such a ~ashion, with the data e~ectively being
multiplexed onto the SONET generating buses such that the SONET
~rames get properly generated. In other words, the SONET ~rames
get generated by combining the output signals o~ the virtual
tributaries o~ the incoming SONET signals onto thirty-two SONET
signal generating buses. When a plurality o~ switch components
~re utilized, the SON~T signal generating buses run vertically
through the switch components and are e~ectively vertically
"daisy-chained".
-52
5 ~ ~
,
It should be appreciated that with the provided SONET
generating arrangement, most of the data used to generate the
SONET signal, including the bytes of the VT SPE and the Vl:V4
bytes generated by the pointer calculation means 930, are taken
from the slices of the switch components. However, overhead
information, including SONET framing bytes Al and A2, SONET SPE
payload pointer bytes Hl and l~2 (set to a value o~ ~ive hundred
twenty-two), multiframe byte H4, and parity check byte B2 are
gener~ted in overhead generation means 980. The multiframe byte
value H4 is dictated to the overhead generation means by the
multiframe clock 966 which is one system bit cycle removed per
component.
Turning to Figure 10, the DS3/SONET converter component 1200
of the invention is seen. The incoming DS~3 signal along with
its associated clock is received from the DS-3 line interface
circuit 500 by the DS-3 frame sync circuit 1205. The frame sync
circuit 1205 searches for and locks to the DS-3 frame and
multiframe patterns as well as conducting an AIS signal detection
along with a loss o~ signal detection. In synchronizing with the
DS~3 frame, the sync circuit 1205 searches for a column of data
value ones corresponding to either column of "Fl" bits in the
DS~3 ~ormat. ~laving ~oun~ the 11 column, the circuitry resolves
which of the two Fl columns is received by looking at two bits of
column zero o~ two sub~rames later. Finally, frame position is
resolved to recover bits M0, Ml, M0 and complete the
synchronization process. If synchronization is not established
21t3~0
within a predefined time, an alarm is raised. Also, parity is
counted over 4704 time slots ~ollowing the ~irst X-bit in an
M-frame and is compared with the received PP bits. I~ the parity
count does not correspond to the appropriate PP value, a parity
error counter is indexed.
Depending on the mode in which the DS3/SONET converter 1200
is to be used, the incoming data is either ~orwarded to the DS-3
stu~ control bu~er 1210, or to the DS-3 destu~ circuit 1215.
In the former case, the entire DS-3 is stuf~ed into a SONET
signal ~rame (although only bytes Al, A2, Hl and H2 need be
identi~ied; hence the signal is not in "substantial SONET
~ormat"), while in the latter case, the twenty eight DS-l
components o~ the DS 3 signal are each individually stu~ed into
VT1.5's. I~ the data is ~orwarded to DS 3 stu~ control bu~er
1210 (which is basically a FIFO), the entire DS-3 signal is
presented to the FIFO at the DS-3 receive line bit rate and is
read out in bursts at the STS-l 51.84 Mb/s rate. Five stu~
control bits are provided at column, bit positions C4-B5, C32-B7,
C32-B6, C61-B7, and C61-B6. Majority voting determines wheter
the bit in column sixty~one, bit zero is a stu~ or in~ormation
bit. I~ during the readout o~ column eighty-seven, bit zero, the
number o~ bits in the FIFO is ~ewer than a ~irst predetermined
value, the stu~ control bits o~ the next row are marked to
"11111" and a zero is placed column eighty-seven, bit zero. I~
the number o~ bits in the FIFO is greater than a second
predetermined value, the stu~ control bits o~ the next row are
-54-
.~113540
-
marked "00000", and an in~ormation bit is placed in column
eighty seven, bit zero. The so-generated STS:l signal is then
forwarded via multiplexer 1240 to parallel to serial converter
1245 as will be described hereinafter.
Where the incoming n~s-3 si~nal is to hroken into its ns l
components for stu~fing into virtual tributaries, the data from
frame sync circuitry 1205 is sent to DS-3 destu~er 1215 which
monitors for and appropriately treats loss of signal, loss of
lock, and for an alarm indication signal. In normal operation,
the DS-3 destuf~er ~orms seven T-2 outputs with associated clocks
~rom the DS:3 signal by taking bytes Il - I7 sequentially Erom
the synchronized DS 3 bit stream and by appropriately deleting
stuff bits. The clock and T-2 data outputs are then sent to the
seven identical DS-2 synchronization and destu~fing blocks 1220a
- 1220g. Each DS 2 sync and destuffing block provides
synchronization to the seven DS-2 signals and extracts the
twenty-eight DS-l signal which are to Eormed into VTs.
Synchronization is obtained by searching for the ...01010101...
framing pattern. Once the Eraminq pattern is located, one more
frame time is needed to acquire the multiErame time. With
synchronization established, each DS 2 signal is destuffed where
appropriate to generate Eour resulting DS-l signals. For
example, if two or three Cxy bits of the DS0-2 subframe x are
value ones, the bit Ix of the sixth group of forty-nine bits of
that sub~rame is a stufE bit for DS~l number x. I~ the bit is a
stuff bit, it is discarded by the DS-2 sync destu~ block 1220.
~55~
~113~gl~
I~ it is not a stu~ bit, it is data, and is passed on to an
appropriate T.l stuf~ control bu~er 1225 which receives the DS:l
data and an uneven clock.
The twenty-eight T-l stu~ control bu~ers 1225 are
essentially independent FIFOs which as.sist in a ~requency
justi~ication o~ the DS 1 signals into the VTl.5s. Eight bits
~or insertion into each o~ bytes ~oue through twenty-seven o~ a
SONET virtual tributary, as well as one bit plus stu~ control
in~ormation ~or insertion into byte number three must be pulled
~y each VTl.5 ~ormatter 123~ ~rom each T-l stu~ control bu~Eer
1225. Then, under control of the STS~l TOH/POH envelope build
block 1235 (which inserts transport and path overhead bytes into
the data stream as required as discussed below), the data is
~orwarded via mux 1240 to the parallel to serial converter 1245.
Parallel to serial converter 1245 converts the byte parallel data
received ~rom the VTl.5 ~ormatter 1230, the STS-l TOH/POH
envelope build block 1235, or ~rom the DS~3 stu~ control bu~fer
1210 into a bit serial substantially SONET ~ormatted signal with
an associated bit clock.
In order to build a substantially SONET ~ormatted signal
~rom the twenty-eight VTl.5 signals, the STS-l TOH/POH envelope
block 1235 utilizes a 51.84 Mb/s clock. Since the transport mode
o~ the signal to be generated is asynchronous, the phase o~ the
locally generated substantially SONET ~ormatted signal is
arbitrary and does not need to be synchronized with the ~rame o~
-56-
~13~40
any other signal Thus, the simplest signal possible, with a
Eixed phase relationship between the STS'l ~rame phase and the
STS-1 SPE phase may be generated. Thus, a ~ixed value Eor the
SPE oEEset pointer is ~rovded, and the only necessary values
inserted into the TOI~ bytes are the framing bytes A1, ~2, the
~ixed pointer, and the network loss o~ sync byte inserted in the
position normally used Eor BIP-8 Bl. All other TOH bytes are set
to zero. In the path overhead, the BIP-8 B3 byte is inserted
along with a locally_generat~d H4 multi~rame byte. ~ytes Vl, V2,
V3, and V4 are inserted with fixed pointer values as the VT SPEs
are inserted in ~ixed positions in the STS-l SPE. The overhead
bytes are inserted as required into the data strea~ via
multi~lexer 1240 as previously described.
The transmit side oE the DS3/SONET converter 1200
essentially conducts the reverse o~ the operation conduct~d by
the receive side. A substantially SONET ~ormatted signal (or a
signal having a SONET Erame and carrying a bulk DS-3 signal) is
received by ~etwork Erame sync block 1255 which searches ~or and
locks to the ~rame pattern oE the incominq signal. The network
~rame sync block 1255 checks ~or parity errors, loss o~ lock, and
loss o~ signal, and outouts bytes o~ data along with a
synchronized byte clock and byte number indication (as well as
any necessary alarm iE signal or lock are lost). The bytes and
clocks are output to either the DS 3 destu~ block 1260 or the VT
disassemble block 1265 based on the mode o~ the DS3/SONET
converter 1200. Where the DS-3 destu~ block 1260 is utilized,
-57-
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the DS-3 signal bits are extract~d ~rom the SO~ET signal by the
DS-3 destu~ block 1260, and a phase locked loop is utilized to
recover the average DS~3 line frequency. The DS-3 signal and
clock are then forwarded via multiplexer 1285 to the DS3 line
inter~ace module 500.
Where the VT disassemble block 1265 is utilized, the
substantially SONET ~ormatted signal is stripped by the
disassemble block 1265 o~ the transport and path overhead, and
the VT SPE is extracted ~rom each asynchronous floating mode
VTl.5 using the VT pointers of bytes ~Il, V2 and V3. Then,
deleting the fixed stuff and stuff control bits, the remaining
data bits are sent along with their clocks to the twenty-eight
T-l stuff control buffers 1270. The T-1 stuff control bu~fers
take the twenty eiqht independent DS~l signals, and provide
therefrom seven DS-2 siqnals with the DS-l signals stuf~ed into
defined positions in the DS-2 signals. The synchronized DS-2
signals are then ~orwarded to the T-2 stu~ frame insert block
1275 where the DS-2 signal frame, multiframe, stu~, stuf~
control bits, and inversion bits are all inserted. The seven
synchronous DS-2 signals are then ~orwarded to the DS~3 ~rame
builder 1280 which properly inserts the DS-2 signals into the
DS-3 signal along with desired overhead. The properly assembled
DS-3 signal i.s then passed via multiplexer 1285 to the DS3 line
interface module 500.
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Returning to Fiqure 1, and with the above-described modules
o~ system 10, it should be appreciated that a plethora o~ desired
systems utilizing subsets o~ the modules of the system can be
arranged. For example, using just a DS-3 line inter~ace module
500, a DS-3/SONET converter 1200, and the SONET Path Terminator
400, a DS-3 line signal can be stuffed into a SONET STS'l line
signal and be sent out over an STS-l line. Likewise, an incoming
SONET STS-l signal can be converted into DS-3 format and sent out
over a DS-3 line.
By adding the WBX 800, and additional SPT modules 4~0, DS-3
line inter~ace modules 500 and DS-3/SO~lET converter modules 1200,
to modules 400, 500, and 1200, more complex systems can be
realized. Cross connects of various DS-3 signals, and
cross-connects between various SONET STS-l signals can be
accomplished. In addition, cross~connects between any of various
SONET STS-l signals and the various DS-3 signals can be carried
out.
Provision of the "back end" components in addition to
modules 400, 500, 800, and 1200 adds another dimension to the
system. With the addition of add/drop mux 700b and pre~erably
the SONET bus inter~ace 600, particular DS l signals may be
placed into VTs o~ a substantially .SONET ~ormatted signal and
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,
switched as part of the substantially SONET ~ormatted signal to
the SPT 400. Or, the DS-l signals may be sent to the DS~3/SONET
converter to comprise part of a DS-3 signal which is sent out to
a DS 3 line via the DS-3 line interface 500. Of course, these
tasks can be accomplished without the W~X 800 if complex
switching ~or numerous STS-l and/or DS-3 lines is not required.
Similarly, if synchronous signals are being processed, dif~erent
add/drop multiplexers such as 700a and/or 700c could be similarly
utilized. Moreover, add/drop multiplexers 700d interfacing to
CEPTn lines could be included such that a CEPT signal could be
switched to comprise part of a SONET STSn or DS-3 signal.
The use of the VTX 900 adds yet another level of complexity
to any system. With the VTX, any channel of any incoming signal
can get cross-connected to any channel o~ any outgoing signal,
provided of course that the signals are first placed into
substanti~lly SONET format such as by the add/drop multiplexers
700 or the DS-3/SONET converter 1200; the STS-l signals already
being in such a format. Thus, for example, the twenty-eight
virtual tributaries of a particular incoming SONET STS-l signal
obtained from an STSn line could be switched into up to
twenty-eight different substantially SONET formatted outgoing
signals, with one or more virtual tributaries being converted
into DS-l channels of one or more DS-3 signals (via components
1200 and 500), one or more VTs being included as VTs in one or
more STSn signal (via components 400, and components 300, 200 and
100 if desired), and one or more VTs being included as VTs in one
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-
or more STS-l signals where particular VTs are dropped at one or
more asynhronous add/drop multiplexers such as 700b.
Of course, the DS-3/SON~T converter 1200 and DS-3 line
inter~ace 500 are not necessary in many other systems. Thus,
using only a plurality o~ SPTs 400 and the WBX 800 and/or VTX
900, cross-connection of SONET signals may be accomplished. I~
the VTX 900 is utilized, VTs within the SONET signals may be
cross-connected. Also, i~ it is desired to add and drop virtual
tributaries, back end components 600 and 700 may be added to such
a system. In ~act, because the back end components build
substantially SONET ~ormatted signals, a combination o~
components 700, 600, and 400 (and 300, 200 and 100, i~ desired)
without the VTX 900 and W~X 800 would be very use~ul. O~ course,
as a~oredescribed, the addition o~ the VTX 900 and/or the WBX 800
permits the sy.stem to accomplish many additional power~ul
~unctions.
Further, it will be recognized that the SONET ~ront end
components (100, 200, 300 and 400) as well as the DS-3 related
components (500 and 1200) need not be utilized, and still a
use~ul system can be obtained. In particular, the combination o~
the add/drop multiplexers 700 with the VTX 900 and/or the WBX can
provide desirable results. In particular, cross-connecting o~
particular add/drop multiplexers can be accomplished thereby.
CA 02113~40 1998-04-06
There has been described and illustrated herein a
modular, non-blocking, expandable SONET compatible cross-
connect system capable of interfacing with and cross-
connecting STSn, DSn and CEPTn signals. While particular
embodiments have been described, it is not intended to be
limited thereto as it is intended that the invention be as
broad in scope as the art will allow. Thus, it should be
appreciated that different circuitry than that disclosed could
be utilized in all of the modular components, provided the
format of the data internal the system is of substantially
SONET format. For example, certain components process the
data in byte-parallel format, while other components utilize
the bit-serial format. In particular, the add/drop
multiplexers are seen to convert data into byte-parallel
format for transport over a bus and to the SONET bus
interface. Of course, if desired, the SONET bus interface
could be deleted if the data were transported on a bit serial
bus as opposed to a byte parallel bus, and if the add/drop
multiplexers could receive and transmit in such a fashion.
Further, while the particular numbers of ports were described
for the chip components of the VTX and WBX cross-connect
modules, it will be appreciated that different numbers of
ports could be utilized per chip. The arrangement of the non-
blocking cross-connect networks could also be changed, as the
WBX need not necessarily be of a folded Clos architecture,
while the VTX need not be of a bus architecture. While both
those architectures are preferred, as they are expandable, it
is only required that the networks be non-blocking.
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72235-lOD
CA 02113~40 1998-04-06
It should further be appreciated that while all
connections and internal timing of the system was described as
being at an STS-1 level, other STSn timings could be utilized,
such as STS-3. Moreover, while a particular arrangement of
system modules was provided in the Figures, different
arrangements can be provided due to the mix and match nature
of the modules. Finally, it will be appreciated that
terminology in the claims is intended to be read in a broad
light, such that terms such as "coupled to" do not suggest
direct connection. Therefore, it will be apparent to those
skilled in the art that yet other modifications may be made to
the invention as described without departing from the spirit
and scope of the claimed invention.
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