Note: Descriptions are shown in the official language in which they were submitted.
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PLANARIZING B~MPS FOR INTERCONNECTING
MATCH~IG ARRAYS OF ELECTRODES
Field of the Invention
S The invention concerns inler~~ P~ g arrays of electrodes of two
electronic devices, e.g., connpcting pads of a semi~Qnd~1ctor device to a ~ tcl-;ng
pattern of traces and/or pads on a printed circuit board or an inteç~ol n~t In
particular, it relates to an improved process for p~.ing metal bumps on the
clec~udes of one electronic device for use in such in~onnecting.
Ba~ u.~d of the Invention
Electronic devices are beco-ning smaller and more complex, e.g.,
having larger n~.l-bel~ of electrodes of finer pitch. Hundreds of individual
co~nPctions between two cle~lronic devices must be made across areas that may
15 be about a square cf ~.t;---e~r in area or even smaller. For PY~mp1e, a
semiconductor device may have a large l-u---ber of electrodes or contact pads, as
they are l~own, to be connPc~ individually to another set of electrodes such as
traces or pads on an in~onne~t or circuit board. For pUl~)O~KS cont~ined herein,the term "electronic deviceH will be under~l~od to refer to active semiconductor20 inlegldted circuits as well as circuit boards and in~,conn~ on which such
circuits are to be mounted and test coupons for testing such circuits.
One method of making such col~nectiolls involves forming a metal
bump on each pad of the semiconductor device or al)propliate traces or pads of the
inler~onn~l or circuit board. Preferably the bumps are formed on the traces or
25 pads of the int~l~onne-;l to reduce the nulllb~l of p,oces~ing steps, and res~11t~nt
yield loss, on the more sensitive s~mi~n~uctor device.
After ~ligning each bump with an electrode to which it is to be
bonded, the two devices can be bonded by applying p,~s~u,e and/or ~--,pe,dl~re
to provide electrical contact b~lween each aligned pair of electrodes. Such
30 electrical contact may be "ain~ined by a metallurgical bond, by an adhesive, or
simply by ...~;nl~;ning the exerted pre~u~.
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The bumps c~n be of a variety of metals, but are commonly of gold
bec~ e of its high elPct~c~l conductivity as well as its corrosion recist~ncR
The bumps can be electroplated directly onto the electrodes or, as
suggested in United Kingdom Patent Spe~ific~tion No. 1,243,097 (Gurler), they
5 can be formed on a ttlllpCI~uy SUbSl1ale and then transferred and bonded to the
electrodes. T,~Çt;l,ing pl~lecls the eleclr~nic device from damage that might
otherwise result from the clp~ning and plating solutions normally used in the
Ço,lllalion of the bumps. In United States Patent No. 4,693,770 (Hatada), bumps
formed on a telll~l~y subsLl~te can be from 5 to 40 ~m in height and have flat
10 contact surfaces that can be 20 ~m square. The bumps can be transferred to
alul,.il,u", electrodes of a first semiconductor device at 250 to 450C and a
pr~ssu,~ on each bump of n 10 to 70 g. " The first semiconductor device can thenbe conn-P~- çd to a second semiconductor device at 250 to 450C and a pres~ure
on each bump of "50 to 200 g."
The pads of a sPmicon~uctor device typically are formed at its top
level and are sep~ Pd from the active cil~uilly by a passivating laya that has an
opening or via at each of the pads. It is known in the art that the surfaces of the
pads should lie in a plane, but they may not be quite coplal~ar due to dirrerences
in unde~lying levels of cir~uil-y and other causes.
Pads and traces on a circuit board or in~l-;onncct also may not be
coplanar due to variations in their thi~`L -es~s. For example, traces formed byelee~oplaling tend to build to dirr~,lel~t thi~Ll~f-c~s in areas of dir~c;nt trace
density. Additionally the contact surfaces of traces and pads may not be coplanar
becA..~ failure to center the traces or pads precisely with respect to the
25 clecl-oplating anode and c~th~e will result in nonunifo,ll.ily of their thicknesses.
Another aspect of the nonplanarity problem is t~iccusce~ in United
States Patent No. 4,749,120 (Hatada) which says that "if a mounting surface of awiring board has some twisted or curved portion and a semiconductor device is
u.-led and fixed on such twisted or curved surface portion through a metal bump
30 com eclion, it may occur that the semiconductor device itself or a metal bumpconnection is destroyed by unneces-..y force owing to the twisted or curved
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surface portion" (col. 1, lines 42 lhlough 49). It copes with this by interposing
a hardenable ins~l~ting resin such as an epoxy resin between the metal bumps of
the semiconductor device and the wiring pattern and then applying s-lffiei~nt
pl~saule to force the bumps and wiring pattern through the resin. The hardened
5 resin is said to prevent an end portion of the semiconductor device from being d~,laged by CQ~ g the wiring p~ttern.
In ~ ition to the fact that the traces and contact pads are not
co~l~n~r, the contact s.-lr~ces of bumps are generally not copl~n~r. ~This is
because when bumps are formed on pads or on traces that deviate from a plane,
10 the contact sulr~ces of the bumps tend to mirror those deviations. Additionally,
it is ~lifflcl~lt to form bumps to unifollll heights for the same reasons that its
liffi~ult to form coplanar pads and traces. These problems are m~gnified with the
bumps bec~use, generally, they are thicker than the pads or traces. At the present
time, bumps are generally formed to a height of 20 ~m to allow for both recesses15 at the pads due to variation of the passivating layer, as well as deviations from
coplanarity of the contact surfaces of bumps, while leaving a gener~us margin oferror.
In known techniques for producing electronic devices in econo",ical,
large-scale production that have large nulllbela of bumps, either on pads or on
20 traces, the contact a.-lraces of the bumps of each electronic device commonlydeviate from a plane by + 1 ~m or more. When such devices are electrically
con~ ~ to other devices, either p~ .lly by bonding or lclll~l~ily by
pr~;.aulc~ it is ~-~c~,~ to apply ~ S and/or ~e,ll~lalules suffirient to
COlllpl~SS the tips of the higher bumps until the contact surfaces of the lower
25 bumps come into contact with a ...~chil-g electrode. Only then will all of the
bumps be in electrical contact with the electrodes. Such lel"peldlu~s and
cSaulcS have the potential of ~l~m~gin~ sensitive electronic devices. Even when
lclll~Jcldlul~s and pl~ saulcs are kept so low that any damage cannot be detected
initially, that damage might lead to eventual failure. Furthermore, even if no
30 actual damage is done, the electronic device may not work while under such
pl~i,a.-le. For example, many III-V semi~onductor materials, such as gallium
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arsenide, are piç7Oelectric. Thus the presaufe gradient res--lting from the
col,lplesaion of the tips of the higher bumps so that the lower bumps make good
electrical contact will also create an electric field across the chip. Such a field
may prevent the chip from opeldting properly even though there is no actual defect
S and the chip would operate pr~pelly upon release of the p~eSall~e.
Re.c~use of concerns about possible damage to semicon~luctor
devices in the bonding process, decigJ ers tend to avoid placing Cifcuitly in areas
under the pads. Any as;,uldnce against such damage would allow more efficient
use of space in placing Cif~ui~y.
The ar~icle "A Planar Approach to High Density Copper-polyimide
Intelc-~nn~t Fabrication," P~oceedin~g~ of the Technical Conference, Eighth
Annual Tntern~tional Electronics P~c~ging Conference, Nov. 7-10, 1988, (Pan et
al.) concellls a method of making a multilayer in~erconn~t that can be used as amulti-chip sul,sLI~le. The intelconl-e~ is built using "pal~lll electroplating to plate
15 copper to form the co~ductQr layers and the pillar layers. These copper features
are over~oaled with nickel for enh~nr~d reliability before polyimide is spin coated
over the plated fe~lul~s to partially planarize the topography. Mech~nic~l
polishing is then carried out to fully pl~n~ni7e the sub~Ll~te surface and expose the
copper pillars. The ~.lbsll~te is then ready for the next layers of conductor and
20 pillar fabrication." A similar process is described in United States Patent No.
4,810,332 (Pan).
United States Patent No. 4,879,258 (Fisher) concernc the
pl~n.,.;7~l;on of an i~ glated circuit by ...~hAI.i~l poliching. Among other
possibilities, one abrasive device taught by the Fisher patent is a glass disk with
25 finely divided ~i~mond particles çmbe~ded therein. An altelllali~/e abrasive device
that is ..,~ ;rn~d is a diamond-tipped stylus.
To the extent that Pan and Fisher employ mech~nic~l poliching to
make rough surfaces more smooth, those surfaces might be called "planarized."
However, it is well-known in the art that surfaces that are not initially coplanar
30 cannot be polished to become coplanar. This is because polishing involves using
ess~nti~lly a constant and equal pressule on all of the surfaces to be polished. This
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removes subst~nti~lly equal amounts of material from across the surfaces except
at areas of differing hardness. Furthermore, it is not possible to di~cclly control
the final height of the bumps with an abrasion pr~cess. Instead the bump height
must be mo~ ored and the process stopped when the desired height is reached.
s
Su,.""~ of the Invention
According to the present invention, an electronic device having a
plurality of elec~odes is ~r~p~d for bonding with another electronic device by
po~itioning metal bumps s,~lloLmded by a resin on sel~ted cle~:lrodes. The bumps
10 are then di~mond turned so that the outer surfaces of all of them lie subst~nti~lly
in a plane. The resin is then removed.
Brief Des~ ion of the Drawin~s
Figures 1 through 8 show an electronic device in various stages of
15 proc~s~ing according to the method of the present invention;
Figure 9 is a flow chart of the most general method accolding to the
invention;
Figure 10 is a flow chart of a first more sperific embo~iment of a
method according to the present invention; and
20Figure 11 is a flow chart of a second more spe~ific emho~imPnt of
a method accor~ing to the present invention.
Detailed Desc,iplion
of a ~e~.led Embodiment
25The present invention provides a method of l)r~dtion for array
bonding of an electronic device bearing a large number of electrodes by the steps
of positioning on sel~ted electrodes mPt~llic bumps ~ul~ounded by a p,ulecli~e
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resin, diamond turning the resin layer and the bumps so that the exposed surfaces
thereof lie subst~nti~lly in a plane, and removing the resin layer to leave the
bumps CA~S~.
The process of the present invention may be better understood by
S l~rercnce to the figures. Figure 1 shows two mPt~llic conductors 10 on a ~ubsLldte
12. Conductors 10 could be contact pads or co~nPctor traces and could be of
copper, ~ , or other applopliale mPt~llic con~uctor m~tPri~l. Substrate 12
could be, for example, a semiconductor inleglated circuit, a circuit board"or any
other intelcol n~t to which an intcgldted circuit may be ~tt~thP~.
As shown in Figure 2, a layer, 14, of a met~llic electrical conductor
is deposiLed on ~lbsL~ate 12 and conductcr 10. Layer 14 could be deposited by
any known technique, such as syuLlcling. Layer 14 will be used in later steps toprovide a field plane for electroplating.
As shown in Figure 3, a layer of resin, 16, is next applied over
15 met~llic conrluctor layer 14. Preferably, resin layer 16 is of a material that, after
curing, will be ,..~l~hin~hle without excessive smearing or chipping at oldinalyroom lclllycldlul~s and will support the bumps during m~hining. Furthermore,
the resin is yl~f~lably a radiation curable resist. The most commonly used typesof radiation curable resists are photoresists. Examples of photoresists that may be
20 m~^hin~d willlou~ undue s...P~.;,-g at o~in~y room lelllyeldlures are cresol
novolak resins and a~ lates. Other resins useful in the present process include
polyimides and epoxies.
Resin layer 16 is next yaLL~llled using a standard process. Typically
resin 16 is pdllcllled by photolithography and is exposed through an dypn~pliate25 mask although other techniques, such as writing the pattern with a laser, may be
used. ~lt~rn~tively, resin 16 could be patternable in other ways, such as by
exposure to an electron beam. After exposure the resist is developed leaving
opening~ in the locations where bumps are desired. As shown in Figure 4, two
openings 18 have been formed.
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A met~llic conductor, p.cfel~bly copper, is then deposited, typically
by electroplating, into the openings such as opening 18 forrned in resin layer 16.
As shown in Figure 5, the copper bumps 20 are preferably slightly shorter than
resin layer 16. In addition the thi~1~ne$s of underlying conductor layer 10 should
S be great enough to be resistant to breakage during m~hining. E~ ce has
shown that thicL~.P~ss of layer 10 of less than 1 ~m are subject to such breakout.
Fu~ c~ o~ such breakage is reduced when conductor layers 10 are wider than
bumps 20.
Resin layer 16 and electrically conductive bumps 20 are next
10 m~rhined by diamond turning to produce a smooth coplanar surface. Diamond
turning is a well-known m~hining technique in which a single point diamond tool
is used to cut to a well controlled depth in the material until the m~çhin~d surface
f~ s a desired profile. Pl~fe dble ~i~mon~ tools for use with the present
invention will have a tip radius in the range of 0.5 to 5 mm.
As previously stated, resin layer 16 is preferably of a material that
is .... ......................... ...~-~hin~l-le without undue s.~ -g or chipping at room telllpcldlurc. If,
however, for some reason it is desired to use a m~teri~l that is not so m~rhin~hle
during the el~:t-opla~ing step, that m~teri~l may be removed and ~ d with a
".~hin~hle m~teri~l afta bumps 20 have been formed.
The use of resin layer 16 during the diamond turning step provides
~ignifi<~nt adv~nt~es. This material pf~tCet:i bumps 20 from abrupt contact withthe ~ ond tool and absoll,s much of the shear force applied to the bumps during
the ~ mond turning process. This helps to prevent the breakage di~c~ ed
previously.
The use of tli~mond turning provides ~ignific~nt advantages over the
prior art. As stated previously, it is very difficult, if not impossible, to form the
bumps to uniÇol." heights due to variations in the deposition p.ocess. This
problem is exace-l,a~ed by underlying variations in height at different locations on
the substrate. For example, if the bumps are formed by an electroplating process,
30 the height difrerence due to process variations will typically be about 5 percent.
This is in addition to the variations due to the unevenness of underlying surface.
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Further, if a constant pfcS~urc abrading process is used to attempt to p1~n~ri7e the
bumps, there will still be sig~ifi~nt height variation due to the nature of the
abrading process. In co~ to this, the height of the bumps following a diamond
turning operation are delelll,ined by the position of the ~ m~nd tool relative to the
5 surface being planari_ed. Thus, the surface being rli~mond turned will be blought
very close to a unifollll plane, identifi~d as plane 22 in Figure 6. Using ~i~mon~
turning techniques it is possible to pl~n~ri7~ the surfaces of bumps 20 such that the
,..~xi..."... deviation from plane 22 is 0.5 miclolll~ter. It is believed that it is
possible to reduce the ~ X;~ deviation to 0.1 micrometer.
If desired a different m~teri~1 may be applied to the pl~n~.;7e~
surfaces of bumps 20. Por ex~mr1e, a thin layer of gold 28, as shown in Figure
7, may be applied. Rec~u~e layer 28 is very thin, it will not signifi~nt1y reduce
the degree of p!~n~.;7i.~;on of the SulÇdccs of bumps 20. If the material is gold,
however, thin layer 28 will provide the desirable electrical contact plupcllies of
15 gold while minimi7ing the amount of gold required and thus the e-~l~n~e. The use
of the process of the present invention makes possible the use of much thinner
layers of gold than would be possible in the prior art. The prior art bumps would
include thicker layers of gold in order to tslce advantage of the greater
colllplcssibility of gold as colllp~d with copper in order to correct for the fact
20 that the sulraces of the bumps are not copl~ar. If greater precision is required,
the tli~mond turning could be pe.r~,rllled after gold layer 28 is applied instead of
before although this inc~ses the amount of gold ~uiled.
Following the application of thin layer 28, resin 16 is stripped away.
Following that, all of layer 14, except that portion directly underlying bumps 20,
25 is removed. The resu1ting structure is shown in Figure 8. When the structure of
Figure 8 is produce~, the device is ready for bonding using standard techniques
of plC~ U~ and/or heat. Rec~u~e the surfaces of the bumps confo~", much more
closely to a plane than in the prior art, however, the amount of pres~.l,c required
is reduced thus re~ucing the incidence of damage to the electronic circuits.
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In an ~ltern~tive embo~im~nt bumps 20 may be formed on a
t~lllpVl~y substrate and later transferred to electrically conductive layers lO as
taught by the Gurler and Hatada patents liccllcsed previously. If this procedure
is used, the bumps should be surrounded by a plute~ e resin prior to
S plan~i~lion by rli~mnnd turning.
Figure 9 is a flow chart of the plocess of the invention in its most
basic form. As shown in Figure 9, a subsll~le having electrodes thereon has
s~ d ele~tludes provided with e~ ;cA11y c~n~luctive bumps that are swlùunded
by a prvlec1i~re resin. In the second step the bumps and the resin layer are
10 ~ mond turned in order to plan~ize their e,.l,osed surfaces. The resin is then
removed to expose the bumps.
Figure lO is a flow chart of a more speeific embodiment of the
invention. According to the process of Figure lO, a substrate having a pluralityof electrodes has a layer of a mPt~llic conductor m~teri~1 sputlered thereon. A
15 layer of a radiation sensili-~e resin is then applied to the substrate covering the
spult~ered metal. The resin is then e,~vsed and developed leaving openings over
sP1e~t~P~l ones of the de~vdes. Electrically conductive bumps are formed in those
ope~ gs by ele~:l,vpl~ g. The e-pos~d surfaces of the resin and the bumps are
then planarized by di~ o~d turning. A thin layer of gold is then applied to the
20 tops of the bumps. Finally the resin and s~.ult~.et mPt~11ic layer, except for that
portion lying b~lween the bumps and the electrodes, are removed.
In an ~ltl -no~;~e e "ho~;---ent, shown in flow chart form in Figure
11, a plurality of bumps are formed on a ~Illpvl~y subslldte pleîel~bly by
ele~upl~l;Qg. Those bumps are removed from the tellll)vl~y substrate and
25 bonded to elecll~des on the pcl",anent ~ub~lldte. A layer of resin is then coated
over the bumps. The resin and the bumps are planarized by diamond turning and
the resin is removed.
The invention will provide significant advantages even in situations
where it is not used to permanently bond two electrical or electronic devices to one
30 another. One field where such advantages arise is that of the testing of integrated
circuits. In order to test such circuits, there must be good electrical contact
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belwæll the circuit under test and the test app~atus. One way to accomplish thisis to install the integlated circuit into its p~ging prior to conducting the test.
In this way the integlaled circuit communi~t~s electrically with the test equipment
in the same manner that it would in actual use. The disadvantage of this approach
5 is that all chips, even those that will eventually be rejected, must incur the expense
of p~ ~ging. FullllGlmo-e, in many cull~,ltly used m~tho~s, the package is
el;..,;n~1P~ entirely, so p~cl~e level testing is not an available option.
An ~ rn~tive to p~l ~ing the chips prior to testing them is to
provide a system for physically con~cting the col-ductor pads on the chip to the10 test app~alus without actually soldering anything to those conductor pads. One
way to do this is to provide appl~liate conductor traces on a test coupon and
cQI~n~t those traces to metal bumps coll~l,ollding to the contact pads on the chip.
These metal bumps may then be pressed into contact with the contact pad on the
chip in order to pel~llll the testfs. Due to the lack of coplanarity of the bumps
15 ~ ur~lur~d according to the prior art, an undue amount of pl~s~ure must be
exerted on the chip and the test coupon in order to insure good electrical contact
to all of the cor.duclol pads of the chip.
If one conductor pad does not make good electrical contact with the
test coupon, the chip may well test as defective even though it is not. If all of the
20 contact pads are in contact with t-h-e bumps on the test coupon, the force required
may cause dalllage to the chip. Al~lllati~ely, as described previously, if the chip
is of a pie~ . ;c material, the electric field caused by the p~s~ule could causethe chip to test as defective.
A test coupon may be m~mlfactured according to the present
25 invention. This will provide a test coupon having bumps whose surfaces are
highly coplallar. In this way the test coupon may be contacted to the chip to betested using much less p~ ule than otherwise would be n~ces~.~r, helping to
~limin~te the problems of prior art test coupons.
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Example 1
The following sequential steps were carried out:
1. A 0.5 mm thick silicon wafer, 10 cm in ~ meter~ was
primed with an ~ih~ion layer to be used as a s.lbs~ te.
2. A copper layer was sputter-de~s;Led to a thic~ness of 0.3
~m.
3. The wafer thir1~ness was Ill~su~d with a digital mic,~",eLer
to deLe."line a b~ ine for later use in deLe""ining the level of planarization.
4. The b~c~cide of the wafer was spin-coated with American
Hoechst AZP 4620 photoresist at 4000 rpm for 20 seconds, and baked at 85C for
15 minutes in a forced-air conveyer belt oven to produce a thin film approximately
15 ~m thick. This commercially available liquid photoresist contains ~cet~tes,
cresol novolak resin, and sulfonic esters. The b~cide photoresist coating was
applied to prevent electroplating onto errant copper that had been spull~red directly
15 onto the reverse side of the wafer.
5. The front side of the wafer was coated with the same
pholo~sist, AZP 4620, which was spin-coated at 2200 rpm for 40 se~on-ls and
baked at 85C for 15 ..;nu~es to produce a film appfoAimately 12 ~m thick.
6. The photoresist-coated wafer was exposed through a
20 lithog,dphic plate (mask) to ultraviolet (IJV) radiation of 405 nm wavelength and
40 mW/cm2 fluence for 15 s~nnds in a JBA brand eAI)oser/aligner. The mask
col~ ed a chrome-on-glass lilllOglaphic pattern col,esponding to an electronic
circuit.
7. The photoresist was developed in 1:4 solution of AZ400K
25 developer and deioni7~d (DI) water for 2 ,.,inl~es and 15 seconds, followed by a
45 minute rinse in DI water and drying under forced air. Regions of the
pholorcsist layer co"~s~nding to the circuit pattern were thereby opened for
plating.
8. The circuit pattern was electroplated with copper to build
30 bumps app,oAi...ately 6 ~m in height.
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9. After plating, the photoresist was stripped using J.T. Baker
PRS-1000, and the heights of the bumps were measured using the Alpha-Step 200
profilometer.
10. As in step 4, the b~c~cide of the wafer was coated again with
5 a thin layer of photoresist to prevent the plating of stray copper.
11. The wafer was coated with AZP 4620 photoresist at a spin
speed of 1600 rpm for 40 s~ol ~lc and baked at 85C for 15 .~inl~ s The spin-on
and bake were again ~p~led to create a double layer of pholor~sist app-o~ ely
30 ~m thick.
12. A photolithographic mask having fealuies co~ ing to
the bumps was aligned with the circuit trace feat~ues on the wafer and the
photoresist layer was ~A~)OSed for 60 secon~s to UV radiation as in Step 6. The
photolesist layer was then developed in 1:4 AZ400K/DI water developing solution
and then rinsed.
13. The bump pattern was electroplated with copper such that the
height of each of the bumps plus underlying circuit trace was a~l,luAil,lalely 23
~m.
14. The photoresist was stripped to allow the bump+trace height
to be Illeas.ll~.
15. A double layer of photoresist was spin coated onto the wafer
surface as in Step 11, covering the bumps and the underlying copper traces. Thisstep r~ ~C~l~ the support film removed in Step 15. In practice it would not be
n~s~.~ to measure the bump height before planali~lion and therefore Steps 14
and 15 would not normally be l~uilt;d.
16. Planarization was pelrulllled with an Anorad diamond-turning
hine; the di~molld tool cQ~cicted of a steel shank on which was mounted a
single crystal diamond with a face rounded to 0.75 mm and 0 rake angle. The
wafer was .--o~-nle~ on the m~ine's vacuum chuck, and the diamond tool was set
to cut the bump/pho~ ist colllpo~ile to a nominal 20 ~m above the wafer
surface; a spindle speed 3000 rpm and 15 cm/min. feed rate were used.
17. The pho~or~sist was stripped from the wafer.
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18. The heights of the planarized bumps+trace fe~t~res were
measured with respect to the surface of the silicon wafer over short ~ist~nc~ls in
several places using an Alpha-Step 200 surface profilometer. The measured
feature heights fell within a range of 19.5 - 20.6 ~m, the average being 20.04 llm
5 with a s~dard deviation of 0.2 ~m.
Example 2
After r~pe~t;ng Steps 1 lhlougll 14 as described in FY~...P,1e 1, the
following s~uen.ial steps were carried out:
15. A layer of Ciga-Geigy Probimiden' 412 polyimide was spin-
coated onto the surface of the wafer at a spin speed of 600 rpm for 40 seconds and
baked at 55C for 30 ...inules and 110C for 1 hour, covering the bumps and
underlying copper traces.
16. Planarization was p~lro,l"ed with an Anorad ~ mon~-turning
15 ~ r-hine; the ~i~moll~ tool consicted of a steel shank on which was mounted asingle crystal ~;~...OI-~ with a face rounded to 0.75 mm and 0 rake angle. The
wafer was ll-ounled on the m~r.hin.~.'s vacuum chuck, and the ~ mon.1 tool was set
to cut the bump/pholor~sisl cG...poc;le to a nominal 20 ,um above the wafer
surface; a spindle speed 3000 rpm and 15 cm/min. feed rate were used.
17. The polyimide was sllipl)ed using eth~nol~mine.
18. The heights of the plan~ui~d bumps were ",easured with
respect to the surface of the silicon wafer over short lict~nces in several places
using an Alpha-Step 200 surface profilometer. The measured feature heights were
within a range of 18.6 ,um to 20.8 ~m with an average height of 20.0 ~m and
25 standard deviation of 0.5 ,um.
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