Note: Descriptions are shown in the official language in which they were submitted.
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CECI EST LE TOME DE
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JUMBO APPLICATIONS/PATEN~S
THIS SECTION OF THE APPUCATION/PATENT CONTAINS MORE
THAN ONE VOLUME
THIS IS VOLUME I OF 3
NOTE: ~or additional volumes please contact ~he Canadian Patent Office
` 2145159
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lNv~nsE QUA~rrIZER
This application claims priority from British Application
No. British Application No. 9405914.4 filed March 24, 1994 and
British Application No. (not yet known) filed February 28, 1995.
R~C~ROUND OF THE lNv~N-llON
The present invention is directed to improvements in
methods and apparatus for decompression which operates to
decompress and/or decode a plurality of differently encoded
input signals. The illustrative embodiment chosen for
description hereinafter relates to the decoding of a plurality
of encoded picture standards. More specifically, this
embodiment relates to the decoding of any one of the well known
standards known as JPEG, MPEG and H.261.
A serial pipeline processing system of the present
invention comprises a single two-wire bus used for carrying
unique and specialized interactive interfacing tokens, in the
form of control tokens and data tokens, to a plurality of
adaptive decompression circuits and the like positioned as a
reconfigurable pipeline processor.
Video compression/decompression systems are generally well-
known in the art. However, such systems have generally been
dedicated in design and use to a single compression standard.
They have also suffered from a number of other inefficiencies
and inflexibility in overall system and subsystem design and
data flow management.
Examples of prior art systems and subsystems are enumerated
as follows:
One prior art system is described in United States Patent
No. 5,216,724. The apparatus comprises a plurality of compute
modules, in a preferred embodiment, for a total of four compute
modules coupled in parallel. Each of the
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compute modules has a processor, dual port memory, scratch-
pad memory, and an arbitration mechanism. A first bus
couples the compute modules and a host processor. The device
comprises a shared memory which is coupled to the host
processor and to the compute modules with a second bus.
United States Patent No. 4,785,349 discloses a full
motion color digital video signal that is compressed,
formatted for transmission, recorded on compact disc media
and decoded at conventional video frame rates. During
compression, regions of a frame are individually analyzed to
select optimum fill coding methods specific to each region.
Region decoding time estimates are made to optimize
compression thresholds. Region descriptive codes conveying
the size and locations of the regions are grouped together in
a first segment of a data stream. Region fill codes
conveying pixel amplitude indications for the regions are
grouped together according to fill code type and placed in
other segments of the data stream. The data stream segments
are individually variable length coded according to their
respective statistical distributions and formatted to form
data frames. The number of bytes per frame is withered by
the addition of auxiliary data determined by a reverse frame
sequence analysis to provide an average number selected to
minimize pauses of the compact disc during playback, thereby
avoiding unpredictable seek mode latency periods
characteristic of compact discs. A decoder includes a
variable length decoder responsive to statistical information
in the code stream for separately variable length decoding
individual segments of the data stream. Region location data
is derived from region descriptive data and applied with
region fill codes to a plurality of region specific decoders
selected by detection of the fill code type (e.g., relative,
absolute, dyad and DPCM) and decoded region pixels are stored
in a bit map for subsequent display.
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United States Patent No. 4,922,341 discloses a method
for scene-model-assisted reduction of image data for digital
television signals, whereby a picture signal supplied at time
is to be coded, whereby a predecessor frame from a scene
already coded at time t-1 is present in an image store as a
reference, and whereby the frame-to-frame information is
composed of an amplification factor, a shift factor, and an
adaptively acquired quad-tree division structure. Upon
initialization of the system, a uniform, prescribed gray
scale value or picture half-tone expressed as a defined
luminance value is written into the image store of a coder at
the transmitter and in the image store of a decoder at the
receiver store, in the same way for all picture elements
(pixels). Both the image store in the coder as well as the
image store in the decoder are each operated with feed back
to themselves in a manner such that the content of the image
store in the coder and decoder can be read out in blocks of
variable size, can be amplified with a factor greater than or
less than 1 of the luminance and can be written back into the
image store with shifted addresses, whereby the blocks of
variable size are organized according to a known quad tree
data structure.
United States Patent No. 5,122,875 discloses an
apparatus for encoding/decoding an HDTV signal. The
apparatus includes a compression circuit responsive to high
definition video source signals for providing hierarchically
layered codewords CW representing compressed video data and
associated codewords T, defining the types of data
represented by the codewords CW. A priority selection
circuit, responsive to the codewords CW and T, parses the
codewords CW into high and low priority codeword sequences
wherein the high and low priority codeword sequences
correspond to compressed video data of relatively greater and
lesser importance to image reproduction respectively. A
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transport processor, responsive to the high and low priority
codeword sequences, forms high and low priority transport
blocks of high and low priority codewords, respectively.
Each transport block includes a header, codewords CW and
error detection check bits. The respective transport blocks
are applied to a forward error check circuit for applying
additional error check data. Thereafter, the high and low
priority data are applied to a modem wherein quadrature
amplitude modulates respective carriers for transmission.
United States Patent No. 5,146,325 discloses a video
decompression system for decompressing compressed image data
wherein odd and even fields of the video signal are
independently compressed in sequences of intraframe and
interframe compression modes and then interleaved for
transmission. The odd and even fields are independently
decompressed. During intervals when valid decompressed
odd/even field data is not available, even/odd field data is
substituted for the unavailable odd/even field data.
Independently decompressing the even and odd fields of data
and substituting the opposite field of data for unavailable
data may be used to advantage to reduce image display latency
during system start-up and channel changes.
United States Patent No. 5,168,356 discloses a video
signal encoding system that includes apparatus for segmenting
2S encoded video data into transport blocks for signal
transmission. The transport block format enhances signal
recovery at the receiver by virtue of providing header data
from which a receiver can determine re-entry points into the
data stream on the occurrence of a loss or corruption of
transmitted data. The re-entry points are maximized by
providing secondary transport headers embedded within encoded
video data in respective transport blocks.
United States Patent No. 5,168,375 discloses a method
for processing a field of image data samples to provide for
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one or more of the functions of decimation, interpolation,
and sharpening. This is accomplished by an array transform
processor such as that employed in a JPEG compression system.
Blocks of data samples are transformed by the discrete even
cosine transform (DECT) in both the decimation and
interpolation processes, after which the number of frequency
terms is altered. In the case of decimation, the number of
frequency terms is reduced, this being followed by inverse
transformation to produce a reduced-size matrix of sample
points representing the original block of data. In the case
of interpolation, additional frequency components of zero
value are inserted into the array of frequency components
after which inverse transformation produces an enlarged data
sampling set without an increase in spectral bandwidth. In
the case of sharpening, accomplished by a convolution or
filtering operation involving multiplication of transforms of
data and filter kernel in the frequency domain, there is
provided an inverse transformation resulting in a set of
blocks of processed data samples. The blocks are overlapped
followed by a savings of designated samples, and a discarding
of excess samples from regions of overlap. The spatial
representation of the kernel is modified by reduction of the
number of components, for a linear-phase filter, and zero-
padded to equal the number of samples of a data block, this
being followed by forming the discrete odd cosine transform
(DOCT) of the padded kernel matrix.
United States Patent No. 5,175,617 discloses a system
and method for transmitting logmap video images through
telephone line band-limited analog channels. The pixel
organization in the logmap image is designed to match the
sensor geometry of the human eye with a greater concentration
of pixels at the center. The transmitter divides the
frequency band into channels, and assigns one or two pixels
to each channel, for example a 3KHz voice quality telephone
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line is divided into 768 channels spaced about 3.9Hz apart.
Each channel consists of two carrier waves in quadrature, so
each channel can carry two pixels. Some channels are
reserved for special calibration signals enabling the
receiver to detect both the phase and magnitude of the
received signal. If the sensor and pixels are connected
directly to a bank of oscillators and the receiver can
continuously receive each channel, then the receiver need not
be synchronized with the transmitter. An FFT algorithm
implements a fast discrete approximation to the continuous
case in which the receiver synchronizes to the first frame
and then acguires subsequent frames every frame period. The
frame period is relatively low compared with the sampling
period so the receiver is unlikely to lose frame synchrony
once the first frame is detected. An experimental video
telephone transmitted 4 frames per second, applied quadrature
coding to 1440 pixel logmap images and obtained an effective
data transfer rate in excess of 40,000 bits per second.
United States Patent No. 5,185,819 discloses a video
compression system having odd and even fields of video signal
that are independently compressed in seguences of intraframe
and interframe compression modes. The odd and even fields of
independently compressed data are interleaved for
transmission such that the intraframe even field compressed
data occurs midway between successive fields of intraframe
odd field compressed data. The interleaved sequence provides
receivers with twice the number of entry points into the
signal for decoding without increasing the amount of data
transmitted.
United States Patent No. 5,212,742 discloses an
apparatus and method for processing video data for
compression/decompression in real-time. The apparatus
comprises a plurality of compute modules, in a preferred
embodiment, for a total of four compute modules coupled in
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parallel. Each of the compute modules has a processor, dual
port memory, scratch-pad memory, and an arbitration
mechanism. A first bus couples the compute modules and host
processor. Lastly, the device comprises a shared memory
which is coupled to the host processor and to the compute
modules with a second bus. The method handles assigning
portions of the image for each of the processors to operate
upon.
United States Patent No. 5,231,484 discloses a system
and method for implementing an encoder suitable for use with
the proposed ISO/IEC MPEG standards. Included are three
cooperating components or subsystems that operate to
variously adaptively pre-process the incoming digital motion
video sequences, allocate bits to the pictures in a sequence,
and adaptively quantize transform coefficients in different
regions of a picture in a video sequence so as to provide
optimal visual quality given the number of bits allocated to
that picture.
United States Patent No. 5,267,334 discloses a method of
removing frame redundancy in a computer system for a sequence
of moving images. The method comprises detecting a first
scene change in the sequence of moving images and generating
a first keyframe containing complete scene information for a
first image. The first keyframe is known, in a preferred
embodiment, as a "forward-facing" keyframe or intraframe, and
it is normally present in CCITT compressed video data. The
process then comprises generating at least one intermediate
compressed frame, the at least one intermediate compressed
frame containing difference information from the first image
for at least one image following the first image in time in
the sequence of moving images. This at least one frame being
known as an interframe. Finally, detecting a second scene
change in the sequence of moving images and generating a
second keyframe containing complete scene information for an
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image displayed at the time just prior to the second scene
change, known as a "backward-facing" keyframe. The first
keyframe and the at least one intermediate compressed frame
are linked for forward play, and the second keyframe and the
intermediate compressed frames are linked in reverse for
reverse play. The intraframe may also be used for generation
of complete scene information when the images are played in
the forward direction. When this sequence is played in
reverse, the backward-facing keyframe is used for the
generation of complete scene information.
United States Patent No. 5,276,513 discloses a first
circuit apparatus, comprising a given number of prior-art
image-pyramid stages, together with a second circuit
apparatus, comprising the same given number of novel motion-
vector stages, perform cost-effective hierarchical motion
- analysis (HMA) in real-time, with minimum system processing
delay and/or employing minimum system processing delay and/or
employing minimum hardware structure. Specifically, the
first and second circuit apparatus, in response to relatively
high-resolution image data from an ongoing input series of
successive given pixel-density image-data frames that occur
at a relatively high frame rate (e.g., 30 frames per second),
derives, after a certain processing-system delay, an ongoing
output series of successive given pixel-density vector-data
frames that occur at the same given frame rate. Each vector-
data frame is indicative of image motion occurring between
each pair of successive image frames.
United States Patent No. 5,283,646 discloses a method
and apparatus for enabling a real-time video encoding system
to accurately deliver the desired number of bits per frame,
while coding the image only once, updates the quantization
step size used to quantize coefficients which describe, for
example, an image to be transmitted over a communications
channel. The data is divided into sectors, each sector
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.
including a plurality of blocks. The blocks are encoded, for
example, using DCT coding, to generate a sequence of
coefficients for each block. The coefficients can be
quantized, and depending upon the quantization step, the
number of bits required to describe the data will vary
significantly. At the end of the transmission of each sector
of data, the accumulated actual number of bits expended is
compared with the accumulated desired number of bits
expended, for a selected number of sectors associated with
the particular group of data. The system then readjusts the
quantization step size to target a final desired number of
data bits for a plurality of sectors, for example describing
an image. Various methods are described for updating the
quantization step size and determining desired bit
allocations.
The article, Chong, Yong M., A Data-Flow Architecture
for Digital Image Processing, Wescon Technical Papers: No.
2 Oct./Nov. 1984, discloses a real-time signal processing
system specifically designed for image processing. More
particularly, a token based data-flow architecture is
disclosed wherein the tokens are of a fixed one word width
having a fixed width address field. The system contains a
plurality of identical flow processors connected in a ring
fashion. The tokens contain a data field, a control field
and a tag. The tag field of the token is further broken down
into a processor address field and an identifier field. The
processor address field is used to direct the tokens to the
correct data-flow processor, and the identifier field is used
to label the data such that the data-flow processor knows
what to do with the data. In this way, the identifier field
acts as an instruction for the data-flow processor. The
system directs each token to a specific data-flow processor
using a module number (MN). If the MN matches the MN of the
particular stage, then the appropriate operations are
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performed upon the data. If unrecognized, the token is
directed to an output data bus.
The article, Kimori, S. et al. An Elastic Pi~eline
Mechanism by Self-Timed Circuits, IEEE J. of Solid-State
Circuits, Vol. 23, No. 1, February 1988, discloses an elastic
pipeline having self-timed circuits. The asynchronous
pipeline comprises a plurality of pipeline stages. Each of
the pipeline stages consists of a group of input data latches
followed by a combinatorial logic circuit that carries out
logic operations specific to the pipeline stages. The data
latches are simultaneously supplied with a triggering signal
generated by a data-transfer control circuit associated with
that stage. The data-transfer control circuits are
interconnected to form a chain through which send and
acknowledge signal lines control a hand-shake mode of data
transfer between the successive pipeline stages.
Furthermore, a decoder is generally provided in each stage to
select operations to be done on the operands in the present
stage. It is also possible to locate the decoder in the
preceding stage in order to pre-decode complex decoding
processing and to alleviate critical path problems in the
logic circuit. The elastic nature of the pipeline eliminates
any centralized control since all the interworkings between
the submodules are determined by a completely localized
decision and, in addition, each submodule can autonomously
perform data buffering and self-timed data-transfer control
at the same time. Finally, to increase the elasticity of the
pipeline, empty stages are interleaved between the occupied
stages in order to ensure reliable data transfer between the
stages.
United States Patent No. 5,124,790 to Nakayama discloses
a reverse quantizer to be used with image memory. The
inverse quantizer is used in the standard way to decode
differential predictive coding method (DPCM) encoded data.
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United States Patent No. 5,136,371 to Savatier et al. is
directed to a de-quantizer having an adjustable
quantizational level which is variable and determined by the
fullness of the buffer. The applicants state that the novel
aspect of their invention is the maximum available data rate
that is achieved. Buffer overflow and underflow is avoided
by adapting the quantization step size the quantizer 152 and
the de-quantizer 156 by means of a quantizational level which
is recalculated after each block has been encoded. The
quantization level is calculated as a function of the amount
of already encoded data for the frame, compared with the
total buffer size. In this manner, the quantization level
can advantageously be recalculated by the decoder and does
not have to be transmitted.
United States Patent No. 5,142,380 to Sakagami et al.
discloses an image compression apparatus suitable for use
with still images such as those formed by electronic still
cameras using solid state image sensors. The quantizer
employed is connected to a memory means from which threshold
values of a quantization matrix for the laminate signal, Y,
and rom 15 stores threshold values of a quantization matrix
for the crominant signals I and Q.
United States Patent No. 5,193,002 to Guichard et al.
disclosed an apparatus for coding/decoding image signals in
real time in conjunction with the CCITT standard H.261. A
digital signal processor carries out direct quantization and
reverse quantization.
United States Patent No. 5,241,383 to Chen et al.
describes an apparatus with a pseudo-constant bit rate video
coding achieved by an adjustable quantization parameter. The
qunatization parameter utilized by the quantizer 32 is
periodically adjusted to increase or decrease the amount of
code bits generated by the coding circuit. The change in
quantization parameters for coding the next group of pictures
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is determined by a deviation measure between the actual
number of code bits generated by the coding circuits for the
previous group of pictures in an estimate number of code bits
for the previous group of pictures. The number of code bits
generated by the coding circuit is controlled by controlling
the quantizer step sizes. In general smaller quantizer step
sizes result in more code bits in larger quantizer step sizes
result in fewer code bits.
United States Patent No. 5,113,255 to Nagata et al;
5,126,842 to Andrews et al; 5,253,058 to Gharavi; 5,260,782
to Hui; and 5,212,742 to Normile et al are included for
background and as a general description of the art.
Accordingly, those concerned with the design,
development and use of video compression/decompression
systems and related subsystems have long recognized a need
for improved methods and apparatus providing enhanced
flexibility, efficiency and performance. The present
invention clearly fulfills all these needs.
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8UMMARY OF T~E lNv~ lON
Briefly, and in general terms, the present invention
provides in a pipeline system having an inverse modeller
stage and an inverse discrete cosine transform stage, the
improvement characterized by a processing stage, positioned
between the inverse modeller stage and the inverse discrete
cosine transform stage, responsive to a token table for
processing data.
In accordance with the invention, the token may be a
QUANT_TABLE token for causing the processing stage to
generate a quantization table.
The above and other objectives and advantages of the
invention will become apparent from the following more
detailed description when taken in conjunction with the
accompanying drawings.
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DE8CRIPTION OF THE DRAWING8
Figure. 1 illustrates six cycles of a six-stage pipeline for
different combinations of two internal control signals;
Figures. 2a and 2b illustrate a pipeline in which each stage
includes auxiliary data storage. They also show the manner
in which pipeline stages can "compress" and "expand" in
response to delays in the pipeline;
Figures. 3a(1), 3a(2), 3b(1) and 3b(2) illustrate the control
of data transfer between stages of a preferred embodiment of
a pipeline using a two-wire interface and a muiti-phase
clock;
Figure. 4 is a block diagram that illustrates a basic
embodiment of a pipeline stage that incorporates a two-wire
transfer control and also shows two consecutive pipeline
lS processing stages with the two-wire transfer control;
Figures. 5a and 5b taken together depict one example of a
timing diagram that shows the relationship between timing
signals, input and output data, and internal control signals
used in the pipeline stage as shown in Figure. 4;
Figure. 6 is a block diagram of one example of a pipeline
stage that holds its state under the control of an extension
bit;
Figure. 7 is a block diagram of a pipeline stage that decodes
stage activation data words;
Figures. 8a and 8b taken together form a block diagram
showing the use of the two-wire transfer control in an
exemplifying "data~duplication" pipeline stage;
Figures. 9a and 9b taken together depict one example of a
timing diagram that shows the two-phase clock, the two-wire
transfer control signals and the other internal data and
control signals used in the exemplifying embodiment shown in
Figures. 8a and 8b.
Figure 10 is a block diagram of a reconfigurable processing
stage;
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Figure 11 is a block diagram of a spatial decoder;
Figure 12 is a block diagram of a temporal decoder;
Figure 13 is a block diagram of a video formatter;
Figures 14a-c show various arrangements of memory blocks used
in the present invention:
Figure 14a is a memory map showing a first
arrangement of macroblocks;
Figure 14b is a memory map showing a second
arrangement of macroblocks;
Figure 14c is a memory map showing a further
arrangement of macroblocks;
Figure 15 shows a Venn diagram of possible table selection
values;
Figure 16 shows the variable length of picture data used in
the present invention;
Figure 17 is a block diagram of the temporal decoder
including the prediction filters;
Figure 18 is a pictorial representation of the prediction
filtering process;
Figure 19 shows a generalized representation of the
macroblock structure;
Figure 20 shows a generalized block diagram of a Start Code
Detector;
Figure 21 illustrates examples of start codes in a data
stream;
Figure 22 is a block diagram depicting the relationship
between the flag generator, decode index, header
generator, extra word generator and output latches;
Figure 23 is a block diagram of the Spatial Decoder DRAM
interface;
Figure 24 is a block diagram of a write swing buffer;
Figure 25 is a pictorial diagram illustrating prediction data
offset from the block being processed;
Figure 26 is a pictorial diagram illustrating prediction data
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16
offset by (1,1);
Figure 27 is a block diagram illustrating the Huffman decoder
and parser state machine of the Spatial Decoder.
Figure 28 is a block diagram illustrating the prediction
filter.
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17
FIGURE8
Figure 29 shows a typical decoder system;
Figure 30 shows a JPEG still picture decoder;
Figure 31 shows a JPEG video decoder;
5 Figure 32 shows a multi-stAn~Ard video decoder;
Figure 33 shows the start and the end of a token;
Figure 34 shows a token address and data fields;
Figure 35 shows a token on an interface wider than
8 bits;
10 Figure 36 shows a macroblock structure;
Figure 37 shows a two-wire interface protocol;
Figure 38 shows the location of external two-wire
interfaces;
Figure 39 shows clock propagation;
15 Figure 40 shows two-wire interface timing;
Figure 41 shows examples of access structure;
Figure 42 shows a read transfer cycle;
Figure 43 shows an access start tlmlng;
Figure 44 shows an example access with two write
20 transfers;
Figure 45 shows a read transfer cycle;
Figure 46 shows a write transfer cycle;
Figure 47 shows a refresh cycle;
Figure 48 shows a 32 bit data bus and a 256 kbit
deep DRAMs (9 bit row address);
Figure 49 shows timing parameters for any strobe
signal;
Figure 50 shows timing parameters between any two
strobe signals;
30 Figure 51 shows timing parameters between a bus and
a strobe;
Figure 52 shows timing parameters between a bus and
a strobe;
Figure 53 shows an MPI read timing;
35 Figure 54 shows an MPI write timing;
Figure 55 shows organization of large integers in
the memory map;
Figure 56 shows a typical decoder clock regime;
Figure 57 ~ shows input clock requirements;
40 Figure 58 shows the Spatial Decoder;
Figure 59 shows the inputs and outputs of the input
circuit;
Figure 60 shows the coded port protocol;
Figure 61 shows the start code detector;
45 Figure 62 shows start codes detected and converted
to Tokens;
Figure 63 shows the start codes detector passing
Tokens; shows overlapping MPEG start codes (byte
aligned);
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18
Figure 65 shows overlapping MPEG start codes (not
byte aligned);
Figure 66 shows jumping between two video
sequences;
5 Figure 67 shows a sequence of extra Token
insertion;
Figure 68 shows decoder start-up control;
Figure 69 shows enabled streams queued before the
output;
10 Figure 70 shows a spatial decoder buffer;
Figure 71 shows a buffer pointer;
Figure 72 shows a video demux;
Figure 73 shows a construction of a picture;
Figure 74 shows a construction of a 4:2:2
15 macroblock;
Figure 75 shows a calculating macroblock dimension
from pel ones;
Figure 76 shows spatial decoding;
Figure 77 shows an overview of H.261 inverse
20 quantization;
Figure 78 shows an overview of JPEG inverse
quantization;
Figure 79 shows an overview of MPEG inverse
quantization;
25 Figure 80 shows a quantization table memory map;
Figure 81 shows an overview of JPEG baseline
sequential structure;
Figure 82 shows a tokenised JPEG picture;
Figure 83 shows a temporal decoder;
30 Figure 84 shows a picture buffer specification;
Figure 85 shows an MPEG picture sequence (m=3);
Figure 86 shows how "I" pictures are stored and
output;
Figure 87 shows how "P" pictures are formed, stored
35 and output;
Figure 88 shows how "B" pictures are formed and
output;
Figure 89 shows P picture formation;
Figure 90 shows H.261 prediction formation;
Figure 91 shows an H.261 "sequence";
Figure 92 shows a hierarchy of H.261 syntax;
Figure 93 shows an H.261 picture layer;
Figure 94 shows an H.261 arrangement of groups of
blocks;
Figure 95 shows an H.261 "slice" layer;
Figure 96 shows an H.261 arrangement of
macroblocks;
Figure 97 shows an H.261 sequence of blocks;
Figure 98 shows an H.261 macroblock layer;
Figure 99 shows an H.261 arrangement of pels in
blocks;
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Figure 100 shows a hierarchy of MPEG syntax;
Figure 101 shows an MPEG sequence layer;
Figure 102 shows an MPEG group of pictures layer;
Figure 103 shows an MPEG picture layer;
5 Figure 104 shows an MPEG "slice" layer;
Figure 105 shows an MPEG sequence of blocks;
Figure 106 shows an MPEG macroblock layer;
Figure 107 shows an "open GOP";
Figure 108 shows examples of access structure;
10 Figure 109 shows access start timing;
Figure 110 shows a fast page read cycle;
Figure 111 shows a fast page write cycle;
Figure 112 shows a refresh cycle;
Figure 113 shows extracting row and column address
15 from a chip address;
Figure 114 shows timing parameters for any strobe
signal;
Figure 115 shows timing parameters between any two
strobe signals;
20 Figure 116 shows timing parameters between a bus and
a strobe;
Figure 117 shows timing parameters between a bus and
a strobe;
Figure 118 shows a Huffman decoder and parser;
Figure 119 shows an H.261 and an MPEG AC Coefficient
Decoding Flow Chart;
Figure 120 shows a block diagram for JPEG (AC and
DC) coefficient decoding;
Figure 121 shows a flow diagram for JPEG (AC and DC)
coefficient decoding;
Figure 122 shows an interface to the Huffman Token
Formatter;
Figure 123 shows a token formatter block diagram;
Figure 124 shows an H.261 and an MPEG AC Coefficient
Decoding;
Figure 125 shows the interface to the Huffman ALU;
Figure 126 shows the basic structure of the Huffman
ALU;
Figure 127 shows the buffer manager;
40 Figure 128 . shows an imodel and hsppk block diagram;
Figure 129 shows an imex state diagra.m;
Figure 130 illustrates the buffer start-up;
Figure 131 shows a DRAM interface;
Figure 132 shows a write swing buffer;
45 Figure 133 shows an arithmetic block;
Figure 134 shows an iq block diagram;
Figure 135 shows an iqca state machine;
Figure 136 shows an IDCT 1-D Transform Algorithm;
Figure 137 shows an IDCT 1-D Transform Architecture;
50 Figure 138 shows a token stream block diagram;
Figure 139 shows a standard block structure;
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Figure 140 is a block diagram showi~g;
microprocessor test access;
Figure 141 shows 1-D Transform Micro-Architecture;
Figure 142 shows a temporal decoder block diagram;
5 Figure 143 shows the structure of a Two-wire
interface stage;
Figure 144 shows the address generator block
diagram;
Figure 145 shows the block and pixel offsets;
10 Figure 146 shows multiple prediction filters;
Figure 147 shows a single prediction filter;
Figure 148 shows the 1-D prediction filter;
Figure 149 shows a block of pixels;
Figure 150 shows the structure of the read rudder;
15 Figure 151 shows the block and pixel offsets;
Figure 152 shows a prediction example;
Figure 153 shows the read cycle;
Figure 154 shows the write cycle;
Figure 155 shows the top-level registers block
diagram with timing references;
Figure 156 shows the control for incrementing
presentation numbers;
Figure 157 shows the buffer manager state machine
(complete);
Figure 158 shows the state machine main loop;
Figure 159 shows the buffer 0 containing an SIF (22
by 18 macroblocks) picture;
Figure 160 shows the SIF component 0 with a display
window;
Figure 161 shows an example picture format showing
storage block address;
Figure 162 shows a buffer 0 containing a SIF (22 by
18 macroblocks) picture;
Figure 163 shows an example address calculation;
35 Figure 164 shows a write address generation state
machine;
Figure 165 shows a slice of the datapath;
Figure 166 shows a two cycle operation of the
datapath;
40 Figure 167 shows mode 1 filtering;
Figure 168 shows a horizontal up-sampler datapath;
and
Figure 169 shows the structure of the color-space
converter.
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LEFT BLANK.
214S159
22
In the ensuing description of the practice of the
invention, the following terms are frequently used and are
generally defined by the following glossary:
GL088ARY
BLOCR: An 8-row by 8-column matrix of pels, or 64 DCT
coefficients (source, quantized or dequantized).
CHROMINANCE ~COMPONENT): A matrix, block or single pel
representing one of the two color difference signals related
to the primary colors in the manner defined in the bit
stream. The symbols used for the color difference signals
are Cr and Cb.
CODED REPRE8ENTATION: A data element as represented in its
encoded form.
CODED VIDEO BIT 8TREAM: A coded representation of a series of
one or more pictures as defined in this specification.
CODED ORDER: The order in which the pictures are transmitted
and decoded. This order is not necessarily the same as the
display order.
COMPONENT: A matrix, block or single pel from one of the
three matrices (luminance and two chrominance) that make up
a picture.
COMPRE88ION: Reduction in the number of bits used to
represent an item of data.
DECODER: An embodiment of a decoding process.
DECODING (PROCESS): The process defined in this specification
that reads an input coded bitstream and produces decoded
pictures or audio samples.
DI8PLAY ORDER: The order in which the decoded pictures are
displayed. Typically, this is the same order in which they
were presented at the input of the encoder.
ENCODING (PROCESS): A process, not specified in this
specification, that reads a stream of input pictures or audio
samples and produces a valid coded bitstream as defined in
this specification.
21~5159
23
INTRA CODING: Coding of a macroblock or picture that uses
information only from that macroblock or picture.
L~TN~NCE (COMrO~ ..): A matrix, block or single pel
representing a monochrome representation of the signal and
related to the primary colors in the manner defined in the
bit stream. The symbol used for luminance is Y.
MACROBLOC~: The four 8 by 8 blocks of luminance data and the
two (for 4:2:0 chroma format) four (for 4:2: 2 chroma format)
or eight (for 4:4:4 chroma format) corresponding 8 by 8
blocks of chrominance data coming from a 16 by 16 section of
the luminance component of the picture. Macroblock is
sometimes used to refer to the pel data and sometimes to the
coded representation of the pel values and other data
elements defined in the macroblock header of the syntax
defined in this part of this specification. To one of
ordinary skill in the art, the usage is clear from the
context.
MOTION COMPENSATION: The use of motion vectors to improve the
efficiency of the prediction of pel values. The prediction
uses motion vectors to provide offsets into the past and/or
future reference pictures containing previously decoded pel
values that are used to form the prediction error signal.
MOTION v~ Ok: A two-dimensional vector used for motion
compensation that provides an offset from the coordinate
position in the current picture to the coordinates in a
reference picture.
NON-INTRA CODING: Coding of a macroblock or picture that uses
information both from itself and from macroblocks and
pictures occurring at other times.
PEL: Picture element.
PICTURE: Source, coded or reconstructed image data. A source
or reconstructed picture consists of three rectangular
matrices of 8-bit numbers representing the luminance and two
chrominance signals. For progressive video, a picture is
2 1`~ 9
24
identical to a frame, while for interlaced video, a picture
can refer to a frame, or the top field or the bottom field of
the frame depending on the context.
PREDICTION: The use of a predictor to provide an estimate of
the pel value or data element currently being decoded.
P~CQNFIGURAR~E PROCE88 8TAGE (RP8): A stage, which in
response to a recognized token, reconfigures itself to
perform various operations.
8LICE: A series of macroblocks.
TOREN: A universal adaptation unit in the form of an
interactive interfacing messenger package for control and/or
data functions.
8TART CODE8 t8YSTEN AND VIDEO]: 32-bit codes embedded in a
coded bitstream that are unique. They are used for several
purposes including identifying some of the structures in the
coding syntax.
VARTARTT~ LENGTH CODING; VLC: A reversible procedure for
coding that assigns shorter code-words to frequent events and
longer code-words to less frequent events.
VIDEO 8EQ~ENCE: A series of one or more pictures.
Detailed Descriptions
21~5159
DESCRIPTION OF THE PREFERRED EMBODIMENT(8)
As an introduction to the most general features used in a
pipeline system which is utilized in the preferred
embodiments of the invention, Fig. 1 is a greatly simplified
illustration of six cycles of a six-stage pipeline. (As is
explained in greater detail below, the preferred embodiment
of the pipeline includes several advantageous features not
shown in Fig 1.).
Referring now to the drawings, wherein like reference
numerals denote like or corresponding elements throughout the
various figures of the drawings, and more particularly to
Fig. 1, there is shown a block diagram of six cycles in
practice of the present invention. Each row of boxes
illustrates a cycle and each of the different stages are
labelled A-F, respectively. Each shaded box indicates that
the corresponding stage holds valid data, i.e., data that is
to be processed in one of the pipeline stages. After
processing (which may involve nothing more than a simple
transfer without manipulation of the data) valid data is
transferred out of the pipeline as valid output data.
Note that an actual pipeline application may include more
or fewer than six pipeline stages. As will be appreciated,
the present invention may be used with any number of pipeline
stages. Furthermore, data may be processed in more than one
stage and the processing time for different stages can
differ.
In addition to clock and data signals (described below),
the pipeline includes two transfer control signals -- a
"VALID" signal and an "ACCEPT" signal. These signals are
used to control the transfer of data within the pipeline.
The VALID signal, which is illustrated as the upper of the
two lines connecting neighboring stages, is passed in a
forward or downstream direction from each pipeline stage to
the nearest neighboring device. This device may be another
~145159
.
26
pipeline stage or some other system. For example, the last
pipeline stage may pass its data on to subsequent processing
circuitry. The ACCEPT signal, which is illustrated as the
lower of the two lines connecting neighboring stages, passes
in the other direction upstream to a preceding device.
A data pipeline system of the type used in the practice of
the present invention has, in preferred embodiments, one or
more of the following characteristics:
1. The pipeline is "elastic" such that a delay at a
particular pipeline stage causes the minimum disturbance
possible to other pipeline stages. Succeeding pipeline
stages are allowed to continue processing and, therefore,
this means that gaps open up in the stream of data
following the delayed stage. Similarly, preceding
pipeline stages may also continue where possible. In this
case, any gaps in the data stream may, wherever possible,
be removed from the stream of data.
2. Control signals that arbitrate the pipeline are
organized so that they only propagate to the nearest
neighboring pipeline stages. In the case of signals
flowing in the same direction as the data flow, this is
the immediately succeeding stage. In the case of signals
flowing in the opposite direction to the data flow, this
is the immediately preceding stage.
3. The data in the pipeline is encoded such that many
different types of data are processed in the pipeline.
This encoding accommodates data packets of variable size
and the size of the packet need not be known in advance.
4. The overhead associated with describing the type of
data is as small as possible.
5. It is possible for each pipeline stage to recognize
only the minimum number of data types that are needed for
its required function. It should, however, still be able
to pass all data types onto the succeeding stage even
2145159
27
though it does not recognize them. This enables
communication between non-adjacent pipeline stages.
Although not shown in Fig. l, there are data lines,
either single lines or several parallel lines, which form a
data bus that also lead into and out of each pipeline stage.
As is explained and illustrated in greater detail below, data
is transferred into, out of, and between the stages of the
pipeline over the data lines.
Note that the first pipeline stage may receive data and
control signals from any form of preceding device. For
example, reception circuitry of a digital image transmission
system, another pipeline, or the like. On the other hand, it
may generate itself, all or part of the data to be processed
in the pipeline. Indeed, as is explained below, a "stage"
may contain arbitrary processing circuitry, including none at
all (for simple passing of data) or entire systems (for
example, another pipeline or even multiple systems or
pipelines), and it may generate, change, and delete data as
desired.
When a pipeline stage contains valid data that is to be
transferred down the pipeline, the VALID signal, which
indicates data validity, need not be transferred further than
to the immediately subsequent pipeline stage. A two-wire
. interface is, therefore, included between every pair of
pipeline stages in the system. This includes a two-wire
interface between a preceding device and the first stage, and
between a subsequent device and the last stage, if such other
devices are included and data is to be transferred between
them and the pipeline.
Each of the signals, ACCEPT and VALID, has a HIGH and a
LOW value. These values are abbreviated as ~H" and "L",
respectively. The most common applications of the pipeline,
in practicing the invention, will typically be digital. In
such digital implementations, the HIGH value may, for
21451~9
28
example, be a logical "1" and the LOW value may be a logical
"O". The system is not restricted to digital
implementations, however, and in analog implementations, the
HIGH value may be a voltage or other similar quantity above
(or below) a set threshold, with the LOW value being
indicated by the corresponding signal being below (or above)
the same or some other threshold. For digital applications,
the present invention may be implemented using any known
technology, such as CMOS, bipolar etc.
It is not necessary to use a distinct storage device and
wires to provide for storage of VALID signals. This is true
even in a digital embodiment. All that is re~uired is that
the indication of "validity" of the data be stored along with
the data. By way of example only, in digital television
pictures that are represented by digital values, as specified
in the international standard CCIR 601, certain specific
values are not allowed. In this system, eight-bit binary
numbers are used to represent samples of the picture and the
values zero and 255 may not be used.
If such a picture were to be processed in a pipeline built
in the practice of the present invention, then one of these
values (zero, for example) could be used to indicate that the
data in a specific stage in the pipeline is not valid.
Accordingly, any non-zero data would be deemed to be valid.
In this example, there is no specific latch that can be
identified and said to be storing the "validness" of the
associated data. Nonetheless, the validity of the data is
stored along with the data.
As shown in Fig. 1, the state of the VALID signal into
each stage is indicated as an "H" or an "L" on an upper,
right-pointed arrow. Therefore, the VALID signal from Stage
A into Stage B is LOW, and the VALID signal from Stage D into
Stage E is HIGH. The state of the ACCEPT signal into each
stage is indicated as an ~H~ or an ~L~ on a lower, left-
- 2145159
.. .
29
pointing arrow. Hence, the ACCEPT signal from Stage E into
Stage D is HIGH, whereas the ACCEPT signal from the device
connected downstream of the pipeline into Stage F is LOW.
Data is transferred from one stage to another during a
cycle (explained below) whenever the ACCEPT signal of the
downstream stage into its upstream neighbor is HIGH. If the
ACCEPT signal is LOW between two stages, then data is not
transferred between these stages.
Referring again to Fig. 1, if a box is shaded, the
corresponding pipeline stage is assumed, by way of example,
to contain valid output data. Likewise, the VALID signal
which is passed from that stage to the following stage is
HIGH. Fig. 1 illustrates the pipeline when stages B, D, and
E contain valid data. Stages A, C, and F do not contain
valid data. At the beginning, the VALID signal into pipeline
stage A is HIGH, meaning that the data on the transmission
line into the pipeline is valid.
Also at this time, the ACCEPT signal into pipeline stage
F is LOW, so that no data, whether valid or not, is
transferred out of Stage F. Note that both valid and invalid
data is transferred between pipeline stages. Invalid data,
which is data not worth saving, may be written over, thereby,
eliminating it from the pipeline. However, valid data must
. not be written over since it is data that must be saved for
processing or use in a downstream device e.g., a pipeline
stage, a device or a system connected to the pipeline that
receives data from the pipeline.
In the pipeline illustrated in Fig. 1, Stage E contains
valid data D1, Stage D contains valid data D2, Stage B
contains valid data D3, and a device (not shown) connected to
the pipeline upstream contains data D4 that is to be
transferred into and processed in the pipeline. Stages B, D
and E, in addition to the upstream device, contain valid data
and, therefore, the VALID signal from these stages or devices
- 2145159
into their respective following devices is HIGH. The VALID
signal from the Stages A, C and F is, however, LOW since
these stages do not contain valid data.
Assume now that the device connected downstream from the
pipeline is not ready to accept data from the pipeline. The
device signals this by setting the corresponding ACCEPT
signal LOW into Stage F. Stage F itself, however, does not
contain valid data and is, therefore, able to accept data
from the preceding Stage E. Hence, the ACCEPT signal from
Stage F into Stage E is set HIGH.
Similarly, Stage E contains valid data and Stage F is
ready to accept this data. Hence, Stage E can accept new
data as long as the valid data D1 is first transferred to
Stage F. In other words, although Stage F cannot transfer
data downstream, all the other stages can do so without any
valid data being overwritten or lost. At the end of Cycle 1,
data can, therefore, be "shifted" one step to the right.
This condition is shown in Cycle 2.
In the illustrated example, the downstream device is still
not ready to accept new data in Cycle 2 and, therefore, the
ACCEPT signal into Stage F is still LOW. Stage F cannot,
therefore, accept new data since doing so would cause valid
data Dl to be overwritten and lost. The ACCEPT signal from
Stage F into Stage E, therefore, goes LOW, as does the ACCEPT
signal from Stage E into Stage D since Stage E also contains
valid data D2. All of the Stages A-D, however, are able to
accept new data (either because they do not contain valid
data or because they are able to shift their valid data
downstream and accept new data) and they signal this
condition to their immediately preceding neighbors by setting
their corresponding ACCEPT signals HIGH.
The state of the pipelines after Cycle 2 is illustrated in
Fig. 1 for the row labelled Cycle 3. By way of example, it
is assumed that the downstream device is still not ready to
2145159
, --
31
accept new data from Stage F (the ACCEPT signal into Stage F
is LOW). Stages E and F, therefore, are still "blocked", but
in Cycle 3, Stage D has received the valid data D3, which has
overwritten the invalid data that was previously in this
stage. Since Stage D cannot pass on data D3 in Cycle 3, it
cannot accept new data and, therefore, sets the ACCEPT signal
into Stage C LOW. However, stages A-C are ready to accept
new data and signal this by setting their corresponding
ACCEPT signals HIGH. Note that data D4 has been shifted from
Stage A to Stage B.
Assume now that the downstream device becomes ready to
accept new data in Cycle 4. It signals this to the pipeline
by setting the ACCEPT signal into Stage F HIGH. Although
Stages C-F contain valid data, they can now shift the data
downstream and are, thus, able to accept new data. Since
each stage is therefore able to shift data one step
downstream, they set their respective ACCEPT signals out
HIGH.
As long as the ACCEPT signal into the final pipeline stage
(in this example, Stage F) is HIGH, the pipeline shown in
Fig. 1 acts as a rigid pipeline and simply shifts data one
step downstream on each cycle. Accordingly, in Cycle 5, data
D1, which was contained in Stage F in Cycle 4, is shifted out
of the pipeline to the subsequent device, and all other data
is shifted one step downstream.
Assume now, that the ACCEPT signal into Stage F goes LOW
in Cycle 5. Once again, this means that Stages D-F are not
able to accept new data, and the ACCEPT signals out of these
stages into their immediately preceding neighbors go LOW.
Hence, the data D2, D3 and D4 cannot shift downstream,
however, the data D5 can. The corresponding state of the
pipeline after Cycle 5 is, thus, shown in Fig. 1 as Cycle 6.
The ability of the pipeline, in accordance with the
preferred embodiments of the present invention, to "fill up"
2145159
32
empty processing stages is highly advantageous since the
processing stages in the pipeline thereby become decouple
from one another. In other words, even though a pipeline
stage may not be ready to accept data, the entire pipeline
S does not have to stop and wait for the delayed stage.
Rather, when one stage is unable to accept valid data it
simply forms a temporary "wall" in the pipeline.
Nonetheless, stages downstream of the "wall" can continue to
advance valid data even to circuitry connected to the
pipeline, and stages to the left of the "wall" can still
accept and transfer valid data downstream. Even when several
pipeline stages temporarily cannot accept new data, other
stages can continue to operate normally. In particular, the
pipeline can continue to accept data into its initial stage
A as long as stage A does not already contain valid data that
cannot be advanced due to the next stage not being ready to
accept new data. As this example illustrates, data can be
transferred into the pipeline and between stages even when
one or more processing stages is blocked.
In the embodiment shown in Fig. 1, it is assumed that the
various pipeline stages do not store the ACCEPT signals they
receive from their immediately following neighbors. Instead,
whenever the ACCEPT signal into a downstream stage goes LOW,
this LOW signal is propagated upstream as far as the nearest
pipeline stage that does not contain valid data. For
example, referring to Fig. 1, it was assumed that the ACCEPT
signal into Stage F goes LOW in Cycle 1. In Cycle 2, the LOW
signal propagates from Stage F back to Stage D.
In Cycle 3, when the data D3 is latched into Stage D, the
ACCEPT signal propagates upstream four stages to Stage C.
When the ACCEPT signal into Stage F goes HIGH in Cycle 4, it
must propagate upstream all the way to Stage C. In other
words, the change in the ACCEPT signal must propagate back
four stages. It is not necessary, however, in the embodiment
2145159
33
illustrated in Fig. 1, for the ACCEPT signal to propagate all
the way back to the beginning of the pipeline if there is
some intermediate stage that is able to accept new data.
In the embodiment illustrated in Fig. 1, each pipeline
stage will still need separate input and output data latches
to allow data to be transferred between stages without
unintended overwriting. Also, although the pipeline
illustrated in Fig. 1 is able to "compress" when downstream
pipeline stages are blocked, i.e., they cannot pass on the
data they contain, the pipeline does not "expand" to provide
stages that contain no valid data between stages that do
contain valid data. Rather, the ability to compress depends
on there being cycles during which no valid data is presented
to the first pipeline stage.
In Cycle 4, for example, if the ACCEPT signal into Stage
F remained LOW and valid data filled pipeline stages A and B,
as long as valid data continued to be presented to Stage A
the pipeline would not be able to compress any further and
valid input data could be lost. Nonetheless, the pipeline
illustrated in Fig. 1 reduces the risk of data loss since it
is able to compress as long as there is a pipeline stage that
does not contain valid data.
Fig. 2 illustrates another embodiment of the pipeline that
can both compress and expand in a logical manner and which
includes circuitry that limits propagation of the ACCEPT
signal to the nearest preceding stage. Although the
circuitry for implementing this embodiment is explained and
illustrated in greater detail below, Fig. 2 serves to
illustrate the principle by which it operates.
For ease of comparison only, the input data and ACCEPT
signals into the pipeline embodiment shown in Fig. 2 are the
same as in the pipeline embodiment shown in Fig. 1.
Accordingly, stages E, D and B contain valid data D1, D2 and
D3, respectively. The ACCEPT signal into Stage F is LOW; and
214~159
34
data D4 is presented to the beginning pipeline Stage A. In
Fig. 2, three lines are shown connecting each neighboring
pair of pipeline stages. The uppermost line, which may be a
bus, is a data line. The middle line is the line over which
the VALID signal is transferred, while the bottom line is the
line over which the ACCEPT signal is transferred. Also, as
before, the ACCEPT signal into Stage F remains LOW except in
Cycle 4. Furthermore, additional data D5 is presented to the
pipeline in Cycle 4.
In Fig. 2, each pipeline stage is represented as a block
divided into two halves to illustrate that each stage in this
embodiment of the pipeline includes primary and secondary
data storage elements. In Fig. 2, the primary data storage
is shown as the right half of each stage. However, it will
be appreciated that this delineation is for the purpose of
illustration only and is not intended as a limitation.
As Fig. 2 illustrates, as long as the ACCEPT signal into
a stage is HIGH, data is transferred from the primary storage
elements of the stage to the secondary storage elements of
the following stage during any given cycle. Accordingly,
although the ACCEPT signal into Stage F is LOW, the ACCEPT
signal into all other stages is HIGH so that the data Dl, D2
and D3 is shifted forward one stage in Cycle 2 and the data
D4 is shifted into the first Stage A.
Up to this point, the pipeline embodiment shown in Fig. 2
acts in a manner similar to the pipeline embodiment shown in
Fig. 1. The ACCEPT signal from Stage F into Stage E,
however, is HIGH even though the ACCEPT signal into Stage F
is LOW. As is explained below, because of the secondary
storage elements, it is not necessary for the LOW ACCEPT
S lgna 1 tO propagate upstream beyond Stage F. Moreover, by
leaving the ACCEPT signal into Stage E HIGH, Stage F signals
that it is ready to accept new data. Since Stage F is not
able to transfer the data Dl in its primary storage elements
2145159
-
downstream (the ACCEPT signal into Stage F is LOW) in Cycle
3, Stage E must, therefore, transfer the data D2 into the
secondary storage elements of Stage F. Since both the
primary and the secondary storage elements of Stage F now
contain valid data that cannot be passed on, the ACCEPT
signal from Stage F into Stage E is set LOW. Accordingly,
this represents a propagation of the LOW ACCEPT signal back
only one stage relative to Cycle Z, whereas this ACCEPT
signal had to be propagated back all the way to Stage C in
the embodiment shown in Fig. 1.
Since Stages A-E are able to pass on their data, the
ACCEPT signals from the stages into their immediately
preceding neighbors are set HIGH. Consequently, the data D3
and D4 are shifted one stage to the right so that, in Cycle
4, they are loaded into the primary data storage elements of
Stage E and Stage C, respectively. Although Stage E now
contains valid data D3 in its primary storage elements, its
secondary storage elements can still be used to store other
data without risk of overwriting any valid data.
Assume now, as before, that the ACCEPT signal into Stage
F becomes HIGH in Cycle 4. This indicates that the
downstream device to which the pipeline passes data is ready
to accept data from the pipeline. Stage F, however, has set
its ACCEPT signal LOW and, thus, indicates to Stage E that
Stage F is not prepared to accept new data. Observe that the
ACCEPT signals for each cycle indicate what will "happen" in
the next cycle, that is, whether data will be passed on
(ACCEPT HIGH) or whether data must remain in place (ACCEPT
LOW). Therefore, from Cycle 4 to Cycle 5, the data D1 is
passed from Stage F to the following device, the data D2 is
shifted from secondary to primary storage in Stage F, but the
data D3 in Stage E is not transferred to Stage F. The data
D4 and D5 can be transferred into the following pipeline
stages as normal since the following stages have their ACCEPT
2145159
.
36
signals HIGH.
Comparing the state of the pipeline in Cycle 4 and Cycle
5, it can be seen that the provision of secondary storage
elements, enables the pipeline embodiment shown in Fig. 2 to
expand, that is, to free up data storage elements into which
valid data can be advanced. For example, in Cycle 4, the
data blocks Dl, D2 and D3 form a "solid wall" since their
data cannot be transferred until the ACCEPT signal into Stage
F goes HIGH. Once this signal does become HIGH, however,
data D1 is shifted out of the pipeline, data D2 is shifted
into the primary storage elements of Stage F, and the
secondary storage elements of Stage F become free to accept
new data if the following device is not able to receive the
data D2 and the pipeline must once again "compress." This is
shown in Cycle 6, for which the data D3 has been shifted into
the secondary storage elements of Stage F and the data D4 has
been passed on from Stage D to Stage E as normal.
Figs. 3a(1), 3a(2), 3b(1) and 3b(2) (which are referred to
collectively as Fig. 3) illustrate generally a preferred
embodiment of the pipeline. This preferred embodiment
implements the structure shown in Fig. 2 using a two-phase,
non-overlapping clock with phases 00 and 01. Although a two-
phase clock is preferred, it will be appreciated that it is
also possible to drive the various embodiments of the
invention using a clock with more than two phases.
As shown in Fig. 3, each pipeline stage is represented as
having two separate boxes which illustrate the primary and
secondary storage elements. Also, although the VALID signal
and the data lines connect the various pipeline stages as
before, for ease of illustration, only the ACCEPT signal is
shown in Fig. 3. A change of state during a clock phase of
certain of the ACCEPT signals is indicated in Fig. 3 using an
upward-pointing arrow for changes from LOW to HIGH.
Similarly, a downward-pointing arrow for changes from HIGH to
- 2145159
-
37
LOW. Transfer of data from one storage element to another is
indicated by a large open arrow. It is assumed that the
~JALID signal out of the primary or secondary storage elements
of any given stage is HIGH whenever the storage elements
contain valid data.
In Fig. 3, each cycle is shown as consisting of a full
period of the non-overlapping clock phases ~0 and ol. As is
explained in greater detail below, data is transferred from
the secondary storage elements (shown as the left box in each
stage) to the primary storage elements (shown as the right
box in each stage) during clock cycle ol, whereas data is
transferred from the primary storage elements of one stage to
the secondary storage elements of the following stage during
the clock cycle o0. Fig. 3 also illustrates that the primary
and secondary storage elements in each stage are further
connected via an internal acceptance line to pass an ACCEPT
signal in the same manner that the ACCEPT signal is passed
from stage to stage. In this way, the secondary storage
element will know when it can pass its date to the primary
storage element.
Fig. 3 shows the ~1 phase of Cycle 1, in which data D1, D2
and D3, which were previously shifted into the secondary
storage elements of Stages E, D and B, respectively, are
shifted into the primary storage elements of the respective
2~ stage. During the ~1 phase of Cycle 1, the pipeline,
therefore, assumes the same configuration as is shown as
Cycle 1 of Fig. 2. As before, the ACCEPT signal into Stage
F is assumed to be LOW. As Fig. 3 illustrates, however, this
means that the ACCEPT signal into the primary storage element
'0 of Stage F is LOW, but since this storage element does not
contain valid data, it sets the ACCEPT signal into its
secondary storage element HIGH.
The ACCEPT signal from the secondary storage elements of
Stage F into the primary storage elements of Stage E is also
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~,
38
set HIGH since the secondary storage elements of Stage F do
not contain valid data. As before, since the primary storage
elements of Stage F are able to accept data, data in all the
upstream primary and secondary storage elements can be
shifted downstream without any valid data being overwritten.
The shift of data from one stage to the next takes place
during the next ~0 phase in Cycle 2. For example, the valid
data D1 contained in the primary storage element of Stage E
is shifted into the secondary storage element of Stage F, the
data D4 is shifted into the pipeline, that is, into the
secondary storage element of Stage A, and so forth.
The primary storage element of Stage F still does not
contain valid data during the 00 phase in Cycle 2 and,
therefore, the ACCEPT signal from the primary storage
elements into the secondary storage elements of Stage F
remains HIGH. During the 01 phase in Cycle 2, data can
therefore be shifted yet another step to the right, i.e.,
from the secondary to the primary storage elements within
each stage.
However, once valid data is loaded into the primary
storage elements of Stage F, if the ACCEPT into Stage F from
the downstream device is still LOW, it is not possible to
shift data out of the secondary storage element of Stage F
without overwriting and destroying the valid data D1. The
ACCEPT signal from the primary storage elements into the
secondary storage elements of Stage F therefore goes LOW.
Data D2, however, can still be shifted into the secondary
storage of Stage F since it did not contain valid data and
its ACCEPT signal out was HIGH.
During the 01 phase of Cycle 3, it is not possible to
shift data D2 into the primary storage elements of Stage F,
although data can be shifted within all the previous stages.
Once valid data is loaded into the secondary storage elemen~s
of Stage F, however, Stage F is not able to pass on this
2145159
39
data. It signals this event setting its ACCEPT signal out
LOW.
Assuming that the ACCEPT signal into Stage F remains LOW,
data upstream of Stage F can continue to be shifted between
stages and within stages on the respective clock phases until
the next valid data block D3 reaches the primary storage
elements of Stage E. As illustrated, this condition is
reached during the al phase of Cycle 4.
During the o0 phase of Cycle 5, data D3 has been loaded
into the primary storage element of Stage E. Since this data
cannot be shifted further, the ACCEPT signal out of the
primary storage elements of Stage E is set LOW. Upstream
data can be shifted as normal.
Assume now, as in Cycle 5 of Fig. 2, that the device
connected downstream of the pipeline is able to accept
pipeline data. It signals this event by setting the ACCEPT
signal into pipeline Stage F HIGH during the 01 phase of
- Cycle 4. The primary storage elements of Stage F can now
shift data to the right and they are also able to accept new
data. Hence, the data D1 was shifted out during the ~1 phase
of Cycle 5 so that the primary storage elements of Stage F no
longer contain data that must be saved. During the 01 phase
of Cycle 5, the data D2 is, therefore, shifted within Stage
F from the secondary storage elements to the primary storage
elements. The secondary storage elements of Stage F are also
able to accept new data and signal this by setting the ACCEPT
signal into the primary storage elements of Stage E HIGH.
During transfer of data within a stage, that is, from its
secondary to its primary storage elements, both sets of
storage elements will contain the same data, but the data in
the secondary storage elements can be overwritten with no
data loss since this data will also be held in the primary
storage elements. The same holds true for data transfer from
the primary storage elements of one stage into the secondary
2145159
storage elements of a subsequent stage.
Assume now, that the ACCEPT signal lnto the primary
storage elements of Stage F goes LOW during the ~1 phase in
Cycle 5. This means that Stage F is not able to transfer the
data D2 out of the pipeline. Stage F, consequently, sets the
ACCEPT signal from its primary to its secondary storage
elements LOW to prevent overwriting of the valid data D2.
The data D2 stored in the secondary storage elements of Stage
F, however, can be overwritten without loss, and the data D3,
is therefore, transferred into the secondary storage elements
of Stage F during the ~O phase of Cycle 6. Data D4 and D5
can be shifted downstream as normal. Once valid data D3 is
stored in Stage F along with data D2, as long as the ACCEPT
signal into the primary storage elements of Stage F is LOW,
neither of the secondary storage elements can accept new
data, and it signals this by setting the ACCEPT signal into
Stage E LOW.
When the ACCEPT signal into the pipeline from the
downstream device changes from LOW to HIGH or vice versa,
this change does not have to propagate upstream within the
pipeline further than to the immediately preceding storage
elements (within the same stage or within the preceding
pipeline stage). Rather, this change propagates upstream
within the pipeline one storage element block per clock
phase.
As this example illustrates, the concept of a "stage" in
the pipeline structure illustrated in Fig. 3 is to some
extent a matter of perception. Since data is transferred
within a stage (from the secondary to the primary storage
~0 elements) as it is between stages (from the primary storage
elements of the upstream stage into the secondary storage
elements of the neighboring downstream stage), one could just
as well consider a stage to consist of "primary" storage
elements followed by "secondary storage elements~' instead of
~1~5159
41
as illustrated in Fig. 3. The concept of "primary" and
~'secondary" storage elements ls, therefore, mostly a question
of labeling. In Fig. 3, the "primary" storage elements can
also be referred to as "output" storage elements, since they
are the elements from which data is transferred out of a
stage into a following stage or device, and the "secondary"
storage elements could be "input" storage elements for the
same stage.
In explaining the aforementioned embodiments, as shown in
Figs. 1-3, only the transfer of data under the control of the
ACCEPT and VALID signals has been mentioned. It is to be
further understood that each pipeline stage may also process
the data it has received arbitrarily before passing it
between its internal storage elements or before passing it to
the following pipeline stage. Therefore, referring once
again to Fig. 3, a pipeline stage can, therefore, be defined
as the portion of the pipeline that contains input and output
storage elements and that arbitrarily processes data stored
in its storage elements.
Furthermore, the "device" downstream from the pipeline
Stage F, need not be some other type of hardware structure,
but rather it can be another section of the same or part of
another pipeline. As illustrated below, a pipeline stage can
set its ACCEPT signal LOW not only when all of the downstream
2~ storage elements are filled with valid data, but also when a
stage requires more than one clock phase to finish processing
its data. This also can occur when it creates valid data in
one or both of its storage elements. In other words, it is
not necessary for a stage simply to pass on the ACCEPT signal
based on whether or not the immediately downstream storage
elements contains valid data that cannot be passed on.
Rather, the ACCEPT signal itself may also be altered within
the stage or, by circuitry external to the stage, in order to
control the passage of data between adjacent storage
21~5159
`
42
elements. The VALID signal may also be processed in an
analogous manner.
A great advantage of the two-wire interface (one wire for
each of the VALID and ACCEPT signals) is its ability to
control the pipeline without the control signals needing to
propagate back up the pipeline all the way to its beginning
stage. Referring once again to Fig. 1, Cycle 3, for example,
although stage F "tells" stage E that it cannot accept data,
and stage E tells stage D, and stage D tells stage C.
Indeed, if there had been more stages containing valid data,
then this signal would have propagated back even further
along the pipeline. In the embodiment shown in Fig. 3, Cycle
3, the LOW ACCEPT signal is not propagated any further
upstream than to Stage E and, then, only to its primary
storage elements.
As described below, this embodiment is able to achieve
this flexibility without adding significantly to the silicon
area that is required to implement the design. Typically,
each latch in the pipeline used for data storage requires
only a single extra transistor (which lays out very
efficiently in silicon). In addition, two extra latches and
a small number of gates are preferably added to process the
ACCEPT and VALID signals that are associated with the data
. latches in each half-stage.
25Fig. 4 illustrates a hardware structure that implements a
stage as shown in Fig. 3.
By way of example only, it is assumed that eight-bit data
is to be transferred (with or without further manipulation in
optional combinatorial logic circuits) in parallel through
~0 the pipeline. However, it will be appreciated that either
~ore or less than eight-bit data can be used in practicin~
the invention. Furthermore, the two-wire interface in
accordance with this embodiment is, however, suitable for use
with any data bus width, and the data bus width may even
2145159
43
change from one stage to the next if a particular application
so requires. The interface in accordance with this
embodiment can also be used to process analog signals.
As discussed previously, while other conventional timing
arrangements may be used, the interface is preferably
controlled by a two-phase, non-overlapping clock. In Figs.
4-9, these clock phase signals are referred to as PHO and
PHl. In Fig. 4, a line is shown for each clock phase signal.
Input data enters a pipeline stage over a multi-bit data
bus IN_DATA and is transferred to a following pipeline stage
or to subsequent receiving circuitry over an output data bus
OUT DATA. The input data is first loaded in a manner
described below into a series of input latches (one for each
input data signal) collectively referred to as LDIN, which
constitute the secondary storage elements described above.
In the illustrated example of this embodiment, it is
assumed that the Q outputs of all latches follow their D
inputs, that is, they are "loaded", when the clock input is
HIGH, i.e., at a logic "1" level. Additionally, the Q
outputs hold their last values. In other words, the Q
outputs are "latched" on the falling edge of their respective
clock signals. Each latch has for its clock either one of
two non-overlapping clock signals PH0 or PH1 (as shown in
Fig. 5), or the logical AND combination of one of these clock
signals PHO, PH1 and one logic signal. The invention works
equally well, however, by providing latches that latch on the
rising edges of the clock signals, or any other known
latching arrangement, as long as conventional methods are
applied to ensure proper timing of the latching operations.
30The output data from the input data latch LDIN passes via
an arbitrary and optional combinatorial logic circuit Bl,
~,hich may be provided to convert output data from input latch
LDIN into intermediate data, which is then later loaded in a~
output data latch LDOUT, which comprises the primary storaae
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44
elements descrlbed above. The output from the output data
latch LDOUT may similarly pass through an arbitrary and
optional combinatorial logic circuit B2 before being passed
onward as OUT_DATA to the next device downstream. This may
be another pipeline stage or any other device connected to
the pipeline.
In the practice of the present invention, each stage of
the pipeline also includes a validation input latch LVIN, a
validation output latch LVOUT, an acceptance input latch
LAIN, and an acceptance output latch LAOUT. Each of these
four latches is, preferably, a simple, single-stage latch.
The outputs from latches LVIN, LVOUT, LAIN and LAOUT are,
respectively, QVIN, QVOUT, QAIN, QAOUT. The output signal
QVIN from the validation input latch is connected either
directly as an input to the validation output latch LVOUT, or
via intermediate logic devices or circuits that may alter the
signal.
Similarly, the output validation signal QVOUT of a given
stage may be connected either directly to the input of the
validation input latch QVIN of the following stage, or via
intermediate devices or logic circuits, which may alter the
validation signal. This output QVIN is also connected to a
logic gate (to be described below), whose output is connected
to the input of the acceptance input latch LAIN. The output
QAOUT from the acceptance output latch LAOUT is connected to
a similar logic gate (described below), optionally via
another logic gate.
As shown in Fig. 4, the output validation signal QVOUT
forms an OUT_VALID signa that can be received by subsequent
stages as an IN_VALID signal, or simply to indicate valid
data to subsequent circuity connected to the pipeline. The
readiness of the following circuit or stage to accept data is
indicated to each stage as the signal OUT_ACCEPT, which is
connected as the input to the acceptance output latch LAOUT,
211S159
preferably via logic circuitry, which is described below.
Similarly, the output QAOUT of the acceptance output latch
LAOUT is connected as the input to the acceptance input latch
LAIN, preferably via logic circuitry, which is described
below.
In practicing the present invention, the output signals
QVIN, QVOUT from the validation latches LVI~, LVOUT are
combined with the acceptance signals QAOUT, OUT_ACCEPT,
respectively, to form the inputs to the acceptance latches
LAIN, LAOUT, respectively. In the embodiment illustrated in
Fig. 4, these input signals are formed as the logical NAND
combination of the respective validation signals QVIN, QVOUT,
with the logical inverse of the respective acceptance output
signals QAOUT, OUT ACCEPT. Conventional logic gates, NAND1
and NAND2, perform the NAND operation, and the inverters
INV1, INV2 form the logical inverses of the respective
acceptance signals.
As is well known in the art of digital design, the output
from a NAND gate is a logical "l" when any or all of its
input signals are in the logical "0" state. The output from
a NAND gate is, therefore, a logical "0" only when all of its
inputs are in the logical "1" state. Also well known in the
art, is that the output of a digital inverter such as INVl is
a logical "1" when its input signal is a "0" and is a "0"
when its input signal is a "1"
The inputs to the NAND gate NAND1 are, therefore, QVIN and
NOT (QAOUT), where "NOT" indicates binary inversion. Using
known techniques, the input to the acceptance latch LAIN can
be resolved as follows:
~o NAND(QVIN,NOT(QAOUT)) = NOT(QVIN) OR QAOUT
In other words, the combination of the inverter INVl and
the NAND gate NAND1 is a logical "1" either when the signal
QVIN is a "0" or the signal QAOUT is a "1", or both. The
gate NAND1 and the inverter INV1 can, therefore, be
2145159
46
implemented by a single OR gate that has one of its inputs
tied directly to the QAOUT output of the acceptance latch
LAOUT and its other input tied to the inverse of the output
signal QVIN of the validation input latch LVIN.
As is well known in the art of digital design, many
latches suitable for use as the validation and acceptance
latches may have two outputs, Q and NOT(Q), that is, Q and
its logical inverse. If such latches are chosen, the one
input to the OR gate can, therefore, be tied directly to the
NOT(Q) output of the validation latch LVIN. The gate NAND1
and the inverter INVl can be implemented using well known
conventional techniques. Depending on the latch architecture
used, however, it may be more efficient to use a latch
without an inverting output, and to provide instead the gate
NAND1 and the inverter INV1, both of which also can be
implemented efficiently in a silicon device. Accordingly,
any known arrangement may be used to generate the Q signal
and/or its logical inverse.
The data and validation latches LDIN, LDOUT, LVIN and
LVOUT, load their respective data inputs when both clock
signals (PH0 at the input side and PH1 at the output side)
and the output from the acceptance latch of the same side are
logical "1". Thus, the clock signal (PH0 for the input
latches LDIN and LVIN) and the output of the respective
acceptance latch (in this case, LAIN) are used in a logical
AND manner and data is loaded only when they are both logical
" 1 " .
In particular appllcations, such as CMOS implementations
of the latches, the logical AND operation that controls the
loading (via the illustrated CK or enabling "input") of the
latches can be implemented easily in a conventional manner by
connecting the respective enabling input signals (for
example, PH0 and QAIN for the latches LVIN and LDIN), to the
gates of MOS transistors connected in series in the input
2145159
47
lines of the latches. Consequently, is necessary to provide
an actual logic AND gate, which might cause problems of
timing due to propagation delay in high-speed applications.
The AND gate shown in the figures, therefore, only indicates
S the logical function to be performed in generating the enable
signals of the various latches.
Thus, the data latch LDIN loads input data only when PHO
and QAIN are both "1". It will latch this data when either
of these two signals goes to a "O".
lo Although only one of the clock phase signals PHO or PH1,
is used to clock the data and validation latches at the input
(and output) side of the pipeline stage, the other clock
phase signal is used, directly, to clock the acceptance latch
at the same side. In other words, the acceptance latch on
either side (input or output) of a pipeline stage is
preferably clocked "out of phase" with the data and
validation latches on the same side. For example, PH1 is
used to clock the acceptance input latch, although PHO is
used in generating the clock signal CK for the data latch
LDIN and the validation latch LVIN.
As an example of the operation of a pipeline augmented by
the two-wire validation and acceptance circuitry assume that
no valid data is initially presented at the input to the
circuit, either from a preceding pipeline stage, or from a
transmission device. In other words, assume that the
validation input signal IN_VALID to the illustrated stage has
not gone to a "1" since the system was most recently reset.
Assume further that several clock cycles have taken place
since the system was last reset and, accordingly, the
circuitry has reached a steady-state condition. The
validation input signal QVIN from the validation latch LVIN
is, therefore, loaded as a "O" during the next positive
period of the clock PHO. The input to the acceptance input
latch LAIN (via the gate NAND1 or another equivalent gatej,
21~5159
48
is, therefore, loaded as a "1" during the next positive
period of the clock signal PH1. In other words, since the
data in the data input latch LDIN is not valid, the stage
signals that it is ready to accept input data (since it does
not hold any data worth saving).
In this example, note that the signal IN_ACCEPT is used to
enable the data and validation latches LDIN and LVIN. Since
the signal IN ACCEPT at this time is a "1", these latches
effectively work as conventional transparent latches so that
whatever data is on the IN_DATA bus simply is loaded into the
data latch LDIN as soon as the clock signal PH0 goes to a
"l". Of course, this invalid data will also be loaded into
the next data latch LDOUT of the following pipeline stage as
long as the output QAOUT from its acceptance latch is a "1".
Hence, as long as a data latch does not contain valid
data, it accepts or "loads" any data presented to it during
the next positive period of its respective clock signal. On
the other hand, such invalid data is not loaded in any stage
for which the acceptance signal from its corresponding
acceptance latch is low (that is, a "0"). Furthermore, the
output signal from a validation latch (which forms the
validation input signal to the subsequent validation latch~
remains a "0" as long as the corresponding IN_VALID (or QVIN)
signal to the validation latch is low.
When the input data to a data latch is valid, the
validation signal IN_VALID indicates this by rising to a "l".
The output of the corresponding validation latch then rises
to a "l" on the next rising edge of its respective clock
phase signal. For example, the validation lnput signal QVI~J
of latch LVIN rises to a "1" when its corresponding IN_VAL_~
signal goes high (that is, rises to a "l") on the next rising
edge of the clock phase signal PH0.
Assume now, instead, that the data input latch LD~
contains valid data. If the data output latch LDOUT is ready
r 2145159
-
49
to accept new data, its acceptance signal QAOUT will be a
"1". In this case, during the next positive period of the
clock signal PH1, the data latch LDOUT and validation latch
LVOUT will be enabled, and the data latch LDOUT will load the
data present at its input. This will occur before the next
rising edge of the other clock signal PH0, since the clock
signals are non-overlapping. At the next rising edge of PH0,
the preceding data latch (LDIN) will, therefore, not latch in
new input data from the preceding stage until the data output
latch LDOUT has safely latched the data transferred from the
latch LDIN.
Accordingly, the same sequence is followed by every
adjacent pair of data latches (within a stage or between
adjacent stages) that are able to accept data, since they
will be operating based on alternate phases of the clock.
Any data latch that is not ready to accept new data because
it contains valid data that cannot yet be passed, will have
an output acceptance signal (the QA output from its
acceptance latch LA) that is LOW, and its data latch LDIN or
LDOUT wlll not be loaded. Hence, as long as the acceptance
signal (the output from the acceptance latch) of a given
stage or side (input or output) of a stage is LOW, its
corresponding data latch will not be loaded.
Fig. 4 also shows a reset feature included in a preferred
embodiment. In the illustrated example, a reset signal
NOTRESET0 is connected to an inverting reset input R
(inversion is hereby indicated by a small circle, as is
conventional) of the validation output latch LVOUT. As is
well known, this means that the validation latch LVOUT will
be forced to output a "0" whenever the reset signal NOTRESET0
becomes a "0". One advantage of resetting the latch when the
reset signal goes low (becomes a "0") is that a break in
transmission will reset the latches. They will then be in
their "null~ or reset state whenever a valid transmission
~1~5159
`_,
begins and the reset signal goes HIGH. The reset signal
NOTRESET0, therefore, operates as a digital "ON/OFF" switch,
such that it must be at a HIGH value in order to activate the
pipeline.
Note that it is not necessary to reset all of the latches
that hold valid data in the pipeline. As depicted in Fig. 4,
the validation input latch LVIN is not directly reset by the
reset signal NOTRESET0, but rather is reset indirectly.
Assume that the reset signal NOTRESET0 drops to a "0". The
validation output signal QVOUT also drops to a "0",
regardless of its previous state, whereupon the input to the
acceptance output latch LAOUT (via the gate NAND1) goes HIGH.
The acceptance output signal QAOUT also rises to a "1". This
QAOUT value of "1" is then transferred as a "1" to the input
of the acceptance input latch LAIN regardless of the state of
the validation input signal QVIN. The acceptance input
signal QAIN then rises to a "1" at the next rising edge of
the clock signal PH1. Assuming that the validation signal
IN VALID has been correctly reset to a "0", then upon the
subsequent rising edge of the clock signal PH0, the output
from the validation latch LVIN will become a "0", as it would
have done if it had been reset directly.
As this example illustrates, it is only necessary to reset
the validation latch in only one side of each stage
(including the final stage) in order to reset all validation
latches. In fact, in many applications, it will not be
necessary to reset every other validation latch: If the
reset signal NOTRESET0 can be guaranteed to be low during
more than one complete cycle of both phases PH0, PH1 of the
clock, then the "automatic reset" (a backwards propagation of
the reset signal) will occur for validation latches in
preceding pipeline stages. Indeed, if the reset signal is
held low for at least as many full cycles of both phases of
the clock as there are pipeline stages, it will only be
;
2145159
r
51
necessary to directly reset the validation output latch in
the final pipeline stage.
Figs. Sa and Sb (referred to collectively as Fig. 5)
illustrate a timing diagram showing the relationship between
S the non-overlapping clock signals PH0, PHl, the effect of the
reset signal, and the holding and transfer of data for the
different permutations of validation and acceptance signals
into and between the two illustrated sides of a pipeline
stage configured in the embodiment shown in Fig. 4. In the
example illustrated in the timing diagram of Fig. 5, it has
been assumed that the outputs from the data latches LDIN,
LDOUT are passed without further manipulation by intervening
logic blocks B1, B2. This is by way of example and not
necessarily by way of limitation. It is to be understood
that any combinatorial logic structures may be included
between the data latches of consecutive pipeline stages, or
between the input and output sides of a single pipeline
stage. The actual illustrated values for the input data (for
example the HEX data words "aa" or "04") are also merely
illustrative. As is mentioned above, the input data bus may
have any width (and may even be analog), as long as the data
latches or other storage devices are able to accommodate and
latch or store each bit or value of the input word.
Preferred Data Structure - "tokens"
In the sample application shown in Fig. 4, each stage
processes all input data, since there is no control circuitry
that excludes any stage from allowing input data to pass
through its combinatorial logic block B1, B2, and so forth.
To provide greater flexibility, the present invention
lncludes a data structure in which ~tokens~ are used to
distribute data and control information throughoUt the
system. Each token consists of a series of binary blts
separated into one or more blocks of token words.
,
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52
Furthermore, the bits fall into one of three types: address
bits (A), data bits (D), or an extension bit (E). Assume by
way of example and, not necessarily by way of limitation,
that data is transferred as words over an 8-bit bus with a 1-
- 5 bit extension bit line. An example of a four-word token is,
in order of transmission:
First word: E A A A D D D D D
Second word: E D D D D D D D D
Third word: E D D D D D D D D
Fourth word: E D D D D D D D D
Note that the extension bit E is used as an addition
(preferably) to each data word. In addition, the address
field can be of variable length and is preferably transmitted
just after the extension bit of the first word.
Tokens, therefore, consist of one or more words of
(binary) digital data in the present invention. Each of
these words is transferred in sequence and preferably in
parallel, although this method of transfer is not necessary:
serial data transfer is also possible using known techniques.
For example, in a video parser, control information is
transmitted in parallel, whereas data is transmitted
serially.
As the example illustrates, each token has, preferably at
the start, an address field (the string of A-bits) that
identifies the type of data that is contained in the token.
In most applications, a single word or portion of a word is
sufficient to transfer the entire address field, but this is
not necessary in accordance with the invention, so long as
logic circuitry is included in the corresponding pipeline
stages that is able to store some representation of partial
address fields long enough for the stages to receive and
decode the entire address field.
2145159
53
Note that no dedicated wires or registers are required to
transmit the address field. It is transmitted using the data
bits. As is explained below, a pipeline stage will not be
slowed down if it is not intended to be activated by the
particular address field, i.e., the stage will be able to
pass along the token without delay.
The remainder of the data in the token following the
address field is not constrained by the use of tokens. These
D-data bits may take on any values and the meaning attached
lo to these bits is of no importance here. That is, the meaning
of the data can vary, for example, depending upon where the
data is positioned within the system at a particular point in
time. The number of data bits D appended after the address
field can be as long or as short as required, and the number
of data words in different tokens may vary greatly. The
address field and extension bit are used to convey control
signals to the pipeline stages. Because the number of words
in the data field (the string of D bits) can be arbitrary, as
can be the information conveyed in the data field can also
vary accordingly. The explanation below is, therefore,
directed to the use of the address and extension bits.
In the present invention, tokens are a particularly useful
data structure when a number of blocks of circuitry are
connected together in a relatively simple configuration. The
2~ simplest configuration is a pipeline of processing steps.
For example, in the one shown in Fig. 1. The use of tokens,
however, is not restricted to use on a pipeline structure.
Assume once again that each box represents a complete
pipeline stage. In the pipeline of Fig. 1, data flows from
left to right in the diagram. Data enters the machine and
passes into processing Stage A. This may or may not modify
the data and it then passes the data to Stage B. The
modification, if any, may be arbitrarily complicated and, in
general, there will not be the same number of data i~ems
` 2145159
54
flowing into any stage as flow out. Stage B modifles the
data again and passes it onto Stage C, and so forth. In a
scheme such as this, it is impossible for data to flow in the
opposite direction, so that, for example, Stage C cannot pass
data to Stage A. This restriction is often perfectly
acceptable.
On the other hand, it is very desirable for Stage A to be
able to communicate information to Stage C even though there
is no direct connection between the two blocks. Stage A and
C communication is only via Stage B. One advantage of the
tokens is their ability to achieve this kind of
communication. Since any processing stage that does not
recognize a token simply passes it on unaltered to the next
block.
According to this example, an extension bit is transmitted
along with the address and data fields in each token so that
a processing stage can pass on a token (which can be of
arbitrary length) without having to decode its address at
all. According to this example, any token in which the
2~ extension bit is HIGH (a "1") is followed by a subsequent
word which is part of the same token. This word also has an
extension bit, which indicates whether there is a further
token word in the token. When a stage encounters a token
word whose extension bit is LOW (a "0"), it is known to be
the last word of the token. The next word is then assumed to
be the first word of a new token.
Note that although the simple pipeline of processing
stages is particularly useful, it will be appreciated that
tokens may be applied to more complicated configurations of
processing elements. An example of a more complicated
processing element is described below.
It is not necessary, in accordance with the present
invention, to use the state of the extension bit to signal
the last word of a given token by giving it an extension bit
214515~
-
set to "0". One alternative to the preferred scheme is to
move the extension bit so that it indicates the first word of
a token instead of the last. This can be accomplished with
appropriate changes in the decoding hardware.
The advantage of using the extension bit of the present
invention to signal the last word in a token rather than the
first, is that it is often useful to modify the behavior of
a block of circuitry depending upon whether or not a token
has extension bits. An example of this is a token that
activates a stage that processes video quantization values
stored in a quantization table (typically a memory device).
For example, a table containing 64 eight-bit arbitrary binary
integers.
In order to load a new quantization table into the
quantizer stage of the pipeline, a "QUANT_TABLE" token is
sent to the quantizer. In such a case the token, for
example, consists of 65 token words. The first word contains
the code "QUANT_TABLE", i.e., build a quantization table.
This is followed by 64 words, which are the integers of the
quantization table.
When encoding video data, it is occasionally necessary to
transmit such a quantization table. In order to accomplish
this function, a QUANT_TABLE token with no extension words
can be sent to the quantizer stage. On seeing this token,
and noting that the extension bit of its first word is LOW,
the quantizer stage can read out its quantization table and
construct a QUANT_TABLE token which includes the 64
quantization table values. The extension bit of the first
word (which was LOW) is changed so that it is HIGH and the
token continues, with HIGH extension bits, until the new end
of the token, indicated by a LOW extension bit on the sixty
fourth quantization table value. This proceeds in the
typical way through the system and is encoded into the bit
stream.
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Continuing with the example, the quantizer may either load
a new quantization table into its own memory device or read
out its table depending on whether the first word of the
QUANT_TABLE token has its extension bit set or not.
The choice of whether to use the extension bit to signal
the first or last token word in a token will, therefore,
depend on the system in which the pipeline will be used.
Both alternatives are possible in accordance with the
invention.
Another alternative to the preferred extension bit scheme
is to include a length count at the start of the token. Such
an arrangement may, for example, be efficient if a token is
very long. For example, assume that a typical token in a
given application is 1000 words long. Using the illustrated
extension bit scheme (with the bit attached to each token
word), the token would require 1000 additional bits to
contain all the extension bits. However, only ten bits would
be required to encode the token length in binary form.
Although there are, therefore, uses for lonq tokens,
experience has shown that there are many uses for short
tokens. Here the preferred extension bit scheme is
advantageous. If a token is only one word long, then only
one bit is required to signal this. However, a counting
scheme would typically require the same ten bits as before.
Disadvantages of a length count scheme include the
following: 1) it is inefficient for short tokens; 2) it
places a maximum length restriction on a token (with only ten
bits, no more than 1023 words can be counted); 3) the length
of a token must be known in advance of generating the count
(which is presumably at the start of the token); 4) every
block of circuitry that deals with tokens would need to be
provided with hardware to count words; and 5) if the count
should get corrupted (due to a data transmission error) it is
not clear whether recovery can be achieved.
21~S159
57
The advantages of the extension bit scheme in accordance
with the present invention include: 1) pipeline stages need
not include a block of circuitry that decodes every token
since unrecoqnized tokens can be passed on correctly by
considering only the extension bit; 2) the coding of the
extension bit is identical for all tokens; 3) there is no
limit placed on the length of a token; 4) the scheme is
efficient (in terms of overhead to represent the length of
the token) for short tokens; and 5) error recovery is
naturally achieved. If an extension bit is corrupted then
one random token will be generated (for an extension bit
corrupted from "1" to "0") or a token will be lost (extension
bit corrupted "0" to "1"). Furthermore, the problem is
localized to the tokens concerned. After that token, correct
operation is resumed automatically.
In addition, the length of the address field may be
varied. This is highly advantageous since it allows the most
common tokens to be squee`zed into the minimum number of
words. This, in turn, is of great importance in video data
pipeline systems since it ensures that all processing stages
can be continuously running at full bandwidth.
In accordance to the present invention, in order to allow
variable length address fields, the addresses are chosen so
. that a short address followed by random data can never be
2~ confused with a longer address. The preferred technique for
encoding the address field (which also serves as the "code"
for activating an intended pipeline stage) is the well-known
technique first described by Huffman, hence the common name
"Huffman Code". Nevertheless, it will be appreciated by one
of ordinary skill in the art, that other coding schemes may
also be successfully employed.
Although Huffman encoding is well understood in the field
of digital design, the following example provides a general
background:
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Huffman codes consist of words made up of a string of
symbols (in the context of digital systems, such as the
present invention, the symbols are usually binary digits).
The code words may have variable length and the special
property of Huffman code words is that a code word is chosen
so that none of the longer code words start with the symbols
that form a shorter code word. In accordance with the
invention, token address fields are preferably (although not
necessarily) chosen using known Huffman encoding techniques.
Also in the present invention, the address field
preferably starts in the most significant bit (MSB) of the
first word token. (Note that the designation of the MSB is
arbitrary and that this scheme can be modified to accommodate
various designations of the MSB.) The address field
continues through contiguous bits of lesser significance.
If, in a given application, a token address requires more
than one token word, the least significant bit in any given
word the address field will continue in the most significant
bit of the next word. The minimum length of the address
field is one bit.
Any of several known hardware structures can be used to
generate the tokens used in the present invention. One such
structure is a microprogrammed state machine. However, known
microprocessors or other devices may also be used.
The principle advantage of the token scheme in accordance
with the present invention, is its adaptability to
unanticipated needs. For example, if a new token is
introduced, it is most likely that this will affect only a
small number of pipeline stages. The most likely case is
~0 that only two stages or blocks of circuitry are affected,
i.e., the one block that generates the tokens in the firs.
place and the block or stage that has been newly designed o~
modified to deal with this new token. Note that it is n~.
necessary to modify any other pipeline stages. Rather, these
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will be able to deal with the new token without modification
to their designs because they will not recognize it and will,
accordingly, pass that token on unmodified.
This ability of the present invention to leave
substantially existing designed devices unaffected has clear
advantages. It may be possible to leave some semiconductor
chips in a chip set completely unaffected by a design
improvement in some other chips in the set. This is
advantageous both from the perspective of a customer and from
that of a chip manufacturer. Even if modifications mean that
all chips are affected by the design change (a situation that
becomes increasingly likely as levels of integration progress
so that the number of chips in a system drops) there will
still be the considerable advantage of better time-to-market
lS than can be achieved, since the same design can be reused.
In particular, note the situation that occurs when it
becomes necessary to extend the token set to include two word
addresses. Even in this case, it is still not necessary to
modify an existing design. Token decoders in the pipeline
stages will attempt to decode the first word of such a token
and will conclude that it does not recognize the token. It
will then pass on the token unmodified using the extension
bit to perform this operation correctly. It will not attempt
to decode the second word of the token (even though this
2~ contains address bits) because it will "assume" that the
second word is part of the data field of a token that it does
not recognize.
In many cases, a pipeline stage or a connected block of
circuitry will modify a token. This usually, but not
necessarily, takes the form of modifying the data field of a
token. In addition, it is common for the number of data
words in the token to be modified, either by removing certain
data words or by adding new ones. In some cases, tokens are
removed entirely from the token stream.
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In most applications, pipeline stages will typically only
decode (be activated by) a few tokens; the stage does not
recognize other tokens and passes them on unaltered. In a
large number of cases, only one token is decoded, the DATA
Token word itself.
In many applications, the operation of a particular stage
will depend upon the results of its own past operations. The
"state" of the stage, thus, depends on its previous states.
In other words, the stage depends upon stored state
information, which is another way of saying it must retain
some information about its own history one or more clock
cycles ago. The present invention is well-suited for use in
pipelines that include such "state machine" stages, as well
as for use in applications in which the latches in the data
path are simple pipeline latches.
The suitability of the two-wire interface, in accordance
with the present invention, for such "state machine" circuits
is a significant advantage of the invention. This is
especially true where a data path is being controlled by a
state machine. In this case, the two-wire interface
technique above-described may be used to ensure that the
"current state" of the machine stays in step with the data
which it is controlling in the pipeline.
Fig. 6 shows a simplified block diagram of one example of
circuitry included in a pipeline stage for decoding a token
address field. This illustrates a pipeline stage that has
the characteristics of a "state machine". Each word of a
token includes an "extension bit" which is HIGH if there are
more words in the token or LOW if this is the last word of
the token. If this is the last word of a token, the next
valid data word is the start of a new token and, therefore,
its address must be decoded. The decision as to whether or
not to decode the token address in any given word, thus,
depends upon knowing the value of the previous extension bit.
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61
For the sake of simplicity only, the two-wire interface
(with the acceptance and validation signals and latches) is
not illustrated and all details dealing with resetting the
circuit are omitted. As before, an 8-bit data word is
5 assumed by way of example only and not by way of limitation.
This exemplifying pipeline stage delays the data bits and
the extension bit by one pipeline stage. It also decodes the
DATA Token. At the point when the first word of the DATA
Token is presented at the output of the circuit, the signal
"DATA_ADDR" is created and set HIGH. The data bits are
delayed by the latches LDIN and LDOUT, each of which is
repeated eight times for the eight data bits used in this
example (corresponding to an 8-input, 8-output latch).
Similarly, the extension bit is delayed by extension bit
latches LEIN and LEOUT.
In this example, the latch LEPREV is provided to store the
most recent state of the extension bit. The value of the
extension bit is loaded into LEIN and is then loaded into
LEOUT on the next rising edge of the non-overlapping clock
phase signal PH1. Latch LEOUT, thus, contains the value of
the current extension bit, but only during the second half of
the non-overlapping, two-phase clock. Latch LEPREV, however,
loads this extension bit value on the next rising edge of the
clock signal PHO, that is, the same signal that enables the
extension bit input latch LEIN. The output QEPREV of the
latch LEPREV, thus, will hold the value of the extension bit
during the previous PHO clock phase.
The five bits of the data word output from the invertinq
Q output, plus the non-inverted MD[2~, of the latch LDIN are
combined with the previous extension bit value QEPREV in a
series of logic gates NAND1, NAND2, and NORl, whose
operations are well known in the art of digital design. The
designation "N MD[m~ indicates the logical inverse of bit m
of the mid-data word MD[7:0]. Using known techniques of
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62
Boolean algebra, it can be shown that the output signal SA
from this logic block (the output from NORl) is HIGH (a "1")
only when the previous extension bit is a "O" (QPREV="O") and
the data word at the output of the non-inverting Q latch (the
original input word) LDIN has the structure "000001xx", that
is, the five high-order bits MD[7]-MD[3] bits are all "0" and
the bit MD[2] is a "l" and the bits in the Zero-one positions
have any arbitrary value.
There are, thus, four possible data words (there are four
permutations of "xx") that will cause SA and, therefore, the
output of the address signal latch LADDR to whose input SA is
connected, to become HIGH. In other words, this stage
provides an activation signal (DATA_ADDR = "1") only when one
of the four possible proper tokens is presented and only when
the previous extension bit was a zero, that is, the previous
data word was the last word in the previous series of token
words, which means that the current token word is the first
one in the current token.
When the signal QPREV from latch LEPREV is LOW, the value
at the output of the latch LDIN is therefore the first word
of a new token. The gates NAND1, NAND2 and NOR1 decode the
DATA token (000001xx). This address decoding signal SA is,
however, delayed in latch LADDR so that the signal DATA_ADDR
` . has the same timing as the output data OUT_DATA and OUT_EXTN.
2~ Fig. 7 is another simple example of a state-dependent
pipeline stage in accordance with the present invention,
which generates the signal LAST_OUT_EXTN to indicate the
value of the previous output extension bit OUT_EXTN. One of
the two enabling signals (at the CK inputs) to the present
and last extension bit latches, LEOUT and LEPREV,
respectively, is derived from the gate AND1 such that these
latches only load a new value for them when the data is valid
and is being accepted (the Q outputs are HIGH from the
output validation and acceptance latches LVOUT and LAouT~
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63
respectively). In this way, they only hold valid extension
bits and are not loaded with spurious values associated with
data that is not valid. In the embodiment shown in Fig. 7,
the two-wire valid/accept logic includes the OR1 and OR2
gates with input signals consisting of the downstream
acceptance signals and the inverting output of the validation
latches LVIN and LVOUT, respectively. This illustrates one
way in which the gates NANDl/2 and INVlt2 in Fig. 4 can be
replaced if the latches have inverting outputs.
Although this is an extremely simple example of a "state-
dependent" pipeline stage, i.e., since it depends on the
state of only a single bit, it is generally true that all
latches holding state information will be updated only when
data is actually transferred between pipeline stages. In
other words, only when the data is both valid and being
accepted by the next stage. Accordingly, care must be taken
to ensure that such latches are properly reset.
The generation and use of tokens in accordance with the
present invention, thus, provides several advantages over
known encoding techniques for data transfer through a
p1peline.
First, the tokens, as described above, allow for variable
length address fields (and can utilize Huffman coding for
example) to provide efficient representation of common
2~ tokens.
Second, consistent encoding of the length of a token
allows the end of a token (and hence the start of the next
token) to be processed correctly (including simple non-
manipulative transfer), even if the token is not recognized
by the token decoder circuitry in a given pipeline stage.
Third, rules and hardware structures for the handling of
unrecognized tokens (that is, for passing them on unmodified)
allow communication between one stage and a downstream sta~e
that is not its nearest neighbor in the pipeline. This aiso
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64
increases the expandability and efficient adaptability of the
pipeline since it allows for future changes in the token set
without requiring large scale redesigning of existing
pipeline stages. The tokens of the present invention are
particularly useful when used in conjunction with the two-
wire interface that is described above and below.
As an example of the above, Figs. 8a and 8b, taken
together (and referred to collectively below as Fig. 8),
depict a block diagram of a pipeline stage whose function is
as follows. If the stage is processing a predetermined token
(known in this example as the DATA token), then it will
duplicate every word in this token with the exception of the
first one, which includes the address field of the DATA
token. If, on the other hand, the stage is processing any
other kind of token, it will delete every word. The overall
effect is that, at the output, only DATA Tokens appear and
each word within these tokens is repeated twice.
Many of the components of this illustrated system may be
the same as those described in the much simpler structures
shown in Figs. 4, 6, and 7. This illustrates a significant
advantage. More complicated pipeline stages will still enjoy
the same benefits of flexibility and elasticity, since the
sar,e two-wire interface may be used with little or no
adaptation.
2~ The data duplication stage shown in Fig. 8 is merely one
example of the endless number of different types of
operations that a pipeline stage could perform in any given
application. This "duplication stage" illustrates, however,
a stage that can form a "bottleneck", so that the pipeline
according to this embodiment will "pack together".
A "bottleneck" can be any stage that either takes a
relatively long time to perform its operations, or that
creates more data in the pipeline than it receives. This
example also illustrates that the two-wire accept/valid
214515 9
interface according to this embodiment can be adapted very
easily to different applications.
The duplication stage shown in Fig. 8 also has two latches
LEIN and LEOUT that, as in the example shown in Fig. 6, latch
the state of the extension bit at the input and at the output
of the stage, respectively. As Fig. 8a shows, the input
extension latch LEIN is clocked synchronously with the input
data latch LDIN and the validation si~nal IN_VALID.
For ease of reference, the various latches included in the
duplication stage are paired below with their respective
output signals:
In the duplication stage, the output from the data latch
LDIN forms intermediate data referred to as MID_DATA. This
intermediate data word is loaded into the data output latch
LDOUT only when an intermediate acceptance signal (labeled
"MID_ACCEPT" in Fig. 8a) is set HIGH.
The portion of the circuitry shown in Fig. 8 below the
acceptance latches LAIN, LAOUT, shows the circuits that are
added to the basic pipeline structure to generate the various
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66
internal control signals used to duplicate data. These
include a "DATA TOKEN" signal that indicates that the
circuitry is currently processing a valid DATA Token, and a
NOT_DUPLICATE signal which is used to control duplication of
data. When the circuitry is processing a DATA Token, the
NOT_DUPLICATE signal toggles between a HIGH and a LOW state
and this causes each word in the token to be duplicated once
(but no more times). When the circuitry is not processing a
valid DATA Token then the NOT_DUPLICATE signal is held in a
HIGH state. Accordingly, this means that the token words
that are being processed are not duplicated.
As Fig. 8a illustrates, the upper six bits of 8-bit
intermediate data word and the output signal QI1 from the
latch LIl form inputs to a group of logic gates NOR1, NOR2,
NAND18. The output signal from the gate NAND18 is labeled
Sl. Using well-known Boolean algebra, it can be shown that
the signal S1 is a "0" only when the output signal QI1 is a
"1" and the MID_DATA word has the following structure:
"000001xx", that is, the upper five bits are all "0", the bit
MID_DATA[2] is a "1" and the bits in the MID_DATA[1] and
MID_DATA[0] positions have any arbitrary value. Signal S1,
therefore, acts as a "token identification signal" which is
low only when the MID DATA signal has a predetermined
structure and the output from the latch LI1 is a "1". The
nature of the latch LI1 and its output QI1 is explained
further below.
Latch LO1 performs the function of latching the last value
of the intermediate extension bit (labeled "MID_EXTN" and as
signal S4), and it loads this value on the next rising edge
of the clock phase PHO into the latch LI1, whose output is
the bit QI1 and is one of the inputs to the token decoding
logic group that forms signal S1. Signal Sl, as is explained
above, may only drop to a "0" if the signal QI1 is a "1" (and
the MID_DATA signal has the predetermined structure). Signal
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67
S1 may, therefore, only drop to a "0" whenever the last
extension bit was "0", indicating that the previous token has
ended. Therefore, the MID_DATA word is the first data word
in a new token.
The latches LO2 and LI2 together with the NAND gates
NAND20 and NAND22 form storage for the signal, DATA_TOKEN.
In the normal situation, the signal QI1 at the input to
NAND20 and the signal S1 at the input to NAND22 will both be
at logic "1". It can be shown, again by the techniques of
Boolean algebra, that in this situation these NAND gates
operate in the same manner as inverters, that is, the signal
QI2 from the output of latch LI2 is inverted in NAND20 and
then this signal is inverted again by NAND22 to form the
signal S2. In this case, since there are two logical
inversions in this path, the signal S2 will have the same
value as QI2.
It can also be seen that the signal DATA_TOKEN at the
output of latch LO2 forms the input to latch LI2. As a
result, as long as the situation remains in which both QI1
and 51 are HIGH, the signal DATA_TOKEN will retain its state
(whether "0" or "1"). This is true even though the clock
signals PHO and PH1 are clocking the latches (LI2 and LO2
respectively). The value of DATA_TOKEN can only change when
. one or both of the signals QI1 and S1 are "0".
As explained earlier, the signal QI1 will be "0" when the
previous extension bit was "0". Thus, it will be "0"
whenever the MID_DATA value is the first word of a token
(and~ thus, includes the address field for the token). In
this situation, the signal Sl may be either "0" or "1". As
.0 explained earlier, signal Sl will be "0" if the MID_DATA word
has the predetermined structure that in this example
indicates a "DATA" Token. If the MID DATA word has any other
structure, (indicating that the token is some other token,
not a DATA Token), Sl will be "1".
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68
If QI1 is "0" and Sl is "1", this indicates there is some
token other than a DATA Token. As is well known in the field
of digital electronics, the output of NAND20 will be "1".
The NAND gate NAND22 will invert this (as previously
explained) and the signal S2 will thus be a "0". As a
result, this "0" value will be loaded into latch LO2 at the
start of the next PH1 clock phase and the DATA TOKEN signal
will become "0", indicating that the circuitry is not
processing a DATA token.
If QI1 is "0" and SO is "0", thereby indicating a DATA
token, then the signal S2 will be "1" (regardless of the
other input to NAND22 from the output of NAND20). As a
result, this "1" value will be loaded into latch LO2 at the
start of the next PH1 clock phase and the DATA_TOKEN signal
will become "1", indicating that the circuitry is processing
a DATA token.
The NOT_DUPLICATE signal (the output signal QO3) is
similarly loaded into the latch LI3 on the next rising edge
of the clock PHO. The output signal QI3 from the latch LI3
is combined with the output signal QI2 in a gate NAND24 to
form the signal S3. As before, Boolean algebra can be used
to show that the signal S3 is a "0" only when both of the
signals QI2 and QI3 have the value "1". If the signal QI2
becomes a "0", that is, the DATA TOKEN signal is a "0", then
the signal S3 becomes a "1". In other words, if there is not
a valid DATA TOKEN (QI2 = O) or the data word is not a
duplicate (QI3 = 0), then the signal S3 goes high.
Assume now, that the DATA TOKEN signal remains HIGH for
more than one clock signal. Since the NOT_DUPLICATE signal
(Q03) is "fed back" to the latch LI3 and will be inverted by
the gate NAND 24 (since its other input QI2 is held HIGH),
the output signal QO3 will toggle between "0" and "1". If
there is no valid DATA Token, however, the signal QI2 will ~e
a "0", and the signal S3 and the output QO3, will be forced
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69
HIGH until the DATE_TOKEN signal once again goes to a "1".
The output Q03 (the NOT_DUPLICATE signal) is also fed back
and is combined with the output QA1 from the acceptance latch
LAIN in a series of logic gates (NAND16 and INV16, which
s together form an AND gate) that have as their output a "1",
only when the signals QA1 and Q03 both have the value "1".
As Fig. 8a shows, the output from the AND gate (the gate
NAND16 followed by the gate INV16) also forms the acceptance
signal, IN_ACCEPT, which is used as described above in the
two-wire interface structure.
The acceptance signal IN ACCEPT is also used as an
enabling signal to the latches LDIN, LEI~, and LVIN. As a
result, if the NOT_DUPLICATE signal is low, the acceptance
signal IN_ACCEPT will also be low, and all three of these
1~ latches will be disabled and will hold the values stored at
their outputs. The stage will not accept new data until the
NOT_DUPLICATE signal becomes HIGH. This is in addition to
the requirements described above for forcing the output from
the acceptance latch LAIN high.
2G As long as there is a valid DATA_TOKEN (the DATA TOKEN
signal Q02 is a "1"), the signal Q03 will toggle between the
HI-GH and LOW states, so that the input latches will be
enabled and will be able to accept data, at most, during
every other complete cycle of both clock phases PH0, PHl.
The additional condition that the following stage be prepared
to accept data, as indicated by a "HIGH" OUT_ACCEPT signal,
must, of course, still be satisfied. The output latch LDOUT
will, therefore, place the same data word onto the output bus
OUT_DATA for at least two full clock cycles. The OUT_VALID
signal will be a "1" only when there is both a valid
DATA_TOKEN (Q02 HIGH) and the validation signal QVOUT is
HIGH.
The signal QEIN, which is the extension bit corresponding
to MID_DATA, is combined with the signal S3 in a series of
21~159
logic gates (INV10 and NAND10) to form a signal S4. During
presentation of a DATA Token, each data word MID_DATA will be
repeated by loading it into the output latch LDOUT twice.
During the first of these, S4 will be forced to a "1" by the
action of NAND10. The signal S4 is loaded in the latch LEOUT
to form OUTEXTN at the same time as MID_DATA is loaded into
LDOUT to form OUT_DATA[7:0].
Thus, the first time a given MID_DATA is loaded into
LEOUT, the associated OUTEXTN will be forced high, whereas,
on the second occasion, OUTEXTN will be the same as the
signal QEIN. Now consider the situation during the very last
word of a token in which QEIN is known to be low. During the
first time MID_DATA is loaded into LDOUT, OUTEXTN will be
"1", and during the second time, OUTEXTN will be "0",
indicating the true end of the token.
The output signal QVIN from the validation latch LVIN is
combined with the signal QI3 in a similar gate combination
(INV12 and NAND12) to form a signal S5. Using known Boolean
techniques, it can be shown that the signal S5 is HIGH either
when the validation signal QVIN is HIGH, or when the signal
QI3 is low (indicating that the data is a duplicate). The
signal S5 is loaded into the validation output latch LVOUT at
the same time that MID_DATA is loaded into LDOUT and the
intermediate extension bit (signal S4) is loaded into LEOUT.
2~ Signal S5 is also combined with the signal QO2 (the data
token signal) in the logic gates NAND30 and INV30 to form the
output validation signal OUT_VALID. As was mentioned
earlier, OUT_VALID is HIGH only when there is a valid token
and the validation signal QVOUT is high.
In the present invention, the MID ACCEPT signal is
combined with the signal S5 in a series of logic gates
(NAND26 and INV26) that perform the well-known AND function
to form a signal S6 that is used as one of the two enabling
signals to the latches LO1, LO2 and LO3. The signal S6 rises
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to a "l" when the MID_ACCEPT signal is HIGH and when either
the validation signal QVIN is high, or when the token is a
duplicate (QI3 is a "O"). If the signal MID_ACCEPT is HIGH,
the latches LO1-LO3 will, therefore, be enabled when the
clock signal PH1 is high whenever valid input data is loaded
at the input of the stage, or when the latched data is a
duplicate.
From the discussion above, one can see that the stage
shown in Figs. 8a and 8b will receive and transfer data
between stages under the control of the validation and
acceptance signals, as in previous embodiments, with the
exception that the output signal from the acceptance latch
LAIN at the input side is combined with the toggling
duplication signal so that a data word will be output twice
before a new word will be accepted.
The various logic gates such as NAND16 and INV16 may, of
course, be replaced by equivalent logic circuitry (in this
case, a single AND gate). Similarly, if the latches LEIN and
LVIN, for example, have inverting outputs, the inverters
INV10 and INV12 will not be necessary. Rather, the
corresponding input to the gates NAND10 and NAND12 can be
tied directly to the inverting outputs of these latches. As
long as the proper logical operation is performed, the stage
will operate in the same manner. Data words and extension
bits will still be duplicated.
One should note that the duplication function that the
illustrated stage performs will not be performed unless the
first data word of the token has a "1" in the third position
of the word and "O's" in the five high-order bits. (Of
course, the required pattern can easily be changed and set by
selecting other logic gates and interconnections other than
the NOR1, NOR2, NND18 gates shown.)
In addition, as Fig. 8 shows, the OUT_VALID signal will be
forced low during the entire token unless the first data word
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72
~as the ~tructure described above. This has the effect that
all token~ except the one that cause~ the duplication process
will be deleted from the token stream, since a device
connected to the output terminals (OUTDATA, OUTEXTN and
OUTVALID) will not recognize these token words as valid data.
As before, both validation latches LVIN, LVOUT in the
stage can be reset by a single conductor NOT RESETO, and a
single resetting input R on the downstream latch LVOUT, with
the reset signal being propagated backwards to cause the
upstream validation latch to be forced low on the next clock
cycle.
It should be noted that in the example shown in Fig. 8,
the duplication of data contained in DATA tokens serves only
as an example of the way in which circuitry may manipulate
the ACCEPT and VALID signals so that more data is leaving the
pipeline stage than that which is arriving at the input.
Similarly, the example in Fig. 8 removes all non-DATA tokens
purely as an illustration of the way in which circuitry may
manipulate the VALID signal to remove data from the stream.
In most typical applications, however, a pipeline stage will
simply pass on any tokens that it does not recognize,
unmodified, so that other stages further down the pipeline
may act upon them if required.
Figs. 9a and 9b taken together illustrate an example of a
timing diagram for the data duplication circuit shown in
Figs. 8a and 8b. As before, the timing diagram shows the
relationship between the two-phase clock signals, the various
internal and external control signals, and the manner in
which data is clocked between the input and output sides of
the stage and is duplicated.
Referring now more particularly to Figure 10, there is
shown a reconfigurable process stage in accordance with one
` 2145159
73
aspect of the present invention.
Input latche~ 34 receive ~n input over a first bus
31. A first ou~ from the input latches 34 is passed over
line 32 to a token decode subsystem 33. A second output from
the input latches 34 i8 pa~6~ as a first input over line 35
to a processing unit 36. A first output from the token decode
subsystem 33 is pASse~ over line 37 as a second input to the
processing unit 36. A second output from the token decode 33
is passed over line 40 to an action identification unit 39.
The action identification unit 39 also receive~ input from
registers 43 and 44 over line 46. The registers 43 and 44
hold the state of the machine as a whole. This state is
determined by the history of tokens previously received. The
output from the action identification unit 39 is passed over
line 38 as a third input to the processing unit 36. The
output from the processing unit 36 is passed to output
latches 41. The output from the output latches 41 is passed
over a second bus 42.
Referring now to Figure 11, a Start Code Detector
(SCD) 51 receives input over a two-wire interface 52. This
input can be either in the form of DATA tokens or as data
bits in a data stream. A first output from the Start Code
Detector 51 is passed over line 53 to a first logical first-
in first-out buffer (FIF0) 54. The output from the first
FIFO 54 is logically passed over line 55 as a first input to
a Huffman decoder 56. A second output from the Start Code
Detector 51 is passed over line 57 as a first input to a DRAM
interface 58. The DRAM interface 58 also receives input from
a buffer manager 59 over line 60. Signals are transmitted to
and received from external DRAM (not shown) by the DRAM
interface 58 over line 61. A first output from the DRAM
interface 58 is passed over line 62 as a first physical input
to the Huffman decoder 56.
C~145159
- 74
The output from the Huffman decoder 56 is passed
over line 63 as an input to an Index to Data Unit (ITOD) 64.
The Huffman decoder 56 and the ITOD 64 work together as a
single logical unit. The output from the ITOD 64 is passed
over line 65 to an arithmetic logic unit (ALU) 66. A first
output from the ALU 66 is passed over line 67 to a read-only
memory (ROM) state machine 68. The output from the ROM state
machine 68 is pAsse~ over line 69 as a second physical input
to the Huffman decoder 56. A second-output from the ALU 66
is passed over line 70 to a Token Formatter (T/F) 71.
A first output 72 from the T/F 71 of the present
invention is passed over line 72 to a second FIFO 73. The
output from the second FIFO 73 is passed over line 74 as a
first input to an inverse modeller 75. A second output from
the T/F 71 is passed over line 76 as a third input to the
DRAM interface 58. A third output from the DRAM interface 58
is passed over line 77 as a second input to the inverse
modeller 75. The output from the inverse modeller 75 is
passed over line 78 as an input to an inverse quantizer 79
The output from the inverse quantizer 79 is passed over line
80 as an input to an inverse zig-zag (IZZ) 81. The output
from the IZZ 81 is passed over line 82 as an input to an
inverse discrete cosine transform (IDCT) 83. The output from
the IDCT 83 is passed over line 84 to a temporal decoder (not
shown).
Referring now more particularly to Figure 12, a
temporal decoder in accordance with the present invention is
shown. A fork 91 receives as input over line 92 the output
from the IDCT 83 (shown in Fig. 11). As a first output from
the fork 91, the control tokens, e.g., motion vectors and the
like, are passed over line 93 to an address generator 94.
Data tokens are also passed to the address generator 94 for
counting purposes. As a second output from the fork 91, the
21451S9
data is p~ 6~ over line 95 to a FIFO 96. The output from the
FIFO 96 is then p~ over line 97 ac a first input to a
summer 98. The output from the address generator 94 is
passed over line 99 as a first input to a DRAM interface 100.
Signals are transmitted to and received from external DRAM
tnot shown) by the DRAM interface 100 over line 101. A first
output from the DRAM interface 100 is passed over line 102 to
a prediction filter 103. The output from the prediction
filter 103 is passed over line 104 as a second input to the
summer 98. A first output from the summer 98 is passed over
line 105 to output selector 106. A second output from the
summer 98 is passed over line 107 as a second input to the
DRAM interface 100. A second output from the DRAM interface
100 is passed over line 108 as a second input to the output
selector 106. The output from the output selector 106 is
passed over line 109 to a Video Formatter (not shown in
Figure 12).
Referring now to Figure 13, a fork 111 receives
input from the output selector 106 (shown in Figure 12) over
line 112. As a first output from the fork 111, the control
tokens are passed over line 113 to an address generator 114.
The output from the address generator 114 is passed over line
115 as a first input to a DRAM interface 116. As a second
output from the fork 111 the data is passed over line 117 as
a second input to the DRAM interface 116. Signals are
transmitted to and received from external DRAM (not shown) by
the DRAM interface 116 over line 118. The output from the
DRAM interface 116 is passed over line 119 to a display pipe
120.
It will be apparent from the above descriptions
that each line may comprise a plurality of lines, as
necessary.
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76
Referring now to Figure 14a, in the MPEG standard
a picture 131 is encoded as one or more slices 132. Each
slice 132 is, in turn, comprised of a plurality of blocks
133, and is encoded row-by-row, left-to-right in each row.
As is shown, each slice 132 may span exactly one full line of
blocks 133, less than one line B or D of blocks 133 or
multiple lines C of blocks 133.
Referring to Figure 14b, ~in the JPEG and H.261
standards, the Common Intermediate Format (CIF) i6 used,
wherein a picture 141 is encoded as 6 rows each containing 2
groups of blocks (GOBs) 142. Each GOB 142 is, in turn,
composed of either 3 rows or 6 rows of an indeterminate
number of blocks 143. Each GOB 142 is encoded in a zigzag
direction indicated by the arrow 144. The GOBs 142 are, in
turn, processed row-by-row, left-to-right in each row.
Referring now to Figure 14c, it can be seen that,
for both MPEG and CIF, the output of the encoder is in the
form of a data stream 151. The decoder receives this data
stream 151. The decoder can then reconstruct the image
according to the format used to encode it. In order to allow
the decoder to recognize start and end points for each
standard, the data stream 151 is segmented into lengths of 33
blocks 152.
Referring to Figure 15, a Venn diagram is shown,
representing the range of values possible for the table
selection from the Huffman decoder 56 (shown in Fig. 11) of
the present invention. The values possible for an MPEG
decoder and an H.261 decoder overlap, indicating that a
single table selection will decode both certain MPEG and
certain H.261 formats. Likewise, the values possible for an
MPEG decoder and a JPEG decoder overlap, indicating that a
single table selection will decode both certain MPEG and
21451~9
certain JPEG formats. Additionally, it is 6hown that the
H.261 values and the JPEG values do not overlap, indicating
that no single table selection exists that will decode both
formats.
Referring now more particularly to Figure 16, there
is shown a schematic representation of variable length
pictur~ data in accordance with the practice of the present
invention. A first picture 161 to be proceF~6~ contains a
first PICTURE START token 162, first-picture information of
indeterminate length 163, and a first PICTURE_END token 164.
A second picture 165 to be processed contains a second
PICTURE_START token 166, second picture information of
indeterminate length 167, and a second PICTURE END token 168.
The PICTURE START tokens 162 and 166 indicate the start of
the pictures 161 and 165 to the processor. Likewise, the
PICTURE END tokens 164 and 168 signify the end of the
pictures 161 and 165 to the processor. This allows the
processor to process picture information 163 and 167 of
variable lengths.
Referring to Figure 17, a split 171 receives input
over line 172. A first output from the split 171 is passed
over line 173 to an address generator 174. The address
generated by the address generator 174 is passed over line
175 to a DRAM interface 176. Signals are transmitted to and
received from external DRAM (not shown) by the DRAM interface
176 over line 177. A first output from the DRAM interface
176 is passed over line 178 to a prediction filter 179. The
output from the prediction filter 179 is passed over line 180
as a first input to a su D er 181. A second output from the
split 171 is passed over line 182 as an input to a first-in
first-out buffer (FIF0) 183. The output from the FIF0 183 is
passed over line 184 as a second input to the summer 181.
The output from the summer 181 is passed over line 185 to a
214~15g
.
78
write signal generator 186. A first output from the write
signal generator 186 i6 pAfi~6~ over line 187 to the DRAM
interface 176. A second output from the write signal
generator 186 i6 pa~ over line 188 as a first input to a
S read signal generator 189. A second output from the DRAM
interface 176 is pa~ over line 190 as a second input to
the read signal generator 189. The output from the read
signal generator 189 is passed over line 191 to a Video
Formatter (not shown in Figure 17). -
Referring now to Figure 18, the prediction
filtering process is illustrated. A forward picture 201 is
passed over line 202 as a first input to a summer 203. A
backward picture 204 is passed over line 205 as a second
input to the summer 203. The output from the summer 203 is
passed over line 206.
Referring to Figure 19, a slice 211 comprises one
or more macroblocks 212. In turn, each macroblock 212
comprises four luminance blocks 213 and two chrominance
blocks 214, and contains the information for an original 16
x 16 block of pixels. Each of the four luminance blocks 213
and two chrominance blocks 214 is 8 x 8 pixels in size. The
four luminance blocks 213 contain a 1 pixel to 1 pixel
mapping of the luminance (Y) information from the original 16
x 16 block of pixels. One chrominance block 214 contains a
representation of the chrominance level of the blue color
signal (Cu/b), and the other chrominance block 214 contains
a representation of the chrominance level of the red color
signal (Cv/r). Each chrominance level is subsampled such
that each 8 x 8 chrominance block 214 contains the
chrominance level of its color signal for the entire original16 x 16 block of pixels.
Referring now to Figure 20, the structure and
function of the Start Code Detector will become apparent. A
214~159
79
value register 221 receives image data over a line 222. The
line 222 iB eight bits wide, allowing for parallel
transmission of eight bits at a time. The output from the
value register 221 is pa-~Qd serially over line 223 to a
decode register 224. A first output from the decode register
224 is pa6~e~ to a detector 225 over a line 226. The line
226 is twenty-four bits wide, allowing for parallel
transmission of twenty-four bits at a time. The detector 225
detects the presence or absence of an-image which corresponds
to a standard-independent start code of 23 "zero" values
followed by a single "one" value. An 8-bit data value image
follows a valid start code image. On detecting the presence
of a start code image, the detector 225 transmits a start
image over a line 227 to a value decoder 228.
A second output from the decode register 224 is
passed serially over line 229 to a value decode shift
register 230. The value decode shift register 230 can hold
a data value image fifteen bits long. The 8-bit data value
following the start code image is shifted to the right of the
value decode shift register 230, as indicated by area 231.
This process eliminates overlapping start code images, as
discussed below. A first output from the value decode shift
register 230 is passed to the value decoder 228 over a line
232. The line 232 is fifteen bits wide, allowing for
parallel transmission of fifteen bits at a time. The value
decoder 228 decodes the value image using a first look-up
table (not shown). A second output from the value decode
shift register 230 is passed to the value decoder 228 which
passes a flag to an index-to-tokens converter 234 over a line
235. The value decoder 228 also passes information to the
index-to-tokens converter 234 over a line 236. The
information is either the data value image or start code
index image obtained from the first look-up table. The flag
21~5159
~ 80
indicates which form of information is r~ The line 236
i~ fifteen bitC wide, allowing for parallel transmission of
fifteen bits at a time. While 15 bits has been chosen here
as the width in the present invention it will be appreciated
that bits of other lengths may also be used. The index-to-
tokens converter 234 converts the information to token images
using a second look-up table (not shown) similar to that
given in Table 12-3 of the Users Manual. The token images
generated by the index-to-tokens converter 234 are then
output over a line 237. The line 237 is fifteen bits wide,
allowing for parallel transmission of fifteen bits at a time.
Referring to Figure 21, a data stream 241
consisting of individual bits 242 is input to a Start Code
Detector (not shown in Figure 21). A first start code image
243 is detected by the Start Code Detector. The Start Code
Detector then receives a first data value image 244. Before
processing the first data value image 244, the Start Code
Detector may detect a second start code image 245, which
overlaps the first data value image 244 at a length 246. If
this occurs, the Start Code Detector does not process the
first data value image 244, and instead receives and
processes a second data value image 247.
Referring now to Figure 22, a flag generator 251
receives data as a first input over a line 252. The line 252
is fifteen bits wide, allowing for parallel transmission of
fifteen bits at a time. The flag generator 251 also receives
a flag as a second input over a line 253, and receives an
input valid image over a first two-wire interface 254. A
first output from the flag generator 251 is passed over a
line 255 to an input valid register (not shown). A second
output from the flag generator 251 is passed over a line 256
to a decode index 257. The decode index 257 generates four
outputs; a picture start image is passed over a line 258, a
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81
picture number image i~ pAS~ over a line 259, an insert
image i~ pa^~eA over a line 260, and a replace image is
pa~ over a line 261. The data from the flag generator 2S1
is passed over a line 262a. A header generator 263 uses a
S look-up table to generate a replace image, which is passed
over a line 262b. An extra word generator 264 uses the MPU
to generate an insert image, which is passed over a line
262c. Line 262a, and line 262b combine to form a line 262,
which is first input to output la~ches 26S. The output
latches 26S pass data over a line 266. The line 266 is
fifteen bits wide, allowing for parallel transmission of
fifteen bits at a time.
The input valid register (not shown) passes an
image as a first input to a first OR gate 267 over a line
268. An insert image is passed over a line 269 as a second
input to the first OR gate 267. The output from the first OR
gate 267 is passed as a first input to a first AND gate 270
over a line 271. The logical negation of a remove image is
passed over a line 272 as a second input to the first AND
gate 270 is passed as a second input to the output latches
265 over a line 273. The output latches 265 pass an output
valid image over a second two-wire interface 274. An output
accept image is received over the second two-wire interface
274 by an output accept latch 275. The output from the
output accept latch 275 is passed to an output accept
register (not shown) over a line 276.
The output accept register (not shown) passes an
image as a first input to a second OR gate 277 over a line
278. The logical negation of the output from the input valid
register is passed as a second input to the second OR gate
277 over a line 279. The remove image is passed over a line
280 as a third input to the second OR gate 277. The output
from the second OR gate 277 is passed as a first input to a
second AND gate 281 over a line 282. The logical negation of
21~5159
82
an in~ert image i~ pa?~e~ a~ a second input to the second AND
gate 281 over a line 283. The output from the second AND
gate 281 is pas6ed over a line 284 to an input accept latch
285. The output from the input accept latch 285 is passed
s over the first two-wire interface 254.
~` 2145159
_ 83
TABLF ~00
Format I~age Received Tokens Generated
1. H.261 SEQUENCE START SEQUENCE START
MPEG PICTURE START GROUP START
S JPEG (None) PICTURE START
PICTURE DATA
2. H.261 (None) PICTURE END
MPEG (None) PADDING
JPEG (None) - FLUSH
STOP AFTER PICTURE
As set forth in Table 600 which shows a relationship
between the absence or presence of standard signals in the
certain machine independent control tokens, the detection.of
an image by the Start Code Detector 51 generates a sequence
of machine independent Control Tokens. Each image listed in
the "Image Received" column starts the generation of all
machine independent control tokens listed in the group in the
"Tokens Generated" column. Therefore, as shown in line 1 of
Table 600, whenever a "sequence start" image is received
during H.261 processing or a "picture start" image is
received during MPEG processing, the entire group of four
control tokens is generated, each followed by its
corresponding data value or values. In addition, as set
forth at line 2 of Table 600, the second group of four
control tokens is generated at the proper time irrespective
of images received by the Start Code Detector 51.
TABLE 601
DISPLAY ORDER: I1 B2 B3 P4 B5 B6 P7 B8 B9 I10
TRANSMIT ORDER: I1 P4 B2 B3 P7 B5 B6 I10 B8 B9
As shown in line 1 of Table 601 which shows the timing
relationship between transmitted pictures and displayed
pictures, the picture frames are displayed in numerical
order. However, in order to reduce the number of frames that
2145159
84
must be stored in memory, the frames are transmitted in a
different order. It is useful to begin the analysis from an
intraframe (I frame). The Il frame is transmitted in the
order it is to be displayed. The next predicted frame (P
frame), P4, is then transmitted. Then, any bi-directionally
interpolated frames (B frames) to be displayed between the Il
frame and P4 frame are transmitted, represented by frames B2
and B3. This allows the transmitted B frames to reference a
previous frame (forward prediction) or a future frame
(backward prediction). After transmitting all the B frames
to be displayed between the I1 frame and the P4 frame, the
next P frame, P7, is transmitted. Next, all the B frames to
be displayed between the P4 and P7 frames are transmitted,
corresponding to B5 and B6. Then, the next I frame, IlO, is
transmitted. Finally, all the B frames to be displayed
between the P7 and I10 frames are transmitted, corresponding
to frames B8 and B9. This ordering of transmitted frames
requires only two frames to be kept in memory at any one
time, and does not require the decoder to wait for the
transmission of the next P frame or I frame to display an
interjacent B frame.
Further information regarding the structure and operation,
as well as the features, objects and advantages, of the
invention will become more readily apparent to one of
ordinary skill in the art from the ensuing additional
detailed description of illustrative embodiment of the
invention which, for purposes of clarity and convenience of
explanation are grouped and set forth in the following
sections:
,0 1. Multi-Standard Configurations
2. JPEG Still Picture Decoding
3. Motion Picture Decompression
. R~ Memory Map
,. Bitstream Characteristics
2145159
a5
6. Reconfigurable Processing Stage
7. Multi-Standard Coding
8. Multi-Standard Processing Circuit-2nd Mode of Operation
9. Start Code Detector
10. Tokens
11. DRAM Interface
12. Prediction Filter
13. Accessing Registers
14. Microprocessor Interface (MPI)
15. MPI Read Timing
16. MPI Write Timing
17. Key Hole Address Locations
18. Picture End
19. Flushing Cperation
20. Flush Function
21. Stop-After-Picture
22. Multi-Standard Search Mode
23. Inverse Modeler
2~. Inverse Quantizer
25. Huffman Decoder and Parser
26. Diverse Discrete Cosine Transformer
27. Buffer Manager
214~159
1. ~nLTI-8$A~DARD CO~FIa~RATIO~8
Since t~e various compression standards, i.e., JPEG,
MPEG and H.261, are well known, as for example as described
in the aforementioned United States Patent No. 5,212,742, the
detailed specification~ of those standards are not repeated
here.
As previously mentioned, the present invention is
capable of decompressing a variety of differently encoded,
picture data bitstreams. In each of ~he different standards
of encoding, some form of output formatter is required to
take the data presented at the output of the spatial decoder
operating alone, or the serial output of a spatial decoder
and temporal decoder operating in combination, ~as
subsequently described herein in greater detail) and
reformatting this output for use, including display in a
computer or other display systems, including a video display
system. Implementation of this formatting varies
significantly between encoding standards and/or the type of
display selected.
In a first embodiment, in accordance with the present
invention, as previously described with reference to Figures
10-12 an address generator is employed to store a block of
formatted data, output from either the first decoder (Spatial
Decoder) or the combination of the first decoder (Spatial
Decoder) and the second decoder (the Temporal Decoder), and
to write the decoded information into and/or from a memory in
a raster order. The video formatter described hereinafter
provides a wide range of output signal combinations.
In the preferred multi-standard video decoder embodiment
of the present invention, the Spatial Decoder and the
Temporal Decoder are required to implement both an MPEG
encoded signal and an H.261 video decoding system. The DRAM
interfaces on both devices are configurable to allow the
quantity of DRAM required to be reduced when working with
21~5159
small picture formats and at low coded data rates. The
reconfiguration of these DRAMs will be further described
hereinafter with reference to the DRAM interface. Typically,
a single 4 megabyte DRAM i~ required by each of the Temporal
Decoder and the Spatial Decoder circuits.
The Spatial Decoder of the present invention performs
all the required processing within a single picture. This
reduces the redundancy within one picture.
The Temporal Decoder reduces the redundancy between the
subject picture with relationship to a picture which arrives
prior to the arrival of the subject picture, as well as a
picture which arrives after the arrival of the subject
picture. One aspect of the Temporal Decoder is to provide an
address decode network which handles the complex addressing
needs to read out the data associated with all of these
pictures with the least number of circuits and with high
speed and improved accuracy.
As previously described with reference to Figure 11, the
data arrives through the Start Code Detector, a FIFO register
which precedes a Huffman decoder and parser, through a second
FIFO register, an inverse modeller, an inverse quantizer,
inverse zigzag and inverse DCT. The two FIFOs need not be on
the chip. In one embodiment, the data does not flow through
a FIFO that is on the chip. The data is applied to the DRAM
interface, and the FIFO-IN storage register and the FIFO-OUT
register is off the chip in both cases. These registers,
whose operation is entirely independent of the standards,
will subsequently be described herein in further detail.
The majority of the subsystems and stages shown in
Figure 11 are actually independent of the particular standard
used and include the DRAM interface 58, the buffer manager 59
which is generating addresses for the DRAM interface, the
inverse modeller 75, the inverse zig-zag 81 and the inverse
214~159
- 88
DCT 83. The standard independent units within the Huffman
decoder and parser include the ALU 66 and the token formatter
71.
Referring now to Figure 12, the standard-
independent units include the DRAM interface 100, the fork91, the FIFO register 96, the summer 98 and the output
selector 106. The standard dependent units are the address
generator 94, which is different in H.261 and in MPEG, and
the prediction filter 103, which i~-reconfigurable to have
the ability to do both H.261 and MPEG. The JPEG data will
flow through the entire machine completely unaltered.
Figure 13 depicts a high level block diagram of the
video formatter chip. The vast majority of this chip is
independent of the standard. The only items that are
affected by the standard is the way the data is written into
the DRAM in the case of H.261, which differs from MPEG or
JPEG; and that in H.261, it is not necessary to code every
single picture. There is some timing information referred to
- as a temporal reference which provides some information
regarding when the pictures are intended to be displayed, and
that is also handled by the address generation type of logic
in the video formatter.
The remainder of the circuitry embodied in the video
formatter, including all of the color space conversion, the
up-sampling filters and all of the gamma correction RAMs, is
entirely independent of the particular compression standard
utilized.
The Start Code Detector of the present invention is
dependent on the compression standard in that it has to
recognize different start code patterns in the bitstream for
each of the standards. For example, H.261 has a 16 bit start
code, MPEG has a 24 bit start code and JPEG uses marker codes
which are fairly different from the other start codes. Once
the Start Code Detector has recognized those different start
214~159
89
. .
codes, its operation i~ e~entially independent of the
compression s~A-rd. For instance, during searc~ing, apart
from the circuitry that recognizes the different category of
markers, much of the operation is very similar between the
three different compression ctandards.
The next unit i8 the state machine 68 (Figure 11)
located within the Huffman decoder and parser. Here, the
actual circuitry is almost identical for each of the three
compression standards. In fact, the only element that is
affected by the standard in operation i8 the reset address of
the machine. If just the parser is recet, then it jumps to
a different address for each standard. There are, in fact,
four standards that are recognized. These standards are
H.261, JPEG, MPEG and one other, where the parser enters a
piece of code that is used for testing. This illustrates
that the circuitry is identical in almost every aspect, but
the difference is the program in the microcode for each of
the standards. Thus, when operating in H.261, one program is
running, and when a different program is running, there is no
overlap between them. The same holds true for JPEG, which is
a third, completely independent program.
The next unit is the Huffman decoder 56 which
functions with the index to data unit 64. Those two units
cooperate together to perform the Huffman decoding. Here,
the algorithm that is used for Huffman decoding is the same,
irrespective of the compression standard. The changes are in
which tables are used and whether or not the data coming into
the Huffman decoder is inverted. Also, the Huffman decoder
itself includes a state machine that understands some aspects
of the coding standards. These different operations are
selected in response to an instruction coming from the parser
state machine. The parser state machine operates with a
different program for each of the three compression standards
21451~9
and issue~ the correct command to the Huffman decoder at
different times consi~tent wit~ the standard in operation.
The lact unit on the chip that is dependent on the
compression standard is the inverse quantizer 79, where the
S mathematics that the inverse guantizer performs are different
for each of the different standards. In this regard, a
CODING_STANDARD token is decoded and the i-nverse guantizer 79
remembers which standard it is operating in. Then, any
subseguent DATA tokens that happen-after that event, but
before another CODING STANDARD may come along, are dealt with
in the way indicated by the CODING STANDARD that has been
remembered inside the inverse quantizer. In the detailed
description, there is a table illustrating different
parameters in the different standards and what circuitry is
responding to those different parameters or mathematics.
The address generation, with reference to H.261, differs
for each of the subsystems shown in Figure 12 and Figure 13.
The address generation in Figure 11, which generates
addresses for the two FIFOs before and after the Huffman
decoder, does not change depending on the coding standards.
Even in H.261, the address generation that happens on that
chip is unaltered. Essentially, the difference between these
standards is that in MPEG and JPEG, there is an organization
of macroblocks that are in linear lines going horizontally
across pictures. As best observed in Figure 14a, a first
macroblock A covers one full line. A macroblock B covers
less than a line. A macroblock C covers multiple lines. The
division in MPEG is into slices 132, and a slice may be one
horizontal line, A, or it may be part of a horizontal line B,
or it may extend from one line into the next line, C. Each
of these slices 132 is made up of a row of macroblocks.
In H.261, the organization is rather different
because the picture is divided into groups of blocks (GOB).
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A group of blocks is three rows of macroblocks high by eleven
macroblocks wide. In the case of a CIF picture, there are
twelve such groups of blocks. However, they are not
organized one above the other. Rather, there are two groups
of blocks next to each other and then six high, i.e., there
are 6 GOB's vertically, and 2 GOB's horizontally.
In all other standards, when performing the
addressing, the macroblocks are addressed in order as
described above. More specificall~, addressing proceeds
along the lines and at the end of the line, the next line is
started. In H.261, the order of the blocks is the same as
described within a group of blocks, but in moving onto the
next group of blocks, it is almost a zig-zag.
The present invention provides circuitry to deal
with the latter affect. That is the way in which the address
generation in the spatial decoder and the video formatter
varies for H.261. This is accomplished whenever information
is written into the DRAM. It is written with the knowledge
of the aforementioned address generation sequence so the
place where it is physically located in the RAM is exactly
the same as if this had been an MPEG picture of the same
size. Hence, all of the address generation circuitry for
reading from the DRAM, for instance, when forming
predictions, does not have to comprehend that it is H.261
standard because the physical placement of the information in
the memory is the same as it would have been if it had been
in MPEG sequence. Thus, in all cases, only writing of data
is affected.
In the Temporal Decoder, there is an abstraction for
H.261 where the circuitry pretends something is different
from what is actually occurring. That is, each group of
blocks is conceptually stretched out so that instead of
having a rectangle which is 11 x 3 macroblocks, the
macroblocks are stretched out into a length of 33 blocks (see
` 2145159
_ 92
Figure 14c) group of blocks which i5 one macroblock high. By
doing that, exactly the same counting mechanisms used on the
Temporal Decoder for counting through the groups of blocks
are also used for MPEG.
There is a correspondence in the way that the
circuitry is designed between an H.261 group of blocks and an
MPEG slice. When H.261 data i8 pro~essA~ after the Start
Code Detector, each group of blocks is preceded by a
slice_start_code. The next group of blocks is preceded by
the next slice_start code. The counting that goes on inside
the Temporal Decoder for counting through this structure
pretends that it is a 33 macroblock-long group that is one
macroblock high. This is sufficient, although the circuitry
also counts every 11th interval. When it counts to the 11th
macroblock or the 22nd macroblock, it resets some counters.
This is accomplished by simple circuitry with another counter
that counts up each macroblock, and when it gets to 11, it
resets to zero. The microcode interrogates that and does
that work. All the circuitry in the temporal decoder of the
present invention is essentially independent of the
compression standard with respect to the physical placement
of the macroblocks.
In terms of multi-standard adaptability, there are
a number of different tables and the circuitry selects the
appropriate table for the appropriate standard at the
appropriate time. Each standard has multiple tables; the
circuitry selects from the set at any given time. Within any
one standard, the circuitry selects one table at one time and
another table another time. In a different standard, the
circuitry selects a different set of tables. There is some
intersection between those tables as indicated previously in
the discussion of Figure 15. For example, one of the tables
used in MPEG is also used in JPEG. The tables are not a
completely isolated set. Figure 15 illustrates an H.261
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93
set, ~n MPEG set and a JPEG set. Note that there is a much
greater overlap between the H.261 set and the MPEG set. They
are quite common in the tables they utilize. There is a
small overlap between MPEG and JPEG, and there is no overlap
at all between H.261 and JPEG so that these standards have
totally different sets of tables.
As previously indicated, most of the system units are
compression standard independent. If a unit is standard
independent, and such units need not remember what
CODING_STANDARD is being processed. All of the units that
are standard dependent remember the compression standard as
the CODING_STANDARD token flows by them. When information
encoded/decoded in a first coding standard is distributed
through the machine, and a machine is changing standards,
prior machines under microprocessor control would normally
choose to perform in accordance with the H.261 compression
standard. The MPU in such prior machines generates signals
stating in multiple different places wlthin the machine that
the compression standard is changing. The MPU makes changes
at different times and, in addition, may flush the pipeline
through.
In accordance with the invention, by issuing a change of
CODING_STANDARD tokens at the Start Code Detector that is
positioned as the first unit in the pipeline, this change of
compression standard is readily handled. The token says a
certain coding standard is beginning and that control
information flows down the machine and config~res all the
other registers at the appropriate time. The MPU need not
program each register.
The prediction token signals how to form predictions
using the bits in the bitstream. Depending on which
compression standard is operating, the circuitry translates
the information that is found in the standard, i.e. from the
bitstream into a prediction mode token. This processing is
214~15~
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94
perfo~m~d by the Huffman decoder and parser state machine,
where it is easy to manipulate bits based on certain
conditions. The Start Code Detector generates this
prediction mode token. The token then flows down the machine
to the circuitry of the Temporal Decoder, which is the device
responsible for forming predictions. The circuitry of the
spatial decoder interprets the token without having to know
what standard it is operating in because the bits in it are
invariant in the three different standards. The Spatial
lo Decoder just does what it is told in response to that token.
By having these tokens and using them appropriately, the
design of other units in the machine is simplified. Although
there may be some complications in the program, benefits are
received in that some of the hard wired logic which would be
difficult to design for multi-standards can be used here.
2. JPEG STILL PICTURE DECODING
As previously indicated, the present invention relates
to signal decompression and, more particularly, to the
decompression of an encoded video signal, irrespective of the
compression standard employed.
One aspect of the present invention is to provide a first
decoder circuit (the Spatial Decoder) to decode a first
encoded signal (the JPEG encoded video signal) in combination
with a second decoder circuit (the Temporal Decoder) to
decode a first encoded signal tthe MPEG or H.261 encoded
video signal) in a pipeline processing system. The Temporal
Decoder is not needed for JPEG decoding.
In this regard, the invention facilitates the
decompression of a plurality of differently encoded signals
through the use of a single pipeline decoder and
decompression system. The decoding and decompression
pipeline processor is organized on a unique and special
confiquration which allows the handling of the multi-standard
214515~
.
.
encode~ -~video signals through the use of techniques all
compatible with the single pipeline decoder and processing
system. The Spatial Decoder is combined with the Temporal
Decoder, and the Video Formatter is used in driving a video
display.
Another aspect of the invention is the use of the
combination of the Spatial Decoder and the Video Formatter
for use with only still pictures. The compression standard
independent Spatial Decoder performs all of the data
lo processing within the boundaries of a single picture. Such
a decoder handles the spatial decompression of the internal
picture data which is passing through the pipeline and is
distributed within associated random access memories,
standard independent address generation circuits for handling
the storage and retrieval of information into the memories.
Still picture data is decoded at the output of the Spatial
Decoder, and this output is employed as input to the multi-
standard, configurable Video Formatter, which then provides
an output to the display terminal. In a first sequence of
similar pictures, each decompressed picture at the output of
the Spatial Decoder is of the same length in bits by the time
the picture reaches the output of the Spatial Decoder. A
second sequence of pictures may have a totally different
picture size and, hence, have a different length when
2~ compared to the first length. Again, all such second
sequence of similar pictures are of the same length in bits
by the time such pictures reach the output of the Spatial
Decoder.
Another aspect of the invention is to internally organize
~o the incoming standard dependent bitstream into a sequence of
control tokens and DATA tokens, in combination with a
plurality of sequentially-positioned reconfigurable
processing stages selected and organized to act as a
standard-independent, reconfigurable-pipeline-processor-
21~SlSg
` 96
Wi~th regard to JPEG decoding, a single Spatial Decoderwith no off chip DRAM can rapidly decode baseline JPEG
images. The Spatial Decoder supports all features of
baseline JPEG encoding standards. However, the image size
that can be decoded may be limited by the size of the output
buffer provided. The Spatial Decoder circuit also includes
a random access memory circuit, having machine-dependent,
standard independent address generation circuits for handling
the storage of information into the memories.
As previously, indicated the Temporal Decoder is not
required to decode JPEG-encoded video. Accordingly, signals
carried by DATA tokens pass directly through the Temporal
Decoder without further processing when the Temporal Decoder
is configured for a JPEG operation.
Another aspect of the present invention is to provide in
the Spatial Decoder a pair of memory circuits, such as buffer
memory circuits, for operating in combination with the
Huffman decodertvideo demultiplexor circuit (HD & VDM). A
first buffer memory is positioned before the HD & VDM, and a
second buffer memory is positioned after the HD & VDM. The
HD & ~DM decodes the bitstream from the binary ones and zeros
that are in the standard encoded bitstream and turns such
stream into numbers that are used downstream. The advantage
of the two buffer system is for implementing a multi-standard
decompression system. These two buffers, in combination with
the identified implementation of the Huffman decoder, are
described hereinafter in greater detail.
A still further aspect of the present multi-standard,
decompression circuit is the combination of a Start Code
Detector circuit positioned upstream of the first forward
buffer operating in combination with the Huffman decoder.
One advantage of this combination is increased flexibility in
dealing with the input bitstream, particularly padding, which
has to be added to the bitstream. The placement of these
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97
ident~ed components, Start Code Detector, memory buffers,
and Huffman decoder enhances the handling of certain
sequences in the input bitstream.
In addition, off chip DRAMs are used for decoding JPEG-
encoded video pictures in real time. The size and speed ofthe buffers used with the DRAMs will depend on the video
encoded data rates.
The coding standards identify all of the standard
dependent types of information that is necessary for storage
in the DRAMs associated with the Spatial Decoder using
standard independent circuitry.
3. MOTION PICTURE DECOMPRES8ION
In the present invention, if motion pictures are being
decompressed through the steps of decoding, a further
Temporal Decoder is necessary. The Temporal Decoder combines
the data decoded in the Spatial Decoder with pictures,
previously decoded, that are intended for display either
before or after the picture being currently decoded. The
Temporal Decoder receives, in the picture coded datastream,
information to identify this temporally-displaced
information. The Temporal Decoder is organized to address
temporally and spatially displaced information, retrieve it,
and combine it in such a way as to decode the information
located in one picture with the picture currently being
decoded and ending with a resultant picture that is complete
and is suitable for transmission to the video formatter for
driving the display screen. Alternatively, the resultant
picture can be stored for subsequent use in temporal decoding
of subsequent pictures.
Generally, the Temporal Decoder performs the processing
between pictures either earlier and/or later in time with
reference to the picture currently being decoded. The
Temporal Decoder reintroduces information that is not encoded
within the coded representation of the picture, becauSe it is
.` 21~5159
98
redundant and is already available at the decoder. More
specifically, it is probable that any given picture will
contain similar information as pictures temporally
surrounding it, both before and after. This similarity can
be made greater if motion compensation is applied. The
Temporal Decoder and decompression circuit also reduces the
redundancy between related pictures.
In another aspect of the present invention, the Temporal
Decoder is employed for handling the standard-dependent
output information from the Spatial Decoder. This standard
dependent information for a single picture is distributed
among several areas of DRAM in the sense that the
decompressed output information, processed by the Spatial
Decoder, is stored in other DRAM registers by other random
access memories having still other machine-dependent,
standard-independent address generation circuits for
combining one picture of spatially decoded information packet
of spatially decoded picture information, temporally
displaced relative to the temporal position of the first
picture.
In multi-standard circuits capable of decoding MPEG-
encoded signals, larger logic DRAM buffers may be required to
support the larger picture formats possible with MPEG.
. The picture information is moving through the serial
pipeline in 8 pel by 8 pel blocks. In one form of the
invention, the address decoding circuitry handles these pel
blocks (storing and retrieving~ along such block boundaries.
The address decoding circuitry also handles the storing and
retrieving of such 8 by 8 pel blocks across such boundaries.
This versatility is more completely described hereinafter.
A second Temporal Decoder may also be provided which
passes the output of the first decoder circuit (the Spatial
Decoder) directly to the Video Formatter for handling without
signal processing delay.
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99
The Temporal Decoder also reorders the blocks of picture
data for display by a display circuit. The address decode
circuitry, described hereinafter, provides handling of this
reordering.
As previously mentioned, one important feature of the
Temporal Decoder is to add picture information together from
a selection of pictures which have arrived earlier or later
than the picture under processing. When a picture is
described in this context, it may mean any one of the
following:
1. The coded data representation of the picture;
2. The result, i.e., the final decoded picture
resulting from the addition of a process step
performed by the decoder;
3. Previously decoded pictures read from the DRAM; and
4. The result of the spatial decoding, i.e., the extent
of data between a PICTURE_START token and a
subsequent PICTURE_END token.
After the picture data information is processed by the
Temporal Decoder, it is either displayed or written back into
a picture memory location. This information is then kept for
further reference to be used in processing another different
coded data picture.
Re-ordering of the MPEG encoded pictures for visual
display involves the possibility that a desired scrambled
picture can be achieved by varying the re-ordering feature of
the Temporal Decoder.
4. RAM MEMORY MAP
The Spatial Decoder, Temporal Decoder and Video
Formatter all use external DRAM. PreferabIy, the same DRAM
is used for all three devices. ~hile all three deviceS use
DRAM, and all three devices use a DRAM interface in
conjunction with an address generator, what each implements
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100
in DRAM i~ different. That is, each chip, e.g. Spatial
Decoder and Temporal n- ~A~r, have a different DRAM interface
and addres~ generation circuitry even through they use a
similar physical, external DRAM.
In brief, the Spatial Decoder implements two FIFOs in
the common DRAM. Referring again to Figure 11, one FIFO 54
is positioned before the Huffman decoder 56 and parser, and
the other is positioned after the Huffman decoder and parser.
The FIFOs are implemented in a relatively straightforward
manner. For each FIFO, a particular portion of DRAM is set
aside as the physical memory in which the FIFO will be
implemented.
The address generator associated with the Spatial
Decoder DRAM interface 58 keeps track of FIFO addresses using
two pointers. One pointer points to the first word stored in
the FIFO, the other pointer points to the last word stored in
the FIFO, thus allowing read/write operation on the
appropriate word. When, in the course of a read or write
operation, the end of the physical memory is reached, the
address generator "wraps around" to the start of the physical
memory.
In brief, the Temporal Decoder of the present invention
must be able to store two full pictures or frames of whatever
encoding standard (MPEG or H.261) is specified. For
simplicity, the physical memory in the DRAM into which the
two frames are stored is split into two halves, with each
half being dedicated (using appropriate pointers) to a
particular one of the two pictures.
~ MPEG uses three different picture types: Intra (I),
Predicted (P) and Bidirectionally interpolated (B). As
previously mentioned, B pictures are based on predictions
from two pictures. One picture is from the future and one
from the past. I pictures require no further decoding by the
Temporal Decoder, but must be stored in one of the two
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.
101
picture ~uffers for later use in decoding P and B pictures.
Decoding P pictures requires forming predictions from a
previously decoded P or I picture. The decoded P picture is
stored in a picture buffer for use decoding P and B pictures.
B pictures can require predictions form both of the picture
buffers. However, B pictures are not stored in the external
DRAM.
Note that I and P pictures are not output from the
Temporal Decoder as they are decoded. Instead, I and P
pictures are written into one of the picture buffers, and are
read out only when a subsequent I or P picture arrives for
decoding. In other words, the Temporal Decoder relies on
subsequent P or I pictures to flush previous pictures out of
the two picture buffers, as further discussed hereinafter in
1~ the section on flushing. In brief, the Spatial Decoder can
provide a fake I or P picture at the end of a video sequence
to flush out the last P or I picture. In turn, this fake
picture is flushed when a subsequent video sequence starts.
The peak memory band width load occurs when decoding B
pictures. The worst case is the B frame may be formed from
predictions from both the picture buffers, with all
predictions being made to half-pixel accuracy.
As previously described, the Temporal Decoder can be
configured to provide MPEG picture reordering. With this
picture reordering, the output of P and I pictures is delayed
until the next P or I picture in the data stream starts to be
decoded by the Temporal Decoder.
As the P or I pictures are reordered, certain tokens are
stored temporarily on chip as the picture is written into the
picture buffers. When the picture is read out for display,
these stored tokens are retrieved. At the output of the
Temporal Decoder, the DATA Tokens of the newly decoded P or
I picture are replaced with DATA Tokens for the older P or I
picture.
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102
In contrast, H.261 makes predictions only from the
picture just decoded. As each picture is decoded, it is
written into one of the two picture buffers so it can be used
in decoding the next picture. The only DRAM memory
operations required are writing 8 x 8 blocks, and forming
predictions with integer accuracy motion vectors.
In brief, the Video Formatter stores three frames or
pictures. Three pictures need to be stored to accommodate
such features as repeating or skipping pictures.
5. BITSTREAM CHARACTERISTICS
Referring now particularly to the Spatial Decoder of the
present invention, it is helpful to review the bitstream
characteristics of the encoded datastream as these
characteristics must be handled by the circuitry of the
l~ Spatial Decoder and the Temporal Decoder. For example, under
one or more compression standards, the compression ratio of
the standard is achieved by varying the number of bits that
it uses to code the pictures of a picture. The number of
bits can vary by a wide margin. Specifically, this means
that the length of a bitstream used to encode a referenced
picture of a picture might be identified as being one unit
long, another picture might be a number of units long, while
still a third picture could be a fraction of that unit.
None of the existing standards (MPEG 1.2, JPEG, H.261)
define a way of ending a picture, the implication being that
when the next picture starts, the current one has finished.
Additionally, the standards (H.261 specifically) allow
incomplete pictures to be generated by the encoder.
In accordance with the present invention, there is
provided a way of indicating the end of a picture by using
one of its tokens: PICTURE_END. The still encoded picture
data leaving the Start Code Detector consists of pictures
starting with a PICTURE_START token and ending with a
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PICTURE END token, but still of widely varying length. There
may be other infor~ation transmitted here (between the first
and second picture), but it is known that the first picture
has fini~hed.
The data stream at the output of the Spatial Decoder
consists of pictures, still with picture-starts and picture-
ends, of the same length (number of bits) for a given
sequence. The length of time between a picture-start and a
picture-end may vary.
The Video Formatter takes these pictures of non-uniform
time and displays them on a screen at a fixed picture rate
determined by the type of display being driven. Different
display rates are used throughout the world, e.g. PAL-NTSC
television standards. This is accomplished by selectively
dropping or repeating pictures in a manner which is unique.
Ordinary "frame rate converters," e.g. 2-3 pulldown, operate
with a fixed input picture rate, whereas the Video Formatter
can handle a variable input picture rate.
6. RFCONFIG~RABLE PROCF88ING 8TA¢E
Referring again to Figure 10, the reconfigurable
processing stage (RPS) comprises a token decode circuit 33
which is employed to receive the tokens coming from a two
wire interface 37 and input latches 34. The output of the
token decode circuit 33 is applied to a processing unit 36
over the two-wire interface 37 and an action identification
circuit 39. The processing unit 36 is suitable for
processing data under the control of the action
identification circuit 39. After the processing is
completed, the processing unit 36 connects such completed
signals to the output, two-wire interface bus 40 through
output latches 41.
The action identification decode circuit 39 has an
input from the token decode circuit 33 over the two-wire
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~ 104
interface bus 40 and/or from memory circuits 43 and 44 over
two-wire interface bus 46. The tokens from the token decode
circuit 33 are applied simultaneou61y to the action
identification circuit 39 and the processing unit 36. The
action identification function as well as the RPS i8
described in further detail by tables and figures in a
subsequent portion of this specification.
The functional block diagram in Figure 10
illustrates those stageC shown in Figures 11, 12 and 13 which
are not standard independent circuits. The data flows
through the token decode circuit 33, through the processing
unit 36 and onto the two-wire interface circuit 42 through
the output latches 41. If the Control Token is recognized by
the RPS, it is decoded in the token decode circuit 33 and
appropriate action will be taken. If it is not recognized,
it will be passed unchanged to the output two-wire interface
42 through the output circuit 41. The present invention
operates as a pipeline processor having a two-wire interface
for controlling the movement of control tokens through the
pipeline. This feature of the invention is described in
greater detail in the previously filed EP0 patent application
number 92306038.8.
In the present invention, the token decode circuit 33 is
employed for identifying whether the token presently entering
through the two-wire interface 42 is a DATA token or control
token. In the event that the token being examined by the
token decode circuit 33 iS recognized, it is exited to the
action identification circuit 39 with a proper index signal
or flag signal indicating that action is to be taken. At the
30 same time, the token decode circuit 33 provides a proper flag
or index signal to the processing unit 36 to alert it to the
presence of the token being handled by the action
identification circuit 39.
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105
Control tokens may also be prores~6~.
A more detailed description of the various type~ of
tokens usable in the present invention will be subsequently
described hereinafter. For the pur~O~~ of this portion of
the specification, it is sufficient to note that the address
carried by the control token is decoded in the decoder 33 and
is used to access registers contained within the action
identification circuit 39. When the token being examined is
a recognized control token, the action identification circuit
39 uses its reconfiguration state circuit for distributing
the control signals throughout the state machine. As
previously mentioned, this activates the state machine of the
action identification decoder 39, which then reconfigures
itself. For example, it may change coding standards. In
this way, the action identification circuit 39 decodes the
required action for handling the particular standard now
passing through the state machine shown with reference to
Figure 10.
Similarly, the processing unit 36 which is under
the control of the action identification circuit 39 is now
ready to process the information contained in the data fields
of the DATA token when it is appropriate for this to occur.
On many occasions, a control token arrives first,
reconfigures the action identification circuit 39 and is
immediately followed by a DATA token which is then processed
by the processing unit 36. The control token exits the
output latches circuit 41 over the output two-wire interface
42 immediately preceding the DATA token which has been
processed within the processing unit 36.
In the present invention, the action identification
circuit, 39, is a state machine holding history state. The
registers, 43 and 44 hold information that has been decoded
from the token decoder 33 and stored in these registers.
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106
Such registers can be either on-chip or-off chip as needed.
These plurality of state registers contain action information
connected to the action identification currently being
identified in the action identification circuit 39. This
action information has been stored from previously decoded
tokens and can affect the action that is selected. The
connection 40 is going straight from the token decode 33 to
the action identification block 39. This is intended to show
that the action can also be affecte~ by the token that is
currently being processed by the token decode circuit 33.
In general, there is shown token decoding and data
processing in accordance with the present invention. The
data processing is performed as configured by the action
identification circuit 39. The action is affected by a
~5 number of conditions and is affected by information generally
derived from a previously decoded token or, more
specifically, information stored from previously decoded
tokens in registers 43 and 44, the current token under
processing, and the state and history information that the
action identification unit 39 has itself acquired. A
distinction is thereby shown between Control tokens and DATA
tokens.
In any RPS, some tokens are viewed by that RPS unit as
being Control tokens in that they affect the operation of the
RPS presumably at some subsequent time. Another set of
tokens are viewed by the RPS as DATA tokens. Such DATA
tokens contain information which is processed by the RPS in
a way that is determined by the design of the particular
circuitry, the tokens that have been previously decoded and
the state of the action identification circuit 39. Although
a particular RPS identifies a certain set of tokens for that
particular RPS control and another set of tokens as data,
that is the view of that particular RPS. Another RPS can
have a different view of the same token. Some of the tokens
~1~5159
107
might-~ viewed by one RPS unit as DATA Tokens while another
RPS unit might decide that it is actually a Control Token.
For example, the quantization table information, as far as
the Huffman decoder and state machine is concerned, is data,
because it arrives on its input as coded data, it gets
formatted up into a series of 8 bit words, and they get
formed into a token called a quantization table token
(QUANT_TABLE) which goes down the processing pipeline. As
far as that machine is concerned, all of that was data; it
was handling data, transforming one sort of data into another
sort of data, which is clearly a function of the processing
performed by that portion of the machine. However, when that
information gets to the inverse quantizer, it stores the
information in that token a plurality of registers. In fact,
because there are 64 8-bit numbers and there are many
registers, in general, many registers may be present. This
information is viewed as control information, and then that
control information affects the processing that is done on
subsequent DATA tokens because it affects the number that you
multiply each data word. There is an example where one stage
viewed that token as being data and another stage viewed it
as being control.
Token data, in accordance with the invention is almost
universally viewed as being data through the machine. One of
the important aspects is that, in general, each stage of
circuitry that has a token decoder will be looking for a
certain set of tokens, and any tokens that it does not
recognize will be passed unaltered through the stage and down
the pipeline, so that subsequent stages downstream of the
current stage have the benefit of seeing those tokens and may
respond to them. This is an important feature, namely there
can be communication between blocks that are not adjacent to
one another using the token mechanism.
Another important feature of the invention is that each of
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108
the stages of circuitry has the proce~ing capability within
it to be able to perform the ne~sF-ry operations for each of
the st~n~rds, and the control, as to which operations are to
be performed at a given ti~e, come as tokens. There is one
processing element that differs between the different stages
to provide thi~ capability. In the state machine ROM of the
parser, there are three separate entirely different programs,
one for each of the standards that are dealt with. Which
program is executed depends upon a CODING STANDARD token. In
otherwords, each of these three programs has within it the
ability to handle both decoding and the CODING_STANDARD
standard token. When each of these programs sees which
coding standard, is to be decoded next, they literally jump
to the start address in the microcode ROM for that particular
program. This is how stages deal with multi-standardness.
Two things are affected by the different standards.
First, it affects what pattern of bits in the bitstream are
recognized as a start-code or a marker code in order to
reconfigure the shift register to detect the length of the
start marker code. Second, there is a piece of information
in the microcode that denotes what that start or marker code
means. Recall that the coding of bits differs between the
three standards. Accordingly, the microcode looks up in a
table, specific to that compressor standard, something that
is independent of the standard, i.e., a type of token that
represents the incoming codes. This token is typically
independent of the standard since in most cases, each of the
various standards provide a certain code that will produce
it.
The inverse quantizer 79 has a mathematical
capability. The quantizer multiplies and adds, and has the
ability to do all three compression standards which are
configured by parameters. For example, a flag bit in the ROM
in control tells the inverse quantizer whether or not to add
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a constant, K. Another flag tells the inver~e quantizer
whether to add another constant. The inverse quantizer
remembers in a register the CODING STANDARD token as it flows
by the quantizer. When DATA tokens pass thereafter, the
S inverse quantizer remembers what the ~tandard is and it looks
up the parameters that it needs to ~pply to the processing
elements in order to perform a proper operation. For
example, the inverse quantizer will look up whether K is set
to 0, or whether it is set to 1 for a particular compression
standard, and will apply that to its processing circuitry.
In a similar sense the Huffman decoder 56 ha~ a number
of tables within it, some for JPEG, some for MPEG and some
for H.261. The majority of those tables, in fact, will
service more than one of those compression standards. Which
tables are used depends on the syntax of the standard. The
Huffman decoder works by receiving a command from the state
machine which tells it which of the tables to use.
Accordingly, the Huffman decoder does not itself directly
have a piece of state going into it, which is remembered and
which says what coding it is performing. Rather, it is the
combination of the parser state machine and Huffman decoder
together that contain information within them.
Regarding the Spatial Decoder of the present
invention, the address generation is modified and is similar
to that shown in Figure 10, in that a number of pieces of
information are decoded from tokens, such as the coding
standard. The coding standard and additional information as
well, is recorded in the registers and that affects the
progress of the address generator state machine as it steps
through and counts the macroblocks in the system, one after
the other. The last stage would be the prediction filter 17g
(Figure 17) which operates in one of two modes, either H.261
or MPEG and are easily identified.
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110
7. MU~ STANDARD CODING
The system of the present invention also provides a
combination of the standard-independent indices generation
circuits, which are strategically placed throughout the
system in combination with the token decode circuits. For
example, the system is employed for specifically decoding
either the H.261 video standard, or the MPEG video standard
or the JPEG video standard. These three compression coding
standards specify similar processes to be done on the
arriving data, but the structure of the datastreams is
different. As previously discussed, it is one of the
functions of the Start Code Detector to detect MPEG start-
codes, H.261 start-codes, and JPEG marker codes, and convert
them all into a form, i.e., a control token which includes a
token stream embodying the current coding standard. The
control tokens are passed through the pipeline processor, and
are used, i.e., decoded, in the state machines to which they
are relevant, and are passed through other state machines to
which the tokens are not relevant. In this regard, the DATA
Tokens are treated in the same fashion, insofar as they are
processed only in the state machines that are configurable by
'he control tokens into processing such DATA Tokens. In the
remaining state machines, they pass through unchanged.
More specifically, a control token in accordance with
the present invention, can consist of more than one word in
the token. In that case, a bit known as the extension bit is
set specifying the use of additional words in the token for
carrying additional information. Certain of these additional
control bits contain indices indicating information for use
1n corresponding state machines to create a set of standard-
independent indices signals. The remaining portions of the
token are used to indicate and identify the internal
processing control function which is standard for all of the
datastreams passing through the pipeline processor. In one
- 21~515~
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foro of the invention, the token extension is used to carry
the current coding sta~-rd which i8 d~co~ by the relative
token decode circuits distributed throughout the machine, and
is used to reconfigure the action identification circuit 39
of stages throughout the machine wherever it is appropriate
to operate under a new coding standard. Additionally, the
token decode circuit can indicate whether a control token is
related to one of the selected standard~ which the circuit
was designed to handle.
More specifically, an MPEG start code and a JPEG marker
are followed by an 8 bit value. The H.261 start code is
followed by a 4 bit value. In this context, the Start Code
Detector 51, by detecting either an MPEG start-code or a JPEG
marker, indicates that the following 8 bits contain the value
lS associated with the start-code. Independently, it can then
create a signal which indicates that it is either an MPEG
start code or a JPEG marker and not an H.261 start code. In
this first instance, the 8 bit value is entered into a decode
circuit, part of which creates a signal indicating the index
and flag which is used within the current circuit for
handling the tokens passing through the circuit. This is
also used to insert portions of the control token which will
be looked at thereafter to determine which standard is being
handled. In this sense, the control token contains a portion
indicating that it is related to an MPEG standard, as well as
a portion which indicates what type of operation should be
performed on the accompanying data. As previously discussed,
this information is utilized in the system to reconfigure the
processing stage used to perform the function required by the
various standards created for that purpose.
For example, with reference to the H.261 start code, it
is associated with a 4 bit value which follows immediately
after the start code. The Start Code Detector passes this
value into the token generator state machine. The value is
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applied to an 8 bit decoder which produces a 3 bit start
number. The start number is employed to identify the
picture-start of a picture number as indicated by the value.
The system also includes a multi-stage parallel
processing pipeline operating under the principles of the
two-wire interface previously described. Each of the stages
comprises a machine generally taking the form illustrated in
Figure 10. The token decode circuit 33 is employed to direct
the token presently entering the state machine into the
action identification circuit 39 or the processing unit 36,
as appropriate. The processing unit has been previously
reconfigured by the next previous control token into the form
needed for handling the current coding standard, which is now
entering the processing stage and carried by the next DATA
token. Further, in accordance with this aspect of the
invention, the succeeding state machines in the processing
pipeline can be functioning under one coding standard, i.e.,
H.261, while a previous stage can be operating under a
separate standard, such as MPEG. The same two-wire interface
is used for carrying both the control tokens and the DATA
Tokens.
The system of the present invention also utilizes
control tokens required to decode a number of coding
standards with a fixed number of reconfigurable processing
stages. More specifically, the PICTURE END control token is
employed because it is important to have an indication of
when a picture actually ends. Accordingly, in designing a
multi-standard machine, it is necessary to create additional
control tokens within the multi-standard pipeline processing
machine which will then indicate which one of the standard
decoding techniques to use. Such a control token is the
PICTURE END token. This PICTURE END token is used to
indicate that the current picture has finished, to force the
buffers to be flushed, and to push the current picture
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through the decoder to the di~play.
8. ~nLTI-8TANDARD P~OC~ G CIRC~IT - ~ECOND
~ODE OF OP~RATION
A compression standard-dependent circuit, in the form of
the previously described Start Code Detector, is suitably
interconnected to a compression standard-independent circuit
over an appropriate bus. The standard-dependent circuit is
connected to a combination dependent-independent circuit over
the same bus and an additional bus. The standard-independent
circuit applies additional input to the ~t~ard dependent-
independent circuit, while the latter provides information
back to the standard-independent circuit. Information from
the standard-independent circuit is applied to the output
over another suitable bus. Table 600 illustrates that the
multiple standards applied as the input to the standard-
dependent Start Code Detector 51 include certain bit streams
which have standard-dependent meanings within each encoded
bit stream.
9. 8TART-CODE D~.~.O~
As previously indicated the Start Code Detector, in
accordance with the present invention, is capable of taking
MPEG, JPEG and H.261 bit streams and generating from them a
sequence of proprietary tokens which are meaningful to the
rest of the decoder. As an example of how multi-standard
decoding is achieved, the MPEG (1 and 2) picture_start_code,
the H.261 picture_start_code and the JPEG start_of_scan (SoS)
marker are treated as equivalent by the Start Code Detector,
and all will generate an internal PICTURE_START token. In a
similar way, the MPEG sequence_start_code and the JPEG SOI
(start of image) marker both generate a machine
sequence start token. The H.261 standard, however, has no
equivalent start code. Accordingly, the Start Code Detector,
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114
in res~nse to the first H.261 picture_start_code, will
generate a sequence_start token.
None of the above described images are directly used
other than in the SCD. Rather, a machine PICTURE_START
token, for example, has been deemed to be equivalent to the
PICTURE_START images contained in the bit stream.
Furthermore, it must be borne in mind that the machine
PICTURE_START by itself, is not a direct image of the
PICTURE_START in the standard. Rather, it is a control token
which is used in combination with other control tokens to
provide standard-independent decoding which emulates the
operation of the images in each of the compression coding
standards. The combination of control tokens in combination
with the reconfiguration of circuits, in accordance with the
information carried by control tokens, is unique in and of
itself, as well as in further combination with indices and/or
flags generated by the token decode circuit portion of a
respective state machine. A typical reconfigurable state
machine will be described subsequently.
Referring again to Table 600, there are shown the names
of a group of standard images in the left column. In the
right column there are shown the machine dependent control
tokens used in the emulation of the standard encoded signal
which is present or not used in the standard image.
2~ With reference to Table 600, it can be seen that a
machine sequence_start signal is generated by the Start Code
Detector, as previously described, when it decodes any one of
the standard signals indicated in Table 600. The Start Code
Detector creates sequence_start, group_start, sequence_end,
'0 slice_start, user-data, extra-data and PICTURE_START tokens
for application to the two-wire interface which is used
throughout the system. Each of the stages which operate in
conjunction with these control tokens are configured by the
contents of the tokens, or are configured by indices created
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by con~ents of the tokens, and are prepared to handle data
which is expected to be received when the picture DATA Token
arrives at that station.
As previously described, one of the compression
standards, such as H.261, does not have a sequence_start
image in its data stream, nor does it have a PICTURE_E~D
image in its data stream. The Start Code Detector indicates
the PICTURE_END point in the incoming bit stream and creates
a PICTURE_END token. In this regard, the system of the
present invention is intended to carry data words that are
fully packed to contain a bit of information in each of the
register positions selected for use in the practice of the
present invention. To this end, lS bits have been selected
as the number of bits which are passed between two start
codes. Of course, it will be appreciated by one of ordinary
skill in the art, that a selection can be made to include
either greater or fewer than 15 bits. In other words, all 15
bits of a data word being passed from the Start Code Detector
into the DRAM interface are required for proper operation.
Accordingly, the Start Code Detector creates extra bits,
called padding, which it inserts into the last word of a DATA
Token. For purposes of illustration 15 data bits has been
selected.
To perform the Padding operation, in accordance with the
present invention, binary O followed by a number of binary
l's are automatically inserted to complete the 15 bit data
word. This data is then passed through the coded data buffer
and presented to the Huffman decoder, which removes the
padding. Thus, an arbitrary number of bits can be passed
through a buffer of fixed size and width.
In one embodiment, a slice_start control token is used
to identify a slice of the picture. A slice_start control
token is employed to segment the picture into smaller
regions. The size of the region is chosen by the encoder,
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and th~ ~tart Code Detector identifies this unique pattern of
the slice_start code in order for the machine-dependent state
stages, located downstream from the Start Code Detector, to
segment the picture being received into smaller regions. The
size of the region is chosen by the encoder, recognized by
the Start Code Detector and used by the recombination
circuitry and control tokens to decompress the encoded
picture. The slice_start_codes are principally used for
error recovery.
The start codes provide a unique method of starting up
the decoder, and this will subsequently be described in
further detail. There are a number of advantages in placing
the Start Code Detector before the coded data buffer, as
opposed to placing the Start Code Detector after the coded
data buffer and before the Huffman decoder and video
demultiplexor. Locating the Start Code Detector before the
first buffer allows it to 1) assemble the tokens, 2) decode
the standard control signals, such as start codes, 3) pad the
bitstream before the data goes into the buffer, and 4) create
the proper sequence of control tokens to empty the buffers,
pushing the available data from the buffers into the Huffman
Decoder.
Most of the control token output by the Start Code
Detector directly reflect syntactic elements of the various
picture and video coding standards. The Start Code Detector
converts the syntactic elements into control tokens. In
addition to these natural tokens, some unique and/or machine-
dependent tokens are generated. The unique tokens include
those tokens which have been specifically designed for use
with the system of the present invention which are unique in
and of themselves, and are employed for aiding in the multi-
standard nature of the present invention. Examples of such
unique tokens include PICTURE_END and CODING_STANDARD-
Tokens are also introduced to remove some of the
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117
syntaetic differences between the coding standards and tofunction in co-operation with the error conditions. The
automatic token generation is done after the serial analysis
of the standard-dependent data. Therefore, the Spatial
Decoder responds equally to tokens that have been supplied
directly to the lnput of the Spatial Decoder, i.e. the SCD,
as well as to tokens that have been generated following the
detection of the start-codes in the coded data. A sequence
of extra tokens is inserted into the two- wire interface in
order to control the multi-standard nature of the present
invention.
The MPEG and H.261 coded video streams contain standard
dependent, non-data, identifiable bit patterns, one of which
is hereinafter called a start image and/or standard-dependent
code. A similar function is served in JPEG, by marker codes.
These start/marker codes identify significant parts of the
syntax of the coded datastream. The analysis of start/marker
codes performed by the Start Code Detector is the first stage
in parsing the coded data.
The start/marker code patterns are designed so that they
can be identified without decoding the entire bit stream.
Thus, they can be used, in accordance with the present
invention, to assist with error recovery and decoder start-
up. The Start Code Detector provides facilities to detect
errors in the coded data construction and to assist the
start-up of the decoder. The error detection capability of
the Start Code Detector will subsequently be discussed in
further detail, as will the process of starting up of the
decoder.
The aforementioned description has been concerned
primarilty with the characteristics of the machine-dependent
bit stream and its relationship with the addressing
characteristics of the present invention. The followin~
description is of the bit stream characteristiCS of the
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standard-dependent coded data with reference to the Start
Code Detector.
Each of the standard compression encoding systems
employs a unique start code configuration or image which has
been selected to identify that particular compression
specification. Each of the start codes also carries with it
a start code value. The start code value is employed to
identify within the language of the standard the type of
operation that the start code is associated with. In the
multi-standard decoder of the present invention, the
compatibility is based upon the control token and DATA token
configuration as previously described. Index signals,
including flag signals, are circuit-generated within each
state machine, and are described hereinafter as appropriate.
The start and/or marker codes contained in the
standards, as well as other standard words as opposed to data
words, are sometimes identified as images to avoid confusion
with the use of code and/or machine-dependent codes to refer
to the contents of control and/or DATA tokens used in the
machine. Also, the term start code is often used as a
generic term to refer to JPEG marker codes as well as MPEG
and H.261 start codes. Marker codes and start codes serve
the same purpose. Also, the term "flush" is used both to
refer to the FLUSH token, and as a verb, for example when
2~ referring to flushing the Start Code Detector shift registers
(including the signal "flushed"). To avoid confusion, the
FLUSH token is always written in upper case. All other uses
of the term (verb or noun) are in lower case.
The standard-dependent coded input picture input stream
~G comprises data and start images of varying lengths. The
start images carry with them a value telling the user what
operation is to be performed on the data which immediatelY
follows according to the standard. However, in the multi-
standard pipeline processing system of the present invention~
21~5159
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where compatibility is required for multiple standards, the
system ha~ been optimized for handling all functions in all
standards. Accordingly, in many situations, unigue start
control tokens must be created which are compatible not only
with the values contained in the v~lues of the encoded signal
standard image, but which are also capable of controlling the
various stages to emulate the operation ~of the standard as
represented by specified parameters for each standard which
are well known in the art. All such ~tAn~Ards are
incorporated by reference into this specification.
It is important to understand the relationship between
tokens which, alone or in combination with other control
tokens, emulate the nondata information contained in the
standard bit stream. A separate set of index signals,
including flag signals, are generated by each state machine
to handle some of the processing within that state machine.
Values carried in the standards can be used to access machine
dependent control signals to emulate the handling of the
standard data and non-data signals. For example, the
slice_start token is a two word token, and it is then entered
onto the two wire interface as previously described.
The data input to the system of the present invention
may be a data source from any suitable data source such as
disk, tape, etc., the data source providing 8 bit data to the
first functional stage in the Spatial Decoder, the Start Code
Detector 51 (Figure 11). The Start Code Detector includes
three shift registers; the first shift register is 8 bits
wide, the next is 24 bits wide, and the next is 15 bits wide.
Each of the registers is part of the two-wire interface. The
data from the data source is loaded into the first register
as a single 8 bit byte during one timing cycle. Thereafter,
the contents of the first shift register is shifted one bit
at a time into the decode (second) shift register. After 24
cycles, the 24 bit register is full.
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~ 120
Every 8 cycle~, the 8 bit bytes are loaded into the
first shift register. Each byte i~ loaded into the value
shift register 221 (Figure 20), and 8 additional cycles are
used to empty it and load the shift register 231. Eight
cycles are used to empty it, so after three of those
operations or 24 cycles, there are still three bytes in the
24 bit register. The value decode shift register 230 is
still empty.
Assuming that there is now a PIeTURE START word in the
24 bit shift register, the detect cycle recognizes the
PICTURE_START code pattern and provides a start signal as its
output. Once the detector has detected a start, the byte
following it is the value associated with that start code,
and this is currently sitting in the value register 221.
Since the contents of the detect shift register has been
identified as a start code, its contents must be removed from
the two wire interface to ensure that no further processing
takes place using these 3 bytes. The decode register is
emptied, and the value decode shift register 230 waits for
the value to be shifted all the way over to such register.
The contents now of the low order bit positions of the
value decode shift register contains a value associated with
the PICTURE START. The Spatial Decoder equivalent to the
standard PICTURE START signal is referred to as the SD
PICTURE START signal. The SD PICTURE START signal itself is
going to now be contained in the token header, and the value
is going to be contained in the extension word to the token
header.
lo. To~N8
In the practice of the present invention, a token is a
universal adaptation unit in the form of an interactive
interfacing messenger package for control and/or data
functions and is adapted for use with a reconfigurable
~` 2145159
121
proce~sing stage (RPS) which is a stage, which in response to
a recognized token, reconfigures itself to perform various
operations.
Tokens may be either position dependent or position
independent upon the processing stages for performance of
various functions. Tokens may also be metamorphic in that
they can be altered by a processing stage and then passed
down the pipeline for performance of further functions.
Tokens may interact with all or less than all of the stages
and in this regard may interact with adjacent and/or non-
adjacent stages. Tokens may be position dependent for some
functions and position independent for other functions, and
the specific interaction with a stage may be conditioned by
the previous processing history of a stage.
A PICTURE_END token is a way of signalling the end of a
picture in a multi-standard decoder.
A multi-standard token is a way of mapping MPEG, JPEG
and H.261 data streams onto a single decoder using a mixture
of standard dependent and standard independent hardware and
control tokens.
A SEARCH_MODE token is a technique for searching MPEG,
JPEG and H.261 data streams which allows random access and
enhanced error recovery.
. A STOP_AFTER_PICTURE token is a method of achieving a
clear end to decoding which signals the end of a picture and
clears the decoder pipeline, i.e., channel change.
Furthermore, padding a token is a way of passing an
arbitrary number of bits through a fixed size, fixed width
buffer.
.0 The present invention is directed to a pipeline
processing system which has a variable configuration which
uses tokens and a two-wire system. The use of control tokens
and DATA Tokens in combination with a two-wire syster,
facilitates a multi-standard system capable of having
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122
exten~ed operating capabilities as compared with those
systems which do not use control tokens.
The control tokens are generated by circuitry within the
decoder processor and emulate the operation of a number of
different type standard-dependent signals passing into the
serial pipeline processor for handling. The technique used
is to study all the parameters of the multi-standards that
are selected for processing by the serial processor and
noting 1) their similarities, 2) their dissimilarities, 3)
lo their needs and requirements and 4) selecting the correct
token function to effectively process all of the standard
signals sent into the serial processor. The functions of the
tokens are to emulate the standards. A control token
function is used partially as an emulation/translation
between the standard dependent signals and as an element to
transmit control information through the pipeline processor.
In prior art system, a dedicated machine is designed
according to well-known techniques to identify the standard
and then set up dedicated circuitry by way of microprocessor
interfaces. Signals from the microprocessor are used to
control the flow of data through the dedicated downstream
components. The selection, timing and organization of this
decompression function is under the control of fixed logic
circuitry as assisted by signals coming from the
2~ microprocessor.
In contrast, the system of the present invention
configures the downstream functional stages under the control
of the control tokens. An option is provided for obtaining
needed and/or alternative control from the MPU.
The tokens provide and make a sensible format for
communicating information through the decompression circuit
pipeline processor. In the design selected hereinafter ar.d
used in the preferred embodiment, each word of a token is ~
minlmum of 8 bits wide, and a single token can extend over
'~145159
123
one or more words. The width of the token is changeable and
can be selected as any number of bits. An extension bit
indicates whether a token is extended beyond the current
word, i.e., if it is set to binary one in all words of a
token, except the last word of a token. If the first word of
a token has an extension bit of zero, this indicates that the
token is only one word long.
Each token is identified by an address field that starts
at bit 7 of the first word of the token. The address field
is variable in length and can potentially extend over
multiple words. In a preferred embodiment, the address is no
longer than 8 bits long. However, this is not a limitation
on the invention, but on the magnitude of the processing
steps elected to be accomplished by use of these tokens. It
is to be noted under the extension bit identification label
that the extension bit in words 1 and 2 is a 1, signifying
that additional words will be coming thereafter. The
extension bit in word 3 is a zero, therefore indicating the
end of that token.
The token is also capable of variable bit length. For
example, there are 9 bits in the token word plus the
extension bit for a total of 10 bits. In the design of the
present invention, output buses are of variable width. The
output from the Spatial Decoder is 9 bits wide, or 10 bits
2~ wide when the extension bit is included. In a preferred
embodiment, the only token that takes advantage of these
extra bits is the DATA token; all other tokens ignore this
extra bit. It should be understood that this is not a
limitation, but only an implementation.
Through the use of the DATA token and control token
configuration, it is possible to vary the length of the data
being carried by these DATA tokens in the sense of the number
of bits in one word. For example, it has been discussed that
data bits in word of a DATA Token can be combined with the
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124
data bits in another word of the same DATA token to form an
11 bit or 10 bit address for use in accessing the random
access memories used throughout this serial decompression
processor. This provides an additional degree of variability
that facilitates a broad range of versatility.
As previously described, the DATA token carries data
from one processing stage to the next. Consequently, the
characteristics of this token change as it passes through the
decoder. For example, at the input to the Spatial Decoder,
DATA Tokens carry bit serial coded video data packed into 8
bit words. Here, there is no limit to the length of each
token. However, to illustrate the versatility of this aspect
of the invention (at the output of the Spatial Decoder
circuit), each DATA Token carries exactly 64 words and each
word is 9 bits wide. More specifically, the standard
encoding signal allows for different length messages to
encode different intensities and details of pictures. The
first picture of a group normally carries the longest number
of data bits because it needs to provide the most information
to the processing unit so that it can start the decompression
with as much information as possible. Words which follow
later are typically shorter in length because they contain
the difference signals comparing the first word with
reference to the second position on the scan information
field.
The words are interspersed with each other, as required
by the standard encoding system, so that variable amounts of
data are provided into the input of the Spatial Decoder.
However, after the Spatial Decoder has functioned, the
information is provided at its output at a picture format
rate suitable for display on a screen. The output rate in
terms of time of the spatial decoder may vary in order to
interface with various display systems throughout the world,
such as NTSC, PAL and SECAM. The video formatter convertS
214~159
- 125
this variable picture rate to a constant picture rate
suitable for display. However, the picture data is still
carried by DATA tokens consisting of 64 words.
~1. DRA~ I~T~RFAC~
A single high performance, configurable DRAM interface
is used on each of the 3 decoder chips. In general, the DRAM
interface on each chip is substantially the same; however,
the interfaces differ from one to another in how they handle
channel priorities. This interface is designed to directly
drive the external DRAMs used by the Spatial Decoder, the
Temporal Decoder and the Video Formatter. Typically, no
external logic, buffers or components will be required to
connect the DRAM interface to the DRAMs in those systems.
In accordance with the present invention, the interface is
configurable in two ways:
1. The detailed timing of the interface can be
configured to accommodate a variety of different
DRAM types.
2. The width of the data interface to the DRAM can
be configured to provide a cost/performance trade
off for different applications.
In general, the DRAM interface is a standard-independent
block implemented on each of the three chips in the system.
Again, these are the Spatial Decoder, Temporal Decoder and
video formatter. Referring again to Figures 11, 12 and 13,
these figures show block diagrams that depict the
relationship between the DRAM interface, and the remaining
blocks of the Spatial Decoder, Temporal Decoder and video
formatter, respectively. On each chip, the DRAM interface
connects the chip to an external DRAM. External DRAM is used
because, at present, it is not practical to fabricate on chip
the relatively large amount of DRAM needed. Note: each chip
has its own external DRAM and its own DRAM interface.
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126
Furthermore, while the DRAM interface is compression
standard-independent, it still must be configured to
implement each of the multiple standards, H.261, JPEG and
MPEG. How the DRAM interface is reconfigured for multi-
standard operation will be subsequently further describedherein.
Accordingly, to understand the operation of the DRAM
interface requires an understanding of the relationship
between the DRAM interface and the address generator, and how
the two communicate using the two wire interface.
In general, as its name implies, the address generator
generates the addresses the DRAM interface needs in order to
address the DRAM (e.g., to read from or to write to a
particular address in DRAM). With a two-wire interface,
reading and writing only occurs when the DRAM interface has
both data (from preceding stages in the pipeline), and a
valid address (from address generator). The use of a
separate address generator simplifies the construction of
both the address generator and the DRAM interface, as
discussed further below.
In the present invention, the DRAM interface can operate
from a clock which is asynchronous to both the address
generator and to the clocks of the stages through which data
is passed. Special techniques have been used to handle this
asynchronous nature of the operation.
Data is typically transferred between the DRAM interface
and the rest of the chip in blocks of 64 bytes (the only
exception being prediction data in the Temporal Decoder).
~ransfers take place by means of a device known as a "swing
~o buffer~. This is essentially a pair of RAMs operated in a
double-buffered configuration, with the DRAM interface
fllling or emptying one RAM while another part of the chip
empties or fills the other RAM. A separate bus which carries
an address from an address generator is associated with each
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swing buffer.
In the present invention, each of the chips has four swing
buffers, but the function of these swing buffers is different
in each case. In the spatial decoder, one swing buffer is
used to transfer coded data to the DRAM, another to read
coded data from the DRAM, the third to transfer tokenized
data to the DRAM and the fourth to read tokenized data from
the DRAM. In the Temporal Decoder, however, one swing buffer
is used to write intra or predicted picture data to the DRAM,
the second to read intra or predicted data from the DRAM and
the other two are used to read forward and backward
prediction data. In the video formatter, one swing buffer is
used to transfer data to the DRAM and the other three are
used to read data from the DRAM, one for each of luminance
(Y) and the red and blue color difference data (Cr and Cb,
respectively).
The following section describes the operation of a
hypothetical DRAM interface which has one write swing buffer
and one read swing buffer. Essentially, this is the same as
the operation of the Spatial Decoder's DRAM interface. The
operation is illustrated in Figure 23.
Figure 23 illustrates that the control interfaces
between the address generator 301, the DRAM interface 302,
and the remaining stages of the chip which pass data are all
two wire interfaces. The address generator 301 may either
generate addresses as the result of receiving control tokens,
or it may merely generate a fixed sequence of addresses
(e.g., for the FIFO buffers of the Spatial Decoder). The
DRAM interface treats the two wire interfaces associated with
the address generator 301 in a special way. Instead of
keeping the accept line high when it is ready to receive an
address, it waits for the address generator to supply a valid
address, processes that address and then sets the accept line
high for one clock period. Thus, it implements a
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request/acknowledge (REQ/ACK) protocol.
A unique feature of the DRAM interface 302 is its
ability to communicate independently with the address
generator 301 and with the stages that provide or accept the
data. For example, the address generator may generate an
address associated with the data in the write swing buffer
(Figure 24), but no action will be taken until the write
swing buffer signals that there is a block of data ready to
be written to the external DRAM. Similarly, the write swing
buffer may contain a block of data which is ready to be
written to the external DRAM, but no action is taken until an
address is supplied on the appropriate bus from the address
generator 301. Further, once one of the RAMs in the write
swing buffer has been filled with data, the other may be
completely filled and "swung" to the DRAM interface side
before the data input is stalled (the two-wire interface
accept signal set low).
In understanding the operation of the DRAM interface 302
of the present invention, it is important to note that in a
properly configured system, the DRAM interface will be able
to transfer data between the swing buffers and the external
DRAM 303 at least as fast as the sum of all the average data
rates between the swing buffers and the rest of the chip.
Each DRAM interface 302 determines which swing buffer it
will service next. In general, this will either be a "round
robin" (i.e., the next serviced swing buffer is the next
available swing buffer which has least recently had a turn),
or a priority encoder, (i.e., in which some swing buffers
have a higher priority than others). In both cases, an
additional request will come from a refresh request generator
which has a higher priority than all the other requests. The
refresh request is generated from a refresh counter which can
be programmed via the microprocessor interface.
Referring now to Figure 24, there is shown a block
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129
diagram of a write swing buffer. The write swing buffer
interface includes two blocks of RAM, RAMl 311 and RAM2 312.
As discus6ed further herein, data is written into RAMl 311
and RAM2 312 from the previous stage, under the control of
the write address 313 and control 314. From RAM1 311 and
RAM2 312, the data is written into DRAM 515. When writing
data into DRAM 315, the DRAM row addres6 is provided by the
address generator, and the column address is provided by the
write address and control, as described further herein. In
operation, valid data is presented at the input 316 (data
in). Typically, the cata is received from the previous
stage. As each piece of data is accepted by the DRAM
interface, it is written into RAMl 311 and the write address
control increments the RAM1 address to allow the next piece
of data to be written into RAMl. Data continues to be
written into RAMl 311 until either there is no more data, or
RAMl is full. When RAMl 311 is full, the input side gives up
control and sends a signal to the read side to indicate that
RAMl is now ready to be read. This signal passes between two
asynchronous clock regimes and, therefore, passes through
three synchronizing flip flops.
Provided RAM2 312 is empty, the next item of data to
arrive on the input side is written into RAM2. Otherwise,
this occurs when RAM2 312 has emptied. When the round robin
or priority encoder (depending on which is used by the
particular chip) indicates that it is now the turn of this
swing buffer to be read, the DRAM interface reads the
contents of RAMl 311 and writes them to the external DRAM
315. A signal is then sent back across the asynchronous
interface, to indicate that RAMl 311 is now ready to be
filled again.
If the DRAM interface empties RAMl 311 and "swings" it
before the input side has filled RAM2 312, then data can be
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130
acce~ted by the swing buffer sontinually. Otherwise, when
RAM2 is filled, the swing buffer will set its accept single
low until RAM1 has been "swung" back for use by the input
side.
The operation of a read swing buffer, in accordance with
the present invention, is similar, but with the input and
output data busses reversed.
The DRAM interface of the present invention is designed
to maximize the available memory bandwidth. Each 8x8 block
of data is stored in the same DRAM page. In this way, full
use can be made of DRAM fast page access modes, where one row
address is supplied followed by many column addresses. In
particular, row addresses are supplied by the address
generator, while column addresses are supplied by the DRAM
interface, as discussed further below.
In addition, the facility is provided to allow the data
bus to the external DRAM to be 8, 16 or 32 bits wide.
Accordingly, the amount of DRAM used can be matched to the
size and bandwidth requirements of the particular
application.
In this example (which is exactly how the DRAM interface
on the Spatial Decoder works) the address generator provides
the DRAM interface with block addresses for each of the read
and write swing buffers. This address is used as the row
address for the DRAM. The six bits of column address are
supplied by the DRAM interface itself, and these bits are
also used as the address for the swing buffer RAM. The data
bus to the swing buffers is 32 bits wide. Hence, if the bus
width to the external DRAM is less than 32 bits, two or four
external DRAM accesses must be made before the next word is
read from a write swing buffer or the next word is written to
a read swing buffer (read and write refer to the direction of
transfer relative to the external DRAM).
The situation is more complex in the case of the
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Temporal nE:_A~r and the Video Formatter. The Temporal
~ er's addre~ing is more complex because of its
predictive aspects as discussed further in this section. The
video formatter'~ addressing is more complex because of
multiple video output st~ rd a~pects, as discussed further
in the ~ection~ relating to the video formatter.
As mentioned previously, the Temporal Decoder has four
swing buffers: two are used to read and write decoded intra
and predicted (I and P) picture data. These operate as
described above. The other two are used to receive
prediction data. These buffers are more interesting.
In general, prediction data will be offset from the
position of the block being processed as specified in the
motion vectors in x and y. Thus, the block of data to be
retrieved will not generally correspond to the block
boundaries of the data as it was encoded (and written into
the DRAM). This is illustrated in Figure 25, where the
shaded area represents the block that is being formed whereas
the dotted outline represents the block from which it is
being predicted. The address generator converts the address
specified by the motion vectors to a block offset (a whole
number of blocks), as shown by the big arrow, and a pixel
offset, as shown by the little arrow.
In the address generator, the frame pointer, base block
address and vector offset are added to form the address of
the block to be retrieved from the DRAM. If the pixel offset
is zero, only one request is generated. If there is an
offset in either the x or y dimension then two requests are
generated, i.e., the original block address and the one
immediately below. With an offset in both x and y, four
requests are generated. For each block which is to be
retrieved, the address generator calculates start and stop
addresses which is best illustrated by an example.
Consider a pixel offset of (1,1), as illustrated by the
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shaded area in Figure 26. The address generator makes four
requests, labelled A through D in the Figure. The problem to
be solved is how to provide the required sequence of row
addresses quickly. The solution is to use "start/stop"
technology, and this is described below.
Consider block A in Figure 26. Reading must start at
position (1,1) and end at position (7,7). Assume for the
moment that one byte is being read at a time (i.e., an 8 bit
DRAM interface). The x value in the-co-ordinate pair forms
the three LSBs of the address, the y value the three MSB.
The x and y start values are both 1, providing the address,
9. Data is read from this address and the x value is
incremented. The process is repeated until the x value
reaches its stop value, at which point, the y value is
incremented by 1 and the x start value is reloaded, giving an
address of 17. As each byte of data is read, the x value is
again incremented until it reaches its stop value. The
process is repeated until both x and y values have reached
their stop values. Thus, the address sequence of 9, 10, 11,
12, 13, 14, 15, 17... , 23, 25, ... ,31, 33,... ,... ,57,... ,63
is generated.
In a similar manner, the start and stop co-ordinates for
block B are: (1,0) and (7,0), for block C: (0,1) and (0,7),
and for block D: (0,0) and (0,0).
The next issue is where this data should be written.
Clearly, looking at block A, the data read from address 9
should be written to address 0 in the swing buffer, while the
data from address 10 should be written to address 1 in the
swing buffer, and so on. Similarly, the data read from
address 8 in block B should be written to address 15 in the
swing buffer and the data from address 16 should be written
to address 15 in the swing buffer. This function turns out
to have a very simple implementation, as outlined below.
Consider block A. At the start of reading, the swing
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buffer address register i8 loaded with the inver~e of the
~top value. The y inverse stop value forms the 3 MSBs and
the x inverse stop value foros the 3 LSB. In this case,
while the DRAM interface is reading address 9 in the external
DRAM, the swing buffer address is zero. The swing buffer
address register is then incremented as the external DRAM
address register is incremented, as consistent with proper
prediction addressing.
The discus~ion so far has centered on an 8 bit DRAM
interface. In the case of a 16 or 32 bit interface, a few
minor modifications must be made. First, the pixel offset
vector must be "clipped" so that it points to a 16 or 32 bit
boundary. In the example we have been using, for block A,
the first DRAM read will point to address o, and data in
addresses 0 through 3 will be read. Second, the unwanted
data must be discarded. This is performed by writing all the
data into the swing buffer (which must now be physically
larger than was necessary in the 8 bit case) and reading with
an offset. When performing MPEG half-pel interpolation, 9
bytes in x andtor y must be read from the DRAM interface. In
this case, the address generator provides the appropriate
start and stop addresses. Some additional logic in the DRAM
interface is used, but there is no fundamental change in the
way the DRAM interface operates.
The final point to note about the Temporal Decoder DRAM
interface of the present invention, is that additional
information must be provided to the prediction filters to
indicate what processing is required on the data. This
consists of the following:
a "last byte" signal indicating the last byte of a
transfer (of 64,72 or 81 bytes);
an H.261 flag;
a bidirectional prediction flag;
two bits to indicate the block~s dimensions (8 or 9 bytes
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in x and y); and
a two bit number to indicate the order of the blocks.
The last byte flag can be generated as the data is read
out of the swing buffer. The other signals are derived from
the address generator and are piped through the DRAM
interface so that they are associated with the correct bloc~
of data as it is read out of the swing buffer by the
prediction filter block.
In the ~'ideo Formatter, data is written into the
external DRAM in blocks, but is read out in raster order.
Writing is exactly the same as already described for the
Spatial Decoder, but reading is a little more complex.
The data in the ~ideo Formatter, external DRAM is
organized so that at least 8 blocks of data fit into a single
1, page. These 8 blocks are 8 consecutive horizontal blocks.
i;hen rasterizing, 8 bytes need to be read out of each of 8
consecutive blocks and written into the swing buffer (i.e.,
the same row in each of the 8 blocks).
Consldering the top row (and assuming a byte-wide
~O interface), the x address (the three LSBS) is set to zero, as
is the y address (3 MSBS). The x address is then incremented
as each of the first 8 bytes are read out. At this point,
the top part of the address (bit 6 and above - LSB = bit O)
is incremented and the x address (3 LSBS) is reset to zero.
2~ This process is repeated until 64 bytes have been read. With
a 16 or 32 bit wide interface to the external DRAM the x
address is merely incremented by two or four, respectively,
instead of by one.
In the present invention, the address generator can
~o signal to the DRAM interface that less than 64 bytes should
be read (this may be required at the beginning or end of a
raster line), although a multiple of 8 bytes is always read.
This is achieved by using start and stop values. The sta~~
value is used for the ~op part of the address (bit 6 a~_
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above), and the stop value i~ compared with the start value
to generate the signal which indicates when reading should
stop.
The DRAM interface timing block in the present invention
uses timing chains to plAce the edge~ of the DRAM signals to
a precision of a quarter of the system clock period. Two
quadrature clocks from the phase locked loop are used. These
are combined to form a notional 2x clock. Any one chain is
then made from two shift registers in parallel, on opposite
phases of the 2x clock.
First of all, there is one chain for the page start
cycle and another for the read/write/refresh cycles. The
length of each cycle is programmable via the microprocessor
interface, after which the page start chain has a fixed
length, and the cycle chain's length changes as appropriate
during a page start.
On reset, the chains are cleared and a pulse is created.
The pulse travels along the chains and is directed by the
state information from the DRAM interface. The pulse
generates the DRAM interface clock. Each DRAM interface
clock period corresponds to one cycle of the DRAM,
consequently, as the DRAM cycles have different lengths, the
DRAM interface clock is not at a constant rate.
Moreover, additional timing chains combine the pulse
from the above chains with the information from the DRAM
interface to generate the output strobes and enables such as
notcas, notras, notwe, notbe.
12. PRE:DICTION FILT}~R8
Referring again to Figures 12, 17, 18, and more
particularly to Figure 12, there is shown a block diagram of
the Temporal Decoder. This includes the prediction filter.
The relationship between the prediction filter and the rest
of the elements of the temporal decoder is shown in greater
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detail in Figure 17. The essence of the structure of the
prediction filter is shown in Figures 18 and 28. A detailed
description of the operation of t~e prediction filter can be
found in the section, "More Detailed Description of the
Invention. n
In general, the prediction filter in accordance with the
pre6ent invention, is used in the MPEG ~nd H.261 modes, but
not in the JPEG mode. Recall that in the JPEG mode, the
Temporal Decoder just pA~se~ the data through to the Video
Formatter, without performing any substantive de~o~ing beyond
that accomplished by the Spatial Decoder. Referring again to
Figure 18, in the MPEG mode the forward and backward
prediction filters are identical and they filter the
respective MPEG forward and backward prediction blocks. In
the H.261 mode, however, only the forward prediction filter
is used, since H.261 does not use backward prediction.
Each of the two prediction filters of the present
invention is substantially the same. Referring again to
Figures 18 and 28 and more particularly to Figure 28, there
is shown a block diagram of the structure of a prediction
filter. Each prediction filter consists of four stages in
series. Data enters the format stage 331 and is placed in a
format that can be readily filtered. In the next stage 332
an I-D prediction is performed on the X-coordinate. After
the necessary transposition is performed by a dimension
buffer stage 333, an I-D prediction is performed on the Y-
coordinate in stage 334. How the stage perform the filtering
is further described in greater detail subsequently. Which
filtering operations are required, are defined by the
compression standard. In the case of H.261, the actual
filtering performed is similar to that of a low pass filter.
Referring again to Figure 17, multi-standard
operation requires that the prediction filters be
reconfigurable to perform either MPEG or H.261 filtering, or
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to perfor~ no filtering at all in JPEG mode. Ac with many
other reconfigurable aspects of the three chip ~ystem, the
prediction filter is reconfigured by means of tokens. Tokens
are al~o used to inform the address generator of the
particular mode of operation. In this way, the address
generator can supply the prediction filter with the addresses
of the needed data, which varies significantly between MPEG
and JPEG.
13. ACCFB8INa R~CI8TER8
Most registers in the microprocessor interface (MPI) can
only be modified if the stage with which they are
associated is stopped. Accordingly, groups of registers
will typically be associated with an access register. The
value zero in an access register indicates that the group
of registers associated with that particular access
register should not be modified. Writing 1 to an access
register requests that a stage be stopped. The stage may
not stop immediately, however, so the stages access
register will hold the value, zero, until it is stopped.
Any user software associated with the MPI and used to
perform functions by way of the MPI should wait "after
writing a 1 to a request access register" until 1 is read
from the access register. If a user writes a value to a
configuration register while its access register is set to
zero, the results are undefined.
1~. MICRO-PROCE880R INTERFACE
A standard byte wide micro-processor interface (MPI) is
used on all circuits with in the Spatial Decoder and
Temporal Decoder. The MPI operates asynchronously with
various Spatial and Temporal Decoder clocks. Referring to
Table A.6.1 of the subsequent further detailed description,
there is shown the various MPI signals that
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are used on thi~ interface. The character of the signal is
shown on the input/output column, the signal name is shown
on the signal name column and a description of the function
of the signal i6 shown in the description column. The MPI
electrical specification are shown with reference to Table
A.6.2. All the specifications are classified according to
type and there types are shown in the column entitled
symbol. The description of what these symbols represent is
shown in the parameter column. The actual specifications
are shown in the respective columns min, max and units.
The DC operating conditions can be seen with reference
to Table A.6.3. Here the column headings are the same as
with reference to Table A.6.2. The DC electrical
characteristics are shown with reference to Table A.6.4 and
carry the same column headings as depicted in Tables A. 6.2
and A.6.3.
15. MPI READ TIMING
The AC characteristics of the MPI read timing diagrams
are shown with reference to Figure 54. Each line of the
Figure is labelled with a corresponding signal name and the
timing is given in nano-seconds. The full microprocessor
interface read timing characteristics are shown with
reference to Table A. 6.5. The column entitled Number is
used to indicate the signal corresponding to the name of
that signal as set forth in the characteristic column. The
columns identified by MIN and MAX provide the minimum
length of time that the signal is present the maximum
amount of time that this signal is available. The Units
column gives the units of measurement used to describe the
signals.
.6 . MPI llRITE TIMING
The general description of the MPI write timing diagrams
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are shown with reference to Figure 54. This Figure shows
each individual signal name as associated with the MPI
write timing. The name, the characteristic of the signal,
and other various physical characteristics are shown with
reference to Table 6.6.
17. ~YFOL~ ADDR~8~ LOCATION8
In the present invention, certain less frequently
ac~e~e~ memory map locations have been placed behind
keyhole registers. A keyhole register has two r~gisters
associated with it. The first register is a keyhole
address register and the second register is a keyhole data
register. The keyhole address specifies a location within
a extended address space. A read or a write operation to a
keyhole data register accesses the locations specified by
the keyhole address register. After accessing a keyhole
data register, the associated keyhole address register
increments. Random access within the extended address
space is only possible by writing in a new value to the
keyhole address register for each access. A circuit within
the present invention may have more than one keyhole memory
maps. Nonetheless, there is no interaction between the
different keyholes.
18. PICTURE-END
Referring again to Figure 11, there is shown a
general block diagram of the Spatial Decoder used in the
present invention. It is through the use of this block
diagram that the function of PICTURE_END will be described.
The PICTURE END function has the multi-standard advantage
of being able to handle H.261 encoded picture information,
MPEG and JPEG signals.
As previously described, the system of Figure 11
is interconnected by the two wire interface previously
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described. Each of the functional block~ is arranged to
operate according to the state machine configuration shown
with reference to Figure 10.
In general, the PICTURE_END function in accordance with
the invention begins at the Start Code Detector which
generates a PICTURE_END control token. The PICTURE_END
control token is passed unaltered throug~ the start-up
control circuit to the DRAM interface. Here it is used to
flush out the write swing buffers in the DRAM interface.
Recall, that the contents of a swing buffer are only
written to RAM when the buffer is full. However, a picture
may end at a point where the buffer is not full, therefore,
causing the picture data to become stuck. The PICTURE_E~D
token forces the data out of the swing buffer.
Since the present invention is a multi-standard machine,
the machine operates differently for each compression
standard. More particularly, the machine is fully
described as operating pursuant to machine-dependent action
cycles. For each compression standard, a certain number of
the total available action cycles can be selected by a
combination of control tokens and/or output signals from
the MPU or they can be selected by the design of the
control tokens themselves. In this regard, the present
invention is organized so as to delay the information from
going into subsequent blocks until all of the information
has been collected in an upstream block. The system waits
until the data has been prepared for passing to the next
stage. In this way, the PICTURE_END signal is applied to
the coded data buffer, and the control portion of the
PICTURE END signal causes the contents of the data buffers
to be read and applied to the Huffman decoder and video
demultiplexor circuit.
Another advantage of the PICTURE END control token is
to identify, for the use by the Huffman decoder
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141
demultiplexor, the end of picture even though it has not
had the typically expected full range andtor number of
signals applied to the Huffman decoder and video
demultiplexor circuit. In this situation, the information
held in the coded data buffer is applied to the Huffman
decoder and video demultiplexor as a total picture. In
this way, the state machine of the Huffman decoder and
video demultiplexor can still handle the data according to
system design.
Another advantage of the PICTURE_END control token is
its ability to completely empty the coded data buffer so
that no stray information will inadvertently remain in the
off chip DRAM or in the swing buffers.
Yet another advantage of the PICTURE_END function is
its use in error recovery. For example, assume the amount
of data being held in the coded data buffer is less than is
typically used for describing the spatial information with
reference to a single picture. Accordingly, the last
picture will be held in the data buffer until a full swing
buffer, but, by definition, the buffer will never fill. At
some point, the machine will determine that an error
condition exits. Hence, to the extent that a PICTURE_END
token is decoded and forces the data in the coded data
buffers to be applied to the Huffman decoder and video
demultiplexor, the final picture can be decoded and the
information emptied from the buffers. Consequently, the
machine will not go into error recovery mode and will
successfully continue to process the coded data.
A still further advantage of the use of a PICTURE_END
token is that the serial pipeline processor will continue
the processing of uninterrupted data. Through the use of a
PICTURE END token, the serial pipeline processor is
configured to handle less than the expected amount of data
and, therefore, continues processing. Typically, a prior
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142
art machine would stop itself because of an error
condition. As previously described, the coded data buffer
counts macroblocks as they come into its storage area. In
addition, the Huffman Decoder and Video Demultiplexor
generally know the amount of information expected for
decoding each picture, i.e., the state machine portion of
the Huffman decode and Video Demultiplexor know the number
of blocks that it will process during each picture recovery
cycle. When the correct number of blocks do not arrive
from the coded data buffer, typically an error recovery
routine would result. However, with the PICTURE_END
control token having reconfigured the Huffman Decoder and
Video Demultiplexor, it can continue to function because
the reconfiguration tells the Huffman Decoder and Video
Demultiplexor that it is, indeed, handling the proper
amount of information.
Referring again to Figure 10, the Token Decoder
portion of the Buffer Manager detects the PICTURE_END
control token generated by the Start Code Detector. Under
normal operations, the buffer registers fill up and are
emptied, as previously described with reference to the
normal operation of the swing buffers. Again, a swing
buffer which is partially full of data will not empty until
it is totally filled and/or it knows that it is time to
empty. The PICTURE_END control token is decoded in the
Token Decoder portion of the Buffer Manager, and it forces
the partially full swing buffer to empty itself into the
coded data buffer. This is ultimately passed to the
Huffman Decoder and Video Demultiplexor either directly or
through the DRAM interface.
19. FLU8HING OPERATION
Another advantage of the PICTURE_END control token is
its function in connection with a FLUSH token. The FLUSH
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token is not a~ociated with either controlling the
reconfiguration of the state machine or in providing data
for the system. Rather, it completes prior partial signals
for handling by the machine-dependent ~tate machine~. Each
of the state machines ~cG~"izes a FLUSH control token as
information not to be processed. Accordingly, the FLUSH
token is used to fill up all of the remaining empty parts
of the coded data buffers and to allow a full set of
information to be sent to the Huffman Decoder and Video
Demultiplexor. In this way, the FLUSH token i8 like
padding for buffers.
The Token Decoder in the Huffman circuit recognizes
the FLUSH token and ignores the pseudo data that the FLUSH
token has forced into it. The Huffman Decoder then operates
only on the data contents of the last picture buffer as it
existed prior-to the arrival of the PICTURE_END token and
FLUSH token. A further advantage of the use of the
PICTURE END token alone or in combination with a FLUSH
token is the reconfiguration and/or reorganization of the
Huffman Decoder circuit. With the arrival of the
PICTURE END token, the Huffman Decoder circuit knows that
it will have less information than normally expected to
decode the last picture. The Huffman decode circuit
finishes processing the information contained in the last
picture, and outputs this information through the DRAM
interface into the Inverse Modeller. Upon the
identification of the last picture, the Huffman Decoder
goes into its cleanup mode and readjusts for the arrival of
the next picture information.
3 0 2 O . FI.U8H F~NCTION
The FLUSH token, in accordance with the present
invention, is used to pass through the entire pipeline
processor and to ensure that the buffers are emptied and
that other circuits are reconfigured to await the arrival
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144
of new data. More specifically, the ~ ent invention
comprises a combination of a PICTURE END token, a padding
word and a FLUSH token indicating to the serial pipeline
proc~sFor that the picture processing for the current
picture form is completed. Thereafter, the various state
machines need reconfiguring to await the arrival of new
data for new handling. Note also that the FLUSH Token acts
as a special reset for the system. The FLUSH token resets
each stage as it p~6~eF through, but-allows subsQquent
stages to continue processing. This prevents a loss of
data. In other words, the FLUSH token is a variable reset,
as opposed to, an absolute reset.
2~. 8TOP-AFTER PICT~RE
The STOP_AFTER_PICTURE function is employed to shut
down the processing of the serial pipeline decompressing
circuit at a logical point in its operation. At this
point, a PICTURE_END token is generated indicating that
data is finished coming in from the data input line, and
the padding operation has been completed. The padding
function fills partially empty DATA tokens. A FLUSH token
is then generated which passes through the serial pipeline
system and pushes all the information out of the registers
and forces the registers back into their neutral stand-by
condition. The STOP_AFTER_PICTURE event is then generated
and no more input is accepted until either the user or the
system clears this state. In other words, while a
PICTURE_END token signals the end of a picture, the
STOP_AFTER_PICTURE operation signals the end of all current
processing.
22. MULTI-8T~n~n - 8~ARCH MODE
Another feature of the present invention is the use of
a SEARCH_MODE control token which is used to reconfigure
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145
the input to the serial pipeline ~LG.er~or to look at the
incoming bit stream. When the search mode is set, the
Start Code Detector searches only for a specific start code
or marker used in any one of the compression standards. It
S will be appreciated, however, that, other images from other
data bitstream~ can be used for this purpose. Accordingly,
these images can be used throughout thiC present invention
to change it to another embodiment which is capable of
using the combination of control tokens, and DATA tokens
along with the reconfiguration circuits, to provide similar
processing.
The use of search mode in the present invention is
convenient in many situations including 1) if a break in
the data bit stream occurs; 2) when the user breaks the
data bit stream by purposely changing channels, e.g., data
arriving, by a cable carrying compressed digital video, or
3) by user activation of fast forward or reverse from a
controllable data source such as an optical disc or video
disc. In general, a search mode is convenient when the
user interrupts the normal processing of the serial
pipeline at a point where the machine does not expect such
an interruption.
When any of the search modes are set, the Start Code
Detector looks for incoming start images which are suitable
for creating the machine independent tokens. All data
coming into the Start Code Detector prior to the
identification of standard-dependent start images is
discarded as meaningless and the machine stands in an
idling condition as it waits this information.
The Start Code Detector can assume any one of a number
of configurations. For example, one of these
configurations allows a search for a group of pictures or
higher start codes. This pattern causes the Start Code
Detector to discard all its input and look for the
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group_~tart ~tAnAard image. When ~uch an image is
identified, the Start Code Detector generate~ a GROUP_START
token and the search mode is reset automatically.
It is important to note that a single circuit, the
Huffman Decoder and Video Demultiplex circuit, is operating
with a combination of input signals including the standard-
independent set-up signals, as well as, the CODING_STANDARD
signals. The CODING_STANDARD signals are conveying
information directly from the incoming bit strea~ as
required by the Huffman Decoder and Video Demultiplex
circuit. Nevertheless, while the functioning of the
Huffman Decoder and Video Demultiplex circuit is under the
operation of the standard independent sequence of signals.
This mode of operation has been selected because it
is the most efficient and could have been designed wherein
special control tokens are employed for conveying the
standard-dependent input to the Huffman Decoder and Video
Demultiplexer instead of conveying the actual signals
themselves.
23. INVER8E MODEL~ER
Inverse modeling is a feature of all three standards,
and is the same for all three standards. In general, DATA
tokens in the token buffer contain information about the
values of the quantized coefficients, and about the number
of zeros between the coefficients that are represented (a
form of run length coding). The Inverse Modeller of the
present invention has been adapted for use with tokens and
simply expands the information about runs of zeros so that
each DATA Token contains the requisite 64 values.
Thereafter, the values in the DATA Tokens are quantized
coefficients which can be used by the Inverse Quantizer.
24. INVER8E Q~ANTIZER
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The Inverse Quantizer of the present invention is a
reguired element in the decoding sequence, but has been
implemented in such away to allow the entire IC set to
handle multi-standard data. In addition, the Inverse
Quantizer has been adapted for use with tokens. The
Inverse Quantizer lies between the Inverse modeller and
inverse DCT (IDCT).
For example, in the present invention, an adder in the
Inverse Quantizer is used to add a constant to the pel
decode number before the data moves on to the IDCT.
The IDCT uses the pel decode number, which will vary
according to each standard used to encode the information.
In order for the information to be properly decoded, a
value of 1024 is added to the decode number by the Inverse
Quantizer before the data continues on to the IDCT.
Using adders, already present in the Inverse
Quantizer, to standardize the data prior to it reaching the
IDCT, eliminates the need for additional circuitry or
software in the IC, for handling data compressed by the
various standards. Other operations allowing for multi-
standard operation are performed during a "post
quantization function" and are discussed below.
The control tokens accompanying the data are decoded
and the various standardization routines that need to be
performed by the Inverse Quantizer are identified in detail
below. These "post quantization" functions are all
implemented to avoid duplicate circuitry and to allow the
IC to handle multi-standard encoded data.
25. ~u~N DECODER AND PAR~ER
Referring again to Figures 11 and 27, the Spatial
Decoder includes a Huffman Decoder for decoding the data
that the various compression standards have Huffman-
encoded. While each of the standards, JPEG, MPEG and
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H.261, require certain data to be Huffman enco~, the
Huffman d~ro~ing required by each standard differs in some
significant waye. In the Spatial Decoder of the present
invention, rather than design and fabricate three separate
Huffman decoders, one for each standard, the present
invention saves valuable die space by identifying common
aspects of each Huffman Decoder, and fabricating these
common aspects only once. Moreover, a clever multi-part
algorithm is used that makes common ~ore aspect~ of each
Huffman Decoder common to the other standards as well than
would otherwise be the case.
In brief, the Huffman Decoder 321 works in
conjunction with the other units shown in Figure 27. These
other units are the Parser State Machine 322, the inshifter
323, the Index to Data unit 324, the ALU 325, and the Token
Formatter 326. As described previously, connection between
these blocks is governed by a two wire interface. A more
detailed description of how these units function is
subsequently described herein in greater detail, the focus
here is on particular aspects of the Huffman Decoder, in
accordance with the present invention, that support multi-
standard operation.
The Parser State Machine of the present invention, is a
programmable state machine that acts to coordinate the
operation of the other blocks of the Video Parser. In
response to data, the Parser State Machine controls the
other system blocks by generating a control word which is
passed to the other blocks, side by side with the data,
upon which this control word acts. Passing the control
word alongside the associated data is not only useful, it
is essential, since these blocks are connected via a two-
wire interface. In this way, both data and control arrive
at the same time. The passing of the control word is
indicated in Figure 27 by a control line 327 that runs
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ben-~th the data line 328 that connects the blocks. Among
other thing~, this code word identifies the particular
standard that is being decoded.
The Huffman decoder 321 also performs certain control
functions. In particular, the Huffman Decoder 321 contains
a state machine that can control certain functions of the
Index to Data 324 and ALU 325. Control of these units by
the Huffman Decoder is neceC~-ry for proper decoding of
block-level information. Having the-Parser State Machine
322 make these decisions would take too much time.
An important aspect of the Huffman Decoder of the
present invention, is the ability to invert the coded data
bits as they are read into the Huffman Decoder. This is
needed to decode H.261 style Huffman codes, since the
particular type of Huffman code used by H.261 (and
substantially by MPEG) has the opposite polarity then the
codes used by JPEG. The use of an inverter, thereby,
allows substantially the same table to be used by the
Huffman Decoder for all three standards. Other aspects of
how the Huffman Decoder implements all three standards are
discussed in further detail in the "More Detailed
Description of the Invention" section.
The Index to Data unit 324 performs the second part of
the multi-part algorithm. This unit contains a look up
table that provides the actual Huffman decoded data.
Entries in the table are organized based on the index
numbers generated by the Huffman Decoder.
The ALU 325 implements the remaining parts of the
multi-part algorithm. In particular, the ALU handles sign-
extension. The ALU also includes a register file whichholds vector predictions and DC predictions, the use of
which is described in the sections related to prediction
filters. The ALU, further, includes counters that count
through the structure of the picture being decoded by the
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Spatial Decoder. In particular, the dimen~ions of the
picture are programmed into registers a~sociated with the
counters, which facilitates detection of "start of
picture, n and ~tart of macroblock codes.
In accordance with the present invention, the Token
Formatter 326 (TF) assembles decoded data into DATA tokens
that are then passed onto the remaining stages or blocks in
the Spatial Decoder.
In the present invention, the in shifter 323 receives
data from a FIFO that buffers the data passing through the
Start Code Detector. The data received by the inshifter is
generally of two types: DATA tokens, and start codes which
the Start Code Detector has replaced with their respective
tokens, as discussed further in the token section. Note
that most of the data will be DATA tokens that require
decoding.
The ln shifter 323 serially passes data to the Huffman
Decoder 321. On the other hand, it passes control tokens
in parallel. In the Huffman decoder, the Huffman encoded
data is decoded in accordance with the first part of the
multi-part algorithm. In particular, the particular
Huffman code is identified, and then replaced with an index
number.
The Huffman Decoder 321 also identifies certain data
that requires special handling by the other blocks shown in
Figure 27. This data includes end of block and escape. In
the present invention, time is saved by detecting these in
the Huffman Decoder 321, rather than in the Index to Data
unit 324.
This index number is then passed to the Index to Data
unit 324. In essence, the Index to Data unit is a look-up
table. In accordance with one aspect of the algorithm, the
look-up table is little more than the Huffman code table
specified by JPEG. Generally, it is in the condensed data
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format that JPEG specifies for transferring an alternate
JPEG table.
From the Index to Data unit 324, the decoded index
number or other data i6 passed, together with the
accompanying control word, to the ALU 325, which performs
the operations previoucly described.
From the ALU 325, the data and control word is passed
to the Token Formatter 326 (TF). In the Token Formatter,
the data is combined as needed with the control word to
lo form tokens. The tokens are then conveyed to the next
stages of the Spatial Decoder. Note that at this point,
there are as many tokens as will be used by the system.
26. INVER8E DI8CR~TJ CO8IN~ TRAN8FORM
The Inverse Discrete Cosine Transform (IDCT), in
accordance with the present invention, decompresses data
related to the frequency of the DC component of the
picture. When a particular picture is being compressed,
the frequency of the light in the picture is quantized,
reducing the overall amount of information needed to be
stored. The IDCT takes this quantized data and
decompresses it back into frequency information.
The IDCT operates on a portion of the picture which is
8x8 pixels in size. The math which performed on this data
is largely governed by the particular standard used to
encode the data. However, in the present invention,
significant use is made of common mathematical functions
between the standards to avoid unnecessary duplication of
clrcultry .
Using a particular scaling order, the symmetry between
the upper and lower portions of the algorithms is
increased, thus common mathematical functions can be reused
which eliminates the need for additional circuitry.
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The IDCT responds to a number of multi-standard tokens.
The first portion of the IDCT checks the entering data to
ensure that the DATA tokens are of the correct size for
processing. In fact, the token stream can be corrected in
some situations if the error is not too large.
27. BUFFER MANAGER
The Buffer Manager of the present invention, receives
incoming video information and supplies the address
generators with information on the timing of the datas
arrival, display and frame rate. Multiple buffers are used
to allow changes in both the presentation and display
rates. Presentation and display rates will typically vary
in accordance with the data that was encoded and the
monitor on which the information is being displayed. Data
arrival rates will generally vary according to errors in
encoding, decoding or the source material used to create
the data. When information arrives at the Buffer Manager,
it is decompressed. However, the data is in an order that
is useful for the decompression circuits, but not for the
particular display unit being used. When a block of data
enters the Buffer Manager, the Buffer Manager supplies
information to the address generator so that the block of
data can be placed in the order that the display device can
use. In doing this, the Buffer Manager takes into account
the frame rate conversion necessary to adjust the incoming
data blocks so they are presentable on the particular
display device being used.
In the present invention, the Buffer Mnager primarily
supplies information to the address generators.
Nevertheless, it is also required to interface with other
elements of the system. For example, there is an interface
with an input FIF0 which transfers tokens to the Buffer
Manager which, in turn, passes these tokens on to the hrite
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addre~;s ~enerators.
The Buffer Manager also interfaces with the display
address generators, receiving information on whether the
display device is ready to display new data. The Buffer
Manager also confirms that the display address generators
have cleared information from a buffer for display.
The Buffer Manager of the present invention keeps track
of whether a particular buffer is empty, full, ready for
use or in use. It also keeps track of the presentation
number associated with the particular data in each buffer.
In this way, the Buffer Manager determines the states of
the buffers, in part, by making only one buffer at a time
ready for display. Once a buffer is displayed, the buffer
is in a "vacant" state. When the Buffer Manager receives a
PICTURE_START, FLUSH, valid or access token, it determines
the status of each buffer and its readiness to accept new
data. For example, the PICTURE_START token causes the
Buffer Manager to cycle through each buffer to find one
which is capable of accepting the new data.
The Buffer Manager can also be configured to handle the
multi-standard requirements dictated by the tokens it
receives. For example, in the H.261 standard, data maybe
skipped during display. If such a token arrives at the
Buffer Mnager, the data to be skipped will be flushed from
the buffer in which it is stored.
Thus, by managing the buffers, data can be effectively
displayed according to the compression standard used to
encode the data, the rate at which the data is decoded and
the particular type of display device being used.
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The foregoing description is believed to
adeguately describe the overall concepts, system
implementation and operation of the various aspects of the
invention in sufficient detail to enable one of ordinary
skill in the art to make and practice the invention with
all of its attendant features, objects and advantages.
However, in order to facilitate a further, more detailed in
depth understanding of the invention,- and additional
details in connection with even more specific, commercial
implementation of various embodiments of the invention, the
following further description and explanation is pr~ferred.
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This i~ a more detailed description for a multi-standard
video decoder chip-set. It is divided into three main
sections: A, B and C.
Again, for purpo~es of organization, clarity and
convenience of explanation, this additional disclosure is
set forth in the following sections.
Description of features common to chips in the
chip-set:
Tokens
Two wire interfaces
DRAM interface
Microprocessor interface
Clocks
Description of the Spatial Decoder chip
Description of the Temporal Decoder chip
SECI'ION A.l
The first description section covers the majority of
the electrical design issues associated with using the
chip-set.
A.~ oy~aphic conv-ntions
A small set of typographic conventions is used to
emphasize some classes of information:
NAME8_OF_TO~N8
wire name active high signal
wire_name active low signal
register_name
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SECTI~I A.2 Video Decoder Family
30 MHz operation
Decodes MPEG, JPEG & H.261
Coded data rates to 25 Mb/s
Video data rates to 21 MB/s
MPEG resolutions up to 704 x 480, 30 Hz, 4:2:0
Flexible chroma sampling formats
Full JPEG baseline decoding
Glue-less page mode DRAM interface
208 pin PQFP package
Independent coded data and decoder clocks
Re-orders MPEG picture sequence
The Video decoder family provides a low chip count
solution for implementing high resolution digital video
decoders. The chip-set is currently configurable to
support three different video and picture coding systems:
JPEG, MPEG and H.261.
Full JPEG baseline picture decoding is supported.
720 x 480, 30 Hz, 4:2:2 JPEG encoded video can be decoded
in real-time.
CIF (Common Interchange Format) and QCIF H.261 video can
be decoded. Full feature MPEG video with formats up to 740
x 480, 30 Hz, 4:2:0 can be decoded.
Note: The above values are merely illustrative, by way
of example and not necessarily by way of limitation, of one
embodiment of the present invention. Accordingly, it will
be appreciated that other values and/or ranges may be used.
A.2.1 System configurations
A.2.1.1 Output formatting
In each of the examples given below, some form of output
formatter will be required to take the data presented at
the output of the Spatial Decoder or Temporal Decoder and
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re-forma~ it for a computer or display system. The details
of this formatting will vary between applications. In a
simple case, all that is required is an address generator
to take the block formatted data output by the decoder chip
and write it into memory in a raster order.
The Image Formatter is a single chip VLSI device
providing a wide range of output formatting functions.
A.2.1.2 JPEG still picture decoding
A single Spatial Decoder, with no-off-chip DRAM, can
rapidly decode baseline JPEG images. The Spatial Decoder
will support all features of baseline JPEG. However, the
image size that can be decoded may be limited by the size
of the output buffer provided by the user. The
characteristics of the output formatter may limit the
chroma sampling formats and color spaces that can be
supported.
A.2.1.3 JPEG video decoding
Adding off-chip DRAMs to the Spatial Decoder allows it
to decode JPEG encoded video pictures in real-time. The
size and speed of the required buffers will depend on the
video and coded data rates. The Temporal Decoder is not
required to decode JPEG encoded video. However, if a
Temporal Decoder is present in a multi-standard decoder
chip-set, it will merely pass the data through the Temporal
Decoder without alteration or modification when the system
is configured for JPEG operation.
A.2.1.4 H.261 decoding
The Spatial Decoder and the Temporal Decoder are both
required to implement an H.261 video decoder. The DRAM
interfaces on both devices are configurable to allow the
quantity of DRAM required for proper operation to be
reduced when working with small picture formats and at low
coded data rates. Typically, a single 4Mb (e.g. 512k x 8)
DRAM will be required by each of the Spatial Decoder and
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the Tempcral Decoder.
A.2.1.5 MPEG decoding
The configuration required for MPEG operation is the
same as for H.261. However, as will be appreciated by one
of ordinary skill in the art, larger DRAM buffers may be
required to support the larger picture formats possible
with MPEG.
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159
SECTION A.3 TOkenS
A. 3 . 1 TOk-D forsat
In accordance with the present invention, tokens provide
an extensible format for communicating information through
the decoder chip-set. While in the present invention, each
word of a Token is a minimum of 8 bits wide, one of
ordinary skill in the art will appreciate that tokens can
be of any width. Furthermore, a single Token can be spread
over one or more words; this is accomplished using an
extension bit in each word. The formats for the tokens are
summarized in Table A.3.1.
The extension bit indicates whether a Token continues
into another word. It is set to 1 in all words of a Token
except the last one. If the first word of a Token has an
extension bit of 0, this indicates that the Token is only
one word long.
Each Token is identified by an Address Field that starts
in bit 7 of the first word of the Token. The Address Field
is of variable length and can potentially extend over
multiple words (in the current chips no address is more
than 8 bits long, however, one of ordinary skill in the art
will again appreciate that addresses can be of any length).
Some interfaces transfer more than 8 bits of data. For
example, the output of the Spatial Decoder is 9 bits wide
(10 bits including the extension bit). The only Token that
takes advantage of these extra bits is the DATA Token. The
DATA Token can have as many bits as are necessary for
carrying out processing at a particular place in the
system. All other Tokens ignore the extra bits.
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A.3.2 ~he DATA Token
The DATA Token carries data from one processing stage to
the next. Consequently, the characteristics of this Token
change as it passes through the decoder. Furthermore, the
meaning of the data carried by the DATA Token varies
depending on where the DATA Token is within the system,
i.e., the data is position dependent. In this regard, the
data may be either frequency domain or Pel domain data
depending on where the DATA Token is within the Spatial
Decoder. For example, at the input of the Spatial Decoder,
DATA Tokens carry bit serial coded video data packed into 8
bit words. At this point, there is no limit to the length
of each Token. In contrast, however, at the output of the
Spatial Decoder each DATA Token carries exactly 64 words
and each word is 9 bits wide.
A.3.3 Using Token formatted data
In some applications, it may be necessary for the
circuitry that connect directly to the input or output of
the Decoder or chip set. In most cases it will be
sufficient to collect DATA Tokens and to detect a few
Tokens that provide synchronization information (such as
PICTURE_START). In this regard, see subsequent sections
A.16, "Connecting to the output of Spatial Decoder", and
A.l9, "Connecting to the output of the Temporal Decoder".
As discussed above, it is sufficient to observe activity
on the extension bit to identify when each new Token
starts. Again, the extension bit signals the last word of
the current token. In addition, the Address field can be
tested to identify the Token. Unwanted or unrecognized
Tokens can be consumed (and discarded) without knowledge of
their content. ~owever, a recognized token causes an
appropria~e a Ct ion to occur.
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Fur~hermore, the data input to the Spatial Decoder can
either be supplied as bytes of coded data, or in DATA
Tokens (see Section A.10, "Coded data input"). Supplying
Tokens via the coded data port or via the microprocessor
interface allows many of the features of the decoder chip
set to be configured from the data stream. This provides
an alternative to doing the configuration via the micro
processor interface.
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7 6 ! s 4 3 2 1 0 Token Nam~ Re~erence
o o 1 QUANT_SCALE
c 1 o PREDICTION_MODE
o ' 1 1 (reser~ed)
o o MVD_FORWARDS
~ o l MVD_BACKWARDS
o, o o o 1 QUANT_TABLE
0 0 o o 0 1 DATA
o o o o COMPONENT_NAME
1 1 o o o 1 DEFINE_SAMPLING
o o 1 o JPEG_TABLE_SELECT
o o 1 1 MPEG_TABLE_SELECT
o 1 o o TEMPORAL_Rtt-tHtl`lCE
o 1 o 1 MPEG_DCH_TABLE
1 0 1 1 0 (reserved)
1 0 1 1 1 (reserved)
0 0 0 0 (reserved) SAVE_STATE
0 O 0 1 (reserved) RESTORE_STATE
o o 1 o TIME_CODE
1 1 1 1 0 0 1 1 (res rved)
o I o o o o o o o NULL
o O O O O O 0 1 (reserved)
o I O O O O 0 1 0 (reserved)
o I o O O O 0 1 1 (reserved)
o o o 1 o o o o SEaUENCE_START
o o o 1 o o o 1 GROUP_START
o o o 1 o o 1 o PICTURE_START
o o o l o o 1 1 SLICE_START
o o o 1 o 1 o o SEQUENCE_END
o o o l o 1 o 1 CODING_STANDARD
o, o o l o 1 1 o PICTURE_END
o' o o l o 1 1 l FLUSH
o ~ o o l 1 o o o FIELD_INFO
Table A.3.1 Summary of Tokens
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163
7 6 5 1 4 3 2 1 0 Token Narne Re~erer,ce
o o o 1 1 0 0 1 MAX_COMP_ID
o o o 1 1 o 1 o EXTENSION_DATA
0 o 0 1 1 0 1 1 USER_DATA
O 0 0 1 1 1 0 0 DHT_MARKER
0 0 0 1 1 1 0 1 DQT_MARKER
o o o 1 1 ~ 1 0 (reserved) DNL_MARKER
0 0 0 1 1 1 1 1 (rerved) DRI_MARKER
1 0 1 0 0 0 (reserved)
o 1 o o ~ (r~se~ve
1 ¦ 1 1 0 1 0 1 0 (reserved)
o 1 0 1 1 (reserv d~
0 1 1 0 0 BIT_RATE
o 1 1 o 1 VBV_BUFFER_SIZE
1 1 1 o 1 1 1 0 VEIV_DELAY
0 - 1 1 1 1 PICTURE_TYPE
o 0 0 0 PICTURE_RATE
0 0 0 1 PEL_ASPECT
1 1 1 1 0 0 1 0 HOReONTAL_SlZE
o o 1 1 VERTICAL_SIZE
o 1 o o BROKEN_CLOSED
0 1 0 1 CONSTRAINED
O 1 0 (reserved) SPECTRAL_LlMlT
o 1 1 1 DEFINE_MAX_SAMPLING
0 0 0 (reserved)
o o 1 (resen~ed)
1 o 1 0 (reserved)
o 1 1 (reserved)
o o HORIZONTAL_MBS
M 1 1 1 1 1 o 1 VERTICAL_MBS
1 1 1 0 (reserveC)
1 (reserved)
Table A.3.1 Summary of Tokens (contd)
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A.3.~ D--cr~ption of To~
This section documents the Token~ which are implemented
in the Spatial Deco~er and the Temporal Decoder chips in
accordance with the present invention; see Table A.3.2.
Note:
."r" signifies bits that are currently reserved and carry
the value O
.unless indicated all integers are unsigned
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E 7 6 5 4 31 2 1 0 Description
1 1 1 0 1 1 0 0 BlT_RATEtestinloonly
1 r r r r r r b b
Carries the MPEG bit rate parameter ~. Generated by ~he Hu~man
b b b b b b b b
decoder when decoding an MpEG bi s~ream. --_
0 b b b b b b b b
b - an 18 bit integer as defined by MPC5
1 1 1 1 1 o 1 o o BROKEN_CLOSED
0 r r r r r r c b
Carries two MpEG nags bits:
c closed_gop
b broken_link
ol o I o 1 o 1 o 1 CODING_STANDARD
o s s, s s s s s s
s - an 8 bit integer indicating the current coding s!andard~ The
values currently assigned are:
0 - H.261
l JPEG
2 - MpEG
1 1 1 o o o o c c COMPONENT_NAME
0 n ni n n n n n n
Communicates the ,ela~;unshiu be~ween a cu",uonent ID and ~e
co" ,ponc. It name. See also . . .
c - 2 bil cr," ,ponent ID
n 8 bit cc",ponc.,l 'name
1 i 1 1 1 o 1 o 1 CONSTRAINED
o r r r r r r r C
c - carnes the Consl,a~ned_parame;er5_1lag decoded trom an
MpEG bitslream.
Table A.3.2 Tokens implemented in the Spatial
Decoder and Temporal Decoder (Sheet 1 of 9)
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E 7 6 ! 5 4 3 2 1 o DescriDtion
0 ! O 1 c c DATA
d dl d d d d d d
Carries data through the decoder chip-sel.
O d d d d d d d d c - a 2 bit integer co"~porenl ID (see A 3 5 1 ). This neld
is not defined for Tokens that carry coded da~a (rzther ~ an pi~el
i"lo",~liOn)-
1 1 1 1 o 1 1 1 DEFINE_MAX_SAMPLING
r r I r r r r h h
Max. Honzonlal and Venical sampling numbets. These descnbe
r r r r r r v v
the maximum number of blocks h..,i~ù,,~ ~yhcr~ally in any
COI III~OQC. ~1 of a "~ ,obloc~. See A.3.5.2
h - 2 bit horizontal sampling number.
v - 2 bit vertical sampling number.
o o o 1 c c DEFINE_SAMPLING
Horizontal and Vertical sampling numbers lor a panicular colour r r r r r r v vco",poncr,l. See A.3.52
c - 2 bit cu"",ono.lt ID.
h - 2 bit horizontal sampling numbec
v - 2 bit vertical sampling number.
o o o o 1 1 1 o o DHT_MARKER
This Token informs the Vdeo Demux thal the DATA Token that
follows contains the sF ? i1r. ~ ~ ol a Huffman table described
using the JPEG 'define Hutlman table segmenr syntax. This Token
is only valid when the coding standard is configured as JPEG.
This Token is genetated by the stan code de~ec~or during JPEG
decoding when a DHT marker has been encoun~ered in the data
stream.
Table A.3.2 Token~ implemented in the 8patial
Decoder and Temporal Decoder (Sheet 2 of 9)
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167
E 7 6 l 5 4 3 2 1 , 0 - Des; ~ ,
o o o o 1 1 1 1 0 DNL_MARKER
This Token inlorms the Video Demux ~hat the DATA Token that
tollows contains the JPEG parameter NL which specifies the
number o~ lines in a irame.
This Token is generated by the staQ code detector during JPEG
decoding when a DNL marker has been encountered in the data
stream.
o o o o 1 1 1 o 1 DQT_MARKER
This Token in~orms the Vdoo Demux that the DATA Token that
~ollows contains the p~ '~ , o~ a quantisation table described
using the JPEG 'define quantisation table segment' syntax. ~his
Token is only valid when the coding standard is configured as
JPEG. The Vdeo Demux generates a QUANT_TABLE Toi(en
containing the new quantisation table ;"~o" "ation.
This Token is generated by the stan code detector dunng JPE5
decoding when a Dt~T marker has been encoun~ered in the Ca a
stream.
o o o o 1 1 1 1 1 DRI_MARKER
This Token iniorms the Vdeo Demux that the DATA Token that
follows contains the JPEG parameter Ri which specifies the
number oi minimum coding units between restaQ markers.
This Token is generated by the staQ code detector during JPE5
decoding when a DRI marker has been encountered in the Ca:a
stream.
Table A.3.2 Tokens implemented in t~e Spatial
Decoder and Temporal Decoder (Sheet 3 of 9)
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E 7 o S 4 3 2 1 0 C)escription
o o o 1 1 o 1 o EXTENSION_DATA JPEG
This Token informs the Video Demux tha~ the DATA Token hat
iollows contains extension data. See A. 11.3, Conversion ol start
codes to Tokens, and A.14.6, ReceMng User and
Extension dala-,
During JPEG operation the 8 bit field ~ carries the JPEG marker
value. This allows the class oi extension data to se identified.
o o o o 1 1 o 1 o EXTENSION_DATA MPEG
This Token iniorms the Video Demux tha~ the DATA Token that
lollows contains extension data. See A.11.3, Conversisn of start
codes to Tokens-, and A.14.6, Receiving User and
Extension data,
1 o o o 1 1 o o o FIELD_INFO
o ~,, I p ~ ~ ~
Carries ;niu.,., ~ asout the pic~ure ~ollowing to aid its display.
This ~uncbon is not signalled by any existing coding standard.
t - i~ the picture is an interlaced frame this bit inCicates ii the ucper
field is first (t-0) or second.
p U pictures are fields this indicates i~ the next picture is upper
(p-0) or lower in the frame.
- a 3 bit number indicating position oi the field in the 8 field PAL
sequence.
o o o o 1 o 1 1 1 FLUSH
Used to indicate the end ol the current coded data and to pusn the
end of the data stream through the decoder.
o o o o 1 o o o 1 GROUP_START
- Generated when the group ol pictures start code is tound wnen
decoding MPEG or the Irame marker is ~ound when decoCing
JPEG.
Table A.3.2 Tokens impiemented in the Spatial Decoder and Temporal i~ecoder (Sheet ~ of
21~S159
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169
E 7 6 5 4 3 2 1 0 - 0escnption
o o HORIZONTAL_MBS
1 r r r h h h h h
h - a 13 bil number integer indicaong ~he hori~ontal width of the
O h h h h h h h h
picture In ",a ,uLlo. 1~.
1 1 1 1 1 0 0 1 0 HORIZONTAL_SIZE
h h h h h h h h
h - 16 bit number integer indicating the hori20ntal width of the
O h h h h h h h h
picture in pixels. This can be any integer value.
1 1 1 0 0 1 0 c c JPEG_TABLE_SELECT
O r r r r r r t t
Informs the inverse quantiser which quantisation table ~o use on
the specified colourco",ponE.lt.
c 2 bit cu",?one.,~ lO (see A.3.5 1
t - 2 bit integer table number.
1 0 0 0 1 l 0 0 1 MAX_COMP_ID
O r r r r r r m m
m - 2 bit integer indicating the maximum value of component ID
(see A.3.5.1 ) that will be used in the next picture.
û 1 1 û 1 o 1 c c MPEG_DCH_TABLE
O r r r r r r t t
Configures which DC coefficient Hut~man table should be used for
colour c~""~r,- ,lt cc.
c - 2 bit co."ponont ID (see A.3.5.1
t 2 bit integer table number.
O 1 1 0 0 1 1 d n MPEG_TABLE_SELECT
Informs the inverse quantiser whether to use the default or user
defined quantisation table for inua or non-intra in~ormaticn.
n O indicates intra ;nfu""al~n, 1 non-intra.
d - O indicates detault table, 1 user defined.
Table A.3.2 Tokens implemented in the spatial
Decoder and Temporal Decoder (Sheet 5 of 9)
~1~5~59
--
170
E ~ 61 5 4 3 2 1 0 Descriplion
1 '1 0 ~1 d v v v v MVD_BACKWARDS
o V V V V V V V V
Carries one co..~trt-~.tl (either vertical or horizontal) ol the
ba~.~a,~b mobon veclor,
d - O indicates x ,,o...pon_. ,t, 1 the y contponGnt
v -12 bit two's C6 ~J~ e.ll number. The LSB prcviCes h~l pixe
resolution.
l 1 0 0 d v v v v MVD_FOFIWARDS
o V V V V V V V V
Carries one ~o...t~tr._. ~t (either vertical or horizontal) ol the
lor~vards motion vectot.
d 0 indicates x co...~tnc"t, 1 the y component
v -12 bit two's a~ ,e.,l number. The LS8 proviCG~ hall pixel
resolution.
0 0 o o o o o o o NULL
Does nothing.
o o o 1 PEL_ASPECT
p - a 4 bit integer as defined by MPEG.
o o o o 1 o 1 1 o PICTURE_END
Inserted by the start code delector to indicate the end ol the current .
pictur~.
o o o o PICTURE_RATE
p - a 4 bit integer as defined by MP'G.
1 o o o 1 o o 1 o PICTURE_START
0 r r r r n n n n
Indicates tt~ start o~ a new picture.
n - a 4 bit picture index allocated to tne picture by the s;ar-. code
detectoc
Table A.3.2 Token~ implemented in the Spatial
Decoder and Temporal Decoder ~Sheet 6 of 9)
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E 7 6 ~ ~ 3 2 1 O DescriDlion
o 1 1 1 1 PICTURE_TYPE MPEG
o, r r p p
p - a 2 bit integer indicating the picture coding type ol the picture
that ~ollows:
O - Intra
1 Predic~ed
2 - ai~li .._tiona::1 Fredicted
3 - DC InUa
o 1 1 1 1 -PICTURE_TYPE H.261
Indicates various H.261 opbons are on ~1 ) or o~l ~O). These options
O r r s d I q 1
are always oft lor MPEG and JPEG:
s - Split Screen Indicator
d Document Camera
- Freeze Picture Release
Source picture lormat:
q = O C~IF
q = 1 CIF
O O 1 O h y x b I PREDICTION_MODE
A set o~ nag bits that indicate the predicOon mooe tor the
t l~l~ that ~ollo~
I lorward predkOon
b backward predicbon
x reset lorward vector predictor
y reset backward vector predictor
h enable H.261 loop filter
O o o 1 s s s s s ~UANT_SCALE
Intorrns the inverse quantiser o~ a new scale lactor
s - 5 bit integer in range 1 ... 31. The value O is reserved.
Table A.3.2 Tokens implemented in the Spatial Decode~ and Temporal Decoder (Sheet 7 of
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_
E 7 6 5 4 3 2 1 ¦ O ~ ~tion
o o o o 1 r t I t OUANT TABLE
Loads the specified inverse quantiser tabie with 64 8 bit uns(gned
integers. The values are in zig-zag order.
O q q q q q q q q
t - 2 bit integer specitying the inverse Cuantiser table to be loaced.
0 0 0 0 1 o 1 o o SEOUENCE_END
The MPEG sequence_end_code and the JPEG EOI marker causz
this Token to be generated.
o o o o 1 o o o o SEOUENCE_START
Generated by the MPEG sequence_start start code.
o o o 1 o o 1 1 SLICE_START
Co~i~r~ to the MPEG slice_stan the H.261 GOEj and the
JPEG resync interval. The interpretation o~ 8 bit integer ~s citters
between coding standards:
MPEG- Slice Vertical Position - l.
H.261 Group ot atocks Number -1.
JPEG resy luofl ) interval identificatlon (4 LSBs only).
o 1 o o t t TEMPORAL_REFERENCE
t - carries the temporal relerence. For MPEG this is a l O bit integer.
For H.261 only the 5 LSas are used. the MSas will always be zero.
1 1 1 1 0 0 1 0 d TIME_CODE
r r h h h h h The MPEG time_code:
1 r r m m m m m m
d - Drop trame ~lag
1 r r s s s s s s
O h 5 bit integer specitying hours
m 6 bit integer speci~ying minutes
s - 6 bit integer specifying seconds
p - 6 bit integer specilying pictures
Table A.3.2 Tokens implemented in the Spatial Decoder and Temporal Decoder (Sheet 8 Of
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E 7 1 o 1 5 ¦ 4 1 3 i 2 1 ~ O Oescnption
0 i I ; 1 j 1 ! 0 1 ~ 1 USER_DATA JPEG
o V V V V V V V:V
This Token informs the Video Cemux 'uhat the DATA Token that
~ollows contains user data. See A.11.3, Converslcn of s:a~t ccces
to Tokens-, and A.14.6, 'Rece!ving Use- and
Extension data-,
During JPEG operation the 3 bit field ~ carr:es tne .,P_G rn.atker
value. This allows the class o~ user c'ata ~o be identlfied.
o o o o 1 1 o 1 1 USER_DATA MPEG
This Token in~orms the Video Demux that tne DATA Token that
~ollows contains user data. See A. 11.3, 'Conversion of start coces
toTokens-, andA.14.6,~ReceivingUserand
Extension data-,
o 1 1 o 1 VBV_BUFFER_SIZE
r, r r s - a 10 bit integer as defined by MPEG.
O sl s s s s s s s
1 o 1 1 1 o VBV_DELAY
b I b b b - a 16 bit integer as defined by MPEG.
G bj b b b b b b b
1 1 1 1 1 1 o 1 VERTICAL_MBS
v - a 13 bn integer indkating the venical size o~ the pic:ure in
O v v v v v v v v
" ,c,,, vbl~5 .
t 1 ' 1, 1 o o 1 l 1 VERTICAL_SIZE
v a 16 bit integer indicatlng the vertical size ol the plcture in ~IIXaiS.
O V, V I V ~ V V V V V
This can be any integer value.
Table A.3.2 Tokens implemented in the Spatial
Decoder and Temporal Decoder (Sheet 9 of 9)
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174
A.3.5 ~u~b-r- ig~ Tok-n-
A.3.5.1 Co~pon-~t Id-~tification ~u~b-r
In accordance with the present invention, the Component
ID number is a 2 bit integer specifying a color component.
This 2 bit field is typically located as part of the Header
in the DATA Token. With MPEG and H.261 the relationship is
set forth in Table A.3.3.
Component ID - M~EG or H.261 colow cr.. "~ntnt
O Luminance (Y~
Blue di~erence signal (Cb / U)
2 Red diHerence signal (Cr / V)
3 Never used
Tabl- A.3.3 Component ID for ~PEG and ~.261
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175
With JPEG the situation i8 more complex as JPEG does not
limit the color component~ that can be used. The decoder
chips permit up to 4 different color components in each
scan. The IDs are allocated sequentially as the
specification of color components arrive at the decoder.
A.3.5.2 ~orizont-l ~d V-rtical ~ pling numb-r-
For each of the 4 color components, there is aspecification for the number of blocks arranged
horizontally and vertically in a macroblock. Thi~
specification comprises a two bit integer which is one less
than the number of blocks.
For example, in MPEG (or H.261) with 4:2:0 chroma
sampling (Figure 36) and component IDs allocated as per
Table A.3.4.
Honzontal Vertical
Component IDsamplingWidUl in blocks sampling Height in blocks
number number
0 1 2 1 2
0 1 0
2 0 1 û
3 NotusedNotused NotusedNot used
Table A.3.~ ~mpling numbers for ~:2:0/MPEG
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176
With JPEG and 4:2:2 chroma 6ampling (allocation of
component to component ID will vary between applications.
See A.3.5.1. Note: JPEG require6 a 2:1:1 structure for its
macroblocks when processing 4:2:2 data. See Table A.3.5.
Honzontal Vertlcal
Compcren~ 1~ samplingWid~,h in blocks sampling He!sht .n blocks
number num~er
Y 1 2 0
U O 1 0
V O 1 0 1 1
T~bl- A.3.5 ~ampling numb-r- for ~:2:2 JPEG
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A.3.6 ~p~cial Token formats
In accordance with the present invention, tokens such as
the DATA Token and the QUANT_TABLE Token are used in their
"extended form" within the decoder chip-set. In the
extended form the Token includes some data. In the case of
DATA Tokens, they can contain coded data or pixel data. In
the case of QUANT_TABLE tokens, they contain quantizer
table information.
Furthermore, "non-extended form" of these Tokens is
defined in the present invention as l'empty". This Token
format provides a place in the Token stream that can be
subsequently filled by an extended version of the same
Token. This format is mainly applicable to encoders and,
therefore, it is not documented further here.
Token Name MPEG JPEG H261
BIT_RATE
BROKEN_CLOSED
CODING_STANDARD
COMPONENT_NAME
CONSTRAINED
DATA
DE~INE_MAX_SAMPLING
DEFINE_SAMPLING
DtlT_MARKER
DNL_MARKER
DQT MARKER
DR l_MAR KER
Table A.3.6 tokens for different standards
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Token Name MPEG JP-G 1~26
EXTENSION_DATA
FIELD_INFO
FLUSH
GROUP_START
HORIZONTAL_MBS
HORIZONTAL_SIZE
JPEG_TABLE_SELECT
MAX_COMP_ID
MPEG_DCH_TABLE
MPEG_TABLE_SELECT
MVD_BACKWARDS
MVD_FORWARDS
NULL
PEL_ASPECT
PICTURE_END
PICTURE_RATE
PICTURE_START
PICTURE_TYPE
PREDICTION_MODE
OUANT_SCALE
aUANT_TABLE
SEQUENCE_END
SEQUENCE_START
SLICE_START
TEMPORAL_REFERENCE
TIME_CODE
USER_DATA
VBV_BUFFER_SIZE
VBV_DELAY
VERTICAL_MBS
VERTICAL_SIZE
Table A.3.6 Tokens for different standards (contd)
~ L4 5 1 5 9
179
A.3.7 Us- of Token~ for different ~tandards
Each stanA~rd uses a different ~ub-set of the defined
Tokens in accordance with the present invention; ss Table
A.3.6.
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180
SECTION A.4 The two wire interface
A.~ r- ~nt-rfac-- ~nd th- Tok-~ Port
A simple two-wire valid/accept protocol is used at all
levels in the chip-set to control the flow of information.
Data is only transferred between blocks when both the
sender and receiver are observed to be ready when the clock
rises.
l)Data transfer
2)Receiver not ready
3)Sender not ready
If the sender is not ready (as in 3 Sender not ready
above) the input of the receiver must wait. If the
receiver is not ready (as in 2 Receiver not ready above)
the sender will continue to present the same data on its
output until it is accepted by the receiver.
When Token information is transferred between blocks the
two-wire interface between the blocks is referred to as a
To~cen Port.
A.~.2 Wh-r- us-d
The decoder chip-set, in accordance with the present
invention, uses two-wire interfaces to connect the three
chips. In addition, the coded data input to the Spatlal
Decoder is also a two-wire interface.
A.~.3 Bu- ig~al-
The width of the data word transferred by the two-wire
interface varies depending upon the needs of the interface
concerned (See Figure 35, ~Tokens on interfaces wider than
8 bits". For example, 12 bit coefficients are input to the
Inverse Discrete Cosine Transform (IDCT), but only g bits
are output.
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181
I nter1ace O a;a WiCth (bits )
Cocea data input to Spaoal Oecoder 8
Output pon o~ Spatial Decoder g
Input Pon o~ Temporal Decoder g
Output pon o~ Temporal Decoder 3
Input pon o~ Image Forrnaner 8
Table A.4.1 Two wire interface data width
In addition to the data signals there are three other
signals transmitted via the two-wire interface:
.valid
.accept
.extension
A.4.3.1 The extension signal
The extension signal corresponds to the Token extension
bit previously described.
A.4.4 Design considerations
The two wire interface is intended for short range,
point to point communication between chips.
The decoder chips should be placed adjacent to each
other, so as to minimize the length of the PCB tracks
1~ between chips. Where possible, track lengths should be
kept below 25 mm. The PCB track capacitance should be kept
to a r,inimum.
214515~
- 182
The clock distribution should be designed to minimize
the clock slew between chip~. If there is any clock slew,
it should be arranged so that "receiving chips" see the
clock before "sending chipen.l
All chipis communicating via two wire interfaces should
operate from the same digital power supply.
A.~.5 I~t-rf-c- t~ug
30 MHz No~e~
Num. Char5c~.rla~ie Unit
Min. Ma~
Inwt si5ntl sel-up bme 5 ns
`nput signal hold time O ns
3 Outj~ut signaJ drive tlme 23 ns
Output slgnai hoid ~me 2 ns
T~bl- A.~.2 ~wo wir- interfac- timing
a. Figures in Table A.4.2 may vary in accordance with
design variations
b. Maximum signal loading is approximately 20 pF
' Note: Figure 38 shows the two-wire interface between the
system de-mux chip and the coded data port of the Spatial
Decoder operating from the main decoder clock. This is
optional as this two wire interface can work from the coded
data clock which can be asynchronous to the decoder clock.
See Section A.10.5, "Coded data clock". Similarly the display
interface of the Image Formatter can operate from a clock that
is asynchronous to the main decoder clock.
- 21~51~3
~,
183
A.4.6 ,S~gnal level~
The two-wire interface uses CMOS inputs and output.
V~Hmjn is approx. 70% of V,,~, and V,~m~x is approx. 30% of VDD.
The values shown in Table A.4.3 are those for VIH and V" at
their respective worst case VDI). Vl)l?=5 . + 25V.
SymDol Parameter Min. Max. Unl~s
V.~ Inpu~loglc 1'voltage 3.6a V~O~O.S V
V!~ Inputloçic O'voltage GND C.S 1.43 j V
VO~ Output loglc '1' ~oltaçe V~O . o~l I V '
VDo - 0.4 j V
Vo~ OU;PUt loglc 'O' volta$e .l v '
0.4 ~c
Inpul leakage current ~ 10 LA
Table A.4.3 DC electrical characteristics
a. lOH<lmA
b. l"H<4mA
c. 1~" clmA
10d. 10l<4mA
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184
A.4.7 Cgntrol clock
In general, the clock controlling the transfers across
the two wire interface is the chip's decoder_clock. The
exception is the coded data port input to the Spatial
Decoder. This is controlled by coded_clock. The clock
signals are further described herein.
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185
SECTION A.5 DRAM Interface
A.5.1 The DRAM interface
A single high performance, configurable, DRAM interface
is used on each of the video decoder chips. In general,
the DRAM interface on each chip is substantially the same;
however, the interfaces differ from one another in how they
handle channel priorities. The interface is designed to
directly drive the DRAM used by each of the decoder chips.
Typically, no external logic, buffers or components will be
necessary to connect the DRAM interface to the DRAMs in
most systems.
A.5.2 Interface signals
Input /
Signal Narne Oescription
Outsut
DRAM_data[31 :0l l/O The 32 bit wide DRAM oala t)us. Optionally this ~us
can be configured to be 16 or 8 bits wide. See
section A.S.a
DRAM_addr[10:0] O The 22 Ditwide DRAM in~er~ace address IS tlme
mul~i~lexed over this 11 Di! wide t~us.
O The DRAM Row Address S~roDe signal
CA5[3:0~ O The DRAM Column Address StroDe 5~snal. One
signal is provided per Dyte of Ihe intertace s data
bus. All the CAS signals are driven simultaneo~!5~y
WE O The DRAM Write EnaDIe signal
i5E O The DRAM Output Enable 5ignal
DRAM_enabl- I This input signal, when low, makes ail the output
signals on the interface go high impedance.
Note: on-chip data p,ocess,ng is no~ stopped when
the DRAM interface is high impedance. So errcrs
wjll occur i~ the chip attempts to access '~RAM whiie
DRAM_enable is low
Table A.5.1 DRAM intertace signals
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186
In a~ordance with the present invention, the interface
is configurable in two ways:
.The detail timing of the interface can be
configured to accommodate a variety of
different DRAM types
.The "width" of the DRAM interface can be
configured to provide a cost/performance
trade-off in different applications.
A.5.3 Configuring the DRAM interface
Generally, there are three groups of registers
associated with the DRAM interface: interface timing
configuration registers, interface bus configuration
registers and refresh configuration registers. The refresh
configuration registers (registers in Table A.5.4) should
be configured last.
A.5.3.1 Conditions after reset
After reset, the DRAM interface, in accordance with the
present invention, starts operation with a set of default
timing parameters (that correspond to the slowest mode of
operation). Initially, the DRAM interface will continually
execute refresh cycles (excluding all other transfers).
This will continue until a value is written into
refresh_interval. The DRAM interface will then be able to
perform other types of transfer between refresh cycles.
A.5.3.2 Bus configuration
Bus configuration (registers in Table A.5.3) should only
be done when no data transfers are being attempted by the
interface. The interface is placed in this condition
immediately after reset, and before a value is written into
refresh_interval. The interface can be re-configured
later, if required, only when no transfers are being
attempted. See the Temporal Decoder chip_access register
(A.18.3.1) and the Spatial Decoder buffer manager_access
register (A.13.1.1).
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187
A.5.3.3 ~nterface timing configuration
In accordance with the present invention, modifications
to the interface timing configuration information are
controlled by the interface_timing_access register.
Writing 1 to this register allows the interface timing
- registers (in Table A.5.2) to be modified. While
interface_timing_access = 1, the DRAM interface continues
operation with its previous configuration. After writing
1, the user should wait until 1 can be read back from the
interface_timing_access before writing to any of the
interface timing registers.
When configuration is compete, 0 should be written to
the interface_timing_access. The new configuration will
then be transferred to the DRAM interface.
lS A.5.3.4 Refresh configuration
The refresh interval of the DRAM interface of the
present invention can only be configured once following
reset. Until refresh_interval is configured, the interface
continually executes refresh cycles. This prevents any
other data transfers. Data transfers can start after a
value is written to refresh_interval.
As is well known in the art, DRAMs typically require a
"pause" of between 100 ~s and 500 ~s after power is first
applied, followed by a number of refresh cycles before
normal operation is possible. Accordingly, these DRAM
start-up requirements should be satisfied before writing a
value to refresh_interval.
A.5.3.5 Read access to configuration registers
All the DRAM interface registers of the present
invention can be read at any time.
A.5.4 Interface timing (ticks)
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188
The DR~M interface timing is derived from a Clock which
is running at four times the input Clock rate of the device
(decoder_clock). This clock is generated by an on-chip
PLL.
For brevity, periods of this high speed clock are
referred to as ticks.
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189
A.S.S I~terface registers
Register name ~3 ci DescnDtion
i r
intertace_timing_access l O This tunctlon enable reSIs:er a,lows access ~o
bit :he DRAM intertace tlmlng ccntigura~on
registers. The configuraoon reSIstets should nol
rw ce modified while this register holds he value
0, Writing a one to this register recuess access
to modity bhe configurabon regis:ers. A~er a O
has been written to bhis regis~er the DR~,`.l
intertace will slarl to use the new values in tt~.e
timing configuration registers.
page_start_length 5 0 Specifies the length ot the access s~art .n ~cks.
bit The minimum value that can be used is 4
(meaning 4 bcks). O selecs the maximum
rw length ot 32 bcks.
transter_cyc~e_length 4 0 Specifies the length o~ the ~ast paSe read or
bit write cycle in ticks, The minimum value that can
be used is 4 (meaning 4 ticks). O s21ecs the
rw maximum length ot 16 bcks.
re~resh_cycle_length 4 0 Specifies the length of the retresh CyCle in ticks.
bit The minimum value that can be used is 4
(meaning 4 ticks). O selecs the maxlmum
rw length ot 16 ticks.
RAS_talling 4 0 Specifies bhe number ol ticks anem~,e start of
bit the access start that l~ ~alls. The minimum
value that can be used is 4 (meanins 4 ticks). O
rw selecs ~he maximum length ot 16 ccYs.
CAS_~alling 4 8 Specifies the number ol ticks aner ;he stan ol a
bit read cycle, write cycle or access s-art that
ialls. The minimum value that can ~ ~sed s
rw meaning l tick). O selecs the ma~imum len
ol 16 ticks.
Table A.5.2 Interface timing configuration registers
21~5159
190
Register name ~ Oescnption
DRAM_data_width 2 0 Soeclties the numt~er o~ bits used on r~e DRA M
bit in~ertace data bus DRAM_data[.,1:0]. See
A.5.9
rw
row_address_bits 2 0 Speafies the number of bits used ~or the row
bit address portion oi the DRAM intertace address
bus. See A.5.10
rw
DRAM_enaDle 1 1 Writing the value 0 in to lhis regis~er torces ~e
bit DRAM intertace into a high . I~eJ~l.e state.
0 will be read ~rom this register i~ either ~e
rw DRAM_enabl- signal is low or 0 has been
written to the register.
CAS_strengtll 3 6 Th~se thr-e bit registers configure the out~ut
RAS_strength bit drive strength o~ DRAM interface signals.
addr_strength
This allows the intertace to be configured ~or
DRAM_data_strength
rw various dit~erent loads.
OEWE_strength
See A.S. 13
Table A.5.3 Interface bus configuration registers
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A.5.6 ~I~terface operation
The DRAM interface uses fast page mode. Three different
types of access are supported:
.Read
.Write
.Refresh
Each read or write access transfers a burst of 1 to 64
bytes to a single DRAM page address. Read and write
transfers are not mixed within a single access and each
successive access is treated as a random access to a new
DRAM page.
Reslsler name ~ ~ OescriDtion
re~resh_interval 8 0 This value specihes tne interval between
bit refresh cycles in Deriods oi 16 decoder_clock
cycles. Values in the range 1..25; can be
rw configured. The value O is automa~ally loaCed
aner reset and lorces the DRAM intedace to
continuously execute re~resh cycles ~ntil a vaiid
retresh interval is configured. It is
r~:o.. ended that retresh_lnterval shculd be
configured only or~ce aner each reset.
no_retresh 1 0 Writing the value 1 to this register preven!s
bit execution ot any retresh cycles.
rv~
Table A.5.4 Refresh configuration registers
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A.5.7 .A~ces~ structure
Each access is composed of two parts:
.Access start
.Data transfer
In the present invention, each access begins with an
access start and is followed by one or more data transfer
cycles. In addition, there is a read, write and refresh
variant of both the access start and the data transfer
cycle.
Upon completion of the last data transfer for a
particular access, the interface enters its default state
(see A.5.7.3) and remains in this state until a new access
is ready to begin. If a new access is ready to
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begin when the last access has finished, then the new
access will begin immediately.
A.5.7.1 Access start
The access start provides the page address for the read
or write transfers and establishes some initial signal
conditions. In accordance with the present invention,
there are three different access starts:
.Start of read
.Start of write
.Start of refresh
Num. Cha. iali~. Min.Max. Unit Notes
RAS precharge period set by register 4 16 tic~
RAS_talling
6 Access start durabon set by register 4 32
page_s2an_1ength
7 CAS precharge iength set by register 1 16
CAS_talllng .
8 Fast page read or write cycle length set by 4 16
the register transfer_cycle_leng2h.
9 Retresh cycle length set by the register 4 16
retresh_cycle.
Table A.5.5 DRAM Interface timing parameters
a. This value must be less than RAS_falling to ensure
~ before RAS refresh occurs.
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In each ca~e, the ti~ing of RAS and the row address is
controllod by the registers RAS falling and
page start length. The state of OE and DRAM data~31:0] is
held from the end of the previous data transfer until **RAS
falls. The three different access start types only vary in
how they drive OE and DRAM_data[31:0] when RAS falls. See
Figure 43.
A.S.7.2 Dat~ tr~n-f-r
In the present invention, there are different types of
data transfer cycles:
.Fast page read cycle
.Fast page late write cycle
.Refresh cycle
A start of refresh can only be followed by a single
refresh cycle. A start of read (or write) can be followed
by one or more fast page read (or write) cycles. At the
start of the read cycle CAS is driven high and the new
column address is driven.
Furthermore, an early write cycle is used. WE is driven
low at the start of the first write transfer and remains
low until the end of the last write transfer. The output
data is driven with the address.
As a CAS before RAS refresh cycle is initiated by the
start of refresh cycle, there is no interface signal
activity during the refresh cycle. The purpose of the
refresh cycle is to meet the minimum RAS low period
required by the DRAM.
A.5.7.3 ~nt-rfac- ~-fault stat-
The interface signals in the present invention enter a
default state at the end of an access:
RAS, CAS and WE high
*data and OE remain in their previous state
.addr remains stable
A.5.8 Data bus width
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The~two bit register, DRAM_data_width, allows the width
of the DRAM interface's data path to be configured. This
allows the DRAM cost to be minimized when working with
small picture formats.
DRAM_dau_width
O' 8 bit wide data bus on DRAM_data[31:241~.
16 bitwide data bus on DRAM_data[31:16]'~l.
2 32 bit wide data bus on DRAM_daul31:0].
Table A.5.6 Configuring DRAM_data_width
a. Default after reset.
b. Unused signals are held high impedance.
A.5.9 row address width
The number of bits that are taken from the middle
lo section of the 24 bit internal address in order to provide
the row address is configured by the register,
row_address_bits.
~ow_addr ss_Oits Width oi row address
10 bits on DRAM_addr~9:0]
2 l l bits on DRAM_addr~ 10:0~
Table A.5.7 Configuring row address bits
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A.5.10~Address bits
On-chip, a 24 bit address is generated. How this
address is used to form the row and column addresses
depends on the width of the data bus and the number of bits
selected for the row address. Some configurations do not
permit all the internal address bits to be used and,
therefore, produce "hidden bits)".
Similarly, the row address is extracted from the middle
portion of the address. Accordingly, this maximizes the
rate at which the DRAM is naturally refreshed.
rowrow address
data buscolumn address Iransla~on
addresstranslation
widthinternal ~ external
widthinternal ~ external
9[14:6] 18:0] ~ [19:15] 0 ~10:6] ~5:0l :~ [5:0]
16 [20:15] O [10:5] [5:1] ~ [4:01
32 [21:15] o [10:4] [5:2] o [3:01
10[15:6] O [9:0] a [19:16] 0 [10:6] [5:0] c~ [5:01
16 [20:16lol1o:s] Is:1]0[4:0]
32 121:16l ~ I10:41 [5:2] O [3-:0]
1l66]~[lo:ol ~ 119171ollo6~ [50l~[sol
16 120:17JOI10:5] [5:1]0[4:0]
32 [21:171 O [10:4l ~s2!~ [3:01
Table A.5.8 Mapping between internal and external addresseS
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A.5.1~.1 Low order column address bits
The least significant 4 to 6 bits of the column address
are used to provide addresses for fast page mode transfers
of up to 64 bytes. The number of address bits required to
control these transfers will depend on the width of the
data bus (see A.5.8).
A.5.10.2 Decoding row address to access more DRAM banks
Where only a single bank of DRAM is used, the width of
the row address used will depend on the type of DRAM used.
Applications that require more memory than can be typically
provided by a single DRAM bank, can configure a wider row
address and then decode some row address bits to select a
single DRAM bank.
NOTE: The row address is extracted from the middle of
the internal address. If some bits of the row address are
decoded to select banks of DRAM, then all possible values
of these "bank select bits" must select a bank of DRAM.
Otherwise, holes will be left in the address space.
A.5.11 DRAM Interface enable
In the present invention, there are two ways to make all
the output signals on the DRAM interface become high
impedance, i.e., by setting the DRAM_enable register and
the DRAM-enable signal. Both the register and the signal
must be at a logic 1 in order for the drivers on the DRAM
interface to operate. If either is low then the interface
is taken to high impedance.
Note: on-chip data processing is not terminated when
the DRAM interface is at high impedance. Therefore, errors
will occur if the chip attempts to access DRAM while the
interface is at high impedance.
In accordance with the present invention, the ability to
take the DRAM interface to high impedance is provided to
allow other devices to test or use the DRAM controlled by
the Spatial Decoder (or the Temporal Decoder) when the
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Spatial ~ecoder (or the Temporal Decoder) is not in use.
It is not intended to allow other devices to share the
memory during normal operation.
A.5.12 Refresh
Unless disabled by writing to the register, no_refresh,
the DRAM interface will automatically refresh the DRAM
using a~~S before R~ refresh cycle at an interval
determined by the register, refresh_interval.
The value in refresh_interval specifies the interval
between refresh cycles in periods of 16 decoder_clock
cycles. Values in the range 1.255 can be configured. The
value 0 is automatically loaded after reset and forces the
DRAM interface to continuously execute refresh cycles (once
enabled) until a valid refresh interval is configured. It
is recommended that refresh_interval should be configured
only once after each reset.
While reset is asserted, the DRAM interface is unable to
refresh the DRAM. However, the reset time required by the
decoder chips is sufficiently short, so that it should be
possible to reset them and then to re-configure the DRAM
interface before the DRAM contents decay.
A.5.13 Signal strengths
The drive strength of the outputs of the DRAM interface
can be configured by the user using the 3 bit registers,
CAS_strength, RAS_strength, addr_strength,
DRAM_data_strength, and OEWE_strength. The MSB of this 3
bit value selects either a fast or slow edge rate. The two
less significant bits configure the output for different
load capacitances.
The default strength after reset is 6 and this
configures the outputs to take approximately 10ns to drive
a signal between GND and VDD if loaded with 24pF.
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s~enSth value Drive ,,h~ ,i5li"5
û Approx. 4 nsN inlo 6 pi load
Approx. 4 ns/V into 12 p~ load
2 Approx. 4 nsN into 24 pi load
3 Approx. 4 nsN into 48 p~ load
4 Approx. 2 ns/~ into 6 p~ bad
S Approx. 2 nsN into 12 p~ load
6- Approx. 2 nsN into 24 p~ load
7 Approx. 2 ns'V into 48 p~ load
Table A.S.9 Output strength configurations
a. Default after reset
When an output is configured appropriately for the load
it is driving, it will meet the AC electrical
characteristics specified in Tables A.5.13 to A.5.16. When
appropriately configured, each output is approximately
matched to its load and, therefore, minimal overshoot will
occur after a signal transition.
A.5.14 Electrical sp-cifications
All information provided in this section is merely
illustrative of one embodiment of the present invention and
is included by example and not necessarily by way of
limitation.
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Sym~ol Parameler Min. Max. Units
VDO SUPPIY voltage relatNe to GND -0.5 6.5 V
VIN Inputvoltageon any pin GND-û.5 VOO I 0 5 V
TA Operaong ~emperature 40 ~85 C
T5 S~orage lemperature -55 ~150 C
Table A.5.10 Maximum Ratings~
Table A.5.10 sets forth maximum ratings for the
illustrative embodiment only. For this particular
embodiment stresses below those listed in this table should
be used to ensure reliability of operation.
Symbol Parameter Min. Max. Units
VDD Supply voltage relatrve to GNO 4.~5 5.25 V
GNO Ground O O V
Vl~ Input logic ~1' voltage 2.0 VOO ~ o.5 V
Vl~ Input logic 'O' voltage GNO 0.5 0.8 V
TA Operabng temperature 0 70 C-
Table A.S.11 DC Operating conditions
a. With TBA linear ft/min transverse airflow
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SymDol Parameter Min. Max. Units
VOL Output logic '0' vollage 0.4 V '
VOH OUtPUt logic '1' voltage 2.8 V
lo Output current ~1 00
oz Output On state leakage current t 20 ~LA
llz Input leakage current ~ 10 I~A
loo RMS power supply current 500 mA
CIN Input capa~itdnce 5 pF
COUT OUtPUt /10 ca~lt.-nce 5 pF
Table A.5.12 DC Electrical characteri~tics
a. AC parameters are specified using VO,ma~ = 0.8V
as the measurement level.
b. This is the steady state drive capability of
the interface.
Transient currents may be much greater.
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A.5.14~-i AC characteristics
Num. Parameler Min.Max.Unil Note '
Cycle time -2 +2 ns
Il Cycletime 2 +2 ns
12 High pulse -5 +2 ns
13 Lowpulse -11 +2 ns
11 Cycletime -8 +2 ns
Table A.5.13 Differences from nominal valueQ for a strobe
a. As will be appreciated by one of ordinary skill in
the art, the driver strength of the signal must be
sconfigured appropriately for its load.
Num. Parame~er Min.Max.Unit No~e '
Strobe to strobe delay -3 +3 ns
16 Low hold time -13 +3 ns
17 Strobe to strobe precharge e.g. tCRP, -9 +3 ns
tRCS, tRCH, tRRH, tRPC
precharge pulse between any two S +2 ns
CAS signals on wide DRAMs e.g. tCP, or
between ~ rising and ~ ~alling e.g.
tRPC
18 Precharge tx~ore disable -12 +3 ns
Table A.5.14 Differences from nominal
values between two strobes
a. The driver strength of the two signals must be
configured appropriately for their loads.
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Num. P . e~er - Min.Max. Unlt No~e
19 Sel up t~me .12 +3 ns
~old ome -12 +3 ns
Address acoess time 12 +3 ns
22 Next valid atter stroOe 12 +3 ns
Table A.5.15 Difference~ from nominal
between a bus and a strobe
a. The driver strength of the bus and the strobe must
be configured appropriately for their loads.
Num Parameter Min.Max.Urit No~e
23 Read data set-up ome Delore CAS signal O n5
starts to rise
24 Read data hold time atter ~ signal r~s
starts ~o go high
Table A.5.16 Difference~ from nominal
between a bus and a ~trobe
When reading from DRAM, the DRAM interface samples
DRAM_data[31:0] as the ~ signals rise.
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Darameter parameter puunete-
name number nume numbe- name numt~er
IPC10 tRSH 16tRHCP 10
tCPRH
tRCl l tCSH tASR l 9
tRP12 tRWL tASC
tCP tCW~ ~OS
tCPN tRAC tRAH 20
tRAS 13 tOACltOE tCAH
tCAS tCHR tDH
ICAC tCRP 17 tAR
tWP tRCS tAA21
tRASP tRCH tRAL
tRASC tRRH tRAD 22
tACP~tCPA 14 tRPC
tRCD 15 tCP
tCSR tRPC
Table A.S.17 Cross-reference between "standard" DRAM
parameter names and timing parameter number~
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SECTIO~ A.6 Microprocessor interface (l~I)
A standard byte wide microprocessor interface (MPI) is
used on all chips in the video decoder chip-set. However,
one of ordinary skill in the art will appreciate that
microprocessor interfaces of other widths may also be used.
- The MPI operates synchronously to various decoder chip
clocks.
A.6.1 MPI signals
Input /
Signal Name ~escriplion
Outpul
enaOle[1:01 Input Two aclive low chip enables. Bo~ll must 3e low to
enaole accesses via the MPI.
rw Input High indicates that a device wishes to read values
~rom the video chip.
This signal should be stable while the chip is
enaOled.
addrtn:OI Input Address specifies one ol 2" locations in the chip s
memory map.
This signal should be stable while the chip is
enabled.
data~7:0] Output J bit wide data l/ O port. These pins are high
;",peJ~nce it either enable signal is hish.
Output An active low, open collector, interrupt request
signal.
Table A.6.1 MPI interface signal~
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A.6.2- ~1 electrical specifications
Symt~ol P~.. -"et~, Min. Max. Units
V~D Supply vol~age relathe to GND 0.5 6.5 V
VIN Input voltage on any pin GNO - 0.5 VDO 0.; V
T~ Operanng temperature -40 ,85 'C
Ts Storage lemperature 5; +150 ~C
Table A.6.2 Absolute Maximum Ratings-
Symool Parametet Min. Max. Units
V~0 Supply voltage relative ~o GNO 4.75 525 V
GNO Ground 0 0 v
V!~, Inputlogic'1'voltage 2.0 VDD, 05 V'
VIL Input logic ~0' voltage GND 0.s 0.8 v (-1
T~ Operating temperature 0 70 C~
Table A.6.3 DC operating conditions
a. AC input parameters are measured at a 1.4V
measurement level.
b. With TBA linear ft/min transverse airflow.
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Symt)d ParameIer Min. Ma~t. Units
vO, Output logic 'û' voltag- 0.4 V
Vo~x Open collector output logic '0' 0.4 v
voltage
vc~ Output logic '1' voltage 2.4 V
Outputcurrent 1 100 ~AD
lox Open colleclor output current 4.0 8.0 r.A '
loz Output ot~ state leakage cunent ~ 20 ~A
Inputlea~agecurrent ~10 ~A
l^o RMS power supply current 500 r,~
C,~ Input capa~.i~nc~ S pF
Cour Output / IO C.~p~itC.~ 5 D'
Table A.6.4 DC Electrical characteristics
a. lo<lo~
b. This is the steady state drive capability of
the interface. Transient currents may be
much greater.
c. When asserted the open collector lrq output
pulls down with an impedance of loon or less.
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A.6.2 .~r AC characteristics
Notes
Num. Char~ ter,,li Min. Max. Unit
Enable low penod lO0 ns
26 Enable high period 50 ns
27 Address or rw set-up to chip enaole 0 ns
28 Address or rw hold irom chip disaDle 0 ns
29 Output turn~n time 20 ns
Read dataaccess time 70 ns
31 Read data hold time S ns
32 Read data turr~oU time 20
Table A.6.5 Microprocessor interface read timing
a. The choice, in this example, of ena~le[0]
to start the cycle and enable[1] to end it
is arbitrary. These signal are of equal
status.
b. The access time is specified for a maximum
load of 50 pF on each of the data[7.0].
Larger loads may increase the access time.
Num. Cha,-,, l..isli, Min. Max. Unit Notes
33 Write data sel-up hme 15 ns
3.1 Write data hold ome o ns
Table A.6.6 Microprocessor interface write timing
a. The choice, in this example, of ena~le[0]
to start the cycle and enaDleL1] to end
it is arbitrary. These signal are of equal
status.
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209
A.6.3 Interrupts
In accordance with the present invention, "event" is the
term used to describe an on-chip condition that a user
might want to observe. An event can indicate an error or
it can be informative to the user's software.
There are two single bit registers associated with each
interrupt or "event". These are the cond i ti on event
register and the condition mask register.
A.6.3.1 condition event register
The condition event register is a one bit read/write
register whose value is set to one by a condition occurring
within the circuit. The register is set to one even if the
condition was merely transient and has now gone away. The
register is then guaranteed to remain set to one until the
user's software resets it (or the entire chip is reset).
The register is set to zero by writing the
value one
Writing zero to the register leaves the register
unaltered.
The register must be set to zero by user
software
before another occurrence of this condition can
be observed.
The register will be reset to zero on reset.
A.6.3.2 Condition ma~k regi~ter
The condition mask register is one bit read/write
register which enables the generation of an interrupt
request if the corresponding condition event register(s)
is(are) set. If the condition event is already set when 1
is written to the condition mask register, an interrupt
request will be issued immediately.
The value 1 enables interrupts.
The register clears to zero on reset.
Unless stated otherwise a block will stop operation
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after ge~erating an interrupt request and will re-start
operation after either the condition event or the condition
mask register is cleared.
A.6.3.3 Event and mask bits
Event bits and mask bits are always grouped into
corresponding bit positions in consecutive bytes in the
memory map (see Table A.9.6 and Table A.17.6). This allows
interrupt service software to use the value read from the
mask registers as a mask for the value in the event
registers to identify which event generated the interrupt.
A.6.3.4 The chip event and mask
Each chip has a single "global" event bit that
summarizes the event activity on the chip. The chip event
register presents the OR of all the on-chip events that
have 1 in their mask bit.
A 1 in the chip mask bit allows the chip to generate
interrupts. A 0 in the chip mask bit prevents any on-chip
events from generating interrupt requests.
Writing 1 to 0 to the chip event has no effect. It will
only clear when all the events (enabled by a 1 in their
mask bit) have been cleared.
A.6.3.5 The irq signal
The irq signal is asserted if both the chip event bit
and the chip event mask are set.
The irq signal is an active low, "open collector" output
which requires an off-chip pull-up resistor. When active
the irq output is pulled down by an impedance of 100Q or
less.
I will be appreciated that pull-up resistor of
approximately 4kn should be suitable for most applications.
A.6.4 Accessing registers
A.6.4.1 Stopping circuits to enable access
In the present invention, most registers can only
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modified if th- block with which they are as~ociated is
~t~pp~. Ther-fore, group6 of registers will normally be
associated with an access register.
The value 0 in an access register indicates that the
group of registers a~sociated with that access register
should not be ~odified. Writing 1 to an access register
reguests that a block be stopped. However, the block may
not stop immediately and block's acce~ register will hold
the value 0 until it is stopped.
Accordingly, user software should wait (after writing 1
to request access) until 1 is read from the access
register. If the user writes a value to a configuration
register while its access register is set to 0, the results
are undefined.
A.6.~.2 R-gi~t-r~ holding int-g-r-
The least significant bit of any byte in the memory mapis that associated with the signal data[0].
Registers that hold integers values greater than 8 bits
are split over either 2 or 4 consecutive byte locations in
the memory map. The byte ordering is "big endian" as shown
in Figure 55. However, no assumptions are made about the
order in which bytes are written into multi-byte
registers.
Unused bits in the memory map will return a 0 when read
2S except for unused bits in registers holding signed
integers. In this case, the most significant bit of the
register will be sign extended. For example, a 12 bit
signed register will be sign extended to fill a 16 bit
memory map location (two bytes). A 16 bit memory map
location holding a 12 bit unsigned integer will return a o
from its most significant bits.
A.6.~.3 ~-yhol-d addr-ss locations
In the present invention, certain less frequently
accessed memory map locations have been placed behind
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"keyho~e~". A "keyhole" has two registers associated with
it, a keyhole address register and a ~eyhole data register.
The keyhole address specifies a location within an
extended address space. A read or a write operation to the
keyhole data register accesses the location specified by
the keyhole address register.
After accessing a keyhole data register the associated
keyhole address register increments. Random access within
the extended address space is only possible by writing a
new value to the keyhole address register for each access.
A chip in accordance with the present invention, may
have more than one "keyholed" memory map. There is no
interaction between the different keyholes.
A.6.5 Special registers
A.6.5.1 Unused registers
Registers or bits described as "not used" are locations
in the memory map that have not been used in the current
implementation of the device. In general, the value O can
be read from these locations. Writing O to these locations
will have no effect.
As will be appreciated by one of ordinary skill in the
art, in order to maintain compatibility with future
variants of these products, it is recommended that the
user's software should not depend upon values read from the
unused locations. Similarly, when configuring the device,
these locations should either be avoided or set to the
value 0.
A.6.5.2 Reserved register~
Similarly, registers or bits described as ~reserved" in
the present invention have un-documented effects on the
behavior of the device and should not be accessed.
A.6.5.3 Test registers
Furthermore, registers or bits described as "test
registers" control various aspects of the device's
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213
testahility. Therefore, these registers have no
application in the normal use of the devices and need not
be accessed by normal device configuration and control
software.
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SECIION A.7 Clocksi
In accordance with the present inventions, many
different clocks can be identified in the video decoder
system. Examples of clocks are illustrated in Figure 56.
As data passes between different clock regimes within
the video decoder chip-~et, it is resynchronized (on-chip~
to each new clock. In the present invention, the maximum
frequency of any input clock iB 30 ~. However, one of
ordinary skill in the art will appreciate that other
frequencies, including those greater than 30MHZ, may also
be used. On each chip, the microprocessor interface (MPI)
operates asynchronously to the chip clocks. In addition,
the Image Formatter can generate a low frequency audio
clock which is synchronous to the decoded video's picture
rate. Accordingly, this clock can be used to provide
audio/video synchronization.
A.7.1 8patial D-co~-r cloc~ ~ignalJ
The Spatial Decoder has two different (and potentially
asynchronous) clock inputs:
InDut /
Signal Name Descnptlon
Output
coa-d-clock Input Thls c!oc~ controls ca;a :rans emn :o ~he coaea aa~a
port o~ the Spaual Decoder.
Cnchip this clock conUols tne processing of ~he
coded data until it reaches the coCed data t~ut~er.
~ecoder_clock Input The CecoCer ciock cor ~rols the malonty ol ~.e
pro:e5a~ lunctions cn tne Spa~lal ~ecoCer.
rhe decoder clock also controls the ~rans~er ol data
out o~ ~he Spatial Decod~r througn its output Dort
Tabl- A.7.1 8patial D-cod-r clock~
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A.7.2 T~por~l Decoder clock ~ign~ls
The Temporal Decoder has only one clock input:
Inpul /
Signal Name Oescription
Output
decoder_clock Input The decoder clock controls all o~ the prucessing
functions on the Temporal Decoder.
~lle decoder clock also controls ;ransler ol data in to
the Temporal Oeco~er through its input port and o~rt
via its output pon.
T~ble A.7.2 Temporal Decoder clock~
A.7.3 Electrical specifications
30 MH2
Num. Cha.. ~ ri,~ic Unit Note
Min. Ma~t.
Clock period 33 ns
36 Clock high period 13 ns
37 Clock low period 13 ns
Table A.7.3 Input clock requirements
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216
Symbol Parameler Min. Max. Units
VIH Input logic ~1' voltage 3.68 VOO + 0 s V
VIL Input logic 'O' voltage GND 0.5 1.43 V
loz Inputleakagecurrent ' 10 ~A
~able A.7.4 Clock input conditions
A.7.3.1 CMOS level~
The clock input signals are CMOS inputs. VIHmin is
approx. 70% of V,)D and V~Lma~ is approx. 30% of VDD. The
values shown in Table A.7.4 are those for VIH and VIL at
their respective worst case VDD. VDD=5. +- 25V.
A.7.3.2 Stability of clocks
In the present invention, clocks used to drive the DRAM
interface and the chip-to-chip interfaces are-derived from
the input clock signals. The timing specifications for
these interfaces assume that the input clock timing is
stable to within + 100 ps.
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SECTI~N A.8 JTAG
As circuit boards become more densely populated, it is
increasingly difficult to verify the connections between
components by traditional means, such as in-circuit testing
using a bed-of-nails approach. In an attempt to resolve
the access problem and standardize on a methodology, the
Joint Test Action Group (JTAG) was formed. The work of
this group culminated in the "Standard Test Access Port and
Boundary Scan Architecture", now adopted by the IEEE as
standard 1149.1. The Spatial Decoder and Temporal Decoder
comply with this standard.
The standard utilizes a boundary scan chain which
serially connects each digital signal pin on the device.
The test circuitry is transparent in normal operation, but
in test mode the boundary scan chain allows test patterns
to be shifted in, and applied to the pins of the device.
The resultant signals appearing on the circuit board at the
inputs to the JTAG device, may be scanned out and checked
by relatively simple test equipment. By this means, the
inter-component connections can be tested, as can areas of
logic on the circuit board.
All JTAG operations are performed via the Test Access
Port (TAP), which consists of five pins. The trst tTest
Reset) pin resets the JTAG circuitry, to ensure that the
device doesn't power-up in test mode. The tck (Test Clock)
pin is used to clock serial test patterns into the tdi
(Test Data Input) pin, and out of the tdo (Test Data
Output) pin. Lastly, the operational mode of the JTAG
circuitry is set by clocking the appropriate sequence of
bits into the tms (Test Mode Select) pin.
The JTAG standard is extensible to provide for
additional features at the discretion of the chip
manufacturer. On the Spatial Decoder and Temporal Decoder,
21451~9
- 2~8
there are 9 user instructions, including three JTAG
mandatory instructions. The extra instructions allow a
degree of internal device testing to be performed, and
provide additional external test flexibility. For example,
all device outputs may be made to float by a simple JTAG
sequence.
For full details of the facilities available and
instructions on how to use the JTAG port, refer to the
following JTAG Applications Notes. --
A.8.1 Conn-ction of JTaa pinJ in non-JTAa y-t-~
Signal Oirecnon C ~ ,~lion
trst Input This pin has an in~emal pull-up, ~ut must ~e taken
low at power-up even i~ the JTAG features are not
heing used. ThiS may be achieved ~y ccnnecting
tr5t in common with the chiD reset pin reset.
W Input These pins have internal pull-ups. and ~ay ~e len
tms d,xonn er if the JTAG circui ry is not ~eing used.
tck Input This pin does not have a pull-up, and snould be tied
to ground if the JTAG circuitry is not used.
tdo Ourput i ligh impedance ~IYcept during JTAG scan
oDerabons. Il JTAG is nol heing used, ~is pin may
~e le~t dis_onnc_~d.
Tabl- A.8.1 ~ow to conn-ct JTAG input~
`; 2145159
219
A.8.2 L~vel of Conformance to IEEE 11~9.1
A.8.2.1 Rulet3
All rules are adhered to, although the following should
be noted:
Rules Description
3.1.1(b) The trs~ pin is provid-d.
3.5.1(b) Guaranteed tor atl public instructions (see IEE-- 1149.1
5.2.1 (c)).
i.2.1 (c) Guaranteed tor all public instrucuons. For some private
instrucDons, the TDO pin may be active during any ot the
states Capture-DR, Exit1-OR, Exit-2-0R ~ Pause-DR.
s.3.1(a) Power on-reset is actlieved by use ol the trst pin.
62.1 (e.n A code tor the BYPASS instruction is loaded in the Tes1-Logic-
Reset state.
7.1.1(d) Un-allocated instruction codes are equivalent to 3YPASS.
7.2.1(c) There is no device ID register.
Table A.8.2 JTAG Rules
2145159
-
220
~ules Description
7.8.1 (b) Single-slep operatlon recuires e~ternal com~ol ol t~e system
clock.
7.9,1(... ,~ There is no RUNBIST lacility.
7,11 1(,,.) There is no IOCOOE insuuction.
7.12.1(.. ) There is no USERCOOE instrucDon,
a.1.1(~) There is no device ;dcnt,lic~t,on register.
8.2.1 (c) Guaranteec tor all puolic insuucoons. The apparent !ength ol
the path from tdi to Ido may chanse under certain
circumstances while private instruction codes are loaded,
8.3.1 (d-l) Guaranteed lo- all puOlic instrucbons. Oata may ~e loaded at
times other than on the rising edge o~ tck while private
instrucoons codes are loaded.
10,4,1 (e) Ouring INTEST, the system clock pin must ~e controlled
externally.
10.6.1 (c) During INTEsTl outPut pins are conUolled ~y data shitted in via
tdi.
T~ble A. 8 . 2 JTAG Rulet3
A. 8 . 2 . 2 Recomm-nd~tion~
necu",. , ~ Oescnption
3.2.1 (b) tck is a high 1.,, ~ce CMOS input.
3.3.1 (c) tm~ has a high ;~voJa~e pUII-uP-
3.6.1 (d) (Applies to use ol chip).
3.7.1 (a) (Applies to use o~ chip).
6.1.1(e) The SAMPLE/PRELOAO instruction code is ,oa~ec during
Capture-lR.
7.2.1 lt) The INTEST instrucoon is supported.
7.7.1(9) Zeros are loaded at system output pins dunng EXTEST.
7.7.2(h) All system outputs may be set high .,.~cda~cr.
7.8.1(t) Zeros are loaded at system input pins during INTEST.
8.1.1(d.e) Design-speclnc test r~ata registers are not put~licly a~cecci~le
Table A.8.3 Recommendations met
2145159
221
10.4. 1 (f) During EXTEST the signal driven into ~e on-chp logic from
the system clock pin is thal supplied e~temally.
Table A.8.4 Recommendation~ not implemented
A.8.2.3 Permissions
Pe ;ssions Description
3.2.1(c) Guaranteed lor all public instrucbons.
6.1.1(~) The inslrucDon regisler is not used to caplure des;sn-specific
i~ l . clion.
7.2.1(9) Several addilional public instructions are provided.
7.3.1 (a) Several private instruct~on codes are allocated.
7 3 1 (c) (Rule?) Such instrucOons codes are documented.
n 4 1 (~ Additional codes pertorm identically lo SYPASS.
10.1.1 (i) Each output pin has its own 3-state control.
10.3.1(h) A parallel lalch is provided.
10.3.1 (i j) During EXTEST input pins are controlled by dala shined in via
tdl.
10.6.1 (d e) 3-slate cells are not lorced inactive in the Test-Logic-Peset
state.
Table A.8.5 Permi~sions met
2145159
~,
222
SECTlON A.9 Spatial Decoder
30 MH7 operation
Decodes MPEG, JPEG & H.261
Coded data rates to 25 Mb/s
Video data rates to 21 MB/s
Flexible chroma sampling formats
Full JPEG baseline decoding
Glue-less DRAM interface
Single +5V supply
208 pin PQFP package
Max. power dissipation 2.5W
Independent coded data and decoder clocks
Uses standard page mode DRAM
The Spatial Decoder is a configurable VLSI decoder chip
for use in a variety of JPEG, MPEG and H.261 picture and
video decoding applications.
In a minimum configuration, with no off-chip DRAM, the
Spatial Decoder is a single chip, high speed JPEG decoder.
Adding DRAM allows the Spatial Decoder to decode JPEG
20 encoded video pictures. 720x480, 30Hz, 4:2:2 "JPEG video"
can be decoded in real-time.
With the Temporal Decoder Temporal Decoder the Spatial
Decoder can be used to decode H.261 and MPEG (as well as
JPEG). 704x480, 30Hz, 4:2:0 MPEG video can be decoded.
Again, the above values are merely illustrative, by way
of example and not necessarily by way of limitation, of
typical values for one embodiment in accordance with the
present invention. Accordingly, those of ordinary skill in
the art will appreciate that other values and/or ranges may
be used.
` 2145159
223
A. 9 .1 sSpatial Decoder Signals
Signal Name VO Pin Nurnber Descr~ptlon
coded_clock 1 182 Coded Oata Por~ Used to supply
coded_data[7:0~ I 172,171, 169, 168,167,166,164, codeo data o- Tokens to the Spatial
163 Oecooer.
coded_e~tn 1 174
coded_valid 1 162 See sections A10.1 and
cor ed_accePt O 161 A.4.1
byte_mode 1 176
enaolel 1 :1 1 126, 127 Miuo Processor Interface ~MPI ).
rv~ 1 125
addr~6:01 1 136,135,133,132, 131,130,128
daU~7:0~ 0 152,151.149,147,145,143,141 See section A.6.1
140
irq 0 154
DRAM-aata~31 :0~ VO 15,17,19, 20, 22, 25, 27, 30,31, DRAM Intertace.
33,35,38,39,42,44,47,49,57,
59,61,63,66,68,70,~2,74,76,
See section AS2
79,81,83,84,85
ORAM_addrl10:0] 0 184, 186,188,189,192,193,195,
197, 19~9, 200, 203
RAS O 11
CAS~3:01 0 2, 4, 6, 8
WE O 12
OE O 2U
DRAM_enable I 112
ou~_Cata[8:0] 0 88, 89, 90, 92. 93, 94, 95, 97, 98 Output Port.
out_estn 0 87
See #c30n A4.1
cut_valid 99
out_accept 1 100
tck 1 115 JTAG pon
tCi I 116
See 5ection A8
tco 0 120
tms I 117
trst 1 121
Ta~le A.9.1 Spatial Decoder signals
2145159
224
Signal Na~ UO Pin Number C)escnFtion
decoohr_clock 1 177 ~he main decoder cloclc See secoon
A.7
reset i 160 ReseL
Table A.9.1 Spatial Decoder signals (contd)
Signal Name UO Pin Num. Description
tphOish I 122 If override -1 Ihen ~phOish and tph1ish are
tph1ish 1 123 inputs ~or the on-chip t~vo phase clock.
override 1 110
For nomlal operation set override = O.
tphOish and tph1 ish are ignored (so connect
to GND o~ VOO~.
chiptest 1 111 Set chiptest = O to- normai operation.
tloop 1 114 Connect lo GND or VOO duing normal
operation.
amtest 1 109 If ramtest = 1 lesl ol the on-chip AAMs ¢
enaoled.
Sel ramtest = O tor normal operznon.
pllselect 1 178 It pll#hct = O the on-chip ph~e locked
loops are disaoled.
Sel pllsebct = 1 tor normal operalion.
Ii 1 180 Two clocks required oy ~e D~AM in~ertace
tq 1 179 during lesl operation.
Connecl lo GND or VDO duing normal
operation.
pdout 0 207 These two pins are cu~ o-ls ~or an
pdin 1 206 external filter tor Ille phase lock loop.
Table A.9.2 Spatial Decoder Test signals
2145159
225
Signal Name ~ Pill Signal Name Pin Signal Name Pin Signal Name Pin
nc 208 nc 156 nc 104 nc 52
test pln 207 nc 155 nc 103 nc S l
tes; p in 206 irq 154 nc 102 nc 50
GND 205 nc 153 VDD 101 DRAM_da~a~lSj 49
OE 204 data~7~ 152 out_accept 100 nc 48
DRAM_addr(0] 203 data~6] lSl out_~aiid 99 DRAM_da;a(161 47
VOD 202 nc 150 out_data[0] 98 nc 46
nc 201 data~S] 149 out_datat1] 97 GNC) 45
DRAM_addr~1] 200 nc 148 GND 96 DRAM_data~17l 44
DRAM_addr~2l 199 data~4] 147 out_data~2] 95 nc 43
GND 198 GND 146 out_data~3] 94 DRAM_data~181 42
DRAM_addrl3] 197 datal3] 145 out_data~4] 93 VDD 41
nc 196 nc 144 out_data~S] 92 nc 40
DRAM_addrl4] 195 data~2] 143 VDD 91 DRAM_data~l9] 39
VDD 194 nc 142 out_data~6] 90 DRAM_data~20] 38
DRAM_a~dr~S] 193 data~l] 141 out_data~7] 89 nc 37
DRAM_addrl6] 192 data~0] 140 out_data~8] 88 GND 36
nc 191 nc 139 out_extn 87 DRAM_data~21] 35
GND 190 VDD 138 GND 86 nc 34
DRAM_addr~7] 189 nc 137 DRAM_data~0]85 DRAM_~ata(221 33
DRAM_ar dr~8] 188 addr~6] 136 DRAM_data~l] 84 VDO 32
VDD 187 addr151 135 DRAM_data(2]83 DRAM_daul23] 31
DRAM_addrlg] 186 GND 134 VDD 82 DRAM_data[241 30
nc 185 addr[4] 133 DRAM_datat3181 nc 29
DRAM_addrl10] 184 addrl3] 132 nc 80 GNO 28
GND 183 addr~21 131 DRAM_daU[41 79 DRAM_dala[251 27
coded_c!ock182 addr~l] 130 GND 78 nc 26
VDD 181 VDD 129 nc 77 DRAM_data~26] 25
test pin 180 aCdr~01 128 DRAM_data~Sl76 nc 24
test pin 179 enable~0] 127 nc 75 VDD 23
test pin 178 enaDIe[l] 126 DRAM_dauj6] 74 DRAM_data(Z7~ 22
decoder_cloc~ 177 rw 125 VDD 73 nc 21
by.e_mode 176 GND 124 DRAM_data~7172 DRAM_data~28] 20
GND 175 test pin 123 nc 71 DRAM_datal29] l9
coded_extn 174 test pin 122 DRAM_daU~8] 70 GND S -
Table A.9.3 Spatial Decoder Pin Assignments
2145~59
.
226
Siglul N me Pin Signal Nan~ Pin Signal Name P!n Signal Name Pin
nc ~ 208 nc 156 nc 1 G4 nc 52
test pin 207 nc 155 nc 1 03 nc S l
test pin 205 ~rq 154 nc 102 nc 50
GND 205 nc 153 VO0 101 ORAM_data~151 49
OE 204 data[7] 152 ou~_accePt 1 C~ nc 48
DRAM_addr~0] 2û3 data(6] 151 out_valid 99 O~AM_data(16] 47
VD0 2û2 nc 150 out_datato] sa nc 46
nc 201 d-ta~Sl 149 out_data[11 97 GNO 45
ORAM_addr(11 200 nc 148 GN0 96 DRAM_data[173 44
DRAM_addr[2] 199 datat41 147 out_Cata~2] 95 nc 43
GND 198 GND 146 out_Cata(31 94 DRAM_datal18] 42
DRAM_addrl3] 197 data[31 145 out_daU[41 93 VDD 41
nc 196 nc 144 out_data[Sl 92 nc 4û
DRAM_addrt41 195 data~21 143 VDD 91 ORAM_data(191 39
VOO 194 nc 142 out_data(6] 90 DRAM_data~203 38
oRAM-addrts] 193 datat1] 141 out_datat73 89 nc 37
ORAM_addrt61 192 data[0l 140 out_datat81 88 GNO 36
nc 191 nc 139 ou~ean 87 DRAM_daut21] 35
GNO 190 VDD 138 GND 86 nc 34
DRAM_addr~ 189 nc 137 DRAM_data(0¦ es DRAM_data~22l 33
DRAM_addr(81 188 addr~61 136 DRAM_data(11 84 VDD 32
VOO 187 addrtS] 135 DRAM_dau~2] a3 DRAM_datat231 31
DRAM_addr~91 186 GNO 134 VOO 82 DRAM_data~243 30
nc 185 addr~4l 133 ORAM_data(3l 81 nc 29
DRAM_addrt10l 184 addrt31 132 nc 80 GNO 28
GND 183 addrl21 1 31 DRAM_datat41 79 DRAM_data(25] 27
coded_ctock 182 addr(13 130 GND 78 nc 26
VOD 181 VDD 129 nc 77 DRAM_datat26] 25
lest pin 180 ~ddrt01 128 DRAM_datatS] 76 nc 24
test pin 179 era~le[0] 127 nc 75 VDD 23
test pin 178 ena~[13 126 DRAM_datal6] 74 DRAM_datat27~ 22
decooer_clock 177 rw 125 VOO 73 nc 21
byte_mode 176 GND 124 DRAM_daul71 72 DRAM_data(28] 20
GNO 175 testpin 123 nc 71 ORAM_oatat29] 15
cooed_e~tn 174 testpin 122 DRAM_datal8] 70 sND ~8
Tab~e A.9.3 Spatial Decoder Pin Assignments
2145159
227
__ _
Sigral NarT~ Pin Signal Name Pin S;gnal Name ?in S,gnal Name Pin
r.c 173 trst 121 GND 69 DRAM_catal301 17
coCed_datal7i 172 tdo 120 OR~M_tata(9] 68 ne 16
~oded_data~61 171 ttC 119 nc 67 CRAM_datal31! 15
V00 170 V00 118 ORAM_dau~101 66 VD0 14
coded-datat5l 169 tms 117 VD0 6i nc 13
ccded-catat4l 168 tdi 116 X 64 ~E 12
ccCed_t~ata[31 167 tck 115 ORAM_data(11] 63 h~ 11
coded_data(21 166 test pin 114 nc 62 nc lO
GND 165 GN0 113 ORAM_datal121 61 GN0 9
coded-datatll 164 DRAM_~nable 112 GN0 60 ~;l a
coded_data[0] 163 teStpin 111 OR~M_datat13] 59 ~C
coded_valid 162 test pin 110 tlC sa ~[ ~ i 6
c~ded_accept 161 test pin 109 DRAM_datat141 67 VD0 5teset 160 ttC 108 VDD j6 ~21 4
V00 159 x 107 nc SS nc 3
nc 158 nc 106 nc 54 ~[31 2
nc 157 nc 1 OS nc i3
Table A.9.3 Spatial Decoder Pin Assignments (contdj
A.9.1.1 "nc" no connect pins
The pins labeled nc in Table A.9.3 are not currently
used these pins should be left unconnected.
A.9.1.2 V~ and GND pins
As will be appreciated by one of ordinary skill in the
art, all the V,,,, and GND pins provided should be connected
to the appropriate power supply. Correct device operation
~ 2145159
228
cannotr!b~ ensured unless all the V~ and GND pins are
correctly used.
A.9.1.3 Test pin connections for normal operation
Nine pins on the Spatial Decoder are reserved for
internal test use.
Pin number Connectlon
Connect lo GNO ior normal oCeraoon
Connect to VDO iOr normal oCe-ation
Leave Open Circwt tor momnal operaoon
Table A.9.4 Default test pin connections
A.9.1.4 JTAG pins for normal operation
See section A.8.1.
2145159
229
A. 9 . 2 Spatial Decoder memory map
Addr. (t~ex) Regist Narne See tat~le
OxOO ... Ox03 Interrupt service uea A.9.6
ox~4 ... Ox07 Input circuit registers A.9.7
Ox08 ... OxOF Start cod de~ector registers
Ox10.... 0x15 Butlerstart~upcontrolte9isters A.9.8
Ox16 ... Ox17 Not used
Ox18.... 0x23 DRAMhter~ace ~ u'~ .registers A.9.9
Ox24 .. . Ox26 ~m ~ manag-r acc ss and keyhole registers A.9. 10
ox27 Not used
Ox28 ... Ox2F Hunrrun decoder registers A.9.13
ox30.... 0x39 InvHsequ ntiserregisters A.9.14
Ox3A ... Ox3~ Not used
Ox3C Reserved
Ox30 ... Ox3F Not used
Ox40 ... Ox7F Test registers
Tabie A.9.5 Overview of Spatial Decoder memory map
2145159
.
230
Addr 3rt
~ ` ~ Regisler Nalr~ Page relerences
(hex) num
OxO0 7 chip_ ven~ CEO_EVENT 0
6 not uSed
S 111 gal_l-ngth_co~ml_event
SCo-lLLEGAL-LENGTH-couNT
4 resenred rnay read 1 or 0
SCO_JF~G_OVERLAPPlNG_STARr
3 JC; r r lng-start-event
SCO_NON_JPEG_OVERWPlNG_STAfiT
2 n 1~ : 9 ~ ~ ~_stan_event
SCO_ UNfJECOGNlSEO_START
stop_aner_picture_event
SCO_STOP_Af TER_PICTURE
0 non_allgned_surt_event
SCO_NON_ALlGNEO_STMr
OxO1 7 chlp_mask CED_MASI~_O
6 nol used
S Illegal_length_count_rrusk
4 reserved wrile O lo this location
SCO_JPEG_OVERLAPPlNG_SrART
3 non_ipe~c 1~ ~ g_sbrt_mask
2 u ~ 5 ~ ~_sbrt_rrusk
t stop_atter_picture_rnask
0 non_aligned_sbrt_mask
Ox02 7 Idct_too_~ev~_event IDCT DEFF NUM
6 idct_too_rnany_event IOCT SUPEf~_NUM
accept_enable_event 8S_STREAM_END_EV~NT
4 target_rnet_event 85_ TAf~GET MET EVENT
3 counUr_~lushed_too_e~rly_event
BS_FLUSI / 8EFORE_ TARCEr_MET_EVENT
2 counter_~lushed_event BS_fLUSH_EVENT
parser_event DEMUX_EVENT
0 hu~man_event IIUFFMAN_EVENT
Table A.9.6 Interrupt service area registers
2145159
.
23
AXr.Bn
~egistetName Page ~leer~,s
(he~) num
0~03 7 Ida_too_lew_m sk
6 idct_too_rt~ ny_mask
5 aecept_ena~le_mask
4 btget_met_mask
3 eounter_flushed_too_earlr_ttlask
2 counter_~lushed_mask
panet_mask
O huttman_m sk
Table A.9.6 Interrupt ~ervice area regi~ter~ (contd)
2145159
232
r
AddrBit
Register Name Page retor~noes
(heY) num
Ox04 7 coded_busy
6 enable_mpl_lnput
5 coded_e~tn
4 0 not used
OYOS 7 0 coded_data
OYO6 7:0 not used
OYO7 7 0 not used
ox03 71 not used
O ssan_cod-_d tenor_acce~
also Input_clrcuit_access
CEO_SCO_ACCESS
OYO9 7 4 not u#d CED_SCO_CON7ROL
3 stop_atter_p;nur
2 discard_er. nsbn_data
discard_user_data
0 Igno e_non_al;gned
oxOA 7 5 not us d CEO_SCO_STATUS
4 in#rt_sequenoe_start
3 discard_~ll_d~
2 0 stan_code_# rch
Table A.9.7 Start code detector and input circuit registers
,
21~159
233
AdCrait
R gist Name Pag- r~
(hex) num
OxOB7 0 Test register kngth_count
O~OC7 0
OxO~7 2 nol used
start_cod-_d tector_coding_stanoard
OxOE7 0 start_value
OxOF7 4 not used
3 0 plaure-number
Table A.9.7 Start code detector and input circuit registers tcontd)
AddrBit
Regist Name Page relerences
(hex) num
Ox 10 7 1 not used
O s~rtup_-cces~ CEO_BS_ACCESS
Ox 11 7 3 not used
2 0 bit_count_prescah CED 8S_PRESCALE
Ox12 7 0 bit_count_t rg t CED_~S_rA~GET
OX13 7 0 bit_count CED_BS_COUNT
OX14 7 1 not used
O o~chip_queu CED_~S_OUEUE
Ox15 7 1 notused
O enabh_stre~m CED_85_ENA8LE_MXT snu
Table A.9.8 Buffer start-up r~ e. :,
21451S9
-
234
- Addr. Bit
RerJist Name Page rekt_nces
(hex) num.
Cxla 7:5 not used
4:0 par~_start_iength
CEO_IT PAGE_SrAf~r LENGT7
- Ox19 7:4 not used
3:0 re d_cycte_kngth
OxlA 7:4 not used
3:0 ~rite_cycb_bngtn
Tab~e A.9.9 DRAM ;.,~ h ~e configuration .~;;,te,~
2145159
23~
Addr ~it
R gisler N~ Page reterences
(hex~ nu~L
Ox1e 74 notus d
3 0relresh_cycb_kngth
Ox1C 74notused
3 0CAS_tdling
Ox1 D 7 4no~ used
3 0RAS_hlling
Ox1E 71notu#d
OInt-rhc-_Umlng_ cc ss
Ox1 F 7 0tettesh_lnterval
Ox20 7not used
6 4DRAM_addr_strengtbt2 0
3 1CAS_I . ~th~2 0]
ORAS_,b. _ b~
Ox21 7 6 RAS_ `~ ~sU [1 0
5 3 OEWE_ tt~ p OI
2 0 DRAM_d ta_strength[2 0]
Ox22 7 ACCESS bit tor p d ~tr~tytb ~tc ?r~t
usedCED_ORAM_CONflGURf
6 ~ o_butrers
5 DRAM_enaOh
4 no_retresh
3 2 row_tddres5_bl~l1 OJ
10 DRAM_d t _~dtht1:0]
Ox23 7 0 Test registers CEO_PLL_RES_CONFIG
Tab~eA.9.9 DRAMi"t~ c~confi~u............ ,lionreg;cters (contd)
Addn Bit
Register Ntrrle Ptge reiçrerlccs
(hex) nurn~
Ox24 71 not used
O butler_rn n ger_acoess
Ox25 7 6 not used
5 0 buffer_rnar~ t~er_keyhde_address
Ox26 70 butter_rran ger_keyhole_d ra
Tab~e A.9.10 Buf~er manager access and keyho~e registers
21~5159
236
Addr. Bit
Regist r Narne Page re~ereneeS
(hex) num.
OxOO 7D not used
OxO1 7 2
1 0 cdb_base
Ox02 ~ 0
Ox03 7.0
Ox04 7:0 not used
OxOS 7~
1 :0 cdb_kngth
Ox06 7:0
Ox07 7:0
Ox08 7:0 not used
OxO9 7:0 cdb_read
OxOA 7:0
OxOB 7 0
OxOC 7 0 not used
OxOD 7.0 cdb_number
OxOE 7D
OxOF 7:0
Ox10 7:0 not used
Ox11 7D tb_b se
Ox12 7D
Ox13 7D
Ox14 7D not us d
Ox15 70 tb_kngth
Ox16 7:0
Ox17 7D
Ox18 7 0 nol used
Ox19 7:0 tb_r d
Ox1A 7 o
Ox1 B 7:0
Ox1C 7D notused
Ox1 D 7:0 tb_number
ox l E 7:0
oxt F 7D
Table A.9.11 Buffer ..-anager extended address space
21~5159
-
237
Add~ Blt
Regislet Narne Page relerences
~x) num.
Ox20 7 0 not used
Ox21 7 0 butler_limit
O~Z 7:0
Ox23 7:0
Ox24 7:4 not used
3 edb_tull
2 cdb_empty
tb_~ull
O tb_empty
Table A.9.11 Buffer ,.anager extended address space (contd)
Addr. Bit
F~egistet Name Page relerences
(hex) num.
Ox2~ 7 dhmus_access CED_H_Cr~
6:4 hutlman_ nor_code 2:01 OED_H_CT~Lt6:4]
3:0 prrvate hunrn n control bits l3] #lects special
CBP [2~ seiects 41~ bit fixed length CBP
OX29 7:0 pat#t_etto-_code CED_H_DhtUX_ER~
Ox2A 7:4 not u#d
30 d mux_keyho~e_addtess
Ox2B 7.0 CED_H KEYHOLE_ADDf~
Ox2C 7 0 demux_k~hoh_rbta CEO_H_KEYHOLE
Ox2D 7 dummy_bst_picture CED_H_ALU_f~EG0,
r_rlummy_bst_thn~e_bit
6 tield_into CED_H_ALU_REG0, r_field_in~o_bn
5:1 not used
0 continu CED_H_ALU_FtEG0, r_conbnue_~it
Ox2E 7:0 rom_rev~ion CED_H_ALLl_f~EG1
Ox2F 7:0 pnvate register
Tabie A.9.12 Video demux regi;.~ers
2145159
238
Addr. Bi^t
Register Name Page n~le._.~es
(hex) num.
Ox2F 7 CED_H_TRACE_EVNT write 1 to single step. one
will be read when the step has been compleled
6 CED_H_TRACE_MASK set to one lo entet single
step mode
CED_H_TRAC_RST panial resel when ser~uenc-d
1,0
4:0 nol u#d
Table A.9.12 Video demux regi~ters ~contd)
21~5159
.
-
239
. ..
ACdtBit
F~egister Narne Pase relerences
(hex) num
OxOO7 0 nol used
OxOF
Ox107 0 hort2~ r honz_oek
Ox1170
Ox127 0 vert_Dels t_wrt_oek
Ox137 0
ox 1 a 7 2 nol used
1 0 butler_si2e r_butrer size
Ox157 0
ox 16 7 4 nol used
3 0 p l_asp~ct r od aspect
Ox 17 7 2 not used
10 bit_rate r_bi~_Rh
Ox1e 7 0
Ox19 7 0
ox 1 A 7 4 nol used
3 0 pit_rate r Dit_rate
Ox1~ 7 1 nolused
O cc ~t ' ~ d r_c~,~t
OY1C 7 0 pitture_t~pe
OY 1 D 7 0 h261 _plc_type
Table A.9.13 Video demux extended address space (Shee~ 1 of 8)
2145159
240
Addr. Bit
RegistNarn Page r~ .~es
(hex) num.
Ox1 E 7.2 not used
1 :0 broixen_closed
Ox1 F 7:5 not used
4:0 p. ~ _mode
Ox20 7 0 vbv_delay
Ox21 7:0
Ox22 7:0priva~etegisluMPEG hll_pel_iwd JPEG
pendinrl frame_change
Ox23 7:0privateregislMPEGtull_pel_bwd JPEG
restan_index
Ox24 7:0privalo regisl hori2_mb_cooy
Ox25 7:0plc_number
Ox26 7:1nolused
1 :0max_h
Ox27 7:1nol used
1 :0m~x_v
Ox25 7:0privale register scratch1
Q~g 7:0privale regist scratch2
Ox2A 7:0privale regisler scralch3
Ox2B 7:0 Nt MPEG unused1 H261 ingob
Ox2C 7 0 priva r~gia MPEG 11 oroup~ JPEG ~rsl_scan
Ox2D 7 0 p ivate regist i~lPEG in_picturrS
Ox2E 7 dummy_bst_pictute e rom_con~ol
6 fi ld_lnto
5:1 nol used
O r;ontinue
Ox2F 7:0 rom_revis;on
Ox30 7.2 nol used
1 :0 dc_hutf_0
Ox31 7 2 nol used
1 :0 dc_hutt_1
Ox32 7 2 not used
1:0 dc h~m 2
Table A.9.13 Video demtJx extended address space (Sheet 2 ot 8)
2145159
241
Addr. Bit
Regisler Name Page reterenceS
(hex) nu~
Ox33 7~ not used
1.0 dc_hutt_3
Ox34 7 2 not used
1 :0 ~c_hun_O
Ox35 7 2 not used
1 :0 ac_nun_1
Ox36 7Z not used
1.0 ~c_hun_2
Ox37 7 2 not used
1 :o ~c_hun_3
ox38 7 2 not used
1 :0 tQO ~_~QO
Ox39 7Z no~ usad
1 :0 tQ1 t_~Q I
Ox3A 7 2 not used
1 0 tQ2 ~ tq 2
ox3e 7Z not used
1 :0 tQ3 ~ ~q 3
Ox3C 7:0 c ~n~ ,t_narne_Or_c_O
Ox3D 7:0 e ~r~ _narne_1 r_c_l
Ox3E 7:0 e . ~t_narn _2 r_c_2
Ox3F 70 c~ r r _n m-_3 r_c_3
Ox40 7:0 privat~ r~gisters
Ox63
Ox40 7 0 r_oc_ored_O
Ox41 7.0
Ox42 7 r_dc_pred_1
Ox43 7:0
Ox44 7:0 r_dc~red_2
Ox45 7 0
Ox4-5 7:0 r_dc_pr d_3
Ox47 7:0
Ox4~ 7:0 not use~
Ox4F
Table A.9.13 Video demux extended address space (Sheet 3 of 8)
2145159
Y~f
242
Addr. Bit
Regisl rName Page relerer~ce5
(hex) nurn.
Ox50 7.0 r_prev_mh~
Ox51 7:0
Ox52 7 0 r_prev_mvS
Ox53 7 0
' Ox54 7:0 r_prev_mhb
OxS5 7.0
Ox56 7:0 r_prev_mvb
Ox57 7:0
Ox58 7 0 no~ used
OxSF
Ox60 7 0 r_horiz_mbcn~
Ox61 7:0
Ox62 7:0 r_ver~mbcnt
Ox63 7.0
Ox64 7:0 horiz_ ~ e ~ ~c ~ r_hori~mbs
Ox6; '-
Ox~6 7 0 vert_. ~lc 1( r_vert_mbs
Ox67 ':
Ox6a 7:0 private regis:err_restart cnt
Ox69 7:0
Ox6A 7:0 rt-rt_lnterv l r_rrtstut_int
Ox6B 7:0
Ox5C 7:0 private regist r_blk_h_cnt
Ox60 7:0 privare regisler r_blk_v_cnt
Ox6E 7:0 privale regisler r_compid
Ox6F 7:0 rrux__ ~ Yl~ id r_max_compid
Ox70 7:0 coding_~Undard r_coding_sld
Ox71 7:0 private register r_patlem
Ox72 7:0 prrvate regisler r_t~d_r_size
Ox73 7:0 pdvate register r_bwd_r_size
Ox74 7:0 not used
0~77
Ox7~ 7 2 not used
1 :0 blr cks_h_0 r_blk_h_0
Tab~e A.9.13 Video demux e~t~nded address space (Sheet 4 of 8)
214~159
-
243
ACd~. 8it
r Register Name Page re~e-ences
(hex) num.
Ox797:2 nol used
blocks_h_1 r_blk_h_1
Ox7A 7~ not used
1 0 blocks_h_2 r_blk_h_2
Ox78 7~ not used
1 0 blocks_h_3 r_blk_h_3
Ox7C 7 not used
1 0 blocks_v_0 r_blk_v_0
Ox7D 7~ noi used
10 blocks_v_1 r_blk_v_1
Ox7E 7 2 not used
1 0 blocks_v_2 r_blk_v_2
Ox7F 7 2 no~ used
1 0 blocks_v_3 r_blk_v_3
Ox7F 7:0 not used
OxFF
Ox100 7 0 dc_bits_0[15:0] CED_H_KEY_DC_CPBO
Ox1OF
Ox110 7:0 dc_bits_1[15:0]CED_H_KEY_DC_CPB1
Ox11F
Ox120 7 0 nol used
Ox13F
Ox140 7.0 ac_bits_OllS:O]CED_H_KEY_AC_CPBO
Ox14F
OxlS0 70 c_bits_1~15:0] CED_H_KEY_AC_CPB1
Ox1 SF
Ox 160 7 0 not used
Ox17F
Ox180 7:0 dc_2ssss_0CED_H_KEY_ZSSSS_lNDEXO
Ox181 7:0 dc_~sssS_l CED-H-KEy-zssss-lNoEx1
oX182 7:0 nol used
0~ 1 ~7
oX188 7:0 ac_eob_0 CED_H_KEY_EOB_lNDEXo
Table A.9.13 Video detllux extended address space (Sheet S of 8)
2145159
244
~ddr. ~tt
Register Narne Pase telerences
(b~x) num.
0x189 7:0 ac_ ob_1 CED_H_KEY_EOB_INDEX1
0x18A 7 0 not used
oxlsa
0x18C 7:0 8c_~rl_0 CED_H_KEY_ZRL_INOEX0
0x180 7:0 Jc-~rl-1 CED_H_KEY_ZRL_INDEX1
0x18E 7:0 notused
0x1FF
0x200 7:0 ac_hut~val_0~161:0]CED_H_KEY_AC_lTOO_o
0x2AF
0x280 7 0 dc_hut~1_0[11:0JCED_H_KEY_0C_lTOo_o
0x2BF
0x2C0 7:0 not used
0x2FF
0x300 7:0 ac_hu~tvsl_1[161:0~ CED_H_KEY_AC_ITOO_l
0x3AF
0x3B0 7:0 dc_hllmtsl_l[l1:0] CED_H_KEY_DC_ITOD_l
0x3BF
0x3C0 7:0 not used
0x7FF
Ox800 7:0 pnvate registers
OxAC
F
0x800 7:0 CED_KEY_TCOEFF_CPB
0x80F
0x810 7:0 CED_KEY_CBP_CPB
0x81F
0x820 7:0 CED_KEY_MBA_CPg
0x82F
0x830 7:0 CED KEY MVD_CP9
0x88F
0x840 7:0 CED_KEY_MTYPE_I_CPB
0x84F
Tab~e A.9.13 Video demux extended address space (Sheet 6 ot 8)
21~515~
- 245
Addr. Bn
Reg~l Name Pa5e~cte.c~
~ex) nu~
Ox850 7:0 CEO_KEY_MTYPE_P_CPB
Ox85F
Ox860 7:0 CED_KEY_MTYPE_B_CPB
Ox86F
Ox870 7:0 CED KEY_MTYPE_H261_CP3
Ox88F
Ox880 7.0 nolused
Ox900
Ox901 7:0 CED_KEY_HOSTROM_0
0x902 7:0 CED_KEY_HOSTROM_1
0x903 7:0 CED_KEY_HDSTROM_2
Ox90F
0x910 7:0 notu~d
0xA3
F
0xAC 7:0 CED_KEY_DMX_WORD_0
o
0xAC 7:0 CED_KY_DMX_WORD_l
0xAC 7:0 CED_KEY_DMX_WORD_2
0xAC 7:0 CED_KEY_DMX_WORD_3
0xAC 7:0 CED_KEY_DMX_WORD_4
0xAC 7:0 CED_KEY_DMX_WORD_5
s
CxAC 7:0 CED_KEY_DMX_WORD_6
~AC 7:0 CED_KEY_DMX_WORD_7
Ta~e A.9.13 V~deo demux e.~- nded address space (Sheet 7 of 8)
2145159
, ,
246
Addr. Bit
Re,qister Name Page rele~ences
ex) num.
OxAC 7:0 CED_KEY_DMX_WORD_8
OxAC 7:0 CED_KEY_DMX_WOQD_9
-
OxAC 7:0 nol used
A
OxAC
B
OxAC 7:0 CED_KEY_DMX_AINCR
C
OxAC 7:0
D
OxAC 7:0 CED_KEY_DMX_CC
E
OxAC 7:0
F
Table A.9.13 Video demux extended address space (Sheet 8 of 8)
Addr. Bit
Register Name Page re~erences
(llex) num.
7:1 not used
Ox30 7:1 not used
0 Iq_access
Ox31 7 2 not used
1 :0 lo_coding_s2andard
Ox32 7:5 nol used
4:0 lest r-gister ir scate
Ox33 7 ~ no~ u#d
1:0 test register h_component
Ox34 7 ~ not used
1:0 ~esl re,qister inverse_quantiser_o.~ n_mode
Ox35 7:0 testregister jpcc: .d' ~ t; n
Table A.9.14 Inverse quant;ser registers
2145159
247
Aod~. Bd
Regis~er Name Pac~e relerences
(hex) num.
Ox36 7 2 notused
1:0 test register mpeg_;nd;.ec~ion
Ox37 7:0 not used
Ox38 7:0 ir table_keyhole_address
Ox39 7:0 Iq t~able_keyhole_data
Table A.9.14 Inverse quantizer regi~ter~ ~contd)
Addr.
Register Name Pase re~etences
(hex)
OxOO:Ox3f JPEG Inverse quantlsaaon taDle 0
MPEG delault inUa ~able
Ox40:0x7F JPEG Inverse quan~lsanon table 1
MpEG delault non-inUa table
OxBO:OxBF JPEG Inverse quan~isaDon table 2
MPEG down-loaded intra table
OxCO:OxFF JPEG Inverse quantisa~on table 3
MPEG down-loaded non-intra table
Table ~.9.15 Iq table extended addres~ space
21~51~9
248
SECTrO~ A.10 Coded data input
The system in accordance with the present invention,
must know what video standard is being input for
processing. Thereafter, the system can accept either pre-
existing Tokens or raw byte data which is then placed intoTokens by the Start Code Detector.
Consequently, coded data and configuration Tokens can be
supplied to the Spatial Decoder via two routes:
The coded data input port
The microprocessor interface (MPI)
The choice over which route(s) to use will depend upon
the application and system environment. For example, at
low data rates it might be possible to use a single
microprocessor to both control the decoder chip-set and to
do the system bitstream de-multiplexing. In this case, it
may be possible to do the coded data input via the MPI.
Alternatively, a high coded data rate might require that
coded data be supplied via the coded data port.
In some applications it may be appropriate to employee a
mixture of MPI and coded data port input.
2145159
249
A.10. ~ he coded data port
Input /
Signal Name Oescription
Output
cod-d_clockInput A clock op-rating at up to 30 MHz controlling the
operation ot the input circuit
coded_daUt7 0l Input Th- standard 11 v~ires required to implemen~ a
cod-d_ xtn~nput Token Pon tl " ,;"9 8 bit data values See sec~on
coded valid Input
A 4 hr an electrical des, "L ~ ~ of this
coded_accept Output
int-rtace
Circuits ott-chip must package ~he coded data imo
Tokens
b~t-_mod- Input Wh-n high this signal indicales that intommation is lo
be t~ ~.r ;~ I,d aoss the coded da~a ponHn byre
mode rather than roken mode.
Table A.10.1 Coded data port signals
2145159
250
Th~c4ded data port in accordance with the present
invention, can be operated in two modes: Token mode and
byte mode.
A. 10.1.1 Token mode
In the present invention, if byte_mode is low, then the
coded data port operates as a Token Port in the normal way
and accepts Tokens under the control of coded_valid and
coded_accept. See section A.4 for details of the
electrical operation of this interface.
The signal byte_mode is sampled at the same time as data
[7:0], coded_extn and coded_valid, i.e., on the rising edge
of coded_clock.
A.10.1.2 Byte mode
If, however, byte_mode is high, then a byte of data is
transferred on data[7:0] under the control of the two wire
interface control signals coded_valid and coded_accept. In
this case, coded_extn is ignored. The bytes are
subsequently assembled on-chip into DATA Tokens until the
input mode is changed.
l)First word ("Head") of Token supplied in token mode.
2)Last word of Token supplied (coded_extn goes low).
3)First byte of data supplied in byte mode. A new
DATA Token is automatically created on-chip.
A. 10 . 2 Supplying data via the MPI
Tokens can be supplied to the Spatial decoder via the
MPI by accessing the coded data input registers.
A. 10 . 2 .1 Writing Tokens via the MPI
The coded data registers of the present invention are
grouped into two bytes in the memory map to allow for
efficient data transfer. The 8 data bits, coded_data[7:0i,
are in one location and the control registers, coded_busy,
enable mpi input and coded extn are in a second location.
21451f~9
251
(Se~Table A.9.7).
When configured for Token input via the MPI, the current
Token is extended with the current value of coded_extn each
time a value is written into coded_data[7:0]. Software is
responsible for setting coded_extn to 0 before the last
word of any Token is written to coded_data[7:0].
For example, a DATA Token is started by writing 1 into
coded_extn and then Ox04 into coded_data[7:0]. The start
of this new DATA Token then passes into the Spatial Decoder
lo for processing.
Each time a new 8 bit value is written to
coded_data[7:0], the current Token is extended. Coded_extn
need only be accessed again when terminating the current
Token, e.g. to introduce another Token. The last word of
the current Token is indicated by writing 0 to coded_extn
followed by writing the last word of the current Token into
coded data[7:0~.
Register nam- ~ ~ D~L ;ption
coded_ertn 1 ~ Tokens can b- supplied lo ~he Spatlal- Oecocer
rw via the MPI 0y wriOng to these reglstets
coded_e-tat7:
w
coded_busy 1 1 ~he state of this registers In~icates If he
r Spatial Decoder is able to aceept Tokens
w,inen into cod-d_d-tat7 0]
Th- value l indicates that the intertace is 0usy
and unabl- to accept data 9ehaviour is
undefined i~ the us- tnes to write to
cod-d_datat7 0l when CodQd_0uSy = l
enable_mpl_input 1 ~he vatue in this function enaDle reglsters
rw controls whether coded data input ~o the Spatial
Decoder is via the cod-d tata porl (0) or via~e
MPI (1)
Table A.10.2 Coded data input registers
` 2145159
252
Each ~ime before writing to coded_data[7:0], coded_busy
should be inspected to see if the interface is ready to
accept more data.
A.10.3 Switching between input modes
Provided suitable precautions are observed, it is
possible to dynamically change the data input mode. In
general, the transfer of a Token via any one route should
be completed before switching modes.
Previous mode Nert Mode Behaviour
Byte Token The on-chip circuitry will use the last byte supplieJ;n
MPI input byte mode as the last byte of the DATA Token that
it was construcbng (i.e. the e~tn bit w~ll be set to ~).
Before accepting the next Token.
Table A.10.3 Switching data input modes
214515~
253
PreV103 moae Ne~ McCe 8ehavlour
oke~ 3~ rhe on~hlp c;~cu~try sucp~ying~he roken In T~ken
moCe is r~por.s ~ e or comolet;n5 t~e Token i.e.
with the extn ~ t ~ ~he last ~e of Ir~or-a~ion se~to
O) ~e~ore selecting ~y~e mo~e.
UPI in~ut Access to Input vla t~e .UPI Wlll nct te ~ran~e~ (-.e.
c~ded_busy ~11 remaln set lo, ) ~In~il .,~e On~.~p
circuitly sucplyin~ :he Token in T~ ~en .~oCe has
completea t~ Token (i.e. with :~e e~ t o~tt~e last
byte o~ n~ t o~ set to 0).
MPI input ~ The conUol sof~ must have !^m~le!eC~le
MPI input Token (i.e. WIC~ U e ex~n bit o~ the l~s~ e o~
set to O) be~ore enable_mpi_inpu~ ~s set
toO.
Table A.10.3 Switching data input modes (contd)
The first byte supplied in byte mode causes a DATA Token
header to be generated on-chip. Any further bytes
transferred in byte mode are thereafter appended to this
DATA Token until the input mode changes. Recall, DATA
Tokens can contain as many bits as are necessary.
The MPI register bit, coded busy, and the signal,
coded_accept, indicate on which interface the Spatial
decoder is willing to accept data. Correct observation of
these signals ensures that no data is lost.
A.10.4 Rate of accepting coded data
In the present invention, the input circuit passes
Tokens to the Start Code Detector (see section A.ll). The
Start code Detector analyses data in the DATA Tokens bit
serially. The Detector's normal rate of
2145159
~,
254
proce~ing is one bit per clock cycle (of coded_clock).
Accordingly, it will typically decode a byte of coded data
every 8 cycles of coded_clock. However, extra processing
cycles are occasionally required, e.g., when a non-DATA
Token is supplied or when a start code is encountered in
the coded data. When such an event occurs, the Start Code
Detector will, for a short time, be unable to accept more
information.
After the Start Code Detector, data passes into a first
logical coded data buffer. If this buffer fills, then the
Start Code Detector will be unable to accept more
information.
Consequently, no more coded data (or other Tokens) will
be accepted on either the coded data port, or via the MPI,
while the Start Code Detector is unable to accept more
information. This will be indicated by the state of the
signal coded_accept and the register coded_busy.
By using coded_accept and/or coded_busy,the user is
guaranteed that no coded information will be lost.
However, as will be appreciated by one of ordinary skill in
the art, the system must either be able to buffer newly
arriving coded data (or stop new data for arriving) if the
Spatial decoder is unable to accept data.
. A.10.5 Coded data clock
In accordance with the present invention, the coded data
port, the input circuit and other functions in the Spatial
Decoder are controlled by coded_clock. Furthermore, this
clock can be asynchronous to the main decoder_clock. Data
transfer is synchronized to decoder_clock on-chip.
2145159
~,
255
SECTrON A.ll Start code detector
A.11.1 Start codes
As is well known in the art, MPEG and H.261 coded video
streams contain identifiable bit patterns called start
codes. A similar function is served in JPEG by marker
codes. Start/marker codes identify significant parts of
the syntax of the coded data stream. The analysis of
start/marker codes performed by the Start Code Detector is
the first stage in parsing the coded data. The Start Code
Detector is the first block on the Spatial Decoder
following the input circuit.
The start/marker code patterns are designed so that they
can be identified without decoding the entire bitstream.
Thus, they can be used in accordance with the present
invention, to help with error recovery and decoder start-
up. The Start Code Detector provides facilities to detect
errors in the coded data construction and to assist the
start-up of the decoder.
A.11.2 Start code detector registers
As previously discussed, many of the Start Code Detector
registers are in constant use by the Start Code Detector.
So, accessing these registers will be unreliable if the
Start Code Detector is processing data. The user is
responsible for ensuring that the Start Code Detector is
halted before accessing its registers.
The register start_code_detector_access is used to halt
the Start Code Detector and so allow access to its
registers. The Start Code Detector will halt after it
generates an interrupt.
There are further constraints on when the start code
search and discard all data modes can be initiated. These
are described in A.11.8 and A.11.5.1.
21~515g
256
Regisler name ~ ~ Descr:phon
~ rQ
slart-code-detector-access 1 0 Wribng 1 lo this regls;er requeS~5 that the s;a
rw code detector stop lo allow access to i;s
registers. rhe user shou~d alt until l~e value
can be read ~rom t~is recister indicat~ng 1hal
ooerabon has stopped and access is ~osslble.
Table A.11.1 Start code detector
registers (Sheet 1 of 5)
214S159
257
Register name ~ = Descr:ption
illegal_l-ngth_count_event ' O An illegal len9th count evenl wlll occur ri wn~ie
rw decoding JPEG data, a length count fieid ;s
illegal_length_count_m sk 1 0 ~ound carrying a value less than 2. This should
rw only OCCu' as the re5ult o' an error in the JPEG
data.
1~ the mask register is set to 1 then an interrupt
can b- generated and the start code detector
will stop. Behaviour lollowing an error is nol
pl~cii-,tdb:e i~ this error is suppressed (mask
regislrtr set to 0). See A. 1~ .4.1
peg_overlapping_stan_event 1 0 ~ the coding standard is JPEG and the
~w sequence OxFF OxFF is lound while looking lor
peg_o~er app ng_start_rrtask 1 0 a marker code this event will occur.
rw This sequence is a legal stut~ing seCuence.
I~ the mask register is set to 1 then an interrupt
can be generated and the s~art code detector
~vill stop. See A. 11.4.2
o~.ldpp;ng_sart_event ' O 1~ the coding standard is ~1PEG or H ~61 and
rw an o:c.lc~p;,.. ,i startcode is ~ound whiie looking
~ r F ng_start_rn~t5k 1 0 lor a start code this event will occur. Il the masK
~w register is set to 1 then an interrupt can ~e
generated and the start code detector will stcp.
S-e A 11.4.2
Table A.11.1 Stan code det~ctor t~gistLrs (Sheet 2 ot 5)
2145159
Regis~er name 3 0 Descrip~lon
ur.rco~gn,;cd_sUn_event 1 0 I' an u",~:ogn.~cd s;an coCe l5 encounterec
rw this event will OCCUt. If the mask reslster is set
ur.. ~cr,gniscC_stan_mask 1 0 to 1 then an internup~ can be generaIed and the
rw start code detector will stop.
stan_value 8 x The stan code value read ~rom ;he cits:ream .s
~O available in the register slan_value while :t e
start code detecror is halted. See A.11.4.3
~uring normal operation stan_value comains
the value oi the most recently decoCed s;anl
marker code.
Only the 4 LS3s ot starn_value are used during
H.261 operaoon. The 4 ~1S~s will be zero.
stop_anet_picture_event 1 0 It the resister stop_aner_picture is set ~o 1
rw then a stoP aher picture event will be generated
stop_atter_plcture_mask 1 0 aner the end ol a plcture has passed through
rw the start code detector.
stop_atter_pictur- 1 0 It the mask register is set to 1 then an in~errupt
rw can be generated and the start code cetec:or
will stop. See A.11.5.1
stop_atter_picture does not reset to 0 ansr
the eno ol a picture has been detected so
should be cleared directly.
Table A.11.1 S~art code detector registers (Sheet 3 of 5)
2145159
.
259
~,
Registet name a~ ~7 Desc~ivtion
non_aligned_stan_event 1 0 When ignore_non_aiigned is set to 1, s:ar
rv~ codes that are not byte aligned are ignored
non_allgned_stan_rnask 1 0 (trea~ed Ae normal dala).
rw When ignore_non_a~igned is set to O ,il 251
ignore_non_alisned 1 0 anC MpEG start codes will ~e de1ect~
rw reg"~ s~ o~ byte alignment and the non-
aligned stan event will be generated
l~ the mask register is set ~o 1 then ~he event
will cause an interrupt and Ihe slan coCe
delector will slop. See A.11.6
l~ the coding s;andatd is configured 25 Ui~cD~
Ignore_non_aligned is ignored andt~e nan- i.
aligned stan event will never be generated.
discara_enension_data 1 1 When these regislers are set to 1 ex~ension cr
rw user data ~hat cannot be decoded by~e
alscard-user-data 1 1 Spatial Dacoder is discarded by the star. code
rw delector. See A.11.3.3
discard_all_data 1 0 When se~ to 1 all data and Tokens are
rw discarded ~y the stan code delector. This
continues until a FLUSH Token is supp!ied or
the register is set to O direcUy.
~he FLUSH Token Uhat resets this reg-s:er s
discarded and no~ output ~y ~e start coce
delector. See A.11.5.
insert_se~uence_start 1 1 See A.11.7
Table A.11.1 Start code detector regiSters (Sheet 4 of 5)
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260
~egister name ~ ~,, D~r,o~4n
i~ '
starS_code_search 3 5 When this registems set to 0 :ne s:an code
r~v detector operates normally. When se~ to a
higher value the star~ coCe r~elec~cr d~so2-~s
Cata unlil L~le specified ~y,.e o~ ssarl cxe Is
detected. When the s,oec:Geo s:2.1 c3de s
Cetected the register is ses :o C and narrnal
ope-ation 'ollows. See A. 11.3
start_coae_detector_coding_standard 2 0 This register configures the ccd ng sl2n:ar~
rw used by the star. coce Ce!~:^c ~he seris;er
can be loaded direct~y or ~y us:ng a
CODING_STANDARD roken
Whenever G~e slan code Ce!ector ~enerates a
CODING_STANDARD ,oken (see Ç
A.~ 1.7.4 it ca.~ies its c.,rrer~l
coding standard confisura~ .n., his Tcken wlil
then configure the coding sænc~ard usec ~y all
other parts ol the decoder chip-se~. See A.21. 1
~d A,11.7
picsure_number 4 0 Each bme the stan coded ~etec:cr de!ec:s a
rv,~ picture stan code in the C2'.2 s-ream (cr ~~.e
H,261 or JPEG ecuivalent~ a
PICTUR~_START Token is gener2te~
which carries the current value of
piCSure_number, ~his rec,is;er then
incre"ær,b.
Table A.11.1 Start code detector registers (Sheet 5 of 5)
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~eSister name ~ Descnption
u~
leng~h_count 16 0 This regist-r contains U7e current value ot tr~e
JPEG lengD'I count. This registet ~ modifie~
under tlle con~ol ol ~he coded Cata cJock an~
should only be read via ~e MPI w~en ~he start
code detoctor is stopped.
Table A.11.2 Start code detector test registers
A.11.3 Conversion of start codes to Tokens
In normal operation the function of the Start Code
Detector is to identify start codes in the data stream and
to then convert them to the appropriate start code Token.
In the simplest case, data is supplied to the Start code
Detector in a single long DATA Token. The output of the
Start Code Detector is a number of shorter DATA Tokens
interleaved with start code Tokens.
Alternatively, in accordance with the present invention,
the input data to the Start Code Detector could be divided
up into a number of shorter DATA Tokens. There is no
restriction on how the coded data is divided into DATA
Tokens other than that each DATA Token must contain 8 x n
bits where n is an integer.
Other Tokens can be supplied directly to the input of
the Start Code Detector. In this case, the Tokens are
passed through the start Code Detector with no processing
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to oth~r ~tages of the Spatial Decoder. These Tokens can
only be inserted just before the location of a start code
in the coded data.
A.11.3.1 Start code formats
Three different start code formats are recognized by the
Start Code Detector of the present invention. This is
configured via the register,
start_code detector_coding standard.
Coding Standard Start Code Panem (hex) Size ol stan code value
MPEG OxOO OxOO Ox01 ~value~ ~ bit
JPEG OxFF ~value~ 8 bit
H.261 OxOO OxOl c~alue~ 4 bit
Table A.11.3 8tart code formatQ
A.11.3.2 Start code Token eguivalents
Having detected a start code, the Start Code Detector
studies the value associated with the start code and
generates an appropriate Token. In general, the Tokens are
named after the relevant MPEG syntax. However, one of
ordinary skill in the art will appreciate that the Tokens
can follow additional naming formats. The coding standard
currently selected configures the relationship between
start code value and the Token generated. This
relationship is shown in Table A.11.4.
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Slan CoCe Value
Start ccCe Token generated MpEG ~1.261 JpEG JP~
~hex~ (hex) (hex) (na~e)
PICTURE_START oxoo oxoo 0xDA SGS
SLICE_START~ oxo1 to 0x0l ~o 0xD0to RSTo ~o
0xAF oxoc OxD7 ~ST~
SEQUENCE_START 0XB3 0xD8
SEQUENCE_END OxB7 OxD9 --Cl
GROUP_START OxB8 OxC0 SOFo~
USER_DATA oxs2 0xE0 to APPO t
0xEF APPF
0xF- C~M
EXTENSION_DATA Ox95 OxC8 JPG
OxF0 to JPGo :
0xFD JPG~
Ox02 to PES
Ox9 F
OxC1 to SOFI to
0xCB SOF"
oxcc DAC
DHT_MARKER 0xC1 DHT
DNL_MARKER 0xDC DNL
DQT_MARKER 0xDB DaT
DRI_MARKER 0xDD ~RI
Table A. 11. 4 Token~ from start code valuest
a. This Token contains an 8 bit data field which is
loaded with a value determined by the start code
value. b. Indicates start of baseline DCT encoded data.
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A.11.3~3 Extended features of the coding standards
The coding standards provide a number of mechanisms to
allow data to be embedded in the data stream whose use is
not currently defined by the coding standard. This might
be application specific "user data" that provides extra
facilities for a particular manufacturer. Alternatively,
it might be "extension data". The coding standards
authorities reserved the right to use the extension data to
add features to the coding standard in the future.
Two distinct mechanisms are employed. JPEG precedes
blocks of user and extension data with marker codes.
However, H.261 inserts "extra information" indicated by an
extra information bit in the coded data. MPEG can use both
these techniques.
In accordance with the present invention, MPEG/JPEG
blocks of user and extension data preceded by start/marker
codes can be detected by the Start Code Detector.
H.261/MPEG "extra information" is detected by the Huffman
decoder of the present invention. See A.14.7, "Receiving
Extra Information".
The registers, discard_extension_data and
discard_user_data, allow the Start Code Detector to be
configured to discard user data and extension data. If
this data is not discarded at the Start Code Detector it
can be accessed when it reaches the Video Demux see A.14.6,
"Receiving User and Extension data".
The Spatial Decoder of the present invention supports
the baseline features of JPEG. The non-baseline features
of JPEG are viewed as extension data by the Spatial
Decoder. So, all JPEG marker codes that precede data for
non-baseline JPEG are treated as extension data.
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A.11.3.~ JP~ T-ble d~fi~it~on-
JPEG support~ down loaded Huffman and quantizer tables.
In JPEG data, the definition of these tables is preceded by
the marker codes DNL and DQT. The Start Code Detector
generates the Tokens DHT MARXER and DQT_MARKER when these
marker codes are detected. These Tokens indicate to the
Video Demux that the DATA Token which follows contains
coded data describing Huffman or quantizer table (using the
formats described in JPEG).
A.ll.~ ~rror d~t~ction
The Start Code Detector can detect certain errors in the
coded data and provides some facilities to allow the
decoder to recover after an error is detected (see A.11.8,
n Start code searching").
~.11.4.1 Illeg~l J~ ngth count
Most JPEG marker codes have a 16 bit length count field
associated with them. This field indicates how much data
is associated with this marker code. Length counts of 0
and 1 are illegal. An illegal length should only occur
following a data error. In the present invention, this
will generate an interrupt if illegal length_count mask is
set to 1.
Recovery from errors in JPEG data is likely to require
additional application specific data due to the difficulty
of searching for start codes in JPEG data (see A.11.8.1).
..11.4.2 Ov~rlappinq start/mark-r cod-s
In the present invention, overlapping start codes should
only occur following a data error. An MPEG, byte aligned,
overlapping start code is illustrated in Figure 64. Here,
the Start Code Detector first sees a pattern that looks
like a picture start code. Next the Start Code Detector
sees that this picture start code is overlapped with a
group start. Accordingly, the Start Code Detector
266
g~nerates a overlapping start event. Furthermore, the
Start Code Detector will generate an interrupt and stop if
overlapping start mask is set to 1.
It is impossible to tell which of the two start codes is
the correct one and which was caused by a data error.
However, the Start Code Detector in accordance with the
present invention, discard~ the first start code and will
proceed decoding the second start code "as if it is
correct" after the overlapping start-code event has been
serviced. If there are a series of overlapped start codes,
the Start Code Detector will discard all but the last
(generating an event for each overlapping start code).
Similar errors are possible in non byte-aligned systems
(H.261 or possibly MPEG). In this case, the state of
ignore non aligned must also be considered. Figure 65
illustrates an example where the first start code found is
byte aligned, but it overlaps a non-aligned start code. If
ignore non aligned is set to 1, then the second overlapping
start code will be treated as data by the Start Code
Detector and, therefore no overlapping start code event
will occur. This conceals a possible data communications
error. If ignore non aligned is set to 0, however the
Start Code Detector will see the second, non aligned, start
code and will see that it overlaps the first start code.
A.11.~.3 ~nr-cogniz-d tart cod--
The Start Code Detector can generate an interrupt whenan unrecognized start code is detected (if
unrecognized start mask = 1). The value of the start code
that caused this interrupt can be read from the register
start value.
The start code value OxB4 (sequence error) is used in
MPEG decoder systems to indicate a channel or media error.
For example, this start code may be inserted into the data
by an ECC circuit if it detects an error that it was unable
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to co~rect.
A.11.4.4 6equence of event generation
In the present invention, certain coded data patterns
(probably indicating an error condition) will cause more
than one of the above error conditions to occur within a
short space of time. Consequently, the sequence in which
the Start Code Detector examines the coded data for error
conditions is:
l)Non-aligned start codes
2)Overlapping start codes
3)Unrecognized start codes
Thus, if a non-aligned start code overlaps another,
later, start code, the first event generated will be
associated with the non-aligned start code. After this
event has been serviced, the Start Code Detector's
operation will proceed, detecting the overlapped start code
a short time later.
The Start Code Detector only attempts to recognize the
start code after all tests for non-aligned and overlapping
start codes are complete.
A.11.5 Decoder start-up and shutdown
The Start Code Detector provides facilities to allow the
current decoding task to be completed cleanly and for a new
task to be started.
There are limitations on using these techniques with
JPEG coded video as data segments can contain values that
emulate marker codes (see A.11.8.1).
A.11.5.1 Clean end to decoding
The Start Code Detector can be configured to generate an
interrupt and stop once the data for the current picture is
complete. This is done by setting stop_after_picture = 1
and stop after_picture_mask = 1.
Once the end of a picture passes through the Start Code
Detector, a FLUSH Token is generated (A.11.7.2),
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an int~r~upt is generated, and the Start Code Detector
stops. Note that the picture just completed will be
decoded in the normal way. In some applications, however,
it may be appropriate to detect the FLUSH arriving at the
output of the decoder chip-set as this will indicate the
end of the current video sequence. For example, the
display could freeze on the last picture output.
When the Start Code Detector stops, there may be data
from the "old" video sequence "trapped" in user implemented
buffers between the media and the decode chips. Setting
the register, discard_all_data, will cause the Spatial
Decoder to consume and discard this data. This will
continue until a FLUSH Token reaches the Start Code
Detector or discard_all_data is reset via the
microprocessor interface.
Having discarded any data from the "old" sequence the
decoder is now ready to start work on a new sequence.
A.11.5.2 When to start discard all mode
The discard all mode will start immediately after a 1 is
written into the discard_all_data register. The result
will be unpredictable if this is done when the Start Code
Detector is actively processing data.
Discard all mode can be safely initiated after any of
the Start Code Detector events (non-aligned start event
etc.) has generated an interrupt.
A.11.5.3 Starting a new seguence
If it is not known where the start of a new coded video
sequence is within some coded data, then the start code
search mechanism can be used. This discards any unwanted
data that precedes the start of the sequence. See A.11.8.
A.11.5.4 Jumping between sequences
This section illustrates an application of some of the
techniques described above. The objective is to "jump"
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from o~e`part of one coded video sequence to another. In
this example, the filing system only allows access to
"blocks" of data. This block structure might be derived
from the sector size of a disc or a block error correction
system. So, the position of entry and exit points in the
coded video data may not be related to the filing system
block structure.
The stop_after_picture and discard all data mechanisms
allow unwanted data from the old video sequence to be
lo discarded. Inserting a FLUSH Token after the end of the
last filing system data block resets the discard_all_data
mode. The start code search mode can then be used to
discard any data in the next data block that precedes a
suitable entry point.
A.11.6 Byte alignment
As is well known in the art, the different coding
schemes have quite different views about byte alignment of
start/marker codes in the data stream.
For example, H.261 views communications as being bit
serial. Thus, there is no concept of byte alignment of
start codes. By setting ignore_non_aligned = 0 the Start
Code Detector is able to detect start codes with any bit
alignment. By setting non-aligned_start mask = 0, the
start code non-alignment interrupt is suppressed.
In contrast, however, JPEG was designed for a computer
environment where byte alignment is guaranteed. Therefore,
marker codes should only be detected when byte aligned.
When the coding standard is configured as JPEG, the
register ignore_non_aligned is ignored and the non-aligned
start event will never be generated. However, setting
ignore_non_aligned = 1 and non-aligned-start-mask = 0 is
recommended to ensure compatibility with future products.
MPEG, on the other hand, was designed to meet the needs
of both communicationS (bit serial) and computer (byte
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oriented) systems. Start codes in MPEG data should
normally be byte aligned. However, the standard is
designed to be allow bit serial searching for start codes
(no MPEG bit pattern, with any bit alignment, will look
like a start code, unless it is a start code). So, an MPEG
decoder can be designed that will tolerate loss of byte
alignment in serial data communications.
If a non-aligned start code is found, it will normally
indicate that a communication error has previously
occurred. If the error is a "bit-slip" in a bit-serial
communications system, then data containing this error will
have already been passed to the decoder. This error is
likely to cause other errors within the decoder. However,
new data arriving at the Start Code Detector can continue
to be decoded after this loss of byte alignment.
By setting ignore_non_aligned = 0 and
non_aligned_start_mask = 1, an interrupt can be generated
if a non-aligned start code is detected. The response will
depend upon the application. All subsequent start codes
will be non-aligned (until byte alignment is restored).
Accordingly, setting non_aligned_start_mask = 0 after byte
alignment has been lost may be appropriate.
MPEG JPEG H.261
ignore_non_aligned 0 1 0
non_aligned_start_rnask 1 0 0
Table A.ll.S Configuring for byte alignment
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a. 11 . 7 autOu~tic To~-~ g-n-r~tio~
In the present invention, most of the Tokens output by
the Start Code Detector directly reflect syntactic elements
of the variou~ picture and video coding standards. In
addition to these "natural" Tokens,some useful "invented"
Tokens are generated. Examples of these proprietary tokens
are PICTURE END and CODING STANDARD. To~ens are also
introduced to remove some of the syntactic differences
between the coding standards and to-~tidy up" under error
conditions.
This automatic Token generation is done after the serial
analysis of the coded data (see Figure 61, "The Start Code
Detectorn). Therefore the system responds equally to -
Tokens that have been supplied directly to the input of the
Spatial Decoder via the Start Code Detector and to Tokens
that have been generated by the Start Code Detector
following the detection of start codes in the coded data.
a. 1l. 7 . 1 Indicating th- nd of a pictur-
In general, the coding standards don't explicitly signal
the end of a picture. However, the Start Code Detector ofthe present invention generates a PICTURE END Token when it
detects information that indicates that the current picture
has been completed.
The Tokens that cause PICTURE END to be generated are:
SEQUENCE START, GROUP START, PICTURE START, SEQUENCE_END
and FLUSH.
A.11.7.2 8top aft-r pictur- nd option
If the register stop after picture is set, then the
Start Code Detector will stop after a PICTURE END Token has
passed through. However, a FLUSH Token is inserted after
the PICTURE END to "push" the tail end of the coded data
through the decoder and to reset the system. See A.11.5.1.
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A.11.~.3 Introducing sequence start for H.261
H.261 does not have a syntactic element equivalent to
sequence start (see Table A.11.4). If the register
insert_sequence_start is set, then the Start Code Detector
will ensure that there is one SEQUENCE_START Token before
the next PICTURE_START, i.e., if the Start Code Detector
does not see a SEQUENCE_START before a PICTURE_START, one
will be introduced. No SEQUENCE_START will be introduced
if one is already present.
o This functlon should not be used with MPEG or JP~G.
A.11.7.4 Setting coding standard for each sequence
All SEQUENCE_START Tokens leaving the Start Code
Detector are always preceded by a CODING_STANDARD Token.
This Token is loaded with the Start Code Detector's current
coding standard. This sets the coding standard for the
entire decoder chip set for each new video sequence.
A.11.8 Start code searching
The Start Code Detector in accordance with the
invention, can be used to search through a coded data
stream for a specified type of start code. This allows the
decoder to re-commence decoding from a specified level
within the syntax of some coded data (after discarding any
data that precedes it). Applications for this include:
start-up of a decoder after jumping into a coded data
file at an unknown position (e.g., random accessing).
to seek to a known point in the data to assist recovery
after a data error.
For example, Table A.11.6 shows the MPEG start codes
searched, for different configurations of
start_code_search. The equivalent H.261 and JPEG
start/marker codes can be seen in Table A.11.4.
,
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sUrt_code_search Stan codes searched ~or . . .
o ~ Normal operatlon
~eserved (will ~enave as dlscard Ca~a)
3 sequence stan
sUrt_cod~_sea-ch Stan cod s searched ~or
group or sequence stan
5 D picture. group or sequence slan
6 slice. picture. group or sequence stan
7 the ne~ stan or marker code
Table A.11.6 Start code search modes
a. A FLUSH Token places the Start Code Detector
in this search mode.
b. This is the default mode after reset.
When a non-zero value is written into the
start_code_search register, the Start Code Detector will
start to discard all incoming data until the specified
start code is detected. The start_code_search register
will then reset to O and normal operation will continue.
The start code search will start immediately after a
non-zero value is written into the start_code_search
register. The result will be unpredictable if this is done
when the Start Code Detector is actively processing data.
So, before initiating a start code search, the Start Code
Detector should be stopped so no data is being processed.
The Start Code Detector is always in this condition if any
of the Start Code Detector events (non-aligned start event
etc.) has just generated an interrupt.
A.11.8.1 Limitations on u~ing start code search with JPEG
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274
Most ~PEG marker codes have a 16 bit length count field
associated with them. This field indicates the length of a
data segment associated with the marker code. This segment
may contain values that emulate marker codes. In normal
operation, the Start Code Detector doesn't look for start
codes in these segments of data.
If a random access into some JPEG coded data "lands" in
such a segment, the start code search mechanism cannot be
used reliably. In general, JPEG coded video will require
additional external information to identify entry points
for random access.
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SECT~ A.12 Decoder start-up control
A.12.1 Overvi-w of d-cod-r ~tart~up
In a decoder, video display will normally be delayed a
short time after coded data is first available. During
this delay, coded data accumulates in the buffers in the
decoder. This pre-filling of the buffers ensures that the
buffers never empty during decoding and, this, therefore
ensures that the decoder is able to decode new pictures at
regular intervals.
Generally, two facilities are required to correctly
start-up a decoder. First, there must be a mechanism to
measure how much data has been provided to the decoder.
Second, there must be a mechanism to prevent the display of
a new video stream. The Spatial Decoder of the invention
provides a bit counter near its input to measure how much
data has arrived and an output gate near its output to
prevent the start of new video stream being output.
There are three levels of complexity for the control of
these facilities:
Output gate always open
Basic control
Advanced control
With the output gate always open, picture output will
start as soon as possible after coded data starts to arrive
at the decoder. This is appropriate for still picture
decoding or where display is being delayed by some other
mechanism.
The difference between basic and advanced control
relates to how many short video streams can be accommodated
in the decoder's buffers at any time. Basic control is
sufficient for most applications. However, advanced
control allows user software to help the decoder manage the
start-up of several very short video streams.
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A.12.~ M*EG video buffer verifier
MPEG describes a "video buffer verifier" (VBV) for
constant data rate systems. Using the VBV information
allows the decoder to pre-fill its buffers before it starts
to display pictures. Again, this pre-filling ensures that
the decoder's buffers never empty during decoding.
In summary, each MPEG picture carries a vbv_delay
parameter. This parameter specifies how long the coded
data buffer of an "ideal decoder" should fill with coded
lo data before the first picture is decoded. Having observed
the start-up delay for the first picture, the requirements
of all subsequent pictures will be met automatically.
MPEG, therefore, specifies the start-up requirements as
a delay. However, in a constant bit rate system this delay
can readily be converted to a bit count. This is the basis
on which the start-up control of the Spatial Decoder of the
present invention operates.
A.12.3 Def inition of a stream
In this application, the term stream is used to avoid
confusion with the MPEG term se~uence. Stream therefore
means a quantity of video data that is "interesting" to an
application. Hence, a stream could be many MPEG sequences
or it could be a single picture.
The decoder start-up facilities described in this
chapter relate to meeting the VBV requirements of the first
picture in a stream. The requirements of subsequent
pictures in that stream are met automatically.
21~5 L59
277
A. 12 . 4 S'c~rt-up control registers
3 3
Resis;er name ;3 ~D Cescnstlon
tr
star2up_access 1 0 Wnting 1 to this regiSter rer~ues;s ;na; ~e Dl;
CEO_3S_ACCESS rw counter ana ga~e opening ~ogic s;op ;o allow
access to their configurabon registers.
bit_count 8 0 This bit counter is Incremente~ as co~e~ ca:a
rw leaves the s;an ccde cetector. The r.u".bet cl
CE~ es CouNr
bit_count_prescale 3 0 bits rer~uired to ir.crement bit_count ^nce :s
rw approx. 2(bl~-~un~ ) x 512
CED_eS_PRESCALE
The bit counter star-s coun~ing blts aner a
FLUSH Token passes throusn ;he bi; coun:ar.
It is reset to 2ero and ;hen stops ircrerr.emJng
atter the bit count targe; has been met,
bit_count_target a x This tegister specifies ;he bit coun; ;arSet. A
CED_BS_TARGET rw target met event is senera:ed whenever 'he lollowing condition becomes true:
bit_count ~3 bit_count_target
targe~_met_event 1 0 When the bit count ;arget is me~ thls even; w
SS_TARGET MET EVENT rw be generated. Il the mask register is se; ;o 1
targe~_met_mask 1 o then an interrupt can be generated, however,
rw the bit counter will ~OT stop prvceSs.ng Ca;a.
This event will occur when ;he bi; ;oun;er
"Icre"~o"ts to its ;arget. It will also oc^ur ;' a
target value i5 written which is le5s C~an or
equal to the current value o~ the Cit ccu~er
WriUng 0 to bi~_count_target wiil aiwa~s
generate a target met event.
T.able A.12.1 Decoder start-up registers
214~1~9
Regis~er name ~i -- Description
counter_tlushed_event 1 0 When a FLUSH Token pa ses througn the Oit
~3S_F-USH_EVENT rw count circuil this event will occur. Il the mask
counter_flushed_mask 1 0 register is set ~o 1 then an interrupt can be
rw generated and the bit counter will stop.
counter_tlushed_too_early_ event 1 0 li a FLUSH Token passe~s through ~e ùe
~S_FLUS~_gEFORE_~ARGET_MET_EVENT rw count circuit and the e~t count target has rot
counter_~lushed_too_early_mask 1 0 been met this event witl occur. 1~ the mask
rw register is set to 1 then an interrupt can be
generated and the bit counter will stop.
See A.12.10
otSchip_queue 1 0 Setting this register to t configures the sate
CED_gS_OUEUE rw opening logic to reCuire ~ upr~r csor
support. When this reSister is set to 0 ~he out ut
gate control logic w~ll eutomatically control he
operation o~ the output gate.
See sections A.12.6 and A.12.7.
enaole_stream 1 0 When an oh-chip r~ueue is in use wn;ing tO
CED_BS_ENA~LE_NXT STM rw enable_stream conuols the behaviou- ot the
output gate aner the end o~ a stream ~asses
through it.
A one in this register enables the cu~put ga:e ;o
open.
The register wtll be resel when an
accept_enable interru~t is generated.
Table A.12.1 ~ecoder start-up registers (contd)
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279
Register name ~ -- Descnption
~/i C
accept_-nat~l-_event 1 0 This event indicates that a FLUSH T5ken ~a5
55_SrFiEAM_ENO_EVENr rw passed through ~;e output gate (causing it to
accept_enaOI-_mask 1 0 close) and tttat an ena~le was availa~le to aliow
rw the gate to open
l~ the mask register is set to 1 then an In errupt
can t~e generated and t)le register
enable_stream will t~e reset See A 12 7 1
Table A.12.1 Decoder ~tart-up regi~ters (contd)
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A.12.~ Output gate always open
The output gate can be configured to remain open. This
configuration is appropriate where still pictures are being
decoded, or when some other mechanism is available to
manage the start-up of the video decoder.
The following configurations are required after reset
(having gained access to the start-up control logic by
writing 1 to startup_access):
set offchip_queue = 1
set enable_stream = 1
ensure that all the decoder start-up event mask
registers are set to 0 disabling their interrupts
(this is the default state after reset).
(See A.12.7.1 for an explanation of why this holds the
output gate open.)
A.12.6 Basic operation
In the present invention, basic control of the start-up
logic is sufficient for the majority of MPEG video
applications. In this mode, the bit counter communicates
directly with the output gate. The output gate will close
automatically as the end of a video stream passes through
it as indicated by a FLUSH Token. The gate will remain
closed until an enable is provided by the bit counter
circuitry when a stream has attained its start-up bit
count.
The following configurations are required after reset
(having gained access to the start-up control logic by
writing 1 to startup_access):
set bit_count_prescale approximately for the expected
range of coded data rates
set counter_flushed_too_early_mask = 1 to enable this
error condition to be detected
Two interrupt service routines are required:
Video Demux service to obtain the value of
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vbv delay for the first picture in each new
stream
Counter flushed too early service to react to
this condition
The video demux (also known as the video parser) can
generate an interrupt when it decodes the vbv_delay for a
new video stream (i.e., the first picture to arrive at the
video demux after a FLUSH). The interrupt service routine
should compute an appropriate value for bit_count_target
lo and write it. When the bit counter reaches this target, it
will insert an enable into a short queue between the bit
counter and the output gate. When the output gate opens it
removes an enable from this queue.
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A.~2.~.~ 8t~rti~g ~ tr~ hortly ~ft-r ~oth-r
f~ J
As an example, the MPEG stream which is about to finish
is called A and the MPEG stream about to start is called B.
A FLUSH Token should be inserted after the end of A. This
pushes the last of its coded data through the decoder and
alerts the various sections of the decoder to expect a new
stream.
Normally, the bit counter will have reset to zero, A
having already met its start-up conditions. After the
FLUSH, the bit counter will start counting the bits in
stream B. When the Video Demux ha~ decoded the vbv_delay
from the first picture in stream B, an interrupt will be
generated allowing the bit counter to be configured.
As the FLUSH marking the end of stream A passes through
the output gate, the gate will close. The gate will remain
closed until B meets its start-up conditions. Depending on
a number of factors such as: the start-up delay for stream
B and the depth of the buffers, it is possible that B will
have already met its start-up conditions when the output
gate closes. In this case, there will be an enable waiting
in the queue and the output gate will immediately open.
Otherwise, stream B will have to wait until it meets its
start-up requirements.
A.12.6.2 A ~ucc-~ion of ~hort ~tr-~mJ
The capacity of the queue located between the bit
counter and the output gate is sufficient to allow 3
separate video streams to have met their start-up
conditions and to be waiting for a previous stream to
finish being decoded. In the present invention, this
situation will only occur if very short streams are being
decoded or if the off-chip buffers are very large as
compared to the picture format being decoded).
In Figure 69 stream A is being decoded and the
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?83
outpu~g~te is open). Streams B and C have met their
start-up conditions and are entirely contained within the
buffers managed by the Spatial Decoder. Stream D is still
arriving at the input of the Spatial Decoder.
Enables for streams B and C are in the queue. So, when
stream A is completed B will be able to start immediately.
Similarly C can follow immediately behind B.
If A is still passing through the output gate when D
meets its start-up target an enable will be added to the
queue, filling the queue. If no enables have been removed
from the queue by the time the end of D passes the bit
counter (i.e., A is still passing through the output gate)
no new stream will be able to start through the bit
counter. Therefore, coded data will be held up at the
input until A completes and an enable is removed from the
queue as the output gate is opened to allow B to pass
through.
A.12.7 Advanced operation
In accordance with the present invention, advanced
control of the start-up logic allows user software to
infinitely extend the length of the enable queue described
in A.12.6, "Basic operation". This level of control will
only be required where the video decoder must accommodate a
series of short video streams longer than that described in
A.12.6.2, "A succession of short streams".
In addition to the configuration required for Basic
operation of the system, the following configurations are
required after reset (having gained access to the start-up
control logic by writing 1 to start_up access):
set offchip queue = 1
set accept enable_mask = 1 to enable interrupts
when an enable has been removed from the queue
set target_met_mask = 1 to enable interrupts
~hen a stream's bit count target is met
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Two additional interrupt service routines are
required:
accept enable interrupt
Target met interrupt
When a target met interrupt occurs, the service routine
should add an enable to its off-chip enable queue.
A.12.7.1 Output gate logic behavior
Writing a 1 to the enable_stream register loads an
enable into a short queue.
When a FLUSH (marking the end of a stream) passes
through the output gate the gate will close. If there is
an enable available at the end of the queue, the gate will
open and generate an accept_enable_event. If
accept_enable_mask is set to one, an interrupt can be
generated and an enable is removed from the end of the
queue (the register enable_stream is reset).
However, if accept_enable_mask is set to zero, no
interrupt is generated following the accept_enable_event
and the enable is NOT removed from the end of the queue.
This mechanism can be used to keep the output gate open as
described in A.12.5.
A.12.8 Bit counting
The bit counter starts counting after a FLUSH Token
passes through it. This FLUSH Token indicates the end of
the current video stream. In this regard, the bit counter
continues counting until it meets the bit count target set
in the bit_count_target register. A target met event is
then generated and the bit counter resets to zero and waits
for the next FLUSH Token.
The bit counter will also stop incrementing when it
reaches it maximum count (255).
A.12.9 Bit count prescale
In the present invention, 2~ Oun'-rrC~ +'' x 512 bits are
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285
required to increment the bit counter once. Furthermore,
bit count prescale is a 3 bit register than can hold a
value between O and 7.
n Range (bits) 1~ r~ ' ~t , (bits)
O O to 26214~ 1024
0 to 524288 2048
7 0 to 31457280 1~880
Table A.12.2 Exampl- bit counter ranges
The bit count is approximate, as some elements of the
video stream will already have been Tokenized (e.g., the
start codes) and, therefore includes non-data Tokens.
A.12.10 Counter flushed too early
If a FLUSH token arrives at the bit counter before the
bit count target is attained, an event is generated which
can cause an interrupt (if counter flushed too_early_mask =
l). If the interrupt is generated, then the bit counter
circuit will stop, preventing further data input. It is
the responsibility of the user's software to decide when to
open the output gate after this event has occurred. The
output gate can be made to open by writing O as the bit
count target. These circumstances should only arise when
trying to decode video streams that last only a few
pictures.
~ 2145159
286
SECTI~ A.13 Buffer Management
The Spatial Decoder manages two logical data buffers:
the coded data buffer (CDB) and the Token buffer (TB).
The CDB buffers coded data between the Start Code
Detector and the input of the Huffman decoder. This
provides buffering for low data rate coded video data. The
TB buffers data between the output of the Huffman decoder
and the input of the spatial video decoding circuits
(inverse modeler, quantizer and DCT). This second logical
buffer allows processing time to include a spread so as to
accommodate processing pictures having varying amounts of
data.
Both buffers are physically held in a single off-chip
DRAM array. The addresses for these buffers are generated
by the buffer manager.
A.13.1 Buffer manager registers
The Spatial Decoder buffer manager is intended to be
configured once immediately after the device is reset. In
normal operation, there is no requirement to reconfigure
the buffer manager.
After reset is removed from the Spatial Decoder, the
buffer manager is halted (with its access register,
buffer_manager_access, set to 1) awaiting configuration.
. After the registers have been configured,
buffer_manager_access can be set to O and decoding can
commence.
Most of the registers used in the buffer manager cannot
be accessed reliably while the buffer manager is operating.
Before any of the buffer manager registers are accessed
buffer_manager_access must be set to 1. This makes it
essential to observe the protocol of waiting until the
value 1 can be read from buffer_manager_access. The time
taken to obtain and release access should be taken into
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consid~r~tion when polling such registers as cdb_full and
cdb empty to monitor buffer conditions.
Register name ~ cj Description
rJ~ o
butter_manager_access 1 1 rhis access tit 510ps the operano n ~e bu~ter manager so tt~at Xs
rw various registers can ~e accessed reliably. See A.6.4. 1
Note: Shis access register is unusual as its de~ault state atter rese~ ;s
1. I.e. atter reset the bu~ter manager is hal~ed awailing corr6isura on
via the ~ ~or intertace.
Q
~ ~o
Register name o Sj Oescription
i~i o
buner_manag-r_keynole_address 6 x Keyhole access to the extendeo adcress s~ace used tCirt~e bubrer
rw manager resistets shown below. See A.6.4.3 for rnore
burter_manager_t~eyhole_data 8 x ;n~or . about accessing resisters throush a key~hole.
rw
butter_limi~ 18 x Thisspecifiestheoverallslzeoi~ht 0Q ~ ~ia'r~: dnacne~tol~e
rw Spatial Decoder. All bu(ter addresses are i ~cu. .ed ~.~CO ~i;s Icutler
size and so will wrap round within the oR19~ prr~vided
~db_base 18 x These registers point to the base oi the co~J~ata (cCb) and Tc~en
tt~_base ~w (tb) bufters.
cdb_length 18 x These ~i51hr~ speciry th~ length (i.e. size) o~ the coded ca;a !cCb)
tb_length ~w and Toi~ ~tb) bu~ters.
cdO_read . 18 x These registe s hold an o~tset ~rom Lhe bu~ base anC incicate
tb_read ~O where data ~ill be read ~rom next.
cdb_number 18 x These f~glsters show how much data ~5 u -ntly held in the but!ers.
tb_number ~O
cdb_tull 1 x Thesf r~ysters will be se~ to 1 i~ the ço~d Cata (ccb) cr T~l(er ttb~
tb_tull ~ bu~ ;~c
cdb_empty 1 x T~c5~ isters will be sel to 1 i~ t~.e coCed data (cdb) or Tcker} 11t)
tD_empty . ~ ro bu~er empbes.
Table A.13.1 Buffer manager registers (cor.td)
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288
A.13.~ 1~Buffer manager pointer values
Typically, data is transferred between the Spatial
Decoder and the off_chip DRAM in 64 byte bursts (using the
DRAM's fast page mode). All the buffer pointers and length
registers refer to these 64 byte ~512 bit) blocks of data.
So, the buffer manager's 18 bit registers describe a 256 k
block linear address space (i.e., 128 Mb).
The 64 byte transfer is independent of the width (8, 16
or 32 bits) of the DRAM interface.
A.13.2 Use of the buffer manager registers
The Spatial Decoder buffer manager has two sets of
registers that define two similar buffers. The buffer
limit register (buffer_limit) defines the physical upper
limit of the memory space. All addresses are calculated
modulo this number.
Within the limits of the available memory, the extent of
each buffer is defined by two registers: the buffer base
(cdb_base and tb_base) and the buffer length (cdb_length
and tb_length). All the registers described thus far must
be configured before the buffers can be used.
The current status of each buffer is visible in 4
registers. The buffer read register (cdb_read and tb_read)
indicates an offset from the buffer base from which data
will be read next. The buffer number registers (cdb_number
and tb_number) indicate the amount of data currently held
by buffers. The status bits cdb_full, tb_full, cdb_empty
and tb_empty indicate if the buffers are full or empty.
As stated in A.13.1.1, the unit for all the above
mentioned registers is a 512 bit block of data.
Accordingly, the value read from cdb_number should be
multiplied by 512 to obtain the number of bits in the coded
data buffer.
A.13.3 Zero buffers
Still picture applications (e.g., using JPEG) that do
2~45159
289
not h~e a "real-time" requirement will not need the large
off-chip buffers supported by the buffer manager. In this
case, the DRAM interface can be configured (by writing 1 to
the zero_buffers register) to ignore the buffer manager to
provide a 128 bit stream on-chip FIFO for the coded data
buffer and the Token buffers.
The zero buffers option may also be appropriate for
applications which operate working at low data rates and
with small picture formats.
Note: the zero_buffers register is part of the DRAM
interface and, therefore, should be set only during the
post-reset configuration of the DRAM interface.
A.13.4 Buffer operation
The data transfer through the buffers is controlled by a
handshake Protocol. Hence, it is guaranteed that no data
errors will occur if the buffer fills or empties. If a
buffer is filled, then the circuits trying to send data to
the buffer will be halted until there is space in the
buffer. If a buffer continues to be full, more processing
stages "up steam" of the buffer will halt until the Spatial
Decoder is unable to accept data on its input port.
Similarly, if a buffer empties, then the circuits trying to
; remove data from the buffer will halt until data is
; available.
As described in A.13.2, the position and size of the
coded data and Token buffer are specified by the buffer
base and length registers. The user is responsible for
configuring these registers and for ensuring that there is
no conflict in memory usage between the two buffers.
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290
SECT~O~ A.14 Video Demux
The Video Demux or Video parser as it is also called,
completes the task of converting coded data into Tokens
started by the Start Code Detector. There are four main
processing blocks in the Video Demux: Parser State Machine,
Huffman decoder (including an ITOD), Macroblock counter and
ALU.
The Parser or state machine follows the syntax of the
coded video data and instructs the other units. The
Huffman decoder converts variable length coded (VLC) data
into integers. The Macroblock counter keeps track of which
section of a picture is being decoded. The ALU performs
the necessary arithmetic calculations.
A.14.1 Video Demux registers
Regis er name ~ ~ Description
u.i ~
demu~_access ~ O This access bit s~ops the operaaon o~ the Video Demux so tha~ ,t s
CED_H_CTf(L17J rw various registers can be accessed reliably See A 6 4 1
huttman_error_code 3 When the Video Demux stops tollowing the genr ralion ol a
CEO_H_CTf1Lr6:4J ro hunman_event interrupt reCu st this 3 bit register holds a value indicating
why the interrupt was gene ~ See A 14 5 1
parser_error_code 8 When the Vldeo Demux SlOpS ~ollowing the gene, ~tion o~ a parser_event
C'D_~I_OMUX_~RR ro interrupt re~uest this 8 bit register holds a value indicating why the
int rrupt was ~ , _ See A 14 5 2
demux_keyhole_address 12 x Keyhole access to the Video Demux~s extended address space See
C~D_H_KEYHOLE_AOOR rw A 6 4 3 lor mor- ;n~o~ dt;on about accessing regis ers
demux_keyhole_data 8 x through a keyhole
15 CEO_H_~EYHOLE rw Tables A 14 2, A 14 3 and A 14 4 describe the registersthat can ~e
accessed via the keyhole
Table A.14.1 Top level Video Demux r~gisters
21451S9
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291
Regist~r na~ ~ ~ O~tion
dummy_last--Dicture 1 0 When this reglstems set to 1 the Video Oemux w~ll generate inlormaoon
CEo-H-ALu-REGo rw ~or a ~dummy' Intra picture as the last plcture ol an MPEG sequence.
r_rom_con~tol This tunction is useiul when the Temporal Decoder is configured lor
automatic picture re-ordering (see A.18.3.5, 'Pic:ure sequence re-
r-dummy-last-frame-bn
ordering'. ~o nush the last P or I p~cture out o~ the lemporal
Oecoder.
~ o ~dummy' picture is required ii:
the Temporal Decoder is not configured ior re-crdenng
another MPEG sequence will be decoCed immediately (as this Will also
nush out the last picture)
the coding standard is not MPEG
tield_into 1 0 When this registet is set to 1 the first byte ot any MPEG
CE3_H_ALU_REGO rw extra_i~ ation_pictureis placed in the FIELD_INFO Token. See
A.14.7.1
r_torrl_conrrol
r_feld_in~o_bit
continue 1 0 This register atlows user so~tware to control how mucn erLra. Lser or
CED_H_ALU_REGO rw extension data it wants to receive when is it is Ce~ected by the decoder.
r-rorrl-con~rol See A.14.6 and A.14.7
r_continue_bit
rom_revision 8 I."."odiatety tollowing reset this holds a copy o~ ~e microcode RChl
CED_H_ALU_REG 1 revision number.
r_rom_rev~sion ~his register is also used to present to control 5Onware data vaiues reaC
irom t~)e coded data. See A.14.6, Receiving User and Extensicn data-
and A.14.7 ~Receiving Ex~a Ir,10,",2tion-,
Table A.14.1 Top level Video Demux regi8ters ~contd)
2145159
Register name ~ D .~C~
~ G
hunman-eyent ~ ~ o A t~unman event is generated it an rror is tound in the coded cata. See
rw A. 14.5.1 ~or a das~ tion o~ these events.
nuttman mask 1 O
It the mask register is set to l then an intetruDl can 0e gene-ated and ~e
rw Vldeo Oemux will stop. Il th- mask register is set to 0 then no interru~t Is
generated and the Video t~emux will at1empt ~o recover trom Ihe errAr.
parser_event l O A Parser event can 0e in responce to errors in the cocee ~ata cr :o ~re
rw arrival ot ;~o~ iO~ at the Vdeo Demux tllat recuires sottware
parser_mask 1 0 ;/~or~C~tion~ See A.14.5.2 tor a Ce~npt~on ot these events.
rw l~ the mask registe- is set to 1 then an intetrupt can 0e generated and ~e
Video oemtJx witl Stop. Il the mask register is set to O then no interrupt is
g-nerated and the Vdeo Demux will attempt to continue.
Table A.14.1 Top level Video Demux regi~ter~ ~contd)
Q
Register name ~ ~ Description
co-"pon~ht_name_O 8 x During JPEG operaoon the register com~,or.-l ,I_name_n holds an 8 bit value
co.,.~,ono,~t_nam-_1 rw indicating ~to an ~r~ ~) whkh colour CO.,.~ne.,l has the co",~n ~n~ IC n.
cG",poncht_name_2
CG" .pGn~nt_name_3
hori2_tJ Is 16 x These registers hold the horizontal and vertical Ji",_ns,ons ol the video tbelng
rw decoded in pixels.
ven_oels 16 x
S-e section A 14.2
rw
hork_".~.,oC 16 x ~hese registers hold the honzontal and vertical di,ll~,oOs ot tt~le viCeo l~elr~g
rw decoded in ",a./oOl~t~s.
vert_,r~oc(;0~:_ 16 x
See section A14.2
rw
Table A.14.2 video demux picture
construction registers
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293
Regisler name ~ rJ7 Descripbon
i~i O
max_n 2 x These reqlsters hold the n,a_,ubl~.. k Wldth anC helsht in blocks (3 x 3 plxels;.
rv~ The values 0 to 3 indicate a ~ tlh~l,e ~ht ot 1 to 4 blocks.
max ~ 2 x
See section A.14.2
rv~
max_coi"ponent_id 2 x The values 0 to 3 indicate that 1 to ~ dinerent video comDcnen:s a-e cutrerrUy
rv~ being decoded.
See section A.14.2
Nt 8 x During JPEG operatton this register holds the parameter ,`i~ (nur-~er ot image
rw co".ponCnts in trame).
blocks_h_0 2 x For each of the 4 colour co",ponc-r,ts Ihe registers blocks_h_n and
btocks_h_1 rw blocks_v_n hold th- number ot blocks hori~ontally and vertically in a
blocks_h_2 Illacrobl~; tor the colour Colllvore.)t with component ID n.
blocks_h_3 See section A.14.2
blocks_v_0 2 x
blocks_v_1 rw
blocks_v_2
blocks_v_3
t~0 2 x The tv~o bit value neld by the reqister tq_n descnt~es whicn Inverse
tq_1 rv~ auantisaoon table is ~o be used when decoding dala With cG""~nent ID n.
tq_2
t~_3
Ti~ble A.14.2 Video demux picture
con~truction register~ (contd)
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A.14.1.1~ Register loading and Token g-neration
Many of the registers in the Video Demux hold values
that relate directly to parameters normally communicated in
the coded picture/video data. For example, the horiz_pels
register corresponds to the MPEG sequence header
information, horizontal size, and the JPEG frame header
parameter, X. These registers are loaded by the Video
Demux when the appropriate coded data is decoded. These
registers are also associated with a Token. For example,
the register, horiz_pels, is associated with Token,
HORIZONTAL_SIZE. The Token is generated by the Video Demux
when (or soon after) the coded data is decoded. The Token
can also be supplied directly to the input of the Spatial
Decoder. In this case, the value carried by the Token will
configure the Video Demux register associated with it.
`-- 2145159
295
~. z
Regist~ nane ~ ~ Ce ".lion
dc_hutt_o 2 Th- two blt value heia by the regtster dc_hut~_n Cexrlbes which HLi~man
dc_hutt_1 rw decoding table is to be used when decoding the OC . oeMcients o~ rJata wlth
dc_hut~_2 co" ,pone"l lO n.
dc_hutt_3 Similarly ac_hut~_n descnbes the table ~o be used wnen cecoC~,-g AC
ac_hutl_O 2
cor~if._".r,t~
ac_hut~_1 rv~
aaseline JPEG requires up to two Hunman tables per scan. rhe or.ly ~a~!es
ac-hun-2
.,. at~ i are O and 1.
ac_hun_3
dc_bits_O~15:0] 8 Each ol these is a table ol 16, eight bit values. rhey j rovlde the 91TS
dc_bits_1~15:0] rw ;r,~o.", ~n (see JPEG Huf~man table sps ' j~' 3n) which tomm parl of the
ac_bits_O~15:0] 8 d~so.. ~,t,on o~ two DC and two AC Hur~man tables.
ac_bits 1~15-01 rw
See sec~ion A.14.3.1
dc_hui~val_O~11:0] 8 Each ol these is a table o~ 12, eighl ba vaiues~ They provide the HUFFvAL
dc-hutfval-1~r11:ol rw into.. " ~n (see JPEG Hunman table s~ ation) Which ~omm par, oi ~:e
d¢~, iption of two DC Hunman tables.
See section A.14.3.1
ac_hu~val_q161:0] 8 Each o~ these is a table ol 162, eight t~it values rhey provide the HUF.-VAL
ac_huthal_1~161 :0l rw i"l~.,.,. . (see JPEG Huttman table sr~ ;r;~ at on) which torm pan ot the
C iiit;on of two AC Hunman tables.
See section A.14.3.1
dc_zssss_O 8 rhese 8 bit registers hold vaiues that are special cased ~o accelera~e ~e
dc_zss~s_1 rw decoding o~ cenain ~requently used JPEG VLCs.
ac_eob_O dc_ssss - magnituds ol DC coenlcient is O
ac_eob 1
ac-eob - end o~ block
ac_~rl_O a
ac_zrl - run ol 16 zeros
ac_zrl_1 rw
Table A.14.3 Video demux Huffman table regi~ters
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296
~"
Regisl ~ name 2 -- Descnption
~n C
butler_si2e 10 This regi5ler is loaaed when decoding MPEG Cata ~th a value Inc,catlng ~e
rw si2e o~ VBV bufler re~uired in an iOeal decoder.
rhis value is no~ used by the decoder chips. However, the value it holds rnal
be useful to user so~tware when configuring the coCed data hu~et sRe andto
detemine whether the decoder is capable ol decoding a panicular .~ _5 ~ata
file.
pel_aspect 4 rhis register is loaded when decoding MPEG data wlth a value InClcat~rgtt~ie
rw pel aspect ratio. rhe value is a 4 bit integer that is used as an inde~ into a
table defined by MPEG.
See th- MPEG standard ~or a definition ol this table.
rhiS value is not used by the decoder chips. However, the value a holcs may
be usehJI to user softwate when configunng a display or output de v ce.
bit_rate 18 rhis register is loaded when aecoding MPEG data With a value incica:i-.g ~i2
rw coded data rate.
See the MPEG standard ~or a definiOon o~ this value.
rhis valu- is not used by th- d coder chips. However, the value it holds may
b- useful to U#t so~rware when configuring the decodet sUn-up regis:ers.
pic_rate 4 rhis regist-r is baded when d coding MPEG data with a value inCicatingt~e
rw picture rate.
See th- MPEG standard lor a definibon o~ this value.
rhis value is not used by the decoder chips. However, the value i~ holCs iT ay
b usetul to U#t sonwate when configuring a display or output device.
con,t- .. ;ned 1 rhis r4isleMs loaded wh n decosing MPEG data to indicale if the coced ~ata
rw meets MPEG's con,t~_:n_d D~ ,le ,.
See the MpEG standard lot a definition ol this nag.
rhis value is not used ~y the oecoder chips. Howev~r, ~.e value it ~olcs i raY
t~e usehl to user sottwate to delemlne whether the decoder is capi ~le of
decoding a panicular MPEG daU ffle.
Table A.14.4 Other Video Demux registers
214~159
297
Register nam~ C~,c ~ h,
~n ¢
picture_type 2 During MPEG operaDon this regis~er holds the picture type ol .ne ~icture being
nw decoded,
h_261_pic_type 5 This register is loaded when Cecoding H.261 data. It .~olds in~orrraoon about
rw the picture ~ormat,
7 1 6 1 5 ~ , I 2 1 1 1 û
¦ r ¦ r ¦ s ¦ d ¦ ¦ C ¦
Flags:
s - Split Screen Indicator
d Document Camera
~ - Freete ~icture Release
This value is not used by the decoder chips. However, the in~orrnar,ion should
be used when configur1ng hori~_p ls, vert_pels anC the display or cutput
device,
broken_closed 2 During MPEG operation this register holds the broken_link and cJosed_gop
rw ;~o.,.. a~ion ~or the group d pictures o-ing decoded.
7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1
¦ r ¦ r ¦ r ¦ r ¦ r ¦ r ¦ c ¦ b ¦
Flags:
c - closed_gop
Table A.14.4 Other Video Dentux regi~ters lcontd)
2145159
~,
298
H gist-r nam~ 7 0 - m i~
~r.i c
preclction_moo- 5 During MPEG and H 2610peration this regis~er holds tn- current value ol
rw prediction mode
1 7 1 6 1 5 1 4 1 3 1 2 1 l I O I
¦ r ¦ r ¦ r ¦ h ¦ y ¦ x ¦ b ¦ ~ ¦
Rags
h - enab~e H 261 loop filter
y - reset backward vector prediction
vbv_delay 16 This register is ioaded wh-n decoding MPEG data with a value indicating the
rw minimum stan up d-lay b-tore decoding should stan
Se- th- MPEG stundud tor a dennition o~ this value
This value is not wed by the decoder chips However he value it holds may
b- us-hl to user w~tware when configuring the decoder start-up registers
pic_number 8 This register holds the pictur- number ~or the pictures that is currently 3eing
rw decoded by th- Video O-mux This number was generated by the stan code
d-tector when this picture arriv-d there
See Tabb A 11 2 ~or a d ~ ~ ti ~ 0~ the picture number
dummy_last_plcture 1 0 Th-s- registers are also visbl- at th- top hvel See Tabl- A14 1
rw
n-ld_lnto 1 0
rw
continu- 1 0
rw
rom_revision 8
rw
coding_standard 2 This register is loadeo by the CODING_STANDARD Token to confsLre
ro th- Video Oemux~s mode o~ operation
See section A 21 1
Table A.14.4 O~er Video Demux r~ t,crs (contd)
2145159
299
~i
Register name a ~nD Cescription
i~i
resutt_ln~erval ~ This register is loaded wnen decocing JPEG data wlttl a value indica~lng ~ne
rw minimum start-up delay beiore decooing should s:an.
See the Mf~EG standard ior a definition o~ ~his value.
Table A.14.4 other Video Demux registers ~contd)
register Tok-nstandard comment
CG--"~on~n~_nam-_n COMPONENT_NAME JPEG in coded da~a.
MpEG nol used in standard.
H.26 1
hork_pels HORIZONTAL_SIZE MPEG in coded data.
vert_pe~s VERTICAL_SIZEJPEG
H.261 automalically derived ~rom pic~ure
type.
hori2_,. 1~ .t o HORIZONTAL_M8S MPEG control sofrware must denve irom
vert_ u ot oo VERTICAL_MBS JpEG honzontalandverticalpicturesize.
H.261 autum "y derived trom pic:ure
type.
max_h DEFINE_MAX_SAMPLING MPEG control sottware must configure.
mav_v Sampling structure is fixed by
standard.
JpEG in coded data.
H.261 auto".a~ configurec lor 4:2:~
video.
Table A.14.5 Register to Token cross reference
2145159
300
regisler Tok-n standard commen~
mas_c~ t_ld MAX_COMP_IDMPEG control sonware musl configure.
Sampling structure is fixed by
slandard.
JPEG in coded data.
H.261 aulomatically configured lot 4:2:0
video.
tq_o JPEG_TAE~LE_SELECT JPEG in coded dala.
tq 1 MPEG not used in standard.
H.261
tq_2
tq_3
310ck5_h_0 DEFINE_SAMPLING MPEG controlsofrqaremuslconfigure.
block-_h_1 Sampling structure is fixed ~y
blocks_h_2 slandard.
blocks_h_3 JpEG in coded data.
H.261 dUtu.l.dli~ y configu~ed lor 4:2:0
blocks_v_0
video.
blocks_v_1
blocks_v_2
blocks_v_3
dc_hun_0 inxanhead rdata JPEG incoded dala.
dc_hutt_1 MPEG_DCH_TABLE MPEG control sonware mwl configure.
H.261 nol used in standard.
dc_hut~_2
dc_hut~_3
ac_hutl_0 in xan h-ader dataJpEG in coded data.
ac_hutt_1 MPEG not used in standard.
H.261
ac_hun_2
ac_hut~_3
Table A.14.5 Register to Token cross
reference (contd)
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