Note: Descriptions are shown in the official language in which they were submitted.
DEMANDES OU BREVETS VOLUMINEUX
LA PRÉSENTE PARTIE DE CETTE DENIANDE OU CE BREVET
COMPREND PLUS D'UN TOME.
CECI EST LE TOME DE
NOTE: Pour les tomes additionels, veuillez contacter ie Bureau canadien des
brevets
2 1~ 5 S'~
J~JMBO APPLICATIONS/PATENTS
THIS SECTION OF THE APPLICATION/iATENT CONTAINS MORE
THAN ONE VOLUME
THIS IS VOLUME l- OF ~ -
NOTE: For additional volumes please c~ntact the Canadian Patent Office
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PIPELINE
This application claims priority from British Application
No. British Application No. 9405914.4 filed March 24, 1994 and
British Application No. (not yet known) filed February 28, 1995.
RA~R~ROUND OF THE lNV~. ~lON
The present invention is directed to improvements in
methods and apparatus for decompression which operates to
decompress and/or decode a plurality of differently encoded
input signals. The illustrative embodiment chosen for
description hereinafter relates to the decoding of a plurality
of encoded picture standards. More specifically, this
embodiment relates to the decoding of any one of the well known
standards known as JPEG, MPEG and H.261.
A serial pipeline processing system of the present
invention comprises a single two-wire bus used for carrying
unique and specialized interactive interfacing tokens, in the
form of control tokens and data tokens, to a plurality of
adaptive decompression circuits and the like positioned as a
reconfigurable pipeline processor.
Video compression/decompression systems are generally well-
known in the art. However, such systems have generally been
dedicated in design and use to a single compression standard.
They have also suffered from a number of other inefficiencies
and inflexibility in overall system and subsystem design and
data flow management.
Examples of prior art systems and subsystems are enumerated
as follows:
One prior art system is described in United States Patent
No. 5,216,724. The apparatus comprises a plurality of compute
modules, in a preferred embodiment, for a total of four compute
modules coupled in parallel. Each of the
`_` 21~54~4
compute modules has a processor, dual port memory, scratch-
pad memory, and an arbitration mechanism. A first bus
couples the compute modules and a host processor. The device
comprises a shared memory which is coupled to the host
processor and to the compute modules with a second bus.
United States Patent No. 4,785,349 discloses a full
motion color digital video signal that is compressed,
formatted for transmission, recorded on compact disc media
and decoded at conventional video frame rates. During
compression, regions of a frame are individually analyzed to
select optimum fill coding methods specific to each region.
Region decoding time estimates are made to optimize
compression thresholds. Region descriptive codes conveying
the size and locations of the regions are grouped together in
a first segment of a data stream. Region fill codes
- conveying pixel amplitude indications for the regions are
grouped together according to fill code type and placed in
other segments of the data stream. The data stream segments
are individually variable length coded according to their
respective statistical distributions and formatted to form
data frames. The number of bytes per frame is withered by
the addition of auxiliary data determined by a reverse frame
sequence analysis to provide an average number selected to
minimize pauses of the compact disc during playback, thereby
avoiding unpredictable seek mode latency periods
characteristic of compact discs. A decoder includes a
variable length decoder responsive to statistical information
in the code stream for separately variable length decoding
individual segments of the data stream. Region location data
is derived from region descriptive data and applied with
region fill codes to a plurality of region specific decoders
selected by detection of the fill code type (e.g., relative,
absolute, dyad and DPCM) and decoded region pixels are stored
in a bit map for subsequent display.
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-
United States Patent No. 4,922,341 discloses a method
for scene-model-assisted reduction of image data for digital
television signals, whereby a picture signal supplied at time
is to be coded, whereby a predecessor frame from a scene
already coded at time t-l is present in an image store as a
reference, and whereby the frame-to-frame information is
composed of an amplification factor, a shift factor, and an
adaptively acquired quad-tree division structure. Upon
initialization of the system, a uniform, prescribed gray
scale value or picture half-tone expressed as a defined
luminance value is written into the image store of a coder at
the transmitter and in the image store of a decoder at the
receiver store, in the same way for all picture elements
(pixels). Both the image store in the coder as well as the
image store in the decoder are each operated with feed back
to themselves in a manner such that the content of the image
store in the coder and decoder can be read out in blocks of
variable size, can be amplified with a factor greater than or
less than 1 of the luminance and can be written back into the
image store with shifted addresses, whereby the blocks of
variable size are organized according to a known quad tree
data structure.
United States Patent No. 5,122,875 discloses an
apparatus for encoding/decoding an HDTV signal. The
apparatus includes a compression circuit responsive to high
definition video source signals for providing hierarchically
layered codewords CW representing compressed video data and
associated codewords T, defining the types of data
represented by the codewords CW. A priority selection
circuit, responsive to the codewords CW and T, parses the
codewords CW into high and low priority codeword sequences
wherein the high and low priority codeword sequences
correspond to compressed video data of relatively greater and
lesser importance to image reproduction respectively. A
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transport processor, responsive to the high and low priority
codeword sequences, forms high and low priority transport
blocks of high and low priority codewords, respectively.
Each transport block includes a header, codewords CW and
error detection check bits. The respective transport blocks
are applied to a forward error check circuit for applying
additional error check data. Thereafter, the high and low
priority data are applied to a modem wherein quadrature
amplitude modulates respective carriers for transmission.
United States Patent No. 5,146,325 discloses a video
decompression system for decompressing compressed image data
wherein odd and even fields of the video signal are
independently compressed in sequences of intraframe and
interframe compression modes and then interleaved for
transmission. The odd and even fields are independently
decompressed. During intervals when valid decompressed
odd/even field data is not available, even/odd field data is
substituted for the unavailable odd/even field data.
Independently decompressing the even and odd fields of data
and substituting the opposite field of data for unavailable
data may be used to advantage to reduce image display latency
during system start-up and channel changes.
United States Patent No. 5,168,356 discloses a video
signal encoding system that includes apparatus for segmenting
encoded video data into transport blocks for signal
transmission. The transport block format enhances signal
recovery at the receiver by virtue of providing header data
from which a receiver can determine re-entry points into the
data stream on the occurrence of a loss or corruption of
transmitted data. The re-entry points are maximized by
providing secondary transport headers embedded within encoded
video data in respective transport blocks.
United States Patent No. 5,168,375 discloses a method
for processing a field of image data samples to provide for
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one or more of the functions of decimation, interpolation,
and sharpening. This is accomplished by an array transform
processor such as that employed in a JPEG compression system.
Blocks of data samples are transformed by the discrete even
cosine transform (DECT) in both the decimation and
interpolation processes, after which the number of frequency
terms is altered. In the case of decimation, the number of
frequency terms is reduced, this being followed by inverse
transformation to produce a reduced-size matrix of sample
points representing the original block of data. In the case
of interpolation, additional frequency components of zero
value are inserted into the array of frequency components
after which inverse transformation produces an enlarged data
sampling set without an increase in spectral bandwidth. In
the case of sharpening, accomplished by a convolution or
filtering operation involving multiplication of transforms of
data and filter kernel in the frequency domain, there is
provided an inverse transformation resulting in a set of
blocks of processed data samples. The blocks are overlapped
followed by a savings of designated samples, and a discarding
of excess samples from regions of overlap. The spatial
representation of the kernel is modified by reduction of the
number of components, for a linear-phase filter, and zero-
padded to equal the number of samples of a data block, this
being followed by forming the discrete odd cosine transform
(DOCT) of the padded kernel matrix.
United States Patent No. 5,175,617 discloses a system
and method for transmitting logmap video images through
telephone line band-limited analog channels. The pixel
organization in the logmap image is designed to match the
sensor geometry of the human eye with a greater concentration
of pixels at the center. The transmitter divides the
frequency band into channels, and assigns one or two pixels
to each channel, for example a 3KHz voice quality telephone
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line is divided into 768 channels spaced about 3.9Hz apart.
Each channel consists of two carrier waves in quadrature, so
each channel can carry two pixels. Some channels are
reserved for special calibration signals enabling the
S receiver to detect both the phase and magnitude `of the
received signal. If the sensor and pixels are connected
directly to a bank of oscillators and the receiver can
continuously receive each channel, then the receiver need not
be synchronized with the transmitter. An FFT algorithm
implements a fast discrete approximation to the continuous
case in which the receiver synchronizes to the first frame
and then acquires subsequent frames every frame period. The
frame period is relatively low compared with the sampling
period so the receiver is unlikely to lose frame synchrony
once the first frame is detected. An experimental video
- telephone transmitted 4 frames per second, applied quadrature
coding to 1440 pixel logmap images and obtained an effective
data transfer rate in excess of 40,000 bits per second.
United States Patent No. 5,185,819 discloses a video
compression system having odd and even fields of video signal
that are independently compressed in sequences of intraframe
and interframe compression modes. The odd and even fields of
independently compressed data are interleaved for
transmission such that the intraframe even field compressed
data occurs midway between successive fields of intraframe
odd field compressed data. The interleaved sequence provides
receivers with twice the number of entry points into the
signal for decoding without increasing the amount of data
transmitted.
United States Patent No. 5,212,742 discloses an
apparatus and method for processing video data for
compression/decompression in real-time. The apparatus
comprises a plurality of compute modules, in a preferred
embodiment, for a total of four compute modules coupled in
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.
parallel. Each of the compute modules has a processor, dual
port memory, scratch-pad memory, and an arbitration
mechanism. A first bus couples the compute modules and host
processor. Lastly, the device comprises a shared memory
which is coupled to the host processor and to the compute
modules with a second bus. The method handles assigning
portions of the image for each of the processors to operate
upon.
United States Patent No. 5,231,484 discloses a system
and method for implementing an encoder suitable for use with
the proposed IS0/IEC MPEG standards. Included are three
cooperating components or subsystems that operate to
variously adaptively pre-process the incoming digital motion
video sequences, allocate bits to the pictures in a sequence,
and adaptively quantize transform coefficients in different
regions of a picture in a video sequence so as to provide
optimal visual quality given the number of bits allocated to
that picture.
United States Patent No. 5,267,334 discloses a method of
removing frame redundancy in a computer system for a sequence
of moving images. The method comprises detecting a first
scene change in the sequence of moving images and generating
a first keyframe containing complete scene information for a
first image. The first keyframe is known, in a preferred
embodiment, as a "forward-facing" keyframe or intraframe, and
it is normally present in CCITT compressed video data. The
process then comprises generating at least one intermediate
compressed frame, the at least one intermediate compressed
frame containing difference information from the first image
for at least one image following the first image in time in
the sequence of moving images. This at least one frame being
known as an interframe. Finally, detecting a second scene
change in the sequence of moving images and generating a
second keyframe containing complete scene information for an
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image displayed at the time just prior to the second scene
change, known as a "backward-facing" keyframe. The first
keyframe and the at least one intermediate compressed frame
are linked for forward play, and the second keyframe and the
intermediate compressed frames are linked in reverse for
reverse play. The intraframe may also be used for generation
of complete scene information when the images are played in
the forward direction. When this sequence is played in
reverse, the backward-facing keyframe is used for the
generation of complete scene information.
United States Patent No. 5,276,513 discloses a first
circuit apparatus, comprising a given number of prior-art
image-pyramid stages, together with a second circuit
apparatus, comprising the same given number of novel motion-
vector stages, perform cost-effective hierarchical motion
analysis (HMA) in real-time, with minimum system processing
delay and/or employing minimum system processing delay and/or
employing minimum hardware structure. Specifically, the
first and second circuit apparatus, in response to relatively
high-resolution image data from an ongoing input series of
successive given pixel-density image-data frames that occur
at a relatively high frame rate (e.g., 30 frames per second),
derives, after a certain processing-system delay, an ongoing
output series of successive given pixel-density vector-data
frames that occur at the same given frame rate. Each vector-
data frame is indicative of image motion occurring between
each pair of successive image frames.
United States Patent No. 5,283,646 discloses a method
and apparatus for enabling a real-time video encoding system
to accurately deliver the desired number of bits per frame,
while coding the image only once, updates the quantization
step size used to quantize coefficients which describe, for
example, an image to be transmitted over a communications
channel. The data is divided into sectors, each sector
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including a plurality of blocks. The blocks are encoded, for
example, using DCT coding, to generate a sequence of
coefficients for each block. The coefficients can be
quantized, and depending upon the quantization step, the
number of bits required to describe the data will vary
significantly. At the end of the transmission of each sector
of data, the accumulated actual number of bits expended is
compared with the accumulated desired number of bits
expended, for a selected number of sectors associated with
the particular group of data. The system then readjusts the
quantization step size to target a final desired number of
data bits for a plurality of sectors, for example describing
an image. Various methods are described for updating the
quantization step size and determining desired bit
allocations.
The article, Chong, Yong M., A Data-Flow Architecture
for Digital Imaqe Processing, Wescon Technical Papers: No.
2 Oct./Nov. 1984, discloses a real-time signal processing
system specifically designed for image processing. More
particularly, a token based data-flow architecture is
disclosed wherein the tokens are of a fixed one word width
having a fixed width address field. The system contains a
plurality of identical flow processors connected in a ring
fashion. The tokens contain a data field, a control field
and a tag. The tag field of the token is further broken down
into a processor address field and an identifier field. The
processor address field is used to direct the tokens to the
correct data-flow processor, and the identifier field is used
to label the data such that the data-flow processor knows
what to do with the data. In this way, the identifier field
acts as an instruction for the data-flow processor. The
system directs each token to a specific data-flow processor
using a module number (MN). If the MN matches the MN of the
particular stage, then the appropriate operations are
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performed upon the data. If unrecognized, the token is
directed to an output data bus.
The article, Kimori, S. et al. An Elastic Pipeline
Mechanism by Self-Timed Circuits, IEEE J. of Solid-State
Circuits, Vol. 23, No. 1, February 1988, discloses an elastic
pipeline having self-timed circuits. The asynchronous
pipeline comprises a plurality of pipeline stages. Each of
the pipeline stages consists of a group of input data latches
followed by a combinatorial logic circuit that carries out
logic operations specific to the pipeline stages. The data
latches are simultaneously supplied with a triggering signal
generated by a data-transfer control circuit associated with
that stage. The data-transfer control circuits are
interconnected to form a chain through which send and
acknowledge signal lines control a hand-shake mode of data
transfer between the successive pipeline stages.
Furthermore, a decoder is generally provided in each stage to
select operations to be done on the operands in the present
stage. It is also possible to locate the decoder in the
preceding stage in order to pre-decode complex decoding
processing and to alleviate critical path problems in the
logic circuit. The elastic nature of the pipeline eliminates
any centralized control since all the interworkings between
the submodules are determined by a completely localized
decision and, in addition, each submodule can autonomously
perform data buffering and self-timed data-transfer control
at the same time. Finally, to increase the elasticity of the
pipeline, empty stages are interleaved between the occupied
stages in order to ensure reliable data transfer between the
stages.
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Accordingly, those concerned with the design,
development and use of video compression/decompression
systems and related subsystems have long recognized a need
for improved methods and apparatus providing enhanced
flexibility, efficiency and performance. The present
invention clearly fulfills all these needs.
8UMMARY OF THE lNV~. .lON
Briefly, and in general terms, the present invention
provides an input, an output and a plurality of processing
stages between the input and the output, the plurality of
processing stages being interconnected by a two-wire
interface for conveyance of tokens along a pipeline, and
control and/or DATA tokens in the form of universal
adaptation units for interfacing with all of the stages in
the pipeline and interacting with selected stages in the
pipeline, whereby the processing stages in the pipeline are
afforded enhanced flexibility in configuration and
processing.
Each of the processing stages in the pipeline may
include both primary and secondary storage, and the stages in
the pipeline are reconfigurable in response to recognition of
selected tokens. The tokens in the pipeline are dynamically
adaptive and may be position dependent upon the processing
stages for performance of functions or position independent
of the processing stages for performance of functions.
In a pipeline machine, in accordance with the invention,
the tokens may be altered by interfacing with the stages, and
the tokens may interact with all of the processing stages in
the pipeline or only with some but less than all of said
processing stages. The tokens in the pipeline may interact
with adjacent processing stages or with non-adjacent
processing stages, and the tokens may reconfigure the
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processing stages. Such tokens may be position dependent for
some functions and position independent for other functions
in the pipeline.
The tokens provide a basic building block for the
pipeline system. The interaction of the tokens with a
processing stage in the pipeline may be conditioned by the
previous processing history of that processing stage. The
tokens may have address fields which characterize the tokens,
and the interactions with a processing stage may be
determined by such address fields.
In an improved pipeline machine, in accordance with the
invention, the tokens may include an extension bit for each
token, the extension bit indicating the presence of
additional words in that token and identifying the last word
in that token. The address fields may be of variable length
and may also be Huffman coded.
In the improved pipeline machine, the tokens may be
generated by a processing stage. Such pipeline tokens may
include data for transfer to the processing stages or the
tokens may be devoid of data. Some of the tokens may be
identified as DATA tokens and provide data to the processing
stages in the pipeline, while other tokens are identified as
control tokens and only condition the processing stages in
the pipeline, such conditioning including reconfiguring of
the processing stages. Still other tokens may provide both
data and conditioning to the processing stages in the
pipeline. Some of said tokens may identify coding standards
to the processing stages in the pipeline, whereas other
tokens may operate independent of any coding standard among
the processing stages. The tokens may be capable of
successive alteration by the processing stages in the
pipeline.
In accordance with the invention, the interactive
flexibility of the tokens in cooperation with the processing
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stages facilitates greater functional diversity of the
processing stages for resident structure in the pipeline, and
the flexibility of the tokens facilitates system expansion
and/or alteration. The tokens may be capable of facilitating
a plurality of functions within any processing stage in the
pipeline. Such pipeline tokens may be either hardware based
or software based. Hence, the tokens facilitate more
efficient uses of system bandwidth in the pipeline. The
tokens may provide data and control simultaneously to the
processing stages in the pipeline.
The invention may include a pipeline processing machine
for handling plurality of separately encoded bit streams
arranged as a single serial bit stream of digital bits and
having separately encoded pairs of control codes and
corresponding data carried in the serial bit stream and
employing a plurality of stages interconnected by a two-wire
interface, further characterized by a start code detector
responsive to the single serial bit stream for generating
control tokens and DATA tokens for application to the two-
wire interface, a token decode circuit positioned in certainof the stages for recognizing certain of the tokens as
control tokens pertinent to that stage and for passing
unrecognized control tokens along the pipeline, and a
reconfigurable decode and parser processing means responsive
to a recognized control token for reconfiguring a particular
stage to handle an identified DATA token.
The pipeline machine may also include first and second
registers, the first register being positioned as an input of
the decode and parser means, with the second register
positioned as an output of the decode and parser means. One
of the processing stages may be a spatial decoder, a second
of the stages being a token generator for generating control
tokens and DATA tokens for passage along the two-wire
interface. A token decode means is positioned in the spatial
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14
decoder for recognizing certain of the tokens as control
tokens pertinent to the spatial decoder and for configuring
the spatial decoder for spatially decoding DATA tokens
following a control token into a first decoded format.
S A further stage may be a temporal decoder positioned
downstream in the pipeline from the spatial decoder, with a
second token decode means positioned in the temporal decoder
for recognizing certain of the tokens as control tokens
pertinent to the temporal decoder and for configuring the
temporal decoder for termporally decoding the DATA tokens
following the control token into a first decoded format. The
temporal decoder may utilize a reconfigurable prediction
filter which is reconfigurable by a prediction token. Data
may be moved along the two-wire interface within the temporal
decoder in 8x8 pel data blocks, and address means may be
provided for storing and retrieving such data blocks along
block boundaries. The address means may store and retrieve
blocks of data across block boundaries. The address means
reorders said blocks as picture data for display. The data
blocks stored and retrieved may be greater and/or smaller
than 8x8 pel data blocks. Circuit means may also be provided
for either displaying the output of the temporal decoder or
writing the output back into a picture memory location. The
decoded format may be either a still picture format or a
moving picture format.
The above and other objectives and advantages of the
invention will become apparent from the following more
detailed description when taken in conjunction with the
accompanying drawings.
214542g
DE8CRIPTION OF THE DRAWING8
Figure. 1 illustrates six cycles of a six-stage pipeline for
different combinations of two internal control signals;
Figures. 2a and 2b illustrate a pipeline in which each stage
includes auxiliary data storage. They also show the manner
in which pipeline stages can "compress" and "expand" in
response to delays in the pipeline;
Figures. 3a(1), 3a(2), 3b(1) and 3b(2) illustrate the control
of data transfer between stages of a preferred embodiment of
a pipeline using a two-wire interface and a multi-phase
clock;
Figure. 4 is a block diagram that illustrates a basic
embodiment of a pipeline stage that incorporates a two-wire
transfer control and also shows two consecutive pipeline
processing stages with the two-wire transfer control;
Figures. Sa and Sb taken together depict one example of a
timing diagram that shows the relationship between timing
signals, input and output data, and internal control signals
used in the pipeline stage as shown in Figure. 4;
Figure. 6 is a block diagram of one example of a pipeline
stage that holds its state under the control of an extension
bit;
Figure. 7 is a block diagram of a pipeline stage that decodes
stage activation data words;
Figures. 8a and 8b taken together form a block diagram
showing the use of the two-wire transfer control in an
exemplifying "data duplication" pipeline stage;
Figures. 9a and 9b taken together depict one example of a
timing diagram that shows the two-phase clock, the two-wire
transfer control signals and the other internal data and
control signals used in the exemplifying embodiment shown in
Figures. 8a and 8b.
Figure 10 is a block diagram of a reconfigurable processing
stage;
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16
Figure 11 is a block diagram of a spatial decoder;
Figure 12 is a block diagram of a temporal decoder;
Figure 13 is a block diagram of a video formatter;
Figures 14a-c show various arrangements of memory blocks used
in the present invention:
Figure 14a is a memory map showing a first
arrangement of macroblocks;
Figure 14b is a memory map showing a second
arrangement of macroblocks;
Figure 14c is a memory map showing a further
arrangement of macroblocks;
Figure 15 shows a Venn diagram of possible table selection
values;
Figure 16 shows the variable length of picture data used in
the present invention;
Figure 17 is a block diagram of the temporal decoder
including the prediction filters;
Figure 18 is a pictorial representation of the prediction
filtering process;
Figure 19 shows a generalized representation of the
macroblock structure;
Figure 20 shows a generalized block diagram of a Start Code
Detector;
Figure 21 illustrates examples of start codes in a data
stream;
Figure 22 is a block diagram depicting the relationship
between the flag generator, decode index, header
generator, extra word generator and output latches;
Figure 23 is a block diagram of the Spatial Decoder DRAM
interface;
Figure 24 is a block diagram of a write swing buffer;
Figure 25 is a pictorial diagram illustrating prediction data
offset from the block being processed;
Figure 26 is a pictorial diagram illustrating prediction data
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offset by (1,1);
Figure 27 is a block diagram illustrating the Huffman decoder
and parser state machine of the Spatial Decoder.
Figure 28 is a block diagram illustrating the prediction
filter.
4 ~4
18
FIGURE8
Figure 29 shows a typical decoder system;
Figure 30 shows a JPEG still picture decoder;
Figure 31 shows a JPEG video decoder;
5 Figure 32 shows a multi-standard video decoder;
Figure 33 shows the start and the end of a token;
Figure 34 shows a token address and data fields;
Figure 35 shows a token on an interface wider than
8 bits;
10 Figure 36 shows a macroblock structure;
Figure 37 shows a two-wire interface protocol;
Figure 38 shows the location of external two-wire
interfaces;
Figure 39 shows clock propagation;
15 Figure 40 shows two-wire interface timing;
Figure 41 shows examples of access structure;
Figure 42 shows a read transfer cycle;
Figure 43 shows an access start timing;
Figure 44 shows an example access with two write
20 transfers;
Figure 45 shows a read transfer cycle;
Figure 46 shows a write transfer cycle;
Figure 47 shows a refresh cycle;
Figure 48 shows a 32 bit data bus and a 256 kbit
deep DRAMs (9 bit row add~ess);
Figure 49 shows timing parameters for any strobe
signal;
Figure 50 shows timing parameters between any two
strobe signals;
30 Figure 51 shows timing parameters between a bus and
a strobe;
Figure 52 shows timing parameters between a bus and
a strobe;
Figure 53 shows an MPI read timing;
35 Figure 54 shows an MPI write timing;
Figure 55 shows organization of large integers in
the memory map;
Figure 56 shows a typical decoder clock regime;
Figure 57 shows input clock requirements;
40 Figure 58 shows the Spatial Decoder;
Figure 59 shows the inputs and outputs of the input
circuit;
Figure 60 shows the coded port protocol;
Figure 61 shows the start code detector;
45 Figure 62 shows start codes detected and converted
to Tokens;
Figure 63 shows the start codes detector passing
Tokens;
Figure 64 shows overlapping MPEG start codes (byte
50 aligned);
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Figure 65 shows overlapping MPEG start codes (not
byte aligned);
Figure 66 shows jumping between two video
sequences;
5 Figure 67 shows a sequence of extra Token
insertion;
Figure 68 shows decoder start-up control;
Figure 69 shows enabled streams queued before the
output;
10 Figure 70 shows a spatial decoder buffer;
Figure 71 shows a buffer pointer;
Figure 72 shows a video demux;
Figure 73 shows a construction of a picture;
Figure 74 shows a construction of a 4:2:2
15 macroblock;
Figure 75 shows a calculating macroblock dimension
from pel ones;
Figure 76 shows spatial decoding;
Figure 77 shows an overview of H.261 inverse
20 quantization;
Figure 78 shows an overview of JPEG inverse
quantization;
Figure 79 shows an overview of MPEG inverse
quantization;
25 Figure 80 shows a quantization table memory map;
Figure 81 shows an overview of JPEG baseline
sequential structure;
Figure 82 shows a tokenised JPEG picture;
Figure 83 shows a temporal decoder;
30 Figure 84 shows a picture buffer specification;
Figure 85 shows an MPEG picture sequence (m=3);
Figure 86 shows how "I" pictures are stored and
output;
Figure 87 shows how "P" pictures are formed, stored
35 and output;
Figure 88 shows how "B" pictures are formed and
output;
Figure 89 shows P picture formation;
Figure 90 shows H.261 prediction formation;
Figure 91 shows an H.261 "sequence";
Figure 92 shows a hierarchy of H.261 syntax;
Figure 93 shows an H.261 picture layer;
Figure 94 shows an H.261 arrangement of groups of
blocks;
Figure 95 shows an H.261 "slice" layer;
Figure 96 shows an H.261 arrangement of
macroblocks;
Figure 97 shows an H.261 sequence of blocks;
Figure 98 shows an H.261 macroblock layer;
Figure 99 shows an H.261 arrangement of pels in
blocks;
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Figure 100 shows a hierarchy of MPEG syntax;
Figure 101 shows an MPEG sequence layer;
Figure 102 shows an MPEG group of pictures layer;
Figure 103 shows an MPEG picture layer;
5 Figure 104 shows an MPEG "slice" layer;
Figure 105 shows an MPEG sequence of blocks;
Figure 106 shows an MPEG macroblock layer;
Figure 107 shows an "open GOP";
Figure 108 shows examples of access structure;
10 Figure 109 shows access start timing;
Figure 110 shows a fast page read cycle;
Figure 111 shows a fast page write cycle;
Figure 112 shows a refresh cycle;
Figure 113 shows extracting row and column address
15 from a chip address;
Figure 114 shows timing parameters for any strobe
signal;
Figure 115 shows timing parameters between any two
strobe signals;
20 Figure 116 shows timing parameters between a bus and
a strobe;
Figure 117 shows timing parameters between a bus and
a strobe;
Figure 118 shows a Huffman decoder and parser;
Figure 119 shows an H.261 and an MPEG AC Coefficient
Decoding Flow Chart;
Figure 120 shows a block diagram for JPEG (AC and
DC) coefficient decoding;
Figure 121 shows a flow diagram for JPEG (AC and DC)
coefficient decoding;
Figure 122 shows an interface to the Huffman Token
Formatter;
Figure 123 shows a token formatter block diagram;
Figure 124 shows an H.261 and an MPEG AC Coefficient
Decoding;
Figure 125 shows the interface to the Huffman ALU;
Figure 126 shows the basic structure of the Huffman
ALU;
Figure 127 shows the buffer manager;
40 Figure 128 shows an imodel and hsppk block diagram;
Figure 129 shows an imex state diagram;
Figure 130 illustrates the buffer start-up;
Figure 131 shows a DRAM interface;
Figure 132 shows a write swing buffer;
45 Figure 133 shows an arithmetic block;
Figure 134 shows an iq block diagram;
Figure 135 shows an iqca state machine;
Figure 136 shows an IDCT 1-D Transform Algorithm;
Figure 137 shows an IDCT 1-D Transform Architecture;
50 Figure 138 shows a token stream block diagram;
Figure 139 shows a standard block structure;
- ~14~24
Figure 140 is a block diagram showing;
microprocessor test access;
Figure 141 shows l-D Transform Micro-Architecture;
Figure 142 shows a temporal decoder block diagram;
5 Figure 143 shows the structure of a Two-wire
interface stage; ~
Figure 144 shows the address generator block
diagram;
Figure 145 shows the block and pixel offsets;
10 Figure 146 shows multiple prediction filters;
Figure 147 shows a single prediction filter;
Figure 148 shows the l-D prediction filter;
Figure 149 shows a block of pixels;
Figure 150 shows the structure of the read rudder;
15 Figure 151 shows the block and pixel offsets;
Figure 152 shows a prediction example;
Figure 153 shows the read cycle;
Figure 154 shows the write cycle;
Figure 155 shows the top-level registers block
diagram with timing references;
Figure 156 shows the control for incrementing
presentation numbers;
Figure 157 shows the buffer manager state machine
(complete);
Figure 158 shows the state machine main loop;
Figure 159 shows the buffer 0 containing an SIF (22
by 18 macroblocks) picture;
Figure 160 shows the SIF component 0 with a display
window;
Figure 161 shows an example picture format showing
storage block address;
Figure 162 shows a buffer 0 containing a SIF (22 by
18 macroblocks) picture;
Figure 163 shows an example address calculatlon;
35 Figure 164 shows a write address generation state
machine;
Figure 165 shows a slice of the datapath;
Figure 166 shows a two cycle operation of the
datapath;
40 Figure 167 shows mode 1 filtering;
Figure 168 shows a horizontal up-sampler datapath;
and
Figure 169 shows the structure of the color-space
converter.
2145424
In the ensuing description of the practice of the
invention, the following terms are frequently used and are
generally defined by the following glossary:
GL088ARY
S BLOCR: An 8-row by 8-column matrix of pels, or 64 DCT
coefficients (source, quantized or dequantized).
CUPo~TN~NcE (COMPONENT): A matrix, block or single pel
representing one of the two color difference signals related
to the primary colors in the manner defined in the bit
stream. The symbols used for the color difference signals
are Cr and Cb.
CODED REPRE8ENTATION: A data element as represented in its
encoded form.
CODED VIDEO BIT 8TREAM: A coded representation of a series of
one or more pictures as defined in this specification.
CODED ORDER: The order in which the pictures are transmitted
and decoded. This order is not necessarily the same as the
display order.
COMPONENT: A matrix, block or single pel from one of the
three matrices (luminance and two chrominance) that make up
a picture.
COMPRE88ION: Reduction in the number of bits used to
represent an item of data.
DECODER: An embodiment of a decoding process.
DECODING ~PROCE88): The process defined in this specification
that reads an input coded bitstream and produces decoded
pictures or audio samples.
DI8PLAY ORDER: The order in which the decoded pictures are
displayed. Typically, this is the same order in which they
were presented at the input of the encoder.
ENCODING (PROCE88): A process, not specified in this
specification, that reads a stream of input pictures or audio
samples and produces a valid coded bitstream as defined in
this specification.
~1~S424
INTRA CODING: Coding of a macroblock or picture that uses
information only from that macroblock or picture.
LUMTN~NCE ~COMPONENT): A matrix, block or single pel
representing a monochrome representation of the signal and
related to the primary colors in the manner defined in the
bit stream. The symbol used for luminance is Y.
MACROBLOCK: The four 8 by 8 blocks of luminance data and the
two (for 4:2:0 chroma format) four (for 4:2:2 chroma format)
or eight (for 4:4:4 chroma format) corresponding 8 by 8
blocks of chrominance data coming from a 16 by 16 section of
the luminance component of the picture. Macroblock is
sometimes used to refer to the pel data and sometimes to the
coded representation of the pel values and other data
elements defined in the macroblock header of the syntax
defined in this part of this specification. To one of
ordinary skill in the art, the usage is clear from the
context.
MOTION COMPEN8ATION: The use of motion vectors to improve the
efficiency of the prediction of pel values. The prediction
uses motion vectors to provide offsets into the past and/or
future reference pictures containing previously decoded pel
values that are used to form the prediction error signal.
MOTION VECTOR: A two-dimensional vector used for motion
compensation that provides an offset from the coordinate
position in the current picture to the coordinates in a
reference picture.
NON-INTRA CODING: Coding of a macroblock or picture that uses
information both from itself and from macroblocks and
pictures occurring at other times.
PEL: Picture element.
PICT~RE: Source, coded or reconstructed image data. A source
or reconstructed picture consists of three rectangular
matrices of 8-bit numbers representing the luminance and two
chrominance signals. For progressive video, a picture is
- 214~ 424
identical to a frame, while for interlaced video, a picture
can refer to a frame, or the top field or the bottom field of
the frame depending on the context.
PREDICTION: The use of a predictor to provide an estimate of
the pel value or data element currently being decoded.
P~:CO~lGURABLE PROCE88 8TAGE ~RP8): A stage, which in
response to a recognized token, reconfigures itself to
perform various operations.
8LICE: A series of macroblocks.
TOREN: A universal adaptation unit in the form of an
interactive interfacing messenger package for control and/or
data functions.
8TART CODE8 t~YS~ AND VIDEO]: 32-bit codes embedded in a
coded bitstream that are unique. They are used for several
purposes including identifying some of the structures in the
coding syntax.
VARIABLE LENGTH CODING; VLC: A reversible procedure for
coding that assigns shorter code-words to frequent events and
longer code-words to less frequent events.
VIDEO 8EQUENCE: A series of one or more pictures.
Detailed Descriptions
21~5~24
DE8CRIPTION OF THE PREFERRED ~MRODIMENT~)
As an introduction to the most general features used in a
pipeline system which is utilized in the preferred
embodiments of the invention, Fig. 1 is a greatly simplified
illustration of six cycles of a six-stage pipeline. (As is
explained in greater detail below, the preferred embodiment
of the pipeline includes several advantageous features not
shown in Fig 1.).
Referring now to the drawings, wherein like reference
numerals denote like or corresponding elements throughout the
various figures of the drawings, and more particularly to
Fig. 1, there is shown a block diagram of six cycles in
practice of the present invention. Each row of boxes
illustrates a cycle and each of the different stages are
labelled A-F, respectively. Each shaded box indicates that
the corresponding stage holds valid data, i.e., data that is
to be processed in one of the pipeline stages. After
processing (which may involve nothing more than a simple
transfer without manipulation of the data) valid data is
transferred out of the pipeline as valid output data.
Note that an actual pipeline application may include more
or fewer than six pipeline stages. As will be appreciated,
the present invention may be used with any number of pipeline
stages. Furthermore, data may be processed in more than one
stage and the processing time for different stages can
differ.
In addition to clock and data signals (described below),
the pipeline includes two transfer control signals -- a
"VALID" signal and an "ACCEPT" signal. These signals are
used to control the transfer of data within the pipeline.
The VALID signal, which is illustrated as the upper of the
two lines connecting neighboring stages, is passed in a
forward or downstream direction from each pipeline stage to
the nearest neighboring device. This device may be another
2145~24
26
pipeline stage or some other system. For example, the last
pipeline stage may pass its data on to subsequent processing
circuitry. The ACCEPT signal, which is illustrated as the
lower of the two lines connecting neighboring stages, passes
in the other direction upstream to a preceding device.
A data pipeline system of the type used in the practice of
the present invention has, in preferred embodiments, one or
more of the following characteristics:
1. The pipeline is "elastic" such that a delay at a
particular pipeline stage causes the minimum disturbance
possible to other pipeline stages. Succeeding pipeline
stages are allowed to continue processing and, therefore,
this means that gaps open up in the stream of data
following the delayed stage. Similarly, preceding
pipeline stages may also continue where possible. In this
case, any gaps in the data stream may, wherever possible,
be removed from the stream of data.
2. Control signals that arbitrate the pipeline are
organized so that they only propagate to the nearest
neighboring pipeline stages. In the case of signals
flowing in the same direction as the data flow, this is
the immediately succeeding stage. In the case of signals
flowing in the opposite direction to the data flow, this
is the immediately preceding stage.
3. The data in the pipeline is encoded such that many
different types of data are processed in the pipeline.
This encoding accommodates data packets of variable size
and the size of the packet need not be known in advance.
4. The overhead associated with describing the type of
data is as small as possible.
5. It is possible for each pipeline stage to recognize
only the minimum number of data types that are needed for
its required function. It should, however, still be able
to pass all data types onto the succeeding stage even
21~542~
though it does not recognize them. This enables
communication between non-adjacent pipeline stages.
Although not shown in Fig. 1, there are data lines,
either single lines or several parallel lines, which form a
S data bus that also lead into and out of each pipeline stage.
As is explained and illustrated in greater detail below, data
is transferred into, out of, and between the stages of the
pipeline over the data lines.
Note that the first pipeline stage may receive data and
control signals from any form of preceding device. For
example, reception circuitry of a digital image transmission
system, another pipeline, or the like. On the other hand, it
may generate itself, all or part of the data to be processed
in the pipeline. Indeed, as is explained below, a "stage"
lS may contain arbitrary processing circuitry, including none at
all (for simple passing of data) or entire systems (for
example, another pipeline or even multiple systems or
pipelines), and it may generate, change, and delete data as
desired.
When a pipeline stage contains valid data that is to be
transferred down the pipeline, the VALID signal, which
indicates data validity, need not be transferred further than
to the immediately subsequent pipeline stage. A two-wire
interface is, therefore, included between every pair of
pipeline stages in the system. This includes a two-wire
interface between a preceding device and the first stage, and
between a subsequent device and the last stage, if such other
devices are included and data is to be transferred between
them and the pipeline.
Each of the signals, ACCEPT and VALID, has a HIGH and a
LOW value. These values are abbreviated as "H" and "L",
respectively. The most common applications of the pipeline,
in practicing the invention, will typically be digital. In
such digital implementations, the HIGH value may, for
~ 214542~
28
example, be a logical "1" and the LOW value may be a logical
"O". The system is not restricted to digital
implementations, however, and in analog implementations, the
HIGH value may be a voltage or other similar quantity above
(or below) a set threshold, with the LOW value being
indicated by the corresponding signal being below (or above)
the same or some other threshold. For digital applications,
the present invention may be implemented using any known
technology, such as CMOS, bipolar etc.
It is not necessary to use a distinct storage device and
wires to provide for storage of VALID signals. This is true
even in a digital embodiment. All that is required is that
the indication of "validity" of the data be stored along with
the data. By way of example only, in digital television
pictures that are represented by digital values, as specified
in the international standard CCIR 601, certain specific
values are not allowed. In this system, eight-bit binary
numbers are used to represent samples of the picture and the
values zero and 255 may not be used.
If such a picture were to be processed in a pipeline built
in the practice of the present invention, then one of these
values (zero, for example) could be used to indicate that the
data in a specific stage in the pipeline is not valid.
Accordingly, any non-zero data would be deemed to be valid.
In this example, there is no specific latch that can be
identified and said to be storing the "validness" of the
associated data. Nonetheless, the validity of the data is
stored along with the data.
As shown in Fig. 1, the state of the VALID signal into
each stage is indicated as an "H" or an "L" on an upper,
right-pointed arrow. Therefore, the VALID signal from Stage
A into Stage B is LOW, and the VALID signal from Stage D into
Stage E is HIGH. The state of the ACCEPT signal into each
stage is indicated as an ~H~ or an "L" on a lower, left-
Z1~5~4
pointing arrow. Hence, the ACCEPT signal from Stage E intoStage D is HIGH, whereas the ACCEPT signal from the device
connected downstream of the pipeline into Stage F is LOW.
Data is transferred from one stage to another during a
cycle (explained below) whenever the ACCEPT signal of the
downstream stage into its upstream neighbor is HIGH. If the
ACCEPT signal is LOW between two stages, then data is not
transferred between these stages.
Referring again to Fig. 1, if a box is shaded, the
corresponding pipeline stage is assumed, by way of example,
to contain valid output data. Likewise, the VALID signal
which is passed from that stage to the following stage is
HIGH. Fig. 1 illustrates the pipeline when stages B, D, and
E contain valid data. Stages A, C, and F do not contain
valid data. At the beginning, the VALID signal into pipeline
stage A is HIGH, meaning that the data on the transmission
line into the pipeline is valid.
Also at this time, the ACCEPT signal into pipeline stage
F is LOW, so that no data, whether valid or not, is
transferred out of Stage F. Note that both valid and invalid
data is transferred between pipeline stages. Invalid data,
which is data not worth saving, may be written over, thereby,
eliminating it from the pipeline. However, valid data must
. not be written over since it is data that must be saved for
processing or use in a downstream device e.g., a pipeline
stage, a device or a system connected to the pipeline that
receives data from the pipeline.
In the pipeline illustrated in Fig. 1, Stage E contains
valid data Dl, Stage D contains valid data D2, Stage B
.0 contains valid data D3, and a device (not shown) connected to
the pipeline upstream contains data D4 that is to be
transferred into and processed in the pipeline. Stages B, D
and E, in addition to the upstream device, contain valid data
and, therefore, the VALID signal from these stages or devices
` -
- 2145424
into their respective following devices is HIGH. The VALID
signal from the Stages A, C and F is, however, LOW since
these stages do not contain valid data.
Assume now that the device connected downstream from the
pipeline is not ready to accept data from the pipeline. The
device signals this by setting the corresponding ACCEPT
signal LOW into Stage F. Stage F itself, however, does not
contain valid data and is, therefore, able to accept data
from the preceding Stage E. Hence, the ACCEPT signal from
Stage F into Stage E is set HIG,H.
Similarly, Stage E contains valid data and Stage F is
ready to accept this data. Hence, Stage E can accept new
data as long as the valid data D1 is first transferred to
Stage F. In other words, although Stage F cannot transfer
data downstream, all the other stages can do so without any
valid data being overwritten or lost. At the end of Cycle 1,
data can, therefore, be "shifted" one step to the right.
This condition is shown in Cycle 2.
In the illustrated example, the downstream device is still
not ready to accept new data in Cycle 2 and, therefore, the
ACCEPT signal into Stage F is still LOW. Stage F cannot,
therefore, accept new data since doing so would cause valid
data Dl to be overwritten and lost. The ACCEPT signal from
Stage F into Stage E, therefore, goes LOW, as does the ACCEPT
signal from Stage E into Stage D since Stage E also contains
valid data D2. All of the Stages A-D, however, are able to
accept new data (either because they do not contain valid
data or because they are able to shift their valid data
downstream and accept new data) and they signal this
condition to their immediately preceding neighbors by setting
their corresponding ACCEPT signals HIGH.
The state of the pipelines after Cycle 2 is illustrated in
Fig. 1 for the row labelled Cycle 3. By way of example, it
is assumed that the downstream device is still not ready to
- 214542~
accept new data from Stage F (the ACCEPT signal into Stage F
is LOW). Stages E and F, therefore, are still "blocked", but
in Cycle 3, Stage D has received the valid data D3, which has
overwritten the invalid data that was previously in this
stage. Since Stage D cannot pass on data D3 in Cycle 3, it
cannot accept new data and, therefore, sets the ACCEPT signal
into Stage C LOW. However, stages A-C are ready to accept
new data and signal this by setting their corresponding
ACCEPT signals HIGH. Note that data D4 has been shifted from
Stage A to Stage B.
Assume now that the downstream device becomes ready to
accept new data in Cycle 4. It signals this to the pipeline
by setting the ACCEPT signal into Stage F HIGH. Although
Stages C-F contain valid data, they can now shift the data
downstream and are, thus, able to accept new data. Since
each stage is therefore able to shift data one step
downstream, they set their respective ACCEPT signals out
HIGH.
As long as the ACCEPT signal into the final pipeline stage
(in this example, Stage F) is HIGH, the pipeline shown in
Fig. 1 acts as a rigid pipeline and simply shifts data one
step downstream on each cycle. Accordingly, in Cycle 5, data
Dl, which was contained in Stage F in Cycle 4, is shifted out
of the pipeline to the subsequent device, and all other data
is shifted one step downstream.
Assume now, that the ACCEPT signal into Stage F goes LOW
in Cycle 5. Once again, this means that Stages D-F are not
able to accept new data, and the ACCEPT signals out of these
stages into their immediately preceding neighbors go LOW.
Hence, the data D2, D3 and D4 cannot shift downstream,
however, the data D5 can. The corresponding state of the
plpeline after Cycle 5 is, thus, shown in Fig. 1 as Cycle 6.
The ability of the pipeline, in accordance with the
preferred embodiments of the present invention, to ~fill up"
'- 214S~24
empty processing stages is highly advantageous since the
processing stages in the pipeline thereby become decouple
from one another. In other words, even though a pipeline
stage may not be ready to accept data, the entire pipeline
does not have to stop and wait for the delayed stage.
Rather, when one stage is unable to accept valid data it
simply forms a temporary "wall" in the pipeline.
Nonetheless, stages downstream of the "wall" can continue to
advance valid data even to circuitry connected to the
pipeline, and stages to the left of the "wall" can still
accept and transfer valid data downstream. Even when several
pipeline stages temporarily cannot accept new data, other
stages can continue to operate normally. In particular, the
pipeline can continue to accept data into its initial stage
A as long as stage A does not already contain valid data that
cannot be advanced due to the next stage not being ready to
accept new data. As this example illustrates, data can be
transferred into the pipeline and between stages even when
one or more processing stages is blocked.
In the embodiment shown in Fig. 1, it is assumed that the
various pipeline stages do not store the ACCEPT signals they
receive from their immediately following neighbors. Instead,
whenever the ACCEPT signal into a downstream stage goes LOW,
this LOW signal is propagated upstream as far as the nearest
pipeline stage that does not contain valid data. For
example, referring to Fig. l, it was assumed that the ACCEPT
signal into Stage F goes LOW in Cycle l. In Cycle 2, the LOW
signal propagates from Stage F back to Stage D.
In Cycle 3, when the data D3 is latched into Stage D, the
ACCEPT signal propagates upstream four stages to Stage C.
When the ACCEPT signal into Stage F goes HIGH in Cycle 4, it
~ust propagate upstream all the way to Stage C. In other
words, the change in the ACCEPT signal must propagate back
four stages. It is not necessary, however, in the embodiment
~14~ 24
illustrated in Fig. 1, for the ACCEPT signal to propagate all
the way back to the beginning of the pipeline if there is
some intermediate stage that is able to accept new data.
In the embodiment illustrated in Fig. 1, each pipeline
stage will still need separate input and output data latches
to allow data to be transferred between stages without
unintended overwriting. Also, although the pipeline
illustrated in Fig. 1 is able to "compress" when downstream
pipeline stages are blocked, i.e., they cannot pass on the
data they contain, the pipeline does not "expand" to provide
stages that contain no valid data between stages that do
contain valid data. Rather, the ability to compress depends
on there being cycles during which no valid data is presented
to the first pipeline stage.
In Cycle 4, for example, if the ACCEPT signal into Stage
F remained LOW and valid data filled pipeline stages A and B,
as long as valid data continued to be presented to Stage A
the pipeline would not be able to compress any further and
valid input data could be lost. Nonetheless, the pipeline
lllustrated in Fig. 1 reduces the risk of data loss since it
is able to compress as long as there is a pipeline stage that
does not contain valid data.
Fig. 2 illustrates another embodiment of the pipeline that
can both compress and expand in a logical manner and which
includes circuitry that limits propagation of the ACCEPT
signal to the nearest preceding stage. Although the
circuitry for implementing this embodiment is explained and
illustrated in greater detail below, Fig. 2 serves to
illustrate the principle by which it operates.
For ease of comparison only, the input data and ACCEPT
signals into the pipeline embodiment shown in Fig. 2 are the
same as in the pipeline embodiment shown in Fig. l.
Accordingly, stages E, D and B contain valid data D1, D2 and
D3, respectively. The ACCEPT signal into Stage F is LOwi and
~145424
34
data D4 is presented to the beginning pipeline Stage A. In
Fig. 2, three lines are shown connecting each neighboring
pair of pipeline stages. The uppermost line, which may be a
bus, is a data line. The middle line is the line over which
the VALID signal is transferred, while the bottom line is the
line over which the ACCEPT signal is transferred. Also, as
before, the ACCEPT signal into Stage F remains LOW except in
Cycle 4. Eurthermore, additional data D5 is presented to the
pipeline in Cycle 4.
In Fig. 2, each pipeline stage is represented as a block
divided into two halves to illustrate that each stage in this
embodiment of the pipeline includes primary and secondary
data storage elements. In Fig. 2, the primary data storage
is shown as the right half of each stage. However, it will
be appreciated that this delineation is for the purpose of
illustration only and is not intended as a limitation.
As Fig. 2 illustrates, as long as the ACCEPT signal into
a stage is HIGH, data is transferred from the primary storage
elements of the stage to the secondary storage elements of
the following stage during any given cycle. Accordingly,
although the ACCEPT signal into Stage F is LOW, the ACCEPT
signal into all other stages is HIGH so that the data D1, D2
and D3 is shifted forward one stage in Cycle 2 and the data
D4 is shifted into the first Stage A.
Up to this point, the pipeline embodiment shown in Fig. 2
acts in a manner similar to the pipeline embodiment shown in
Fig. 1. The ACCEPT signal from Stage F into Stage E,
however, is HIGH even though the ACCEPT signal into Stage F
is LOW. As is explained below, because of the secondary
storage elements, it is not necessary for the LOW ACCEPT
signal to propagate upstream beyond Stage F. Moreover, by
leaving the ACCEPT signal into Stage E HIGH, Stage F signals
that it is ready to accept new data. Since Stage F is not
able to transfer the data D1 in its primary storage elements
`' 21~5424
downstream (the ACCEPT signal into Stage F is LOW) in Cycle
3, Stage E must, therefore, transfer the data D2 into the
secondary storage elements of Stage F. Since both the
primary and the secondary storage elements of Stage F now
5 contain valid data that cannot be passed on, the ACCEPT
signal from Stage F into Stage E is set LOW. Accordingly,
this represents a propagation of the LOW ACCEPT signal back
only one stage relative to Cycle 2, whereas this ACCEPT
signal had to be propagated back all the way to Stage C in
the embodiment shown in Fig. 1.
Since Stages A-E are able to pass on their data, the
ACCEPT signals from the stages into their immediately
preceding neighbors are set HIGH. Consequently, the data D3
and D4 are shifted one stage to the right so that, in Cycle
4, they are loaded into the primary data storage elements of
Stage E and Stage C, respectively. Although Stage E now
contains valid data D3 in its primary storage elements, its
secondary storage elements can still be used to store other
data without risk of overwriting any valid data.
Assume now, as before, that the ACCEPT signal into Stage
F becomes HIGH in Cycle 4. This indicates that the
downstream device to which the pipeline passes data is ready
to accept data from the pipeline. Stage F, however, has set
its ACCEPT signal LOW and, thus, indicates to Stage E that
Stage F is not prepared to accept new data. Observe that the
ACCEPT signals for each cycle indicate what will "happen" in
the next cycle, that is, whether data will be passed on
(ACCEPT HIGH) or whether data must remain in place (ACCEPT
LOW). Therefore, from Cycle 4 to Cycle 5, the data D1 is
passed from Stage F to the following device, the data D2 is
shifted from secondary to primary storage in Stage F, but the
data D3 in Stage E is not transferred to Stage F. The data
D4 and Ds can be transferred into the following pipeline
stages as normal since the following stages have their ACCEPT
~ 2145~2~
signals HIGH.
Comparing the state of the pipeline in Cycle 4 and Cycle
5, it can be seen that the provision of secondary storage
elements, enables the pipeline embodiment shown in Fig. 2 to
expand, that is, to free up data storage elements into which
valid data can be advanced. For example, in Cycle 4, the
data blocks Dl, D2 and D3 form a "solid wall" since their
data cannot be transferred until the ACCEPT signal into Stage
F goes HIGH. Once this signal does become HIGH, however,
data Dl is shifted out of the pipeline, data D2 is shifted
into the primary storage elements of Stage F, and the
secondary storage elements of Stage F become free to accept
new data if the following device is not able to receive the
data D2 and the pipeline must once again "compress." This is
shown in Cycle 6, for which the data D3 has been shifted into
the secondary storage elements of Stage F and the data D4 has
been passed on from Stage D to Stage E as normal.
Figs. 3a(1), 3a(2), 3b(1) and 3b(2) (which are referred to
collectively as Fig. 3) illustrate generally a preferred
embodiment of the pipeline. This preferred embodiment
implements the structure shown in Fig. 2 using a two-phase,
non-overlapping clock with phases 00 and 01. Although a two-
phase clock is preferred, it will be appreciated that it is
also possible to drive the various embodiments of the
invention using a clock with more than two phases.
As shown in Fig. 3, each pipeline stage is represented as
having two separate boxes which illustrate the primary and
secondary storage elements. Also, although the VALID signal
and the data lines connect the various pipeline stages as
before, for ease of illustration, only the ACCEPT signal is
shown in Fig. 3. A change of state during a clock phase of
certaln of the ACCEPT signals is indicated in Fig. 3 using an
upward-pointing arrow for changes from LOW to HIGH.
Si~ilarly, a downward-pointing arrow for changes from HIGH to
` ` 2145424
LOW. Transfer of data from one storage element to another is
indicated by a large open arrow. It is assumed that the
~ALID signal out of the primary or secondary storage elements
of any given stage is HIGH whenever the storage elements
contain valid data.
In Fig. 3, each cycle is shown as consisting of a full
- period of the non-overlapping clock phases o0 and ol. As is
explained in greater detail below, data is transferred from
the secondary storage elements (shown as the left box in each
stage) to the primary storage elements (shown as the right
box in each stage) during clock cycle O1, whereas data is
transferred from the primary storage elements of one stage to
the secondary storage elements of the following stage during
the clock cycle o0. Fig. 3 also illustrates that the primary
and secondary storage elements in each stage are further
connected via an internal acceptance line to pass an ACCEPT
signal in the same manner that the ACCEPT signal is passed
from stage to stage. In this way, the secondary storage
element will know when it can pass its date to the primary
storage element.
Fig. 3 shows the ol phase of Cycle 1, in which data D1, D2
and D3, which were previously shifted into the secondary
storage elements of Stages E, D and B, respectively, are
. shifted into the primary storage elements of the respective
2~ stage. During the ol phase of Cycle 1, the pipeline,
therefore, assumes the same configuration as is shown as
Cycle 1 of Fig. 2. As before, the ACCEPT signal into Stage
F is assumed to be LOW. As Fig. 3 illustrates, however, this
means that the ACCEPT signal into the primary storage element
'0 of Stage F is LOW, but since this storage element does not
conlain valid data, it sets the ACCEPT signal into its
secondary storage element HIGH.
~ he ACCEPT signal from the secondary storage elements of
Stage F into the primary storage elements of Stage E is also
214~ 2~
set HIGH since the secondary storage elements of Stage F do
not contain valid data. As before, since the primary storage
elements of Stage F are able to accept data, data in all the
upstream primary and secondary storage elements can be
shifted downstream without any valid data being overwritten.
The shift of data from one stage to the next takes place
during the next ~0 phase in Cycle 2. For example, the valid
data D1 contained in the primary storage element of Stage E
is shifted into the secondary storage element of Stage F, the
data D4 is shifted into the pipeline, that is, into the
secondary storage element of Stage A, and so forth.
The primary storage element of Stage F still does not
contain valid data during the 00 phase in Cycle 2 and,
therefore, the ACCEPT signal from the primary storage
elements into the secondary storage elements of Stage F
remains HIGH. During the 01 phase in Cycle 2, data can
therefore be shifted yet another step to the right, i.e.,
from the secondary to the primary storage elements within
each stage.
However, once valid data is loaded into the primary
storage elements of Stage F, if the ACCEPT into Stage F from
the downstream device is still LOW, it is not possible to
shift data out of the secondary storage element of Stage F
without overwriting and destroying the valid data Dl. The
ACCEPT signal from the primary storage elements into the
secondary storage elements of Stage F therefore goes LOW.
Data D2, however, can still be shifted into the secondary
storage of Stage F since it did not contain valid data and
its ACCEPT signal out was HIGH.
'0 During the 01 phase of Cycle 3, it is not possible to
shift data D2 into the primary storage elements of Stage F,
although data can be shifted within all the previous stages.
Once valid data is loaded into the secondary storage elements
of Stage F, however, Stage F is not able to pass on this
214~424
data. It signals this event setting its ACCEPT signal out
LOW.
Assuming that the ACCEPT signal into Stage F remains LOW,
data upstream of Stage F can continue to be shifted between
stages and within stages on the respective clock phases until
the next valid data block D3 reaches the primary storage
elements of Stage E. As illustrated, this condition is
reached during the al phase of Cycle 4.
During the o0 phase of Cycle 5, data D3 has been loaded
into the primary storage element of Stage E. Since this data
cannot be shifted further, the ACCEPT signal out of the
primary storage elements of Stage E is set LOW. Upstream
data can be shifted as normal.
Assume now, as in Cycle 5 of Fig. 2, that the device
connected downstream of the pipeline is able to accept
pipeline data. It signals this event by setting the ACCEPT
signal into pipeline Stage F HIGH during the al phase of
Cycle 4. The primary storage elements of Stage F can now
shift data to the right and they are also able to accept new
data. Hence, the data D1 was shifted out during the ~l phase
of Cycle 5 so that the primary storage elements of Stage F no
longer contain data that must be saved. During the 01 phase
of Cycle 5, the data D2 is, therefore, shifted within Stage
F from the secondary storage elements to the primary storage
2~ elements. The secondary storage elements of Stage F are also
able to accept new data and signal this by setting the ACCEPT
signal into the primary storage elements of Stage E HIGH.
During transfer of data within a stage, that is, from its
secondary to its primary storage elements, both sets of
storage elements will contain the same data, but the data in
~he secondary storage elements can be overwritten with no
data loss since this data will also be held in the primary
storage elements. The same holds true for data transfer from
the primary storage elements of one stage into the secondarf
`- 2145424
storage elements of a subsequent stage.
Assume now, that the ACCEPT signal into the primary
storage elements of Stage F goes LOW during the 01 phase in
Cycle 5. This means that Stage F is not able to transfer the
data D2 out of the pipeline. Stage F, consequently, sets the
ACCEPT signal from its primary to its secondary storage
elements LOW to prevent overwriting of the valid data D2.
The data D2 stored in the secondary storage elements of Stage
F, however, can be overwritten without loss, and the data D3,
is therefore, transferred into the secondary storage elements
of Stage F during the ~0 phase of Cycle 6. Data D4 and D5
can be shifted downstream as normal. Once valid data D3 is
stored in Stage F along with data D2, as long as the ACCEPT
signal into the primary storage elements of Stage F is LOW,
neither of the secondary storage elements can accept new
data, and it signals this by setting the ACCEPT signal into
Stage E LOW.
When the ACCEPT signal into the pipeline from the
downstream device changes from LOW to HIGH or vice versa,
this change does not have to propagate upstream within the
pipeline further than to the immediately preceding storage
elements (within the same stage or within the preceding
plpeline stage). Rather, this change propagates upstream
within the pipeline one storage element block per clock
phase.
As this example illustrates, the concept of a "stage" in
the pipeline structure illustrated in Fig. 3 is to some
extent a matter of perception. Since data is transferred
within a stage (from the secondary to the primary storage
'0 ele~ents) as it is between stages (from the primary storage
elements of the upstream stage into the secondary storage
ele~ents of the neighboring downstream stage), one could just
as well consider a stage to consist of "primary" storage
elements followed by "secondary storage elements~ instead of
- ~14S42~
as illustrated in Fig. 3. The concept of "primary" and
"secondary" storage elements is, therefore, mostly a question
of labeling. In Fig. 3, the "primary" storage elements can
also be referred to as "output" storage elements, since they
are the elements from which data is transferred out of a
stage into a following stage or device, and the "secondary"
storage elements could be "input" storage elements for the
same stage.
In explaining the aforementioned embodiments, as shown in
Figs. 1-3, only the transfer of data under the control of the
ACCEPT and VALID signals has been mentioned. It is to be
further understood that each pipeline stage may also process
the data it has received arbitrarily before passing it
between its internal storage elements or before passing it to
the following pipeline stage. Therefore, referring once
again to Fig. 3, a pipeline stage can, therefore, be defined
as the portion of the pipeline that contains input and output
storage elements and that arbitrarily processes data stored
in its storage elements.
Furthermore, the "device" downstream from the pipeline
Stage F, need not be some other type of hardware structure,
but rather it can be another section of the same or part of
another pipeline. As illustrated below, a pipeline stage can
set its ACCEPT signal LOW not only when all of the downstream
storage elements are filled with valid data, but also when a
stage requires more than one clock phase to finish processing
its data. This also can occur when it creates valid data in
one or both of its storage elements. In other words, it is
not necessary for a stage simply to pass on the ACCEPT signal
based on whether or not the immediately downstream storage
elements contains valid data that cannot be passed on.
Rather, the ACCEPT signal itself may also be altered within
the stage or, by circuitry external to the stage, in order to
control the passage of data between adjacent storage
214~424
42
elements. The VALID signal may also be processed in an
analogous manner.
A great advantage of the two-wire interface (one wire for
each of the VALID and ACCEPT signals) is its ability to
control the pipeline without the control signals needing to
propagate back up the pipeline all the way to its beginning
stage. Referring once again to Fig. 1, Cycle 3, for example,
although stage F "tells" stage E that it cannot accept data,
and stage E tells stage D, and stage D tells stage C.
Indeed, if there had been more stages containing valid data,
then this signal would have propagated back even further
along the pipeline. In the embodiment shown in Fig. 3, Cycle
3, the LOW ACCEPT signal is not propagated any further
upstream than to Stage E and, then, only to its primary
storage elements.
As described below, this embodiment is able to achieve
this flexibility without adding significantly to the silicon
area that is required to implement the deslgn. Typically,
each latch in the pipeline used for data storage requires
only a single extra transistor (which lays out very
efficiently in silicon). In addition, two extra latches and
a small number of gates are preferably added to process the
ACCEPT and VALID signals that are associated with the data
. latches in each half-stage.
25Fig. 4 illustrates a hardware structure that implements a
stage as shown in Fig. 3.
By way of example only, it is assumed that eight-bit data
is to be transferred (with or without further manipulation in
optional combinatorial logic circuits) in parallel through
~0 the pipeline. However, it will be appreciated that either
~ore or less than eight-bit data can be used in practicing
the invention. Furthermore, the two-wire interface in
accordance with this embodiment is, however, suitable for use
with any data bus width, and the data bus width may even
-- 214~42~
change from one stage to the next if a particular application
so requires. The interface in accordance with this
embodiment can also be used to process analog signals.
As discussed previously, while other conventional timing
arrangements may be used, the interface is preferably
controlled by a two-phase, non-overlapping clock. In Figs.
4-9, these clock phase signals are referred to as PH0 and
PH1. In Fig. 4, a line is shown for each clock phase signal.
Input data enters a pipeline stage over a multi-bit data
bus IN_DATA and is transferred to a following pipeline stage
or to subsequent receiving circuitry over an output data bus
OUT_DATA. The input data is first loaded in a manner
described below into a series of input latches (one for each
input data signal) collectively referred to as LDIN, which
constitute the secondary storage elements described above.
In the illustrated example of this embodiment, it is
assumed that the Q outputs of all latches follow their D
inputs, that is, they are "loaded", when the clock input is
HIGH, i.e., at a logic "1" level. Additionally, the Q
outputs hold their last values. In other words, the Q
outputs are "latched" on the falling edge of their respective
clock signals. Each latch has for its clock either one of
two non-overlapping clock signals PH0 or PH1 (as shown in
Fig. 5), or the logical AND combination of one of these clock
signals PH0, PHl and one logic signal. The invention works
equally well, however, by providing latches that latch on the
rising edges of the clock signals, or any other known
latching arrangement, as long as conventional methods are
applied to ensure proper timing of the latching operations.
.0 The output data from the input data latch LDIN passes via
an arbitrary and optional combinatorial logic circuit B1,
which may be provided to convert output data from input latch
LDIN into intermediate data, which is then later loaded in an
output data latch LDOUT, which comprises the primary stora~e
~14S429
elements described above. The output from the output data
latch LDOUT may similarly pass through an arbitrary and
optional combinatorial logic circuit B2 before being passed
onward as OUT_DATA to the next device downstream. This may
be another pipeline stage or any other device connected to
the pipeline.
In the practice of the present invention, each stage of
the pipeline also includes a validation input latch LVIN, a
validation output latch LVOUT, an acceptance input latch
LAIN, and an acceptance output latch LAOUT. Each of these
four latches is, preferably, a simple, single-stage latch.
The outputs from latches LVIN, LVOUT, LAIN and LAOUT are,
respectively, QVIN, QVOUT, QAIN, QAOUT. The output signal
QVIN from the validation input latch is connected either
directly as an input to the validation output latch LVOUT, or
via intermediate logic devices or circuits that may alter the
signal.
Similarly, the output validation signal QVOUT of a given
stage may be connected either directly to the input of the
validation input latch QVIN of the following stage, or via
lntermediate devices or logic circuits, which may alter the
validation signal. This output QVIN is also connected to a
logic gate ~to be described below), whose output is connected
to the input of the acceptance input latch LAIN. The output
QAOUT from the acceptance output latch LAOUT is connected to
a similar logic gate (described below), optionally via
another logic gate.
As shown in Fig. 4, the output validation signal QVOUT
forms an OUT_VALID signa that can be received by subsequent
stages as an IN_VALID signal, or simply to indicate valid
data to subsequent circuity connected to the pipeline. The
readiness of the following circuit or stage to accept data is
indicated to each stage as the signal OUT ACCEPT, which is
connected as the input to the acceptance output latch LAOUT,
21~5424
preferably via logic circuitry, which is described below.
Similarly, the output QAOUT of the acceptance output latch
LAOUT is connected as the input to the acceptance input latch
LAIN, preferably via logic circuitry, which is described
below.
In practicing the present invention, the output signals
QVIN, QVOUT from the validation latches LVIN, LVOUT are
combined with the acceptance signals QAOUT, OUT_ACCEPT,
respectively, to form the inputs to the acceptance latches
LAIN, LAOUT, respectively. In the embodiment illustrated in
Fig. 4, these input signals are formed as the logical NAND
combination of the respective validation signals QVIN, QVOUT,
with the logical inverse of the respective acceptance output
signals QAOUT, OUT_ACCEPT. Conventional logic gates, NANDl
and NAND2, perform the NAND operation, and the inverters
INV1, INV2 form the logical inverses of the respective
acceptance signals.
As is well known in the art of digital design, the output
from a NAND gate is a logical "1" when any or all of its
input signals are in the logical "0" state. The output from
a NAND gate is, therefore, a logical "0" only when all of its
inputs are in the logical "1" state. Also well known in the
art, is that the output of a digital inverter such as INV1 is
a logical "1" when its input signal is a "0" and is a "0"
when its input signal is a "1"
The inputs to the NAND gate NANDl are, therefore, QVIN and
NOT (QAOUT), where "NOT" indicates binary inversion. Using
known techniques, the input to the acceptance latch LAIN can
be resolved as follows:
~0 NAND(QVIN,NOT(QAOUT)) = NOT(QVIN) OR QAOUT
In other words, the combination of the inverter INV1 and
the NAND gate NANDl is a logical "1" either when the signal
QVIN is a "0" or the signal QAOUT is a "1", or both. Ihe
gate NAND1 and the inverter INV1 can, therefore, be
- 214~424
46
implemented by a single OR gate that has one of its inputs
tied directly to the QAOUT output of the acceptance latch
LAOUT and its other input tied to the inverse of the output
signal QVIN of the validation input latch LVIN.
As is well known in the art of digital design, many
latches suitable for use as the validation and acceptance
latches may have two outputs, Q and NOT(Q), that is, Q and
its logical inverse. If such latches are chosen, the one
input to the OR gate can, therefore, be tied directly to the
NOT(Q) output of the validation latch LVIN. The gate NAND1
and the inverter INV1 can be implemented using well known
conventional techniques. Depending on the latch architecture
used, however, it may be more efficient to use a latch
without an inverting output, and to provide instead the gate
NAND1 and the inverter INV1, both of which also can be
implemented efficiently in a silicon device. Accordingly,
any known arrangement may be used to generate the Q signal
and/or its logical inverse.
The data and validation latches LDIN, LDOUT, LVIN and
LVOUT, load their respective data inputs when both clock
signals (PH0 at the input side and PH1 at the output side)
and the output from the acceptance latch of the same side are
logical "1". Thus, the clock signal (PHO for the input
latches LDIN and LVIN) and the output of the respective
acceptance latch (in this case, LAIN) are used in a logical
AND manner and data is loaded only when they are both logical
" 1 " .
In particular applications, such as CMOS implementations
of the latches, the logical AND operation that controls the
loading (via the illustrated CK or enabling "input") of the
latches can be implemented easily in a conventional manner by
connecting the respective enabling input signals (for
example, PH0 and QAIN for the latches LVIN and LDIN), to the
gates of MOS transistors connected in series in the input
`-- 2145424
47
lines of the latches. Consequently, is necessary to provide
an actual logic AND gate, which might cause problems of
timing due to propagation delay in high-speed applications.
The AND gate shown in the figures, therefore, only indicates
the logical function to be performed in generating the enable
signals of the various latches.
Thus, the data latch LDIN loads input data only when PH0
and QAIN are both "1". It will latch this data when either
of these two signals goes to a "0".
Although only one of the clock phase signals PH0 or PHl,
is used to clock the data and validation latches at the input
(and output) side of the pipeline stage, the other clock
phase signal is used, directly, to clock the acceptance latch
at the same side. In other words, the acceptance latch on
either side (input or output) of a pipeline stage is
preferably clocked "out of phase" with the data and
validation latches on the same side. For example, PH1 is
used to clock the acceptance input latch, although PH0 is
used in generating the clock signal CK for the data latch
LDIN and the validation latch LVIN.
As an example of the operation of a pipeline augmented by
the two-wire validation and acceptance circuitry assume that
no valid data is initially presented at the input to the
circuit, either from a preceding pipeline stage, or from a
transmission device. In other words, assume that the
validation input signal IN_VALID to the illustrated stage has
not gone to a "1" since the system was most recently reset.
Assume further that several clock cycles have taken place
since the system was last reset and, accordingly, the
circuitry has reached a steady-state condition. The
validation input signal QVIN from the validation latch LVI~
is, therefore, loaded as a "0" during the next positive
period of the clock PH0. The input to the acceptance input
latch LAIN (via the gate NAND1 or another equivalent gate),
-
.. - 21g5~2~
48
is, therefore, loaded as a "1" during the next positive
period of the clock signal PH1. In other words, since the
data in the data input latch LDIN is not valid, the stage
signals that it is ready to accept input data (since it does
not hold any data worth saving).
In this example, note that the signal IN ACCEPT is used to
enable the data and validation latches LDIN and LVIN. Since
the signal IN_ACCEPT at this time is a "1", these latches
effectively work as conventional transparent latches so that
lo whatever data is on the IN_DATA bus simply is loaded into the
data latch LDIN as soon as the clock signal PHO goes to a
"1". Of course, this invalid data will also be loaded into
the next data latch LDOUT of the following pipeline stage as
long as the output QAOUT from its acceptance latch is a "1".
Hence, as long as a data latch does not contain valid
data, it accepts or "loads" any data presented to it during
the next positive period of its respective clock signal. On
the other hand, such invalid data is not loaded in any stage
for which the acceptance signal from its corresponding
acceptance latch is low (that is, a "O"). Furthermore, the
output signal from a validation latch twhich forms the
validation input signal to the subsequent validation latch)
remains a "O" as long as the corresponding IN_VALID (or QVIN)
signal to the validation latch is low.
When the input data to a data latch is valid, the
validation signal IN_VALID indicates this by rising to a "1".
The output of the corresponding validation latch then rises
to a "1" on the next rising edge of its respective clock
phase signal. For example, the validation input signal QVI~
of latch LVIN rises to a "1" when its corresponding IN_VALI~
signal goes high (that is, rises to a "1") on the next rising
edge of the clock phase signal PHO.
Assume now, instead, that the data input latch LDIN
contains valid data. If the data output latch LDOUT is ready
~ ~lkS42~
to accept new data, its acceptance signal QAOUT will be a
"1". In this case, during the next positive period of the
clock signal PH1, the data latch LDOUT and validation latch
;VoUT will be enabled, and the data latch LDOUT will load the
data present at its input. This will occur before the next
rising edge of the other clock signal PH0, since the clock
signals are non-overlapping. At the next rising edge of PH0,
the preceding data latch (LDIN) will, therefore, not latch in
new input data from the preceding stage until the data output
latch LDOUT has safely latched the data transferred from the
latch LDIN.
Accordingly, the same sequence is followed by every
adjacent pair of data latches (within a stage or between
adjacent stages) that are able to accept data, since they
will be operating based on alternate phases of the clock.
Any data latch that is not ready to accept new data because
it contains valid data that cannot yet be passed, will have
an output acceptance signal (the QA output from its
acceptance latch LA) that is LOW, and its data latch LDIN or
LDOUT will not be loaded. Hence, as long as the acceptance
signal (the output from the acceptance latch) of a given
stage or side (input or output) of a stage is LOW, its
corresponding data latch will not be loaded.
Fig. 4 also shows a reset feature included in a preferred
embodiment. In the illustrated example, a reset signal
NOTRESET0 is connected to an inverting reset input R
(inversion is hereby indicated by a small circle, as is
conventional) of the validation output latch LVOUT. As is
well known, this means that the validation latch LVOUT will
be forced to output a "0" whenever the reset signal NOTRESET0
becomes a "0". One advantage of resetting the latch when the
reset signal goes low (becomes a "0") is that a break in
transmission will reset the latches. They will then be in
their ~null~ or reset state whenever a valid transmissiOn
~14542g
beglns and the reset signal goes HIGH. The reset signal
NOTRESET0, therefore, operates as a digital "ON/OFF" switch,
such that it must be at a HIGH value in order to activate the
pipeline.
Note that it is not necessary to reset all of the latches
that hold valid data in the pipeline. As depicted in Fig. 4,
the validation input latch LVIN is not directly reset by the
reset signal NOTRESET0, but rather is reset indirectly.
Assume that the reset signal NOTRESET0 drops to a "0". The
validation output signal QVOUT also drops to a "0",
regardless of its previous state, whereupon the input to the
acceptance output latch LAOUT (via the gate NANDl) goes HIGH.
The acceptance output signal QAOUT also rises to a "1". This
QAOUT value of "1" is then transferred as a "1" to the input
of the acceptance input latch LAIN regardless of the state of
the validation input signal QVIN. The acceptance input
signal QAIN then rises to a "1" at the next rising edge of
the clock signal PHl. Assuming that the validation signal
IN_VALID has been correctly reset to a "0", then upon the
subsequent rising edge of the clock signal PH0, the output
from the validation latch LVIN will become a "0", as it would
have done if it had been reset directly.
As this example illustrates, it is only necessary to reset
the validation latch in only one side of each stage
(including the final stage) in order to reset all validation
latches. In fact, in many applications, it will not be
necessary to reset every other validation latch: If the
reset signal NOTRESET0 can be guaranteed to be low during
more than one complete cycle of both phases PH0, PHl of the
clock, then the "automatic reset" (a backwards propagation of
the reset signal) will occur for validation latches in
preceding pipeline stages. Indeed, if the reset signal is
held low for at least as many full cycles of both phases of
the clock as there are pipeline stages, it will only be
`~ 214~2~
necessary to directly reset the validation output latch in
the final pipeline stage.
Figs. 5a and Sb (referred to collectively as Fig. S~
illustrate a timing diagram showing the relationship between
the non-overlapping clock signals PH0, PH1, the effect of the
reset signal, and the holding and transfer of data for the
different permutations of validation and acceptance signals
into and between the two illustrated sides of a pipeline
stage configured in the embodiment shown in Fig. 4. In the
example illustrated in the timing diagram of Fig. S, it has
been assumed that the outputs from the data latches LDIN,
LDOUT are passed without further manipulation by intervening
logic blocks B1, B2. This is by way of example and not
necessarily by way of limitation. It is to be understood
that any combinatorial logic structures may be included
between the data latches of consecutive pipeline stages, or
between the input and output sides of a single pipeline
stage. The actual illustrated values for the input data (for
example the HEX data words "aa" or "04") are also merely
illustrative. As is mentioned above, the input data bus may
have any width (and may even be analog), as long as the data
latches or other storage devices are able to accommodate and
latch or store each bit or value of the input word.
Preferred Data Structure - "tokenQ"
In the sample application shown in Fig. 4, each stage
processes all input data, since there is no control circuitry
that excludes any stage from allowing input data to pass
through its combinatorial logic block B1, B2, and so forth.
To provide greater flexibility, the present invention
lncludes a data structure in which "tokens" are used to
distribute data and control information throughout the
system. Each token consists of a series of binary bi.s
separated into one or more blocks of token words.
21~424
Furthermore, the bits fall into one of three types: address
bits (A), data bits (D), or an extension bit (E). Assume by
way of example and, not necessarily by way of limitation,
that data is transferred as words over an 8-bit bus with a 1-
bit extension bit line. An example of a four-word token is,
in order of transmission:
First word: E A A A D D D D D
Second word: E D D D D D D D D
Third word: E D D D D D D D D
Fourth word: E D D D D D D D D
Note that the extension bit E is used as an addition
(preferably) to each data word. In addition, the address
field can be of variable length and is preferably transmitted
just after the extension bit of the first word.
Tokens, therefore, consist of one or more words of
(binary) digital data in the present invention. Each of
these words is transferred in sequence and preferably in
parallel, although this method of transfer is not necessary:
serial data transfer is also possible using known techniques.
For example, in a video parser, control information is
transmitted in parallel, whereas data is transmitted
serially.
As the example illustrates, each token has, preferably at
the start, an address field (the string of A-bits) that
identifies the type of data that is contained in the token.
In most applications, a single word or portion of a word is
sufficient to transfer the entire address field, but this is
not necessary in accordance with the invention, so long as
logic circuitry is included in the corresponding pipeline
stages that is able to store some representation of partial
address fields long enough for the stages to receive and
decode the entire address field.
~14~424
Note that no dedicated wires or registers are required to
transmit the address field. It is transmitted using the data
bits. As is explained below, a pipeline stage will not be
slowed down if it is not intended to be activated by the
particular address field, i.e., the stage will be able to
pass along the token without delay.
The remainder of the data in the token following the
address field is not constrained by the use of tokens. These
D-data bits may take on any values and the meaning attached
!~ to these bits is of no importance here. That is, the meaning
of the data can vary, for example, depending upon where the
data is positioned within the system at a particular point in
time. The number of data bits D appended after the address
field can be as long or as short as required, and the number
1~ of data words in different tokens may vary greatly. The
address field and extension bit are used to convey control
slgnals to the pipeline stages. Because the number of words
1n the data field (the string of D bits) can be arbitrary, as
can be the information conveyed in the data field can also
vary accordingly. The explanation below is, therefore,
directed to the use of the address and extension bits.
In the present invention, tokens are a particularly useful
data structure when a number of blocks of circuitry are
connected together in a relatively simple configuration. The
2~ simplest configuration is a pipeline of processing steps.
For example, in the one shown in Fig. 1. The use of tokens,
however, is not restricted to use on a pipeline structure.
Assume once again that each box represents a complete
pipeline stage. In the pipeline of Fig. 1, data flows from
left to right in the diagram. Data enters the machine and
passes into processing Stage A. This may or may not modlfy
the data and it then passes the data to Stage B. The
modification, if any, may be arbitrarily complicated and, in
general, there will not be the same number of data ite~s
2145424
-
flowing into any stage as flow out. Stage B modifies the
data again and passes it onto Stage C, and so forth. In a
scheme such as this, it is impossible for data to flow in the
opposite direction, so that, for example, Stage C cannot pass
data to Stage A. This restriction is often perfectly
acceptable.
On the other hand, it is very desirable for Stage A to be
able to communicate information to Stage C even though there
is no direct connection between the two blocks. Stage A and
C communication is only via Stage 8. One advantage of the
tokens is their ability to achieve this kind of
communication. Since any processing stage that does not
recognize a token simply passes it on unaltered to the next
block.
According to this example, an extension bit is transmitted
along with the address and data fields in each token so that
a processing stage can pass on a token (which can be of
arbitrary length) without having to decode its address at
all. According to this example, any token in which the
extension bit is HIGH (a "1") is followed by a subsequent
word which is part of the same token. This word also has an
extension bit, which indicates whether there is a further
token word in the token. When a stage encounters a token
word whose extension bit is LOW (a "0"), it is known to be
the last word of the token. The next word is then assumed to
be the first word of a new token.
Note that although the simple pipeline of processing
stages is particularly useful, it will be appreciated that
tokens may be applied to more complicated configurations of
processing elements. An example of a more complicated
processing element is described below.
It is not necessary, in accordance with the present
invention, to use the state of the extension bit to signal
the last word of a given token by giving it an extension bit
.- 21~5424
set to "0". One alternative to the preferred scheme is to
move the extension bit so that it indicates the first word of
a token instead of the last. This can be accomplished with
appropriate changes in the decoding hardware.
The advantage of using the extension bit of the present
invention to signal the last word in a token rather than the
first, is that it is often useful to modify the behavior of
a block of circuitry depending upon whether or not a token
has extension bits. An example of this is a token that
activates a stage that processes video quantization values
stored in a quantization table (typically a memory device).
For example, a table containing 64 eight-bit arbitrary binary
integers.
In order to load a new quantization table into the
quantizer stage of the pipeline, a "QUANT_TABLE" token is
sent to the quantizer. In such a case the token, for
example, consists of 65 token words. The first word contains
the code "QUANT_TABLE", i.e., build a quantization table.
This is followed by 64 words, which are the integers of the
quantization table.
When encoding video data, it is occasionally necessary to
transmit such a quantization table. In order to accomplish
this function, a QUANT_TABLE token with no extension words
can be sent to the quantizer stage. On seeing this token,
2~ and noting that the extension bit of its first word is LOW,
the quantizer stage can read out its quantization table and
construct a QUANT_TABLE token which includes the 64
quantization table values. The extension bit of the first
word (which was LOW) is changed so that it is HIGH and the
token continues, with HIGH extension bits, until the new end
of the token, lndicated by a LOW extension bit on the sixty
fourth quantization table value. This proceeds in the
typical way through the system and is encoded into the bit
stream.
`- 21~5q2~
56
Continuing with the example, the quantizer may either load
a new quantization table into its own memory device or read
out its table depending on whether the first word of the
QUANT_TABLE token has its extension bit set or not.
The choice of whether to use the extension bit to signal
the first or last token word in a token will, therefore,
depend on the system in which the pipeline will be used.
Both alternatives are possible in accordance with the
invention.
Another alternative to the preferred extension bit scheme
is to include a length count at the start of the token. Such
an arrangement may, for example, be efficient if a token is
very long. For example, assume that a typical token in a
given application is lO00 words long. Using the illustrated
extension bit scheme (with the bit attached to each token
word), the token would require 1000 additional bits to
contain all the extension bits. However, only ten bits would
be required to encode the token length in binary form.
Although there are, therefore, uses for long tokens,
experience has shown that there are many uses for short
tokens. Here the preferred extension bit scheme is
advantageous. If a token is only one word long, then only
one bit is required to signal this. However, a counting
scheme would typically require the same ten bits as before.
Disadvantages of a length count scheme include the
following: 1) it is inefficient for short tokens; 2) it
places a maximum length restriction on a token (with only ten
bits, no more than 1023 words can be counted); 3) the length
of a token must be known in advance of generating the count
.0 (which is presumably at the start of the token); 4) every
block of circuitry that deals with tokens would need to be
provided with hardware to count words; and 5) if the count
should get corrupted (due to a data transmission error) it is
not clear whether recovery can be achieved.
2145~24
The advantages of the extension bit scheme in accordance
with the present invention include: 1) pipeline stages need
not include a block of circuitry that decodes every token
since unrecognized tokens can be passed on correctly by
considering only the extension bit; 2) the coding of the
extension bit is identical for all tokens; 3) there is no
limit placed on the length of a token; 4) the scheme is
efficient (in terms of overhead to represent the length of
the token) for short tokens; and 5) error recovery is
naturally achieved. If an extension bit is corrupted then
one random token will be generated (for an extension bit
corrupted from "1" to "0") or a token will be lost (extension
bit corrupted "0" to "l"). Furthermore, the problem is
localized to the tokens concerned. After that token, correct
operation is resumed automatically.
In addition, the length of the address field may be
varied. This is highly advantageous since it allows the most
common tokens to be squeezed into the minimum number of
words. This, in turn, is of great importance in video data
pipeline systems since it ensures that all processing stages
can be continuously running at full bandwidth.
In accordance to the present invention, in order to allow
variable length address fields, the addresses are chosen so
that a short address followed by random data can never be
2~ confused with a longer address. The preferred technique for
encoding the address field (which also serves as the "code"
for activating an intended pipeline stage) is the well-known
technique first described by Huffman, hence the common name
"Huffman Code". Nevertheless, it will be appreciated by one
of ordinary skill in the art, that other coding schemes may
also be successfully employed.
Although Huffman encoding is well understood in the field
of digital design, the following example provides a general
background:
ZlgS424
Huffman codes consist of words made up of a string of
symbols (in the context of digital systems, such as the
present invention, the symbols are usually binary digits).
The code words may have variable length and the special
property of Huffman code words is that a code word is chosen
so that none of the longer code words start with the symbols
that form a shorter code word. In accordance with the
invention, token address fields are preferably (although not
necessarily) chosen using known Huffman encoding techniques.
Also in the present invention, the address field
preferably starts in the most significant bit (MSB) of the
first word token. (Note that the designation of the MSB is
arbitrary and that this scheme can be modified to accommodate
various designations of the MSB.) The address field
continues through contiguous bits of lesser significance.
If, in a given application, a token address requires more
than one token word, the least significant bit in any given
word the address field will continue in the most significant
bit of the next word. The minimum length of the address
field is one bit.
Any of several known hardware structures can be used to
generate the tokens used in the present invention. One such
structure is a microprogrammed state machine. However, known
microprocessors or other devices may also be used.
The principle advantage of the token scheme in accordance
with the present invention, is its adaptability tO
unanticipated needs. For example, if a new token is
introduced, it is most likely that this will affect only a
small number of pipeline stages. The most likely case is
'0 that only two stages or blocks of circuitry are affected,
i.e., the one block that generates the tokens in the firs~
place and the block or stage that has been newly designed or
modified to deal with this new token. Note that it is not
necessary to modify any other pipeline stages. Rather, these
'_ 2145424
59
will be able to deal with the new token without modification
to their designs because they will not recognize it and will,
accordingly, pass that token on unmodified.
This ability of the present invention to leave
substantially existing designed devices unaffected has clear
advantages. It may be possible to leave some semiconductor
chips in a chip set completely unaffected by a design
improvement in some other chips in the set. This is
advantageous both from the perspective of a customer and from
that of a chip manufacturer. Even if modifications mean that
all chips are affected by the design change ta situation that
becomes increasingly likely as levels of integration progress
so that the number of chips in a system drops) there will
still be the considerable advantage of better time-to-market
than can be achieved, since the same design can be reused.
In particular, note the situation that occurs when it
becomes necessary to extend the token set to include two word
addresses. Even in this case, it is still not necessary to
modify an existing design. Token decoders in the pipeline
stages will attempt to decode the first word of such a token
and will conclude that it does not recognize the token. It
will then pass on the token unmodified using the extension
bit to perform this operation correctly. It will not attempt
to decode the second word of the token (even though this
2~ contains address bits) because it will "assume" that the
second word is part of the data field of a token that it does
not recognize.
In many cases, a pipeline stage or a connected block of
circuitry will modify a token. This usually, but not
necessarily, takes the form of modifying the data field of a
token. In addition, it is common for the number of data
words ln the token to be modified, either by removing certain
data words or by adding new ones. In some cases, tokens are
removed entirely from the token stream.
~14542~
In most applications, pipeline stages will typically only
decode (be activated by) a few tokens; the stage does not
recognize other tokens and passes them on unaltered. In a
large number of cases, only one token is decoded, the DATA
Token word itself.
In many applications, the operation of a particular stage
will depend upon the results of its own past operations. The
"state" of the stage, thus, depends on its previous states.
In other words, the stage depends upon stored state
information, which is another way of saying it must retain
some information about its own history one or more clock
cycles ago. The present invention is well-suited for use in
pipelines that include such "state machine" stages, as well
as for use in applications in which the latches in the data
path are simple pipeline latches.
The suitability of the two-wire interface, in accordance
with the present invention, for such "state machine" circuits
is a significant advantage of the invention. This is
especially true where a data path is being controlled by a
state machine. In this case, the two-wire interface
technique above-described may be used to ensure that the
"current state" of the machine stays in step with the data
which it is controlling in the pipeline.
Fig. 6 shows a simplified block diagram of one example of
circuitry included in a pipeline stage for decoding a token
address field. This illustrates a pipeline stage that has
the characteristics of a "state machine". Each word of a
token includes an "extension bit" which is HIGH if there are
more words in the token or LOW if this is the last word of
~0 the token. If this is the last word of a token, the next
valid data word is the start of a new token and, therefore,
its address must be decoded. The decision as to whether or
not to decode the token address in any given word, thus,
depends upon knowing the value of the previous extension bit.
~:145~24
61
For the sake of simplicity only, the two-wire interface
(with the acceptance and validation signals and latches) is
not illustrated and all details dealing with resetting the
circuit are omitted. As before, an 8-bit data word is
S assumed by way of example only and not by way of limitation.
This exemplifying pipeline stage delays the data bits and
the extension bit by one pipeline stage. It also decodes the
DATA Token. At the point when the first word of the DATA
Token is presented at the output of the circuit, the signal
"DATA_ADDR" is created and set HIGH. The data bits are
delayed by the latches LDIN and LDOUT, each of which is
repeated eight times for the eight data bits used in this
example (corresponding to an 8-input, 8-output latch).
Similarly, the extension bit is delayed by extension bit
latches LEIN and LEOUT.
In this example, the latch LEPREV is provided to store the
most recent state of the extension bit. The value of the
extension bit is loaded into LEIN and is then loaded into
LEOUT on the next rising edge of the non-overlapping clock
phase signal PH1. Latch LEOUT, thus, contains the value of
the current extension bit, but only during the second half of
the non-overlapping, two-phase clock. Latch LEPREV, however,
loads this extension bit value on the next rising edge of the
clock signal PHO, that is, the same signal that enables the
extension bit input latch LEIN. The output QEPREV of the
latch LEPREV, thus, will hold the value of the extension bit
during the previous PHO clock phase.
The five bits of the data word output from the invertinq
Q output, plus the non-inverted MD[2], of the latch LDIN are
combined with the previous extension bit value QEPREV in a
series of logic gates NAND1, NAND2, and NOR1, whose
operations are well known in the art of digital design. The
designation "N MD[m] indicates the logical inverse of bit
of the mid-data word MD[7:0]. Using known techniques of
- 2145~24
Boolean algebra, it can be shown that the output signal SA
from this logic block (the output from NOR1) is HIGH (a "1")
only when the previous extension bit is a "O" (QPREV="O") and
the data word at the output of the non-inverting Q latch (the
original input word~ LDIN has the structure "000001xx", that
is, the five high-order bits MD[7]-MD[3] bits are all "0" and
the bit MD[2] is a "1" and the bits in the Zero-one positions
have any arbitrary value.
There are, thus, four possible data words (there are four
permutations of "xx") that will cause SA and, therefore, the
output of the address signal latch LADDR to whose input SA is
connected, to become HIGH. In other words, this stage
provides an activation signal (DATA ADDR = "1") only when one
of the four possible proper tokens is presented and only when
the previous extension bit was a zero, that is, the previous
data word was the last word in the previous series of token
words, which means that the current token word is the first
one in the current token.
When the signal QPREV from latch LEPREV is LOW, the value
at the output of the latch LDIN is therefore the first word
of a new token. The gates NAND1, NAND2 and NORl decode the
DATA token (000001xx). This address decoding signal SA is,
however, delayed in latch LADDR so that the signal DATA_ADDR
. has the same timing as the output data OUT_DATA and OUT_EXTN.
Fig. 7 is another simple example of a state-dependent
pipeline stage in accordance with the present invention,
which generates the signal LAST_OUT_EXTN to indicate the
value of the previous output extension bit OUT_EXTN. One of
the two enabling signals (at the CK inputs) to the present
and last extension bit latches, LEOUT and LEPREV,
respectively, is derived from the gate ANDl such that these
latches only load a new value for them when the data is valid
and is being accepted (the Q outputs are HIGH from the
output validation and acceptance latches LVOUT and LAOUT,
- ~145~Z4
63
respectively). In this way, they only hold valid extension
bits and are not loaded with spurious values associated with
data that is not valid. In the embodiment shown in Fig. 7,
the two-wire valid/accept logic includes the OR1 and OR2
gates with input signals consisting of the downstream
acceptance signals and the inverting output of the validation
latches LVIN and LVOUT, respectively. This illustrates one
way in which the gates NAND1/2 and INVl/2 in Fig. 4 can be
replaced if the latches have inverting outputs.
Although this is an extremely simple example of a "state-
dependent" pipeline stage, i.e., since it depends on the
state of only a single bit, it is generally true that all
latches holding state information will be updated only when
data is actually transferred between pipeline stages. In
other words, only when the data is both valid and being
accepted by the next stage. Accordingly, care must be taken
to ensure that such latches are properly reset.
The generation and use of tokens in accordance with the
present invention, thus, provides several advantages over
known encoding techniques for data transfer through a
pipeline.
First, the tokens, as described above, allow for variable
length address fields (and can utilize Huffman coding for
example) to provide efflcient representation of common
2~ tokens.
Second, consistent encoding of the length of a token
allows the end of a token (and hence the start of the next
token) to be processed correctly (including simple non-
~anipulative transfer)~ even if the token is not recognized
by the token decoder circuitry in a given pipeline stage.
Third, rules and hardware structures for the handling of
unrecognized tokens (that is, for passing them on unmodified~
allow communication between one stage and a downstream staqe
that is not its nearest neighbor in the pipeline. This also
-~ ~145424
64
increases the expandability and efflcient adaptability of the
pipeline since it allows for future changes in the token set
without requiring large scale redesigning of existing
pipeline stages. The tokens of the present invention are
particularly useful when used in conjunction with the two-
wire interface that is described above and below.
As an example of the above, Figs. 8a and 8b, taken
together (and referred to collectively below as Fig. 8),
depict a block diagram of a pipeline stage whose function is
lo as follows. If the stage is processing a predetermined token
(known in this example as the DATA token), then it will
duplicate every word in this token with the exception of the
first one, which includes the address field of the DATA
token. If, on the other hand, the stage is processing any
other kind of token, it will delete every word. The overall
effect is that, at the output, only DATA Tokens appear and
each word within these tokens is repeated twice.
Many of the components of this illustrated system may be
the same as those described in the much simpler structures
shown in Figs. 4, 6, and 7. This illustrates a significant
advantage. More complicated pipeline stages will still enjoy
the same benefits of flexibility and elasticity, since the
sam,e two-wire interface may be used with little or no
adaptation.
2~ The data duplication stage shown in Fig. 8 is merely one
example of the endless number of different types of
operations that a pipeline stage could perform in any given
application. This "duplication stage" illustrates, however,
a stage that can form a "bottleneck", so that the pipeline
according to this embodiment will "pack together".
A "bottleneck" can be any stage that either takes a
relatively long time to perform its operations, or that
creates more data in the pipeline than it receives. ~his
example also illustrates that the two-wire accept/valid
214~2~
interface according to this embodiment can be adapted very
easily to different applications.
The duplication stage shown ln Fig. 8 also has two latches
LEIN and LEOUT that, as in the example shown in Fig. 6, latch
the state of the extension bit at the input and at the output
of the stage, respectively. As Fig. 8a shows, the input
extension latch LEIN is clocked synchronously with the input
data latch LDIN and the validation signal IN_VALID.
For ease of reference, the various latches included in the
duplication stage are paired below with their respective
output signals:
In the duplication stage, the output from the data latch
LDIN forms intermediate data referred to as MID_DATA. This
intermediate data word is loaded into the data output latch
1~ LDoUT only when an intermediate acceptance signal ~labeled
"MID_ACCEPT" in Fig. 8a) is set HIGH.
The portion of the circuitry shown in Fig. 8 below the
acceptance latches LAIN, LAOVT, shows the circuits that are
added to the basic pipeline structure to generate the various
- 2~45g24
66
internal control signals used to duplicate data. These
include a "DATA_TOKEN" signal that indicates that the
circuitry is currently processing a valid DATA Token, and a
NOT_D~PLICATE signal which is used to control duplication of
data. When the circuitry is processing a DATA Token, the
NOT_DUPLICATE signal toggles between a HIGH and a LOW state
and this causes each word in the token to be duplicated once
(but no more times). When the circuitry is not processing a
valid DATA Token then the NOT DUPLICATE signal is held in a
HIGH state. Accordingly, this means that the token words
that are being processed are not duplicated.
As Fig. 8a illustrates, the upper six bits of 8-bit
intermediate data word and the output signal QIl from the
latch LI1 form inputs to a group of logic gates NOR1, NOR2,
NAND18. The output signal from the gate NAND18 is labeled
Sl. ~sing well-known Boolean algebra, it can be shown that
the signal S1 is a "0" only when the output signal QI1 is a
"1" and the MID_DATA word has the following structure:
"000001xx", that is, the upper five bits are all "0", the bit
MID_DATA[2~ is a "1" and the bits in the MID_DATA[l] and
MID_DATA[0] positions have any arbitrary value. Signal S1,
therefore, acts as a "token identification signal" which is
low only when the MID_DATA signal has a predetermined
structure and the output from the latch LIl is a "1". The
nature of the latch LIl and its output QIl is explained
further below.
Latch LO1 performs the function of latching the last value
of the intermediate extension bit (labeled "MID_EXTN" and as
signal 54), and it loads this value on the next rising edge
of the clock phase PHO into the latch LIl, whose output is
the bit QIl and is one of the inputs to the token decoding
logic group that forms signal Sl. Signal Sl, as is explained
above, may only drop to a "0" if the signal QIl is a "1" (and
the MID DATA signal has the predetermined structure). Signal
~lq5q24
Sl may, therefore, only drop to a "0" whenever the last
extension bit was "0", indicating that the previous token has
ended. Therefore, the MID_DATA word is the first data word
in a new token.
The latches LO2 and LI2 together with the NAND gates
NAND20 and NAND22 form storage for the signal, DATA TOKEN.
In the normal situation, the signal QIl at the input to
NAND20 and the signal Sl at the input to NAND22 will both be
at logic "1". It can be shown, again by the techniques of
Boolean algebra, that in this situation these NAND gates
operate in the same manner as inverters, that is, the signal
QI2 from the output of latch LI2 is inverted in NAND20 and
then this signal is inverted again by NAND22 to form the
signal S2. In this case, since there are two logical
inversions in this path, the signal S2 will have the same
value as QI2.
It can also be seen that the signal DATA TOKEN at the
output of latch LO2 forms the input to latch LI2. As a
result, as long as the situation remains in which both QIl
and Sl are HIGH, the signal DATA_TOKEN will retain its state
(whether "O" or "1"). This is true even though the clock
signals PHO and PHl are clocking the latches (LI2 and LO2
respectively). The value of DATA TOKEN can only change when
. one or both of the signals QIl and Sl are "0".
As explained earlier, the signal QIl will be "0" when the
previous extension bit was "0". Thus, it will be "o"
whenever the MID DATA value is the first word of a token
(and, thus, includes the address field for the token). In
this situation, the signal Sl may be either "0" or "1". As
.0 explained earlier, signal Sl will be "O" if the MID DATA word
has the predetermined structure that in this example
indicates a "DATA" Token. If the MID_DATA word has any other
structure, (indicating that the token is some other token,
not a DATA Token), Sl will be "1".
`~ ~14~424
68
If QI1 is "0" and S1 is "1", this indicates there is some
token other than a DATA Token. As is well known in the field
of digital electronics, the output of NAND20 will be "1".
The NAND gate NAND22 will invert this (as previously
explained) and the signal S2 will thus be a "0". As a
result, this "0" value will be loaded into latch LO2 at the
start of the next PH1 clock phase and the DATA_TOKEN signal
will become "0", indicating that the circuitry is not
processing a DATA token.
If QI1 is "0" and SO is "0", thereby indicating a DATA
token, then the signal S2 will be "1" (regardless of the
other input to NAND22 from the output of NAND20). As a
result, this "1" value will be loaded into latch LO2 at the
start of the next PH1 clock phase and the DATA TOKEN signal
will become "1", indicating that the circuitry is processing
a DATA token.
The NOT_DUPLICATE signal (the output signal QO3) is
similarly loaded into the latch LI3 on the next rising edge
of the clock PHO. The output signal QI3 from the latch LI3
is combined with the output signal QI2 in a gate NAND24 to
form the signal S3. As before, Boolean algebra can be used
to show that the signal S3 is a "0" only when both of the
signals QI2 and QI3 have the value "1". If the signal QI2
becomes a "0", that is, the DATA TOKEN signal is a "0", then
the signal S3 becomes a "1". In other words, if there is not
a valid DATA TOKEN (QI2 = 0) or the data word is not a
duplicate (QI3 = 0), then the signal S3 goes high.
Assume now, that the DATA TOKEN signal remains HIGH for
~ore than one clock signal. Since the NOT_DUPLICATE signal
(QO3) is "fed back" to the latch LI3 and will be inverted by
the gate NAND 24 (since its other input QI2 is held HIGH),
the output signal QO3 will toggle between "0" and "1". ~f
there is no valid DATA Token, however, the signal QI2 will be
a "o", and the signal S3 and the output QO3, will be fcrced
~ 2145424
69
HIGH until the DATE_TOKEN signal once again goes to a "1".
The output Q03 (the NOT DUPLICATE signal) is also fed back
and is combined with the output QAl from the acceptance latch
LAIN in a series of logic gates (NAND16 and INV16, which
together form an AND gate) that have as their output a "1",
only when the signals QA1 and Q03 both have the value "1".
As Fig. 8a shows, the output from the AND gate (the gate
NAND16 followed by the gate INV16) also forms the acceptance
signal, I~_ACCEPT, which is used as described above in the
two-wire interface structure.
The acceptance signal IN_ACCEPT is also used as an
enabling signal to the latches LDIN, LEIN, and LVIN. As a
result, if the NOT_DUPLICATE signal is low, the acceptance
signal IN_ACCEPT will also be low, and all three of these
l~ latches will be disabled and will hold the values stored at
their outputs. The stage will not accept new data until the
~OT_DUPLICATE signal becomes HIGH. This is in addition to
the requirements described above for forcing the output from
the acceptance latch LAIN high.
As long as there is a valid DATA_TOKEN (the DATA_ TOKEN
signal Q02 is a "1"), the signal Q03 will toggle between the
HIGH and LOW states, so that the input latches will be
enabled and will be able to accept data, at most, during
every other complete cycle of both clock phases PH0, PHl.
2~ The additional condition that the following stage be prepared
to accept data, as indicated by a "HIGH" OUT_ACCEPT signal,
must, of course, still be satisfied. The output latch LDOUT
will, therefore, place the same data word onto the output bus
OUT_DATA for at least two full clock cycles. The OUT_VALID
signal will be a "1" only when there is both a valid
DATA_TOKEN (Q02 HIGH) and the validation signal QVOUT is
HIGH .
The signal QEIN, which is the extension bit corresponding
to MID_DATA, is combined with the signal S3 in a series of
2145424
-
logic gates (INV10 and NANDlO) to form a signal S4. During
presentation of a DATA Token, each data word MID_DATA will be
repeated by loading it into the output latch LDOUT twice.
During the first of these, S4 will be forced to a "1" by the
action of NAND10. The signal S4 is loaded in the latch LEOUT
to form OUTEXTN at the same time as MID_DATA is loaded into
LDOUT to form OUT_DATA[7:0].
Thus, the first time a given MID_DATA is loaded into
LEOUT, the associated OUTEXTN will be forced high, whereas,
on the second occasion, OUTEXTN will be the same as the
signal QEIN. Now consider the situation during the very last
word of a token in which QEIN is known to be low. During the
first time MID_DATA is loaded into LDOUT, OUTEXTN will be
"1", and during the second time, OUTEXTN will be "0",
indicating the true end of the token.
The output signal QVIN from the validation latch LVIN is
combined with the signal QI3 in a similar gate combination
(INV12 and NAND12) to form a signal S5. Using known Boolean
techniques, it can be shown that the signal S5 is HIGH either
when the validation signal QVIN is HIGH, or when the signal
QI3 is low (indicating that the data is a duplicate). The
signal S5 is loaded into the validation output latch LVOUT at
the same time that MID_DATA is loaded into LDOUT and the
intermediate extension bit (signal S4) is loaded into LEOUT.
Signal S5 is also combined with the signal QO2 (the data
token signal) in the logic gates NAND30 and INV30 to form the
output validation signal OUT_VALID. As was mentioned
earlier, OUT_VALID is HIGH only when there is a valid token
and the validation signal QVOUT is high.
In the present invention, the MID_ACCEPT signal is
combined with the signal S5 in a series of logic gates
(NAND26 and INV26) that perform the well-known AND function
to form a signal 56 that is used as one of the two enabling
signals to the latches LO1, LO2 and LO3. The signal S6 rises
~14~42~
-
to a "1" when the MID ACCEPT signal is HIGH and when either
the validation signal QVIN is high, or when the token is a
duplicate (QI3 is a "O"). If the signal MID_ACCEPT is HIGH,
the latches LOl-LO3 will, therefore, be enabled when the
clock signal PHl is high whenever valid input data is loaded
at the input of the stage, or when the latched data is a
duplicate.
From the discussion above, one can see that the stage
shown in Figs. 8a and 8b will receive and transfer data
between stages under the control of the validation and
acceptance signals, as in previous embodiments, with the
exception that the output signal from the acceptance latch
LAIN at the input side is combined with the toggling
duplication signal so that a data word will be output twice
before a new word will be accepted.
The various logic gates such as NANDl6 and INVl6 may, of
course, be replaced by equivalent logic circuitry (in this
case, a single AND gate). Similarly, if the latches LEIN and
LVIN, for example, have inverting outputs, the inverters
INV10 and INVl2 will not be necessary. Rather, the
corresponding input to the gates NAND10 and NAND12 can be
tied directly to the inverting outputs of these latches. As
long as the proper logical operation is performed, the stage
will operate in the same manner. Data words and extension
2~ bits will still be duplicated.
One should note that the duplication function that the
illustrated stage performs will not be performed unless the
first data word of the token has a "l" in the third position
of the word and "O's" in the five high-order bits. (Of
course, the required pattern can easily be changed and set by
selecting other logic gates and interconnections other than
the NORl, NOR2, NNDl8 gates shown.)
In addition, as Fig. 8 shows, the OUT_VALID signal will be
forced low during the entire token unless the first data wora
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has the structure described above. This has the effect that
all tokens except the one that causes the duplication process
will be deleted from the token stream, since a device
connected to the output terminals (OUTDATA, OUTEXTN and
OUTVALID) will not recognize these token words as valid data.
As before, both validation latches LVIN, LVOUT in the
stage can be reset by a single conductor NOT RESETO, and a
single resetting input R on the downstream latch LVOUT, with
the reset signal being propagated backwards to cause the
upstream validation latch to be forced low on the next clock
cycle.
It should be noted that in the example shown in Fig. 8,
the duplication of data contained in DATA tokens serves only
as an example of the way in which circuitry may manipulate
the ACCEPT and VALID signals so that more data is leaving the
pipeline stage than that which is arriving at the input.
Similarly, the example in Fig. 8 removes all non-DATA tokens
purely as an illustration of the way in which circuitry may
manipulate the VALID signal to remove data from the stream.
In most typical applications, however, a pipeline stage will
simply pass on any tokens that it does not recognize,
unmodified, so that other stages further down the pipeline
may act upon them if required.
Figs. 9a and 9b taken together illustrate an example of a
timing diagram for the data duplication circuit shown in
Figs. 8a and 8b. As before, the timing diagram shows the
relationship between the two-phase clock signals, the various
internal and external control signals, and the manner in
which data is clocked between the input and output sides of
the stage and is duplicated.
Referring now more particularly to Figure 10, there is
shown a reconfigurable process stage in accordance with one
2 1~424
a~pect of the present invention.
Input latches 34 receive an input over a first bus
31. A first output from the input latches 34 is passed over
line 32 to a token decode subsystem 33. A second output from
the input latches 34 is passed as a first input over line 35
to a processing unit 36. A first output from the token decode
subsystem 33 is passed over line 37 as a second input to the
processing unit 36. A second output from the token decode 33
is passed over line 40 to an action identification unit 39.
The action identification unit 39 also receives input from
registers 43 and 44 over line 46. The registers 43 and 44
hold the state of the machine as a whole. This state is
determined by the history of tokens previously received. The
output from the action identification unit 39 is passed over
line 38 as a third input to the processing unit 36. The
output from the processing unit 36 is passed to output
latches 41. The output from the output latches 41 is passed
over a second bus 42.
Referring now to Figure 11, a Start Code Detector
(SCD) 51 receives input over a two-wire interface 52. This
input can be either in the form of DATA tokens or as data
bits in a data stream. A first output from the Start Code
Detector 51 is passed over line 53 to a first logical first-
in first-out buffer (FIF0) 54. The output from the first
FIF0 54 is logically passed over line 55 as a first input to
a Huffman decoder 56. A second output from the Start Code
Detector 51 is passed over line 57 as a first input to a DRAM
interface 58. The DRAM interface 58 also receives input from
a buffer manager 59 over line 60. Signals are transmitted to
and received from external DRAM (not shown) by the DRAM
interface 58 over line 61. A first output from the DRAM
interface 58 is passed over line 62 as a first physical input
to the Huffman decoder 56.
~1459~4
The output from the Huffman decoder 56 is passed
over line 63 ~s an input to an Index to Data Unit (ITOD) 64.
The Huffman decoder 56 and the ITOD 64 work together as a
single logical unit. The output from the ITOD 64 is passed
over line 65 to an arithmetic logic unit (ALU) 66. A first
output from the ALU 66 is passed over line 67 to a read-only
memory (ROM) state machine 68. The output from the ROM state
machine 68 is passed over line 69 as a second physical input
to the Huffman decoder 56. A second-output from the ALU 66
is passed over line 70 to a Token Formatter (T/F) 71.
A first output 72 from the T/F 71 of the present
invention is passed over line 72 to a second FIFO 73. The
output from the second FIFO 73 is passed over line 74 as a
first input to an inverse modeller 75. A second output from
the T/F 71 is passed over line 76 as a third input to the
DRAM interface 58. A third output from the DRAM interface 58
is passed over line 77 as a second input to the inverse
modeller 75. The output from the inverse modeller 75 is
passed over line 78 as an input to an inverse quantizer 79
The output from the inverse quantizer 79 is passed over line
80 as an input to an inverse zig-zag (IZZ) 81. The output
from the IZZ 81 is passed over line 82 as an input to an
inverse discrete cosine transform (IDCT) 83. The output from
the IDCT 83 is passed over line 84 to a temporal decoder (not
shown).
Referring now more particularly to Figure 12, a
temporal decoder in accordance with the present invention is
shown. A fork 91 receives as input over line 92 the output
from the IDCT 83 (shown in Fig. 11). As a first output from
the fork 91, the control tokens, e.g., motion vectors and the
like, are passed over line 93 to an address generator 94.
Data tokens are also passed to the address generator 94 for
counting purposes. As a second output from the fork 91, the
~I 4~424
data is passed over line 95 to a FIF0 96. The output from the
FIF0 96 i8 then passed over line 97 as a first input to a
summer 98. The output from the address generator 94 is
passed over line 99 as a first input to a DRAM interface 100.
Signals are transmitted to and received from external DRAM
(not shown) by the DRAM interface lO0 over line 101. A first
output from the DRAM interface 100 is passed over line 102 to
a prediction filter 103. The output from the prediction
filter 103 is passed over line 104 a a second input to the
summer 98. A first output from the summer 98 is passed over
line 105 to output selector 106. A second output from the
summer 98 is passed over line 107 as a second input to the
DRAM interface 100. A second output from the DRAM interface
100 is passed over line 108 as a second input to the output
selector 106. The output from the output selector 106 is
passed over line 109 to a Video Formatter (not shown in
Figure 12).
Referring now to Figure 13, a fork 111 receives
input from the output selector 106 (shown in Figure 12) over
line 112. As a first output from the fork 111, the control
tokens are passed over line 113 to an address generator 114.
The output from the address generator 114 is passed over line
115 as a first input to a DRAM interface 116. As a second
output from the fork 111 the data is passed over line 117 as
a second input to the DRAM interface 116. Signals are
transmitted to and received from external DRAM (not shown) by
the DRAM interface 116 over line 118. The output from the
DRAM interface 116 is passed over line 119 to a display pipe
120.
It will be apparent from the above descriptions
that each line may comprise a plurality of lines, as
necessary.
21~5 i24
Referring now to Figure 14a, in the MPEG standard
a picture 131 is encoded as one or more slices 132. Each
slice 132 is, in turn, comprised of a plurality of blocks
133, and is encoded row-by-row, left-to-right in each row.
As is shown, each slice 132 may span exactly one full line of
blocks 133, less than one line B or D of blocks 133 or
multiple lines C of blocks 133.
Referring to Figure 14b, in the JPEG and H.261
standards, the Common Intermediate Format (CIF) is used,
wherein a picture 141 is encoded as 6 rows each containing 2
groups of blocks (GOBs) 142. Each GOB 142 is, in turn,
composed of either 3 rows or 6 rows of an indeterminate
number of blocks 143. Each GOB 142 is encoded in a zigzag
direction indicated by the arrow 144. The GOBs 142 are, in
turn, processed row-by-row, left-to-right in each row.
Referring now to Figure 14c, it can be seen that,
for both MPEG and CIF, the output of the encoder is in the
form of a data stream 151. The decoder receives this data
stream 151. The decoder can then reconstruct the image
according to the format used to encode it. In order to allow
the decoder to recognize start and end points for each
standard, the data stream 151 is segmented into lengths of 33
blocks 152.
Referring to Figure 15, a Venn diagram is shown,
representing the range of values possible for the table
selection from the Huffman decoder 56 (shown in Fig. 11) of
the present invention. The values possible for an MPEG
decoder and an H.261 decoder overlap, indicating that a
single table selection will decode both certain MPEG and
certain H.261 formats. Likewise, the values possible for an
MPEG decoder and a JPEG decoder overlap, indicating that a
single table selection will decode both certain MPEG and
~14~42~
certain JPEG formats. Additionally, it is shown that the
H.261 values and the JPEG values do not overlap, indicating
that no single table selection exists that will decode both
formats.
Referring now more particularly to Figure 16, there
i8 shown a schematic representation of variable length
picture data in accordance with the practice of the present
invention. A first picture 161 to be processed contains a
first PICTURE START token 162, first picture information of
indeterminate length 163, and a first PICTURE_END token 164.
A second picture 165 to be processed contains a second
PICTURE_START token 166, second picture information of
indeterminate length 167, and a second PICTURE_END token 168.
The PICTURE_START tokens 162 and 166 indicate the start of
the pictures 161 and 165 to the processor. Likewise, the
PICTURE_END tokens 164 and 168 signify the end of the
pictures 161 and 165 to the processor. This allows the
processor to process picture information 163 and 167 of
variable lengths.
Referring to Figure 17, a split 171 receives input
over line 172. A first output from the split 171 is passed
over line 173 to an address generator 174. The address
generated by the address generator 174 is passed over line
175 to a DRAM interface 176. Signals are transmitted to and
received from external DRAM (not shown) by the DRAM interface
176 over line 177. A first output from the DRAM interface
176 is passed over line 178 to a prediction filter 179. The
output from the prediction filter 179 is passed over line 180
as a first input to a summer 181. A second output from the
split 171 is passed over line 182 as an input to a first-in
first-out buffer (FIFO) 183. The output from the FIFO 183 is
passed over line 184 as a second input to the summer 181.
The output from the summer 181 is passed over line 185 to a
~145~2~
write signal generator 186. A first output from the write
signal generator 186 is pAæ~e~ over line 187 to the DRAM
interface 176. A second output from the write signal
generator 186 is passed over line 188 as a first input to a
read signal generator 189. A second output from the DRAM
interface 176 is passed over line 190 as a second input to
the read signal generator 189. The output from the read
signal generator 189 is passed over line 191 to a Video
Formatter (not shown in Figure 17). -
Referring now to Figure 18, the prediction
filtering process is illustrated. A forward picture 201 is
passed over line 202 as a first input to a summer 203. A
backward picture 204 is passed over line 205 as a second
input to the summer 203. The output from the summer 203 is
passed over line 206.
Referring to Figure 19, a slice 211 comprises one
or more macroblocks 212. In turn, each macroblock 212
comprises four luminance blocks 213 and two chrominance
blocks 214, and contains the information for an original 16
x 16 block of pixels. Each of the four luminance blocks 213
and two chrominance blocks 214 is 8 x 8 pixels in size. The
four luminance blocks 213 contain a 1 pixel to 1 pixel
mapping of the luminance (Y) information from the original 16
x 16 block of pixels. One chrominance block 214 contains a
representation of the chrominance level of the blue color
signal (Cu/b), and the other chrominance block 214 contains
a representation of the chrominance level of the red color
signal (Cv/r). Each chrominance level is subsampled such
that each 8 x 8 chrominance block 214 contains the
chrominance level of its color signal for the entire original16 x 16 block of pixels.
Referring now to Figure 20, the structure and
function of the Start Code Detector will become apparent. A
, 214S42~
value register 221 receives image data over a line 222. The
line 222 is eight bit~ wide, allowing for parallel
transmi6sion of eight bits at a time. The output from the
value register 221 is passed serially over line 223 to a
S decode register 224. A first output from the decode register
224 is passed to a detector 225 over a line 226. The line
226 is twenty-four bits wide, allowing for parallel
transmission of twenty-four bits at a time. The detector 225
detects the presence or absence of an-image which corresponds
to a standard-independent start code of 23 "zero" values
followed by a single "one" value. An 8-bit data value image
follows a valid start code image. On detecting the presence
of a start code image, the detector 225 transmits a start
image over a line 227 to a value decoder 228.
A second output from the decode register 224 is
passed serially over line 229 to a value decode shift
register 230. The value decode shift register 230 can hold
a data value image fifteen bits long. The 8-bit data value
following the start code image is shifted to the right of the
value decode shift register 230, as indicated by area 231.
This process eliminates overlapping start code images, as
discussed below. A first output from the value decode shift
register 230 is passed to the value decoder 228 over a line
232. The line 232 is fifteen bits wide, allowing for
parallel transmission of fifteen bits at a time. The value
decoder 228 decodes the value image using a first look-up
table (not shown). A second output from the value decode
shift register 230 is passed to the value decoder 228 which
passes a flag to an index-to-tokens converter 234 over a line
235. The value decoder 228 also passes information to the
index-to-tokens converter 234 over a line 236. The
information is either the data value image or start code
index image obtained from the first look-up table. The flag
~14~
indicates which form of information is passed. The line 236
i~ fifteen bits wide, allowing for parallel transmission of
fifteen bits at a time. While 15 bits has been chosen here
as the width in the present invention it will be appreciated
that bits of other lengths may also be used. The index-to-
tokens converter 234 converts the information to token images
using a second look-up table (not shown) similar to that
given in Table 12-3 of the Users Manual. The token images
generated by the index-to-tokens c~nverter 234 are then
output over a line 237. The line 237 is fifteen bits wide,
allowing for parallel transmission of fifteen bits at a time.
Referring to Figure 21, a data stream 241
consisting of individual bits 242 is input to a Start Code
Detector (not shown in Figure 21). A first start code image
243 is detected by the Start Code Detector. The Start Code
Detector then receives a first data value image 244. Before
processing the first data value image 244, the Start Code
Detector may detect a second start code image 245, which
overlaps the first data value image 244 at a length 246. If
this occurs, the Start Code Detector does not process the
first data value image 244, and instead receives and
processes a second data value image 247.
Referring now to Figure 22, a flag generator 251
receives data as a first input over a line 252. The line 252
is fifteen bits wide, allowing for parallel transmission of
fifteen bits at a time. The flag generator 251 also receives
a flag as a second input over a line 253, and receives an
input valid image over a first two-wire interface 254. A
first output from the flag generator 251 is passed over a
line 255 to an input valid register (not shown). A second
output from the flag generator 251 is passed over a line 256
to a decode index 257. The decode index 257 generates four
outputs; a picture start image is passed over a line 258, a
~145424
picture number image is passed over a line 259, an insert
image is passed over a line 260, and a replace image is
passed over a line 261. The data from the flag generator 251
is passed over a line 262a. A header generator 263 uses a
look-up table to generate a replace image, which is passed
over a line 262b. An extra word generator 264 uses the MPU
to generate an insert image, which is passed over a line
262c. Line 262a, and line 262b combine to form a line 262,
which is first input to output lat-ches 265. The output
latches 265 pass data over a line 266. The line 266 is
fifteen bits wide, allowing for parallel transmission of
fifteen bits at a time.
The input valid register (not shown) passes an
image as a first input to a first OR gate 267 over a line
268. An insert image is passed over a line 269 as a second
input to the first OR gate 267. The output from the first OR
gate 267 is passed as a first input to a first AND gate 270
over a line 271. The logical negation of a remove image is
passed over a line 272 as a second input to the first AND
gate 270 is passed as a second input to the output latches
265 over a line 273. The output latches 265 pass an output
valid image over a second two-wire interface 274. An output
accept image is received over the second two-wire interface
274 by an output accept latch 275. The output from the
output accept latch 275 is passed to an output accept
register (not shown) over a line 276.
The output accept register (not shown) passes an
image as a first input to a second OR gate 277 over a line
278. The logical negation of the output from the input valid
register is passed as a second input to the second OR gate
277 over a line 279. The remove image is passed over a line
280 as a third input to the second OR gate 277. The output
from the second OR gate 277 is passed as a first input to a
second AND gate 281 over a line 282. The logical negation of
~145429
82
an insert image is pA~ed as a second input to the second AND
gate 281 over a line 283. The output from the second AND
gate 281 is passed over a line 284 to an input accept latch
285. The output from the input accept latch 285 is passed
over the first two-wire interface 254.
~ 145~24
83
TABLL 600
Format Image Received Tokens Generated
1. H.261 SEQUENCE START SEQUENCE START
MPEG PICTURE START GROUP START
JPEG (None) PICTURE START
PICTURE DATA
2. H.261 (None) PICTURE END
MPEG (None) PADDING
JPEG (None) - FLUSH
STOP AFTER PICTURE
As set forth in Table 600 which shows a relationship
between the absence or presence of standard signals in the
certain machine independent control tokens, the detection of
an image by the Start Code Detector 51 generates a sequence
of machine independent Control Tokens. Each image listed in
the "Image Received" column starts the generation of all
machine independent control tokens listed in the group in the
"Tokens Generated" column. Therefore, as shown in line 1 of
Table 600, whenever a "sequence start" image is received
during H.261 processing or a "picture start" image is
received during MPEG processing, the entire group of four
control tokens is generated, each followed by its
corresponding data value or values. In addition, as set
forth at line 2 of Table 600, the second group of four
control tokens is generated at the proper time irrespective
of images received by the Start Code Detector 51.
TABLE 601
DISPLAY ORDER: Il B2 B3 P4 B5 B6 P7 B8 B9 I10
TRANSMIT ORDER: Il P4 B2 B3 P7 B5 B6 I10 B8 B9
As shown in line 1 of Table 601 which shows the timing
relationship between transmitted pictures and displayed
pictures, the picture frames are displayed in numerical
order. However, in order to reduce the number of frames that
" ~14~424
84
must be stored in memory, the frames are transmitted in a
different order. It is useful to begin the analysis from an
intraframe (I frame). The I1 frame is transmitted in the
order it is to be displayed. The next predicted frame (P
frame), P4, is then transmitted. Then, any bi-directionally
interpolated frames (B frames) to be displayed between the I1
frame and P4 frame are transmitted, represented by frames B2
and B3. This allows the transmitted B frames to reference a
previous frame (forward prediction) or a future frame
(backward prediction). After transmitting all the B frames
to be displayed between the I1 frame and the P4 frame, the
next P frame, P7, is transmitted. Next, all the B frames to
be displayed between the P4 and P7 frames are transmitted,
corresponding to B5 and B6. Then, the next I frame, I10, is
transmitted. Finally, all the B frames to be displayed
between the P7 and I10 frames are transmitted, corresponding
to frames B8 and B9. This ordering of transmitted frames
requires only two frames to be kept in memory at any one
time, and does not require the decoder to wait for the
transmission of the next P frame or I frame to display an
interjacent B frame.
Further information regarding the structure and operation,
as well as the features, objects and advantages, of the
ir.vention will become more readily apparent to one of
ordinary skill in the art from the ensuing additional
detailed description of illustrative embodiment of the
invention which, for purposes of clarity and convenience of
explanation are grouped and set forth in the following
sections:
'0 1. Multi-Standard Configurations
2. JPEG Still Picture Decoding
3. Motion Picture Decompression
4. F~M Memory Map
5. Bitstream Characteristics
14g424
6. Reconfigurable Processing Stage
7. Multi-Standard Coding
8. Multi-Standard Processing Circuit-2nd Mode of Operation
9. Start Code Detector
10. Tokens
11. DRAM Interface
12. Prediction Filter
13. Accessing Registers
14. Microprocessor Interface (MPI)
15. MPI Read Ti~ing
16. MPI write Timing
17. Key Hole Address Locations
18. Picture End
19. Flushing Operation
20. Flush Function
21. Stop-After-Picture
22. Multi-Standard Search Mode
23. Inverse Modeler
24. Inverse Quantizer
25. Huffman Decoder and Parser
26. Diverse Discrete Cosine Transformer
27. Buffer Manager
~lq5424
86
1. ~nLTI-8TANDARD CONFIa~RATION8
Since the various compression standards, i.e., JPEG,
MPEG and H.261, are well known, as for example as described
in the aforementioned United States Patent No. 5,212,742, the
detailed specifications of those standards are not repeated
here.
As previously mentioned, the present invention is
capable of decompressing a variety of differently encoded,
picture data bitstreams. In each of -the different standards
of encoding, some form of output formatter is required to
take the data presented at the output of the spatial decoder
operating alone, or the serial output of a spatial decoder
and temporal decoder operating in combination, ~as
subsequently described herein in greater detail) and
reformatting this output for use, including display in a
computer or other display systems, including a video display
system. Implementation of this formatting varies
significantly between encoding standards and/or the type of
display selected.
In a first embodiment, in accordance with the present
invention, as previously described with reference to Figures
10-12 an address generator is employed to store a block of
formatted data, output from either the first decoder (Spatial
Decoder) or the combination of the first decoder (Spatial
Decoder) and the second decoder (the Temporal Decoder), and
to write the decoded information into and/or from a memory in
a raster order. The video formatter described hereinafter
provides a wide range of output signal combinations.
In the preferred multi-standard video decoder embodiment
of the present invention, the Spatial Decoder and the
Temporal Decoder are required to implement both an MPEG
encoded signal and an H.261 video decoding system. The DRAM
interfaces on both devices are configurable to allow the
quantity of DRAM required to be reduced when working with
2~4~424
small picture formats and at low coded data rates. The
reconfiguration of these DRAMs will be further described
hereinafter with reference to the DRAM interface. Typically,
a single 4 megabyte DRAM i8 required by each of the Temporal
Decoder and the Spatial Decoder circuits.
The Spatial Decoder of the present invention performs
all the required processing within a single picture. This
reduces the redundancy within one picture.
The Temporal Decoder reduces the redundancy between the
subject picture with relationship to a picture which arrives
prior to the arrival of the subject picture, as well as a
picture which arrives after the arrival of the subject
picture. One aspect of the Temporal Decoder is to provide an
address decode network which handles the complex addressing
needs to read out the data associated with all of these
pictures with the least number of circuits and with high
speed and improved accuracy.
As previously described with reference to Figure 11, the
data arrives through the Start Code Detector, a FIFO register
which precedes a Huffman decoder and parser, through a second
FIFO register, an inverse modeller, an inverse quantizer,
inverse zigzag and inverse DCT. The two FIFOs need not be on
the chip. In one embodiment, the data does not flow through
a FIFO that is on the chip. The data is applied to the DRAM
interface, and the FIFO-IN storage register and the FIFO-OUT
register is off the chip in both cases. These registers,
whose operation is entirely independent of the standards,
will subsequently be described herein in further detail.
The majority of the subsystems and stages shown in
Figure 11 are actually independent of the particular standard
used and include the DRAM interface 58, the buffer manager 59
which is generating addresses for the DRAM interface, the
inverse modeller 75, the inverse zig-zag 81 and the inverse
21454~4
DCT 83. The standard independent unitC within the Huffman
decoder and parser include the ALU 66 and the token formatter
71.
Referring now to Figure 12, the standard-
independent units include the DRAM interface 100, the fork91, the FIFO register 96, the summer 98 and the output
selector 106. The standard dependent units are the address
generator 94, which is different in H.261 and in MPEG, and
the prediction filter 103, which is reconfigurable to have
the ability to do both H.261 and MPEG. The JPEG data will
flow through the entire machine completely unaltered.
Figure 13 depicts a high level block diagram of the
video formatter chip. The vast majority of this chip is
independent of the standard. The only items that are
affected by the standard is the way the data is written into
the DRAM in the case of H.261, which differs from MPEG or
JPEG; and that in H.261, it is not necessary to code every
single picture. There is some timing information referred to
as a temporal reference which provides some information
regarding when the pictures are intended to be displayed, and
that is also handled by the address generation type of logic
in the video formatter.
The remainder of the circuitry embodied in the video
formatter, including all of the color space conversion, the
up-sampling filters and all of the gamma correction RAMs, is
entirely independent of the particular compression standard
utilized.
The Start Code Detector of the present invention is
dependent on the compression standard in that it has to
recognize different start code patterns in the bitstream for
each of the standards. For example, H.261 has a 16 bit start
code, MPEG has a 24 bit start code and JPEG uses marker codes
which are fairly different from the other start codes. Once
the Start Code Detector has recognized those different start
21~42~
-
89
codes, it~ operation is essentially independent of the
compression standard. For instance, during searching, apart
from the circuitry that recognizes the different category of
markers, much of the operation is very similar between the
three different compression standards.
The next unit is the state machine 68 (Figure 11)
located within the Huffman decoder and parser. Here, the
actual circuitry is almost identical for each of the three
compression standards. In fact, the only element that is
affected by the standard in operation is the reset address of
the machine. If just the parser is reset, then it jumps to
a different address for each standard. There are, in fact,
four standards that are recognized. These standards are
H.261, JPEG, MPEG and one other, where the parser enters a
piece of code that is used for testing. This illustrates
that the circuitry is identical in almost every aspect, but
the difference is the program in the microcode for each of
the standards. Thus, when operating in H.261, one program is
running, and when a different program is running, there is no
overlap between them. The same holds true for JPEG, which is
a third, completely independent program.
The next unit is the Huffman decoder 56 which
functions with the index to data unit 64. Those two units
cooperate together to perform the Huffman decoding. Here,
the algorithm that is used for Huffman decoding is the same,
irrespective of the compression standard. The changes are in
which tables are used and whether or not the data coming into
the Huffman decoder is inverted. Also, the Huffman decoder
itself includes a state machine that understands some aspects
of the coding standards. These different operations are
selected in response to an instruction coming from the parser
state machine. The parser state machine operates with a
different program for each of the three compression standards
~14~4~g
9o
and issues the correct command to the Huffman decoder at
different times consistent with the standard in operation.
The last unit on the chip that is dependent on the
compression stAn~rd is the inverse quantizer 79, where the
mathematics that the inverse quantizer performs are different
for each of the different standards. In this regard, a
CODING_STANDARD token is decoded and the inverse quantizer 79
remembers which standard it is operating in. Then, any
subsequent DATA tokens that happen-after that event, but
before another CODING_STANDARD may come along, are dealt with
in the way indicated by the CODING_STANDARD that has been
remembered inside the inverse quantizer. In the detailed
description, there is a table illustrating different
parameters in the different standards and what circuitry is
responding to those different parameters or mathematics.
The address generation, with reference to H.261, differs
for each of the subsystems shown in Figure 12 and Figure 13.
The address generation in Figure 11, which generates
addresses for the two FIFOs before and after the Huffman
decoder, does not change depending on the coding standards.
Even in H.261, the address generation that happens on that
chip is unaltered. Essentially, the difference between these
standards is that in MPEG and JPEG, there is an organization
of macroblocks that are in linear lines going horizontally
across pictures. As best observed in Figure 14a, a first
macroblock A covers one full line. A macroblock B covers
less than a line. A macroblock C covers multiple lines. The
division in MPEG is into slices 132, and a slice may be one
horizontal line, A, or it may be part of a horizontal line B,
or it may extend from one line into the next line, C. Each
of these slices 132 is made up of a row of macroblocks.
In H.261, the organization is rather different
because the picture is divided into groups of blocks (GOB).
21~5~4
A group of blocks is three rows of macroblocks high by eleven
macroblocks wide. In the case of a CIF picture, there are
twelve such groups of blocks. However, they are not
organized one above the other. Rather, there are two groups
of blocks next to each other and then six high, i.e., there
are 6 GOB's vertically, and 2 GOB'S horizontally.
In all other standards, when performing the
addressing, the macroblocks are addressed in order as
described above. More specifically, addressing proceeds
along the lines and at the end of the line, the next line is
started. In H.261, the order of the blocks is the same as
described within a group of blocks, but in moving onto the
next group of blocks, it is almost a zig-zag.
The present invention provides circuitry to deal
with the latter affect. That is the way in which the address
generation in the spatial decoder and the video formatter
varies for H.261. This is accomplished whenever information
is written into the DRAM. It is written with the knowledge
of the aforementioned address generation sequence so the
place where it is physically located in the RAM is exactly
the same as if this had been an MPEG picture of the same
size. Hence, all of the address generation circuitry for
reading from the DRAM, for instance, when forming
predictions, does not have to comprehend that it is H.261
standard because the physical placement of the information in
the memory is the same as it would have been if it had been
in MPEG sequence. Thus, in all cases, only writing of data
is affected.
In the Temporal Decoder, there is an abstraction for
H.261 where the circuitry pretends something is different
from what is actually occurring. That is, each group of
blocks is conceptually stretched out so that instead of
having a rectangle which is 11 x 3 macroblocks, the
macroblocks are stretched out into a length of 33 blocks (see
214~4
Figure 14c) group of blocks which is one macroblock high. By
doing that, exactly the same counting mechanisms used on the
Temporal Decoder for counting through the groups of blocks
are also used for MPEG.
There is a correspondence in the way that the
circuitry is designed between an H.261 group of blocks and an
MPEG slice. When H.261 data is processed after the Start
Code Detector, each group of blocks is preceded by a
slice_start_code. The next group o blocks is preceded by
the next slice_start code. The counting that goes on inside
the Temporal Decoder for counting through this structure
pretends that it is a 33 macroblock-long group that is one
macroblock high. This is sufficient, although the circuitry
also counts every 11th interval. When it counts to the 11th
macroblock or the 22nd macroblock, it resets some counters.
This is accomplished by simple circuitry with another counter
that counts up each macroblock, and when it gets to 11, it
resets to zero. The microcode interrogates that and does
that work. All the circuitry in the temporal decoder of the
present invention is essentially independent of the
compression standard with respect to the physical placement
of the macroblocks.
In terms of multi-standard adaptability, there are
a number of different tables and the circuitry selects the
appropriate table for the appropriate standard at the
appropriate time. Each standard has multiple tables; the
circuitry selects from the set at any given time. Within any
one standard, the circuitry selects one table at one time and
another table another time. In a different standard, the
circuitry selects a different set of tables. There is some
intersection between those tables as indicated previously in
the discussion of Figure 15. For example, one of the tables
used in MPEG is also used in JPEG. The tables are not a
completely isolated set. Figure 15 illustrates an H.261
~ 14~424
; `
93
set, an MPEG set and a JPEG set. Note that there is a much
greater overlap between the H.261 set and the MPEG set. They
are quite common in the tables they utilize. There is a
small overlap between MPEG and JPEG, and there is no overlap
at all between H.261 and JPEG so that these standards have
totally different sets of tables.
As previously indicated, most of the system units are
compression standard independent. If a unit is standard
independent, and such units need not remember what
CODING_STANDARD is being processed. All of the units that
are standard dependent remember the compression standard as
the CODING_STANDARD token flows by them. When information
encoded/decoded in a first coding standard is distributed
through the machine, and a machine is changing standards,
prior machines under microprocessor control would normally
choose to perform in accordance with the H.261 compression
standard. The MPU in such prior machines generates signals
stating in multiple different places within the machine that
the compression standard is changing. The MPU makes changes
at different times and, in addition, may flush the pipeline
through.
In accordance with the invention, by issuing a change of
CODING_STANDARD tokens at the Start Code Detector that is
positioned as the first unit in the pipeline, this change of
2~ compression standard is readily handled. The token says a
certain coding standard is beginning and that control
information flows down the machine and configures all the
other registers at the appropriate time. The MPU need not
program each register.
The prediction token signals how to form predictions
using the bits in the bitstream. Depending on which
compression standard is operating, the circuitry translateS
the information that is found in the standard, i.e. from the
bitstream into a prediction mode token. This processing is
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94
performed by the Huffman decoder and parser state machine,
where it is easy to manipulate bits based on certain
conditions. The Start Code Detector generates this
prediction mode token. The token then flow down the machine
to the circuitry of the Temporal Decoder, wnich is the device
responsible for forming predictions. The circuitry of the
spatial decoder interprets the token without having to know
what standard it is operating in because the bits in it are
invariant in the three different standards. The Spatial
Decoder just does what it is told in response to that token.
By having these tokens and using them appropriately, the
design of other units in the machine is simplified. Although
there may be some complications in the program, benefits are
received in that some of the hard wired logic which would be
difficult to design for multi-standards can be used here.
2. JPEG STILL PICTURE DECODING
As previously indicated, the present invention relates
to signal decompression and, more particularly, to the
decompression of an encoded video signal, irrespective of the
compression standard employed.
One aspect of the present invention is to provide a first
decoder circuit (the Spatial Decoder) to decode a first
encoded signal (the JPEG encoded video signal) in combination
with a second decoder circuit (the Temporal Decoder) to
decode a first encoded signal (the MPEG or H.261 encoded
video signal) in a pipeline processing system. The Temporal
Decoder is not needed for JPEG decoding.
In this regard, the invention facilitates the
decompression of a plurality of differently encoded signals
through the use of a single pipeline decoder and
decompression system. The decoding and decompression
p1peline processor is organized on a unique and special
confiquraticn which allows the handling of the multi-standard
~ ` 2145424
encoded video signals through the use of techniques all
compatible with the single pipeline decoder and processing
system. The Spatial Decoder is combined with the Temporal
Decoder, and the Video ~ormatter is used in driving a video
display.
Another aspect of the invention is the use of the
combination of the Spatial Decoder and the Video Formatter
for use with only still pictures. The compression standard
independent Spatial Decoder performs all of the data
processing within the boundaries of a single picture. Such
a decoder handles the spatial decompression of the internal
picture data which is passing through the pipeline and is
distributed within associated random access memories,
standard independent address generation circuits for handllng
the storage and retrieval of information into the memories.
Still picture data is decoded at the output of the Spatial
Decoder, and this output is employed as input to the multi-
standard, configurable Video Formatter, which then provides
an output to the display terminal. In a first sequence of
similar pictures, each decompressed picture at the output of
the Spatial Decoder is of the same length in bits by the time
the picture reaches the output of the Spatial Decoder. A
second sequence of pictures may have a totally different
picture size and, hence, have a different length when
compared to the first length. Again, all such second
sequence of similar pictures are of the same length in bits
by the time such pictures reach the output of the Spatial
Decoder.
Another aspect of the invention is to internally organize
~o the incoming standard dependent bitstream into a sequence of
control tokens and DATA tokens, in combination with a
plurality of sequentially-positioned reconfigurable
processing stages selected and organized to act as a
standard-independent, reconfigurable-pipeline-processor.
21454~
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96
With regard to JPEG decoding, a single Spatial Decoder
with no off chip DRAM can rapidly decode baseline JPEG
images. The Spatial Decoder supports all features of
baseline JPEG encoding standards. However, the image size
that can be decoded may be limited by the size of the output
buffer provided. The Spatial Decoder circuit also includes
a random access memory circuit, having machine-dependent,
standard independent address generation circuits for handling
the storage of information into the memories.
As previously, indicated the Temporal Decoder is not
required to decode JPEG-encoded video. Accordingly, signals
carried by DATA tokens pass directly through the Temporal
Decoder without further processing when the Temporal Decoder
is configured for a JPEG operation.
Another aspect of the present invention is to provide in
the Spatial Decoder a pair of memory circuits, such as buffer
memory circuits, for operating in combination with the
Huffman decoder/video demultiplexor circuit (HD & VDM). A
first buffer memory is positioned before the HD & VDM, and a
second buffer memory is positioned after the HD & VDM. The
HD & VDM decodes the bitstream from the binary ones and zeros
that are in the standard encoded bitstream and turns such
stream into numbers that are used downstream. The advantage
of the two buffer system is for implementing a multi-standard
decompression system. These two buffers, in combination with
the identified implementation of the Huffman decoder, are
described hereinafter in greater detail.
A still further aspect of the present multi-standard,
decompression circuit is the combination of a Start Code
Detector circuit positioned upstream of the first forward
buffer operating in combination with the Huffman decoder.
One advantage of this combination is increased flexibility in
dealing with the input bitstream, particularly padding, which
has to be added to the bitstream. The placement of these
Z145~24
.
ident,~ ed components, Start Code Detector, memory buffers,
and Huffman decoder enhances the handling of certain
sequences in the input bitstream.
In addition, off chip DRAMs are used for decoding JPEG-
encoded video pictures in real time. The size and speed ofthe buffers used with the DRAMs will depend on the video
encoded data rates.
The coding standards identify all of the standard
dependent types of information that is necessary for storage
in the DRAMs associated with the Spatial Decoder using
standard independent circuitry.
3. MOTION PICTURE DECOMPRE88ION
In the present invention, if motion pictures are being
decompressed through the steps of decoding, a further
Temporal Decoder is necessary. The Temporal Decoder combines
the data decoded in the Spatial Decoder with pictures,
previously decoded, that are intended for display either
before or after the picture being currently decoded. The
Temporal Decoder receives, in the picture coded datastream,
information to identify this temporally-displaced
information. The Temporal Decoder is organized to address
temporally and spatially displaced information, retrieve it,
and combine it in such a way as to decode the information
located in one picture with the picture currently being
2~ decoded and ending with a resultant picture that is complete
and is suitable for transmission to the video formatter for
driving the display screen. Alternatively, the resultant
picture can be stored for subsequent use in temporal decoding
of subsequent pictures.
Generally, the Temporal Decoder performs the processing
between pictures either earlier and/or later in time with
reference to the picture currently being decoded. The
Temporal Decoder reintroduces information that is not encoded
within the coded representation of the picture, because it is
~14~Z4
redun~ant and is already available at the decoder. More
specifically, it is probable that any given picture will
contain similar information as pictures temporally
surrounding it, both before and after. This similarity can
be made greater if motion compensation is applied. The
Temporal Decoder and decompression circuit also reduces the
redundancy between related pictures.
In another aspect of the present invention, the Temporal
Decoder is employed for handling the standard-dependent
lo output information from the Spatial Decoder. This standard
dependent information for a single picture is distributed
among several areas of DRAM in the sense that the
decompressed output information, processed by the Spatial
Decoder, is stored in other DRAM registers by other random
access memories having still other machine-dependent,
standard-independent address generation circuits for
combining one picture of spatially decoded information packet
of spatially decoded picture information, temporally
displaced relative to the temporal position of the first
picture.
In multi-standard circuits capable of decoding MPEG-
encoded signals, larger logic DRAM buffers may be required to
support the larger picture formats possible with MPEG.
. The picture information is moving through the serial
pipeline in 8 pel by 8 pel blocks. In one form of the
invention, the address decoding circuitry handles these pel
blocks (storing and retrieving) along such block boundaries.
The address decoding circuitry also handles the storing and
retrieving of such 8 by 8 pel blocks across such boundaries.
This versatility is more completely described hereinafter.
A second Temporal Decoder may also be provided which
passes the output of the first decoder circuit (the Spatial
Decoder) directly to the Video Formatter for handling without
signal processing delay.
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99
The Temporal Decoder also reorders the blocks of picture
data for display by a display circuit. The address decode
circuitry, described hereinafter, provides handling of this
reordering.
As previously mentioned, one important feature of the
Temporal Decoder is to add picture information together from
a selection of pictures which have arrived earlier or later
than the picture under processing. When a picture is
described in this context, it may mean any one of the
following:
1. The coded data representation of the picture;
2. The result, i.e., the final decoded picture
resulting from the addition of a process step
performed by the decoder;
3. Previously decoded pictures read from the DRAM; and
4. The result of the spatial decodinq, i.e., the extent
of data between a PICTURE_START token and a
subsequent PICTURE_END token.
After the picture data information is processed by the
Temporal Decoder, it is either displayed or written back into
a picture memory location. This information is then kept for
further reference to be used in processing another different
coded data picture.
Re-ordering of the MPEG encoded pictures for visual
2~ display involves the possibility that a desired scrambled
picture can be achieved by varying the re-ordering feature of
the Temporal Decoder.
4. RAM MEMORY MAP
The Spatial Decoder, Temporal Decoder and Video
Formatter all use external DRAM. Preferably, the same DRAM
is used for all three devices. While all three devices use
DRAM, and all three devices use a DRAM interface in
conjunction with an address generator, what each implements
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100
in DRAM is different. That is, each chip, e.g. Spatial
Decoder and Temporal Decoder, have a different DRAM interface
and address generation circuitry even through they use a
similar physical, external DRAM.
In brief, the Spatial Decoder implements two FIFOs in
the common DRAM. Referring again to Figure 11, one FIFO 54
is positioned before the Huffman decoder 56 and parser, and
the other is positioned after the Huffman decoder and parser.
The FIFOs are implemented in a relatively straightforward
manner. For each FIFO, a particular portion of DRAM is set
aside as the physical memory in which the FIFO will be
implemented.
The address generator associated with the Spatial
Decoder DRAM interface 58 keeps track of FIFO addresses using
two pointers. One pointer points to the first word stored in
the FIFO, the other pointer points to the last word stored in
the FIFO, thus allowing read/write operation on the
appropriate word. When, in the course of a read or write
operation, the end of the physical memory is reached, the
address generator "wraps around" to the start of the physical
memory.
In brief, the Temporal Decoder of the present invention
must be able to store two full pictures or frames of whatever
encoding standard (MPEG or H.261) is specified. For
simplicity, the physical memory in the DRAM into which the
two frames are stored is split into two halves, with each
half being dedicated (using appropriate pointers) to a
particular one of the two pictures.
~ MPEG uses three different picture types: Intra (I),
Predicted (P) and Bidirectionally interpolated (B). As
previously mentioned, B pictures are based on predictions
from two pictures. One picture is from the future and one
from the past. I pictures require no further decoding by the
Temporal Decoder, but must be stored in one of the two
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101
piCtU~Q buffers for later use in decoding P and B pictures.
Decoding P pictures requires forming predictions from a
previously decoded P or I picture. The decoded P picture is
stored in a picture buffer for use decoding P and B pictures.
B pictures can require predictions form both of the picture
buffers. However, B pictures are not stored in the external
DRAM.
~ ote that I and P pictures are not output from the
Temporal Decoder as they are decoded. Instead, I and P
pictures are written into one of the picture buffers, and are
read out only when a subsequent I or P picture arrives for
decoding. In other words, the Temporal Decoder relies on
subsequent P or I pictures to flush previous pictures out of
the two picture buffers, as further discussed hereinafter in
1~ the section on flushing. In brief, the Spatial Decoder can
provide a fake I or P picture at the end of a video sequence
to flush out the last P or I picture. In turn, this fake
picture is flushed when a subsequent video sequence starts.
The peak memory band width load occurs when decoding B
pictures. The worst case is the B frame may be formed from
predictions from both the picture buffers, with all
predictions being made to half-pixel accuracy.
As previously described, the Temporal Decoder can be
configured to provide MPEG picture reordering. With this
picture reordering, the output of P and I pictures is delayed
until the next P or I picture in the data stream starts to be
decoded by the Temporal Decoder.
As the P or I pictures are reordered, certain tokens are
stored temporarily on chip as the picture is written into the
picture buffers. When the picture is read out for display,
these stored tokens are retrieved. At the output of the
Temporal Decoder, the DATA Tokens of the newly decoded P or
I picture are replaced with DATA Tokens for the older P or I
picture.
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102
In contrast, H.261 makes predictions only from the
picture just decoded. As each picture is decoded, it is
written into one of the two picture buffers so it can be used
in decoding the next picture. The only DRAM memory
operations required are writing 8 x 8 blocks, and forming
predictions with integer accuracy motion vectors.
In brief, the Video Formatter stores three frames or
pictures. Three pictures need to be stored to accommodate
such features as repeating or skipping pictures.
5. BTTSTREAM CHARACTERISTICS
Referring now particularly to the Spatial Decoder of the
present invention, it is helpful to review the bitstream
characteristics of the encoded datastream as these
characteristics must be handled by the circuitry of the
l~ Spatial Decoder and the Temporal Decoder. For example, under
one or more compression standards, the compression ratio of
the standard is achieved by varying the number of bits that
it uses to code the pictures of a picture. The number of
bits can vary by a wide margin. Specifically, this means
that the length of a bitstream used to encode a referenced
picture of a picture might be identified as being one unit
long, another picture might be a number of units long, while
still a third picture could be a fraction of that unit.
None of the existing standards (MPEG 1.2, JPEG, H.261)
2~ define a way of ending a picture, the implication being that
when the next picture starts, the current one has finished.
Additionally, the standards (H.261 specifically) allow
incomplete pictures to be generated by the encoder.
In accordance with the present invention, there is
provlded a way of indicating the end of a picture by using
one of its tokens: PICTURE_END. The still encoded picture
data leaving the Start Code Detector consists of pictures
starting with a PICTURE_START token and ending with a
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103
PICTURE END token, but still of widely varying length. There
may be other information transmitted here (between the first
and second picture), but it is known that the first picture
ha~ finished.
The data stream at the output of the Spatial Decoder
consists of pictures, still with picture-starts and picture-
ends, of the same length (number of bits) for a given
sequence. The length of time between a picture-start and a
picture-end may vary.
The Video Formatter takes these pictures of non-uniform
time and displays them on a screen at a fixed picture rate
determined by the type of display being driven. Different
display rates are used throughout the world, e.g. PAL-NTSC
television standards. This is accomplished by selectively
dropping or repeating pictures in a manner which is unique.
Ordinary "frame rate converters," e.g. 2-3 pulldown, operate
with a fixed input picture rate, whereas the Video Formatter
can handle a variable input picture rate.
6. RECONFIGURABEE PROCE88ING 8TAGE
Referring again to Figure 10, the reconfigurable
processing stage (RPS) comprises a token decode circuit 33
which is employed to receive the tokens coming from a two
wire interface 37 and input latches 34. The output of the
token decode circuit 33 is applied to a processing unit 36
over the two-wire interface 37 and an action identification
circuit 39. The processing unit 36 is suitable for
processing data under the control of the action
identification circuit 39. After the processing is
completed, the processing unit 36 connects such completed
signals to the output, two-wire interface bus 40 through
output latches 41.
The action identification decode circuit 39 has an
input from the token decode circuit 33 over the two-wire
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104
interface bus 40 and/or from memory circuit~ 43 and 44 over
two-wire interface bu~ 46. The token~ from the token decode
circuit 33 are applied simultaneouely to the action
identification circuit 39 and the processing unit 36. The
action identification function as well as the RPS is
described in further detail by table~ and figures in a
subsequent portion of this specification.
The functional block diagram in Figure 10
illustrates those stages shown in Figures 11, 12 and 13 which
are not standard independent circuits. The data flows
through the token decode circuit 33, through the processing
unit 36 and onto the two-wire interface circuit 42 through
the output latches 41. If the Control Token is recognized by
the RPS, it is decoded in the token decode circuit 33 and
appropriate action will be taken. If it is not recognized,
it will be passed unchanged to the output two-wire interface
42 through the output circuit 41. The present invention
operates as a pipeline processor having a two-wire interface
for controlling the movement of control tokens through the
pipeline. This feature of the invention is described in
greater detail in the previously filed EPO patent application
number 92306038.8.
In the present invention, the token decode circuit 33 is
employed for identifying whether the token presently entering
through the two-wire interface 42 is a DATA token or control
token. In the event that the token being examined by the
token decode circuit 33 is recognized, it is exited to the
action identification circuit 39 with a proper index signal
or flag signal indicating that action is to be taken. At the
same time, the token decode circuit 33 provides a proper flag
or index signal to the processing unit 36 to alert it to the
presence of the token being handled by the action
identification circuit 39.
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105
Control tok~nc may also be processed.
A more detailed description of the various types of
tokens usable in the present invention will be subsequently
described hereinafter. For the purpose of this portion of
the specification, it is sufficient to note that the address
carried by the control token is decoded in the decoder 33 and
is used to access registers contained within the action
identification circuit 39. When the token being examined is
a recognized control token, the action identification circuit
39 uses its reconfiguration state circuit for dictributing
the control signals throughout the state machine. As
previously mentioned, this activates the state machine of the
action identification decoder 39, which then reconfigures
itself. For example, it may change coding standards. In
this way, the action identification circuit 39 decodes the
required action for handling the particular standard now
passing through the state machine shown with reference to
Figure 10.
Similarly, the processing unit 36 which is under
the control of the action identification circuit 39 is now
ready to process the information contained in the data fields
of the DATA token when it is appropriate for this to occur.
On many occasions, a control token arrives first,
reconfigures the action identification circuit 39 and is
immediately followed by a DATA token which is then processed
by the processing unit 36. The control token exits the
output latches circuit 41 over the output two-wire interface
42 immediately preceding the DATA token which has been
processed within the processing unit 36.
In the present invention, the action identification
circuit, 39, is a state machine holding history state. The
registers, 43 and 44 hold information that has been decoded
from the token decoder 33 and stored in these registers.
~19~12~
106
Such registers can be either on-chip or-off chip as needed.
These plurality of state regi~ters contain action information
connected to the action identification currently being
identified in the action identification circuit 39. This
action information has been stored from previously decoded
tokens and can affect the action that is selected. The
connection 40 is going straight from the token decode 33 to
the action identification block 39. This is intended to show
that the action can also be affected by the token that is
currently being processed by the token decode circuit 33.
In general, there is shown token decoding and data
processing in accordance with the present invention. The
data processing is performed as configured by the action
identification circuit 39. The action is affected by a
number of conditions and is affected by information generally
derived from a previously decoded token or, more
specifically, information stored from previously decoded
tokens in registers 43 and 44, the current token under
processing, and the state and history information that the
action identification unit 39 has itself acquired. A
distinction is thereby shown between Control tokens and DATA
tokens.
In any RPS, some tokens are viewed by that RPS unit as
being Control tokens in that they affect the operation of the
RPS presumably at some subsequent time. Another set of
tokens are viewed by the RPS as DATA tokens. Such DATA
tokens contain information which is processed by the RPS in
a way that is determined by the design of the particular
circuitry, the tokens that have been previously decoded and
the state of the action identification circuit 39. Although
a particular RPS identifies a certain set of tokens for that
particular RPS control and another set of tokens as data,
that is the view of that particular RPS. Another RPS can
have a different view of the same token. Some of the tokens
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.
107
might be viewed by one RPS unit as DATA Tokens while another
RPS unit might decide that it is actually a Control Token.
For example, the quantization table information, as far as
the Huffman decoder and state machine is concerned, is data,
because it arrives on its input as coded data, it gets
formatted up into a series of 8 bit words, and they get
formed into a token called a quantization table token
(QUANT_TABLE) which goes down the processing pipeline. As
far as that machine is concerned, all of that was data; it
was handling data, transforming one sort of data into another
sort of data, which is clearly a function of the processing
performed by that portion of the machine. However, when that
information gets to the inverse quantizer, it stores the
information in that token a plurality of registers. In fact,
because there are 64 8-bit numbers and there are many
registers, in general, many registers may be present. This
information is viewed as control information, and then that
control information affects the processing that is done on
subsequent DATA tokens because it affects the number that you
~o ~ultiply each data word. There is an example where one stage
viewed that token as being data and another stage viewed it
as being control.
Token data, in accordance with the invention is almost
universally viewed as being data through the machine. One of
the important aspects is that, in general, each stage of
circuitry that has a token decoder will be looking for a
certain set of tokens, and any tokens that it does not
recognize will be passed unaltered through the stage and down
the pipeline, so that subsequent stages downstream of the
current stage have the benefit of seeing those tokens and may
respond to them. This is an important feature, namely there
can be communication between blocks that are not adjacent to
one another using the token mechanism.
Another important feature of the invention is that each of
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108
the stages of circuitry has the processing capability within
it to be able to perform the necessary operations for each of
the standards, and the control, as to which operations are to
be performed at a given time, come as tokens. There is one
processing element that differs between the different stages
to provide this capability. In the state machine ROM of the
parser, there are three separate entirely different programs,
one for each of the standards that are dealt with. Which
program is executed depends upon a CODING STANDARD token. In
otherwords, each of these three programs has within it the
ability to handle both decoding and the CODING_STANDARD
standard token. When each of these programs sees which
coding standard, is to be decoded next, they literally jump
to the start address in the microcode ROM for that particular
program. This is how stages deal with multi-standardness.
Two things are affected by the different standards.
First, it affects what pattern of bits in the bitstream are
recognized as a start-code or a marker code in order to
reconfigure the shift register to detect the length of the
start marker code. Second, there is a piece of information
in the microcode that denotes what that start or marker code
means. Recall that the coding of bits differs between the
three standards. Accordingly, the microcode looks up in a
table, specific to that compressor standard, something that
is independent of the standard, i.e., a type of token that
represents the incoming codes. This token is typically
independent of the standard since in most cases, each of the
various standards provide a certain code that will produce
it.
The inverse quantizer 79 has a mathematical
capability. The quantizer multiplies and adds, and has the
ability to do all three compression standards which are
configured by parameters. For example, a flag bit in the ROM
in control tells the inverse quantizer whether or not to add
424
109
a constant, K. Another flag tells the inverse quantizer
whether to add another constant. The inverse quantizer
remembers in a register the CODING STANDARD token as it flows
by the quantizer. When DATA tokens pass thereafter, the
inver~e quantizer remembers what the st~ d is and it looks
up the parameters that it needs to apply to the processing
elements in order to perform a proper operation. For
example, the inverse quantizer will look up whether K is set
to 0, or whether it is set to 1 for a-particular compression
standard, and will apply that to its processing circuitry.
In a similar sense the Huffman decoder 56 has a number
of tables within it, some for JPEG, some for MPEG and some
for H.261. The majority of those tables, in fact, will
service more than one of those compression standards. Which
tables are used depends on the syntax of the standard. The
Huffman decoder works by receiving a command from the state
machine which tells it which of the tables to use.
Accordingly, the Huffman decoder does not itself directly
have a piece of state going into it, which is remembered and
which says what coding it is performing. Rather, it is the
combination of the parser state machine and Huffman decoder
together that contain information within them.
Regarding the Spatial Decoder of the present
invention, the address generation is modified and is similar
to that shown in Figure 10, in that a number of pieces of
information are decoded from tokens, such as the coding
standard. The coding standard and additional information as
well, is recorded in the registers and that affects the
progress of the address generator state machine as it steps
through and counts the macroblocks in the system, one after
the other. The last stage would be the prediction filter 179
(Figure 17) which operates in one of two modes, either H.261
or MPEG and are easily identified.
~14512~
,
110
7. MU~ STANDARD CODING
The system of the present invention also provides a
combination of the standard-independent indices generation
circuits, which are strategically placed throughout the
system in combination with the token decode circuits. For
example, the system is employed for specifically decoding
either the H.261 video standard, or the MPEG video standard
or the JPEG video standard. These three compression coding
standards specify similar processes to be done on the
arriving data, but the structure of the datastreams is
different. As previously discussed, it is one of the
functions of the Start Code Detector to detect MPEG start-
codes, H.261 start-codes, and JPEG marker codes, and convert
them all into a form, i.e., a control token which includes a
token stream embodying the current coding standard. The
control tokens are passed through the pipeline processor, and
are used, i.e., decoded, in the state machines to which they
are relevant, and are passed through other state machines to
~hich the tokens are not relevant. In this regard, the DATA
Tokens are treated in the same fashion, insofar as they are
processed only in the state machines that are configurable by
the control tokens into processing such DATA Tokens. In the
remaining state machines, they pass through unchanged.
More specifically, a control token in accordance with
the present invention, can consist of more than one word in
the token. In that case, a bit known as the extension bit is
set specifying the use of additional words in the token for
carrying additional information. Certain of these additional
control bits contain indices indicating information for use
.0 in corresponding state machines to create a set of standard-
independent indices signals. The remaining portions of the
token are used to indicate and identify the internal
processing control function which is standard for all of the
datastreams passing through the pipeline processor. In one
~145~
111
for~ of the invention, the token exten~ion i6 used to carry
the current coding standard which is decoded by the relative
token decode circuits distributed throughout the machine, and
is used to reconfigure the action identification circuit 39
of ~tages throughout the machine wherever it is appropriate
to operate under a new coding standard. Additionally, the
token decode circuit can indicate whether a control token is
related to one of the selected standards which the circuit
was designed to handle.
More specifically, an MPEG start code and a JPEG marker
are followed by an 8 bit value. The H.261 start code is
followed by a 4 bit value. In this context, the Start Code
Detector 51, by detecting either an MPEG start-code or a JPEG
marker, indicates that the following 8 bits contain the value
associated with the start-code. Independently, it can then
create a signal which indicates that it is either an MPEG
start code or a JPEG marker and not an H.261 start code. In
this first instance, the 8 bit value is entered into a decode
circuit, part of which creates a signal indicating the index
and flag which is used within the current circuit for
handling the tokens passing through the circuit. This is
also used to insert portions of the control token which will
be looked at thereafter to determine which standard is being
handled. In this sense, the control token contains a portion
indicating that it is related to an MPEG standard, as well as
a portion which indicates what type of operation should be
performed on the accompanying data. As previously discussed,
this information is utilized in the system to reconfigure the
processing stage used to perform the function required by the
various standards created for that purpose.
For example, with reference to the H.261 start code, it
is associated with a 4 bit value which follows immediately
after the start code. The Start Code Detector passes this
value into the token generator state machine. The value is
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applied to an 8 bit decoder which produces a 3 bit start
number. The start number is employed to identify the
picture-start of a picture number as indicated by the value.
The system also includes a multi-stage parallel
processing pipeline operating under the principles of the
two-wire interface previously described. Each of the stages
comprises a machine generally taking the form illustrated in
Figure 10. The token decode circuit 33 is employed to direct
the token presently entering the state machine into the
action identification circuit 39 or the processing unit 36,
as appropriate. The processing unit has been previously
reconfigured by the next previous control token into the form
needed for handling the current coding standard, which is now
entering the processing stage and carried by the next DATA
token. Further, in accordance with this aspect of the
invention, the succeeding state machines in the processing
pipeline can be functioning under one coding standard, i.e.,
H.261, while a previous stage can be operating under a
separate standard, such as MPEG. The same two-wire interface
is used for carrying both the control tokens and the DATA
Tokens.
The system of the present invention also utilizes
control tokens required to decode a number of coding
standards with a fixed number of reconfigurable processing
stages. More specifically, the PICTURE END control token is
employed because it is important to have an indication of
when a picture actually ends. Accordingly, in designing a
multi-standard machine, it is necessary to create additional
control tokens within the multi-standard pipeline processing
machine which will then indicate which one of the standard
decoding techniques to use. Such a control token is the
PICTURE_END token. This PICTURE_END token is used to
indicate that the current picture has finished, to force the
buffers to be flushed, and to push the current picture
Z l 4 ~
-
113
through the dDcoA~r to the display.
S. ~n~ 8TANDaRD PROCE~J~Na CIRCUI~ - 8ECOND
MOD~ OF OP~RATION
A compression standard-dependent circuit, in the form of
the previously deæcribed Start Code Detector, is suitably
interconnected to a compression stAnAArd-independent circuit
over an appropriate bus. The standard-dependent circuit is
connected to a combination dependent-independent circuit over
the same bus and an additional bus. The standard-independent
circuit applies additional input to the standard dependent-
independent circuit, while the latter provides information
back to the standard-independent circuit. Information from
the standard-independent circuit is applied to the output
over another suitable bus. Table 600 illustrates that the
multiple standards applied as the input to the standard-
dependent Start Code Detector 51 include certain bit streams
which have standard-dependent meanings within each encoded
bit stream.
9. 8TART-CODE D~ R
As previously indicated the Start Code Detector, in
accordance with the present invention, is capable of taking
MPEG, JPEG and H.261 bit streams and generating from them a
sequence of proprietary tokens which are meaningful to the
rest of the decoder. As an example of how multi-standard
decoding is achieved, the MPEG (1 and 2) picture_start_code,
the H.261 picture_start_code and the JPEG start_of_scan (SOS)
marker are treated as equivalent by the Start Code Detector,
and all will generate an internal PICTURE_START token. In a
similar way, the MPEG sequence_start_code and the JPEG SOI
(start_of_image) marker both generate a machine
sequence_start_token. The H.261 standard, however, has no
equivalent start code. Accordingly, the Start Code Detector,
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114
in r~sponse to the first H.261 picture_start_code, will
generate a sequence_start token.
None of the above described images are directly used
other than in the SCD. Rather, a machine PICTURE_START
token, for example, has been deemed to be equivalent to the
PICTURE_START images contained in the bit stream.
Furthermore, it must be borne in mind that the machine
PICTURE_START by itself, is not a direct image of the
PICTURE_START in the standard. Rather, it is a control token
which is used in combination with other control tokens to
provide standard-independent decoding which emulates the
operation of the images in each of the compression coding
standards. The combination of control tokens in combination
with the reconfiguration of circuits, in accordance with the
information carried by control tokens, is unique in and of
itself, as well as in further combination with indices and/or
flags generated by the token decode circuit portion of a
respective state machine. A typical reconfigurable state
machine will be described subsequently.
~G Referring again to Table 600, there are shown the names
of a group of standard images in the left column. In the
right column there are shown the machine dependent control
tokens used in the emulation of the standard encoded signal
which is present or not used in the standard image.
2~ With reference to Table 600, it can be seen that a
machine sequence_start signal is generated by the Start Code
Detector, as previously described, when it decodes any one of
the standard signals indicated in Table 600. The Start Code
Detector creates sequence_start, group_start, sequence_end,
~0 slice_start, user-data, extra-data and PICTURE_START tokens
for application to the two-wire interface which is used
throughout the system. Each of the stages which operate in
conjunction with these control tokens are configured by the
contents of the tokens, or are configured by indices created
` ` ~14~4~
115
by contents of the tokens, and are prepared to handle data
which is expected to be received when the picture DATA Token
arrives at that station.
As previously described, one of the compression
standards, such as H.261, does not have a sequence_start
image in its data stream, nor does it have a PICTURE_END
image in its data stream. The Start Code Detector indicates
the PICTURE_END point in the incoming bit stream and creates
a PICTURE_END token. In this regard, the system of the
present invention is intended to carry data words that are
fully packed to contain a bit of information in each of the
register positions selected for use in the practice of the
present invention. To this end, 15 bits have been selected
as the number of bits which are passed between two start
codes. Of course, it will be appreciated by one of ordinary
skill in the art, that a selection can be made to include
either greater or fewer than 15 bits. In other words, all 15
bits of a data word being passed from the start Code Detector
into the DRAM interface are required for proper operation.
Accordingly, the Start Code Detector creates extra bits,
called padding, which it inserts into the last word of a DATA
Token. For purposes of illustration 15 data bits has been
selected.
To perform the Padding operation, in accordance with the
present invention, binary O followed by a number of binary
l's are automatically inserted to complete the 15 bit data
word. This data is then passed through the coded data buffer
and presented to the Huffman decoder, which removes the
padding. Thus, an arbitrary number of bits can be passed
through a buffer of fixed size and width.
In one embodiment, a slice_start control token is used
to identify a slice of the picture. A slice start control
token is employed to segment the picture into smaller
regionS. The size of the region is chosen by the encoder,
Z14~24
1^16
and t~e Start Code Detector identifies this unique pattern of
the slice_start code in order for the machine-dependent state
stages, located downstream from the Start Code Detector, to
segment the picture being received into smaller regions. The
size of the region is chosen by the encoder, recognized by
the Start Code Detector and used by the recombination
circuitry and control tokens to decompress the encoded
picture. The slice_start_codes are principally used for
error recovery.
lo The start codes provide a unique method of starting up
the decoder, and this will subsequently be described in
further detail. There are a number of advantages in placing
the Start Code Detector before the coded data buffer, as
opposed to placing the Start Code Detector after the coded
data buffer and before the Huffman decoder and video
demultiplexor. Locating the Start Code Detector before the
first buffer allows it to 1) assemble the tokens, 2) decode
the standard control signals, such as start codes, 3) pad the
bitstream before the data goes into the buffer, and 4) create
the proper sequence of control tokens to empty the buffers,
pushing the available data from the buffers into the Huffman
Decoder.
Most of the control token output by the Start Code
Detector directly reflect syntactic elements of the various
picture and video coding standards. The Start Code Detector
converts the syntactic elements into control tokens. In
addition to these natural tokens, some unique and/or machine-
dependent tokens are generated. The unique tokens include
those tokens which have been specifically designed for use
with the system of the present invention which are unique in
and of themselves, and are employed for aiding in the multi-
standard nature of the present invention. Examples of such
unique tokens include PICTURE-END and CODING_STANDARD.
Tokens are also introduced to remove some of the
~ ~145~24
117
synta~tiC differences between the coding standards and to
function in co-operation with the error conditions. The
automatic token generation is done after the serial analysis
of the standard-dependent data. Therefore, the Spatial
Decoder responds equally to tokens that have been supplied
directly to the input of the Spatial Decoder, i.e. the SCD,
as well as to tokens that have been generated following the
detection of the start-codes in the coded data. A sequence
of extra tokens is inserted into the two- wire interface in
order to control the multi-standard nature of the present
invention.
The MPEG and H.261 coded video streams contain standard
dependent, non-data, identifiable bit patterns, one of which
is hereinafter called a start image and/or standard-dependent
code. A similar function is served in JPEG, by marker codes.
These start/marker codes identify significant parts of the
syntax of the coded datastream. The analysis of start/marker
codes performed by the Start Code Detector is the first stage
in parsing the coded data.
The start/marker code patterns are designed so that they
can be identified without decoding the entire bit stream.
Thus, they can be used, in accordance with the present
invention, to assist with error recovery and decoder start-
up. The Start Code Detector provides facilities to detect
errors in the coded data construction and to assist the
start-up of the decoder. The error detection capability of
the Start Code Detector will subsequently be discussed in
further detail, as will the process of starting up of the
decoder.
The aforementioned description has been concerned
primarilty with the characteristiCS of the machine-dependent
bit stream and its relationship with the addressing
characteristic5 of the present invention. The follo-~ing
description is of the bit stream characteristics of ~he
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118
standard-dependent coded data with reference to the Start
Code Detector.
Each of the standard compression encoding systems
employs a unique start code configuration or image which has
5 been selected to identify that particular compression
specification. Each of the start codes also carries with it
a start code value. The start code value is employed to
identify within the language of the standard the type of
operation that the start code is associated with. In the
multi-standard decoder of the present invention, the
compatibility is based upon the control token and DATA token
configuration as previously described. Index signals,
including flag signals, are circuit-generated within each
state machine, and are described hereinafter as appropriate.
The start andtor marker codes contained in the
standards, as well as other standard words as opposed to data
words, are sometimes identified as images to avoid confusion
with the use of code and/or machine-dependent codes to refer
to the contents of control and/or DATA tokens used in the
machine. Also, the term start code is often used as a
generic term to refer to JPEG marker codes as well as MPEG
and H.261 start codes. Marker codes and start codes serve
the same purpose. Also, the term "flush" is used both to
refer to the FLUSH token, and as a verb, for example when
referring to flushing the Start Code Detector shift registers
(including the signal "flushed"). To avoid confusion, the
FLUSH token is always written in upper case. All other uses
of the term (verb or noun) are in lower case.
The standard-dependent coded input picture input stream
~G comprises data and start images of varying lengths. The
start images carry with them a value telling the user what
operation is to be performed on the data which immediatelY
follows according to the standard. However, in the multi-
standard pipeline processing system of the present invention,
~1~5~Z4
119
where compatibility is required for multiple standards, the
system has been optimized for handling all functions in all
standards. Accordingly, in many situations, unique start
control tokens must be created which are compatible not only
with the values contained in the values of the encoded signal
standard image, but which are also capable of controlling the
various stages to emulate the operation of the standard as
represented by specified parameters for each standard which
are well known in the art. Al-l such stAn~Ards are
incorporated by reference into this specification.
It is important to understand the relationship between
tokens which, alone or in combination with other control
tokens, emulate the nondata information contained in the
standard bit stream. A separate set of index signals,
including flag signals, are generated by each state machine
to handle some of the processing within that state machine.
Values carried in the standards can be used to access machine
dependent control signals to emulate the handling of the
standard data and non-data signals. For example, the
slice_start token is a two word token, and it is then entered
onto the two wire interface as previously described.
The data input to the system of the present invention
may be a data source from any suitable data source such as
disk, tape, etc., the data source providing 8 bit data to the
first functional stage in the Spatial Decoder, the Start Code
Detector 51 (Figure 11). The Start Code Detector includes
three shift registers; the first shift register is 8 bits
wide, the next is 24 bits wide, and the next is 15 bits wide.
Each of the registers is part of the two-wire interface. The
data from the data source is loaded into the first register
as a single 8 bit byte during one timing cycle. Thereafter,
the contents of the first shift register is shifted one bit
at a time into the decode (second) shift register. After 24
cycles, the 24 bit register is full.
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120
Every 8 cycles, the 8 bit bytes are loaded into the
fir~t shift regi~ter. Each byte is loaded into the value
shift register 221 (Figure 20), and 8 additional cycles are
used to empty it ~nd load the shift register 231. Eight
cycles are used to empty it, so after three of those
operations or 24 cycles, there are still three bytes in the
24 bit register. The value decode shift register 230 is
still empty.
Assuming that there is now a PIeTURE_START word in the
24 bit shift register, the detect cycle recognizes the
PICTURE START code pattern and provides a start signal as its
output. Once the detector has detected a start, the byte
following it is the value associated with that start code,
and this is currently sitting in the value register 221.
Since the contents of the detect shift register has been
identified as a start code, its contents must be removed from
the two wire interface to ensure that no further processing
takes place using these 3 bytes. The decode register is
emptied, and the value decode shift register 230 waits for
the value to be shifted all the way over to such register.
The contents now of the low order bit positions of the
value decode shift register contains a value associated with
the PICTURE_START. The Spatial Decoder equivalent to the
standard PICTURE_START signal is referred to as the SD
PICTURE_START signal. The SD PICTURE_START signal itself is
going to now be contained in the token header, and the value
is going to be contained in the extension word to the token
header.
lo. TO~N8
In the practice of the present invention, a token is a
universal adaptation unit in the form of an interactive
interfacing messenger package for control and/or data
functions and is adapted for use with a reconfigurable
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121
processLng stage (RPS) which is a stage, which in response to
a recognized token, reconfigures itself to perform various
operations.
Tokens may be either position dependent or position
independent upon the processing stages for performance of
various functions. Tokens may also be metamorphic in that
they can be altered by a processing stage and then passed
down the pipeline for performance of further functions.
Tokens may interact with all or less than all of the stages
lo and in this regard may interact with adjacent and/or non-
adjacent stages. Tokens may be position dependent for some
functions and position independent for other functions, and
the specific interaction with a stage may be conditioned by
the previous processing history of a stage.
A PICTURE_END token is a way of signalling the end of a
picture in a multi-standard decoder.
A multi-standard token is a way of mapping MPEG, JPEG
and H.261 data streams onto a single decoder using a mixture
of standard dependent and standard independent hardware and
control tokens.
A SEARCH_MODE token is a technique for searching MPEG,
JPEG and H.261 data streams which allows random access and
enhanced error recovery.
. A STOP_AFTER_PICTURE token is a method of achieving a
2~ clear end to decoding which signals the end of a picture and
clears the decoder pipeline, i.e., channel change.
Furthermore, padding a token is a way of passing an
arbitrary number of bits through a fixed size, fixed width
buffer.
.0 The present invention is directed to a pipeline
processing system which has a variable configuration which
uses tokens and a two-wire system. The use of control tokens
and DATA Tokens in combination with a two-wire system
facilitates a multi-standard system capable of having
`- 21~542g
122
extended operating capabilities as compared with those
systems which do not use control tokens.
The control tokens are generated by circuitry within the
decoder processor and emulate the operation of a number of
different type standard-dependent signals passing into the
serial pipeline processor for handling. The technique used
is to study all the parameters of the multi-standards that
are selected for processing by the serial processor and
noting 1) their similarities, 2) their dissimilarities, 3)
lo their needs and requirements and 4) selecting the correct
token function to effectively process all of the standard
signals sent into the serial processor. The functions of the
tokens are to emulate the standards. A control token
function is used partially as an emulation/translation
between the standard dependent signals and as an element to
transmit control information through the pipeline processor.
In prior art system, a dedicated machine is designed
according to well-known techniques to identify the standard
and then set up dedicated circuitry by way of microprocessor
interfaces. Signals from the microprocessor are used to
control the flow of data through the dedicated downstream
components. The selection, timing and organization of this
decompression function is under the control of fixed logic
circuitry as assisted by signals coming from the
2~ microprocessor.
In contrast, the system of the present invention
configures the downstream functional stages under the control
of the control tokens. An option is provided for obtaining
needed and/or alternative control from the MPU.
The tokens provide and make a sensible format for
communicating information through the decompression circuit
pipeline processor. In the design selected hereinafter and
used in the preferred embodiment, each word of a token lS a
mini~um of 8 bits wide, and a single token can extend over
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123
one or more words. The width of the token is changeable and
can be selected as any number of bits. An extension bit
indicates whether a token is extended beyond the current
word, i.e., if it is set to binary one in all words of a
token, except the last word of a token. If the first word of
a token has an extension bit of zero, this indicates that the
token is only one word long.
Each token is identified by an address field that starts
at bit 7 of the first word of the token. The address field
is variable in length and can potentially extend over
multiple words. In a preferred embodiment, the address is no
longer than 8 bits long. However, this is not a limitation
on the invention, but on the magnitude of the processing
steps elected to be accomplished by use of these tokens. It
is to be noted under the extension bit identification label
that the extension bit in words 1 and 2 is a 1, signifying
that additional words will be coming thereafter. The
extension bit in word 3 is a zero, therefore indicating the
end of that token.
The token is also capable of variable bit length. For
example, there are 9 bits in the token word plus the
extension bit for a total of 10 bits. In the design of the
present invention, output buses are of variable width. The
output from the Spatial Decoder is 9 bits wide, or 10 bits
2~ wide when the extension bit is included. In a preferred
embodiment, the only token that takes advantage of these
extra bits is the DATA token; all other tokens ignore this
extra bit. It should be understood that this is not a
limitation, but only an implementation.
Through the use of the DATA token and control token
configuration, it is possible to vary the length of the data
being carried by these DATA tokens in the sense of the number
of bits in one word. For example, it has been discussed that
data bits in word of a DATA Token can be combined with the
``-- 21~5424
124
data bits in another word of the same DATA token to form an
11 bit or 10 bit address for use in accessing the random
access memories used throughout this serial decompression
processor. This provides an additional degree of variability
that facilitates a broad range of versatility.
As previously described, the DATA token carries data
from one processing stage to the next. Consequently, the
characteristics of this token change as it passes through the
decoder. For example, at the input to the Spatial Decoder,
DATA Tokens carry bit serial coded video data packed into 8
bit words. Here, there is no limit to the length of each
token. However, to illustrate the versatility of this aspect
of the invention (at the output of the Spatial Decoder
circuit), each DATA Token carries exactly 64 words and each
word is 9 bits wide. More specifically, the standard
encoding signal allows for different length messages to
encode different intensities and details of pictures. The
first picture of a group normally carries the longest number
of data bits because it needs to provide the most information
to the processing unit so that it can start the decompression
with as much information as possible. Words which follow
later are typically shorter in length because they contain
the difference signals comparing the first word with
reference to the second position on the scan information
2~ field.
The words are interspersed with each other, as required
by the standard encoding system, so that variable amounts of
data are provided into the input of the Spatial Decoder.
However, after the Spatial Decoder has functioned, the
information is provided at its output at a picture format
rate suitable for display on a screen. The output rate in
terms of time of the spatial decoder may vary in order tO
interface with various display systems throughout the world,
such as NTSC, PAL and SECAM. The video formatter converts
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125
thi~ variable picture rate to a constant picture rate
suitable for display. However, the picture data is still
carried by DATA tokens consisting of 64 words.
11. DRAN INTERFac~
A single high performance, configurable DRAM interface
is used on each of the 3 decoder chips. In general, the DRAM
interface on each chip is substantially the same; however,
the interfaces differ from one to another in how they handle
channel priorities. This interface is designed to directly
drive the external DRAMs used by the Spatial Decoder, the
Temporal Decoder and the Video Formatter. Typically, no
external logic, buffers or components will be required to
connect the DRAM interface to the DRAMs in those systems.
In accordance with the present invention, the interface is
configurable in two ways:
1. The detailed timing of the interface can be
configured to accommodate a variety of different
DRAM types.
2. The width of the data interface to the DRAM can
be configured to provide a cost/performance trade
off for different applications.
In general, the DRAM interface is a standard-independent
block implemented on each of the three chips in the system.
Again, these are the Spatial Decoder, Temporal Decoder and
video formatter. Referring again to Figures 11, 12 and 13,
these figures show block diagrams that depict the
relationship between the DRAM interface, and the remaining
blocks of the Spatial Decoder, Temporal Decoder and video
formatter, respectively. On each chip, the DRAM interface
connects the chip to an external DRAM. External DRAM is used
because, at present, it is not practical to fabricate on chip
the relatively large amount of DRAM needed. Note: each chip
has its own external DRAM and its own DRAM interface.
21~42~
126
Furthermore, while the DRAM interface is compression
standard-independent, it still must be configured to
implement each of the multiple standards, H.261, JPEG and
~PEG. How the DRAM interface is reconfigured for multi-
s standard operation will be subsequently further describedherein.
Accordingly, to understand the operation of the DRAM
interface requires an understanding of the relationship
between the DRAM interface and the address generator, and how
the two communicate using the two wire interface.
In general, as its name implies, the address generator
generates the addresses the DRAM interface needs in order to
address the DRAM (e.g., to read from or to write to a
particular address in DRAM). With a two-wire interface,
reading and writing only occurs when the DRAM interface has
both data (from preceding stages in the pipeline), and a
valid address (from address generator). The use of a
separate address generator simplifies the construction of
both the address generator and the DRAM interface, as
discussed further below.
In the present invention, the DRAM interface can operate
from a clock which is asynchronous to both the address
generator and to the clocks of the stages through which data
is passed. Special techniques have been used to handle this
asynchronous nature of the operation.
Data is typically transferred between the DRAM interface
and the rest of the chip in blocks of 64 bytes (the only
exception being prediction data in the Temporal Decoder).
Transfers take place by means of a device known as a "swing
~o buffer~. This is essentially a pair of RAMs operated in a
double-buffered configuration, with the DRAM interface
filling or emptying one RAM while another part of the chip
empties or fills the other RAM. A separate bus which carries
an address from an address generator is associated with each
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swing buffer.
In the present invention, each of the chips has four swing
buffers, but the function of these swing buffers is different
in each case. In the ~patial decoder, one swing buffer is
used to transfer coded data to the DRAM, another to read
coded data from the DRAM, the third to transfer tokenized
data to the DRAM and the fourth to read tokenized data from
the DRAM. In the Temporal Decoder, however, one swing buffer
is used to write intra or predicted picture data to the DRAM,
the second to read intra or predicted data from the DRAM and
the other two are used to read forward and backward
prediction data. In the video formatter, one swing buffer is
used to transfer data to the DRAM and the other three are
used to read data from the DRAM, one for each of luminance
(Y) and the red and blue color difference data (Cr and Cb,
respectively).
The following section describes the operation of a
hypothetical DRAM interface which has one write swing buffer
and one read swing buffer. Essentially, this is the same as
the operation of the Spatial Decoder's DRAM interface. The
operation is illustrated in Figure 23.
Figure 23 illustrates that the control interfaces
between the address generator 301, the DRAM interface 302,
and the remaining stages of the chip which pass data are all
two wire interfaces. The address generator 301 may either
generate addresses as the result of receiving control tokens,
or it may merely generate a fixed sequence of addresses
(e.g., for the FIF0 buffers of the Spatial Decoder). The
DRAM interface treats the two wire interfaces associated with
the address generator 301 in a special way. Instead of
keeping the accept line high when it is ready to receive an
address, it waits for the address generator to supply a valid
address, processes that address and then sets the accept line
high for one clock period. Thus, it implements a
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request/acknowledge (REQ/ACX) protocol.
A unique feature of the DRAM interface 302 is its
ability to communicate independently with the address
generator 301 and with the stages that provide or accept the
data. For example, the address generator may generate an
address associated with the data in the write swing buffer
(Figure 24), but no action will be taken until the write
swing buffer signals that there is a block of data ready to
be written to the external DRAM. Similarly, the write swing
buffer may contain a block of data which is ready to be
written to the external DRAM, but no action is taken until an
address is supplied on the appropriate bus from the address
generator 301. Further, once one of the RAMs in the write
swing buffer has been filled with data, the other may be
completely filled and "swung" to the DRAM interface side
before the data input is stalled (the two-wire interface
accept signal set low).
In understanding the operation of the DRAM interface 302
of the present invention, it is important to note that in a
properly configured system, the DRAM interface will be able
to transfer data between the swing buffers and the external
DRAM 303 at least as fast as the sum of all the average data
rates between the swing buffers and the rest of the chip.
Each DRAM interface 302 determines which swing buffer it
will service next. In general, this will either be a "round
robin" (i.e., the next serviced swing buffer is the next
available swing buffer which has least recently had a turn),
or a priority encoder, (i.e., in which some swing buffers
have a higher priority than others). In both cases, an
additional request will come from a refresh request generator
which has a higher priority than all the other requests. The
refresh request is generated from a refresh counter which can
be programmed via the microprocessor interface.
Referring now to Figure 24, there is shown a block
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129
diagram of a write swing buffer. The write swing buffer
interface includes two blocks of RAM, RAMl 311 and RAM2 312.
As discussed further herein, data iB written into RAM1 311
and RAM2 312 from the previous stage, under the control of
the write address 313 and control 314. From RAMl 311 and
RAM2 312, the data is written into DRAM 515. When writing
data into DRAM 315, the DRAM row address is provided by the
address generator, and the column address is provided by the
write address and control, as described further herein. In
operation, valid data is presented at the input 316 (data
in). Typically, the data is received from the previous
stage. As each piece of data is accepted by the DRAM
interface, it is written into RAMl 311 and the write address
control increments the RAM1 address to allow the next piece
of data to be written into RAM1. Data continues to be
written into RAM1 311 until either there is no more data, or
RAMl is full. When RAM1 311 is full, the input side gives up
control and sends a signal to the read side to indicate that
RAMl is now ready to be read. This signal passes between two
asynchronous clock regimes and, therefore, passes through
three synchronizing flip flops.
Provided RAM2 312 is empty, the next item of data to
arrive on the input side is written into RAM2. Otherwise,
this occurs when RAM2 312 has emptied. When the round robin
or priority encoder (depending on which is used by the
particular chip) indicates that it is now the turn of this
swing buffer to be read, the DRAM interface reads the
contents of RAM1 311 and writes them to the external DRAM
315. A signal is then sent back across the asynchronous
interface, to indicate that RAM1 311 is now ready to be
filled again.
If the DRAM interface empties RAM1 311 and "swings" it
before the input side has filled RAM2 312 , then data can be
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accep~ed by the swing buffer sontinually. Otherwise, when
RAM2 is filled, the swing buffer will set its accept single
low until RAMl has been "swung" back for use by the input
side.
The operation of a read swing buffer, in accordance with
the present invention, is similar, but with the input and
output data busses reversed.
The DRAM interface of the present invention is designed
to maximize the available memory bandwidth. Each 8x8 block
of data is stored in the same DRAM page. In this way, full
use can be made of DRAM fast page access modes, where one row
address is supplied followed by many column addresses. In
particular, row addresses are supplied by the address
generator, while column addresses are supplied by the DRAM
interface, as discussed further below.
In addition, the facility is provided to allow the data
bus to the external DRAM to be 8, 16 or 32 bits wide.
Accordingly, the amount of DRAM used can be matched to the
size and bandwidth requirements of the particular
application.
In this example (which is exactly how the DRAM interface
on the Spatial Decoder works) the address generator provides
the DRAM interface with block addresses for each of the read
and write swing buffers. This address is used as the row
address for the DRAM. The six bits of column address are
supplied by the DRAM interface itself, and these bits are
also used as the address for the swing buffer RAM. The data
bus to the swing buffers is 32 bits wide. Hence, if the bus
width to the external DRAM is less than 32 bits, two or four
~O external DRAM accesses must be made before the next word is
read from a write swing buffer or the next word is written to
a read swing buffer (read and write refer to the direction of
transfer relative to the external DRAM).
The situation is more complex in the case of the
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Temporal ~co~r and the Video Formatter. The Temporal
D~ r ' ~ addressing i8 more complex becau~e of its
predictive aspects as discussed further in this section. The
video formatter's addressing is more complex because of
multiple video output stA~A~rd aspects, as discussed further
in the sections relating to the video formatter.
As mentioned previously, the Temporal Decoder has four
swing buffers: two are used to read and write decoded intra
and predicted (I and P) picture data. These operate as
described above. The other two are used to receive
prediction data. These buffers are more interesting.
In general, prediction data will be offset from the
position of the block being processed as specified in the
motion vectors in x and y. Thus, the block of data to be
retrieved will not generally correspond to the block
boundaries of the data as it was encoded (and written into
the DRAM). This is illustrated in Figure 25, where the
shaded area represents the block that is being formed whereas
the dotted outline represents the block from which it is
being predicted. The address generator converts the address
specified by the motion vectors to a block offset (a whole
number of blocks), as shown by the big arrow, and a pixel
offset, as shown by the little arrow.
In the address generator, the frame pointer, base block
address and vector offset are added to form the address of
the block to be retrieved from the DRAM. If the pixel offset
is zero, only one request is generated. If there is an
offset in either the x or y dimension then two requests are
generated, i.e., the original block address and the one
immediately below. With an offset in both x and y, four
requests are generated. For each block which is to be
retrieved, the address generator calculates start and stop
addresses which is best illustrated by an example.
Consider a pixel offset of (1,1), as illustrated by the
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132
shaded area in Figure 26. The address generator makes four
requests, labelled A through D in the Figure. The problem to
be solved is how to provide the required sequence of row
addresses quickly. The solution is to use "start/stop"
technology, and this is described below.
Consider block A in Figure 26. Reading must start at
position (1,1) and end at position (7,73. Assume for the
moment that one byte is being read at a time (i.e., an 8 bit
DRAM interface). The x value in the-co-ordinate pair forms
the three LSBs of the address, the y value the three MSB.
The x and y start values are both 1, providing the address,
9. Data is read from this address and the x value is
incremented. The process is repeated until the x value
reaches its stop value, at which point, the y value is
incremented by 1 and the x start value is reloaded, giving an
address of 17. As each byte of data is read, the x value is
again incremented until it reaches its stop value. The
process is repeated until both x and y values have reached
their stop values. Thus, the address sequence of 9, 10, 11,
12, 13, 14, 15, 17... , 23, 25, ... ,31, 33,... ,... ,57,... ,63
is generated.
In a similar manner, the start and stop co-ordinates for
block B are: (1,0) and (7,0), for block C: (0,1) and (0,7),
and for block P: (0,0) and (0,0).
The next issue is where this data should be written.
Clearly, looking at block A, the data read from address 9
should be written to address 0 in the swing buffer, while the
data from address 10 should be written to address 1 in the
swing buffer, and so on. Similarly, the data read from
address 8 in block B should be written to address 15 in the
swing buffer and the data from address 16 should be written
to address 15 in the swing buffer. This function turns out
to have a very simple implementation, as outlined below.
Consider block A. At the start of reading, the swing
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buffer address register is loaded with the inverse of the
stop value. The y inver6e stop value forms the 3 MSBs and
the x inverse ~top value forms the 3 LSB. In this case,
while the DRAM interface is reading address 9 in the external
DRAM, the swing buffer address is zero. The swing buffer
address register is then incremented as the external DRAM
address register is incremented, as consistent with proper
prediction addressing.
The discucsion so far has centered on an 8 bit DRAM
interface. In the case of a 16 or 32 bit interface, a few
minor modifications must be made. First, the pixel offset
vector must be "clipped" so that it points to a 16 or 32 bit
boundary. In the example we have been using, for block A,
the first DRAM read will point to address 0, and data in
addresses 0 through 3 will be read. Second, the unwanted
data must be discarded. This is performed by writing all the
data into the swing buffer (which must now be physically
larger than was necessary in the 8 bit case) and reading with
an offset. When performing MPEG half-pel interpolation, 9
bytes in x andtor y must be read from the DRAM interface. In
this case, the address generator provides the appropriate
start and stop addresses. Some additional logic in the DRAM
interface is used, but there is no fundamental change in the
way the DRAM interface operates.
The final point to note about the Temporal Decoder DRAM
interface of the present invention, is that additional
information must be provided to the prediction filters to
indicate what processing is required on the data. This
consists of the following:
a "last byte" signal indicating the last byte of a
transfer (of 64,72 or 81 bytes);
an H.261 flag;
a bidirectional prediction flag;
two bits to indicate the block~s dimensions (8 or 9 bytes
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in x and y); and
a two bit number to indicate the order of the blocks.
The last byte flag can be generated as the data is read
out of the swing buffer. The other signals are derived from
the address generator and are piped through the DRAM
interface so that they are associated with the correct block
of data as it is read out of the swing buffer by the
prediction filter block.
In the Video Formatter, data is written into the
external DRAM in blocks, but is read out in raster order.
Writing is exactly the same as already described for the
Spatial Decoder, but reading is a little more complex.
The data in the Video Formatter, external DRAM is
organized so that at least 8 blocks of data fit into a single
page. These 8 blocks are 8 consecutive horizontal blocks.
When rasterizing, 8 bytes need to be read out of each of 8
consecutive blocks and written into the swing buffer (i.e.,
the same row in each of the 8 blocks).
Considering the top row (and assuming a byte-wide
interface), the x address (the three LSBS) is set to zero, as
is the y address (3 MSBS). The x address is then incremented
as each of the first 8 bytes are read out. At this point,
the top part of the address (bit 6 and above - LSB = bit 0)
is incremented and the x address (3 LSBS) is reset to zero.
This process is repeated until 64 bytes have been read. With
a 16 or 32 bit wide interface to the external DRAM the x
address is merely incremented by two or four, respectively,
instead of by one.
In the present invention, the address generator can
signal to the DRAM interface that less than 64 bytes should
be read (this may be required at the beginning or end of a
raster line), although a multiple of 8 bytes is always read.
~his is achieved by using start and stop values. The start
value is used for the top part of the address (bit 6 and
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135
above), and the stop value is compared with the start value
to generate the signal which indicates when reading should
stop.
The DRAM interface timing block in the present invention
uses timing chains to place the edges of the DRAM signals to
a precision of a quarter of the ~ystem clock period. Two
quadrature clocks from the phase locked loop are used. These
are combined to form a notional 2x clock. Any one chain is
then made from two shift registers in parallel, on opposite
phases of the 2x clock.
First of all, there is one chain for the page start
cycle and another for the read/write/refresh cycles. The
length of each cycle is programmable via the microprocessor
interface, after which the page start chain has a fixed
length, and the cycle chain's length changes as appropriate
during a page start.
On reset, the chains are cleared and a pulse is created.
The pulse travels along the chains and is directed by the
state information from the DRAM interface. The pulse
generates the DRAM interface clock. Each DRAM interface
clock period corresponds to one cycle of the DRAM,
consequently, as the DRAM cycles have different lengths, the
DRAM interface clock is not at a constant rate.
Moreover, additional timing chains combine the pulse
from the above chains with the information from the DRAM
interface to generate the output strobes and enables such as
notcas, notras, notwe, notbe.
12. PREDICTION FILTER8
Referring again to Figures 12, 17, 18, and more
particularly to Figure 12, there is shown a block diagram of
the Temporal Decoder. This includes the prediction filter.
The relationship between the prediction filter and the rest
of the elements of the temporal decoder is shown in greater
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detail in Figure 17. The essence of the structure of the
prediction filter is shown in Figures 18 and 28. A detailed
description of the operation of the prediction filter can be
found in the section, "More Detailed Description of the
Invention. n
In general, the prediction filter in accordance with the
present invention, is used in the MPEG and H.261 modes, but
not in the JPEG mode. Recall that in the JPEG mode, the
Temporal Decoder just passes the data through to the Video
Formatter, without performing any substantive decoding beyond
that accomplished by the Spatial Decoder. Referring again to
Figure 18, in the MPEG mode the forward and backward
prediction filters are identical and they filter the
respective MPEG forward and backward prediction blocks. In
the H.261 mode, however, only the forward prediction filter
is used, since H.261 does not use backward prediction.
Each of the two prediction filters of the present
invention is substantially the same. Referring again to
Figures 18 and 28 and more particularly to Figure 28, there
is shown a block diagram of the structure of a prediction
filter. Each prediction filter consists of four stages in
series. Data enters the format stage 331 and is placed in a
format that can be readily filtered. In the next stage 332
an I-D prediction is performed on the X-coordinate. After
the necessary transposition is performed by a dimension
buffer stage 333, an I-D prediction is performed on the Y-
coordinate in stage 334. How the stage perform the filtering
is further described in greater detail subsequently. Which
filtering operations are required, are defined by the
compression standard. In the case of H.261, the actual
filtering performed is similar to that of a low pass filter.
Referring again to Figure 17, multi-standard
operation requires that the prediction filters be
reconfigurable to perform either MPEG or H.261 filtering, or
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137
to perforo no filtering at all in JPEG mode. As with many
other reconfigurable aspects of the three chip system, the
prediction filter is reconfigured by means of tokens. Tokens
are also used to inform the address generator of the
particular mode of operation. In this way, the address
generator can supply the prediction filter with the addresses
of the needed data, which varies significantly between MPEG
and JPEG.
13. ~ eIN~ REGI8TER8
Most registers in the microprocessor interface (MPI) can
only be modified if the stage with which they are
associated is stopped. Accordingly, groups of registers
will typically be associated with an access register. The
value zero in an access register indicates that the group
of registers associated with that particular access
register should not be modified. Writing 1 to an access
register requests that a stage be stopped. The stage may
not stop immediately, however, so the stages access
register will hold the value, zero, until it is stopped.
Any user software associated with the MPI and used to
perform functions by way of the MPI should wait "after
writing a 1 to a request access register" until 1 is read
from the access register. If a user writes a value to a
configuration register while its access register is set to
zero, the results are undefined.
14. MICRO-PROCEB80R INTERFACE
A standard byte wide micro-processor interface (MPI) is
used on all circuits with in the Spatial Decoder and
Temporal Decoder. The MPI operates asynchronously with
various Spatial and Temporal Decoder clocks. Referring to
Table A.6.1 of the subsequent further detailed description,
there is shown the various MPI signals that
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are used on this interface. The character of the signal is
shown on the input/output column, the signal name i8 shown
on the signal name column and a description of the function
of the signal iB shown in the description column. The MPI
electrical specification are shown with reference to Table
A.6.2. All the specifications are classified according to
type and there types are shown in the column entitled
symbol. The description of what these symbols represent is
shown in the parameter column. The actual specifications
are shown in the respective columns min, max and units.
The DC operating conditions can be seen with reference
to Table A.6.3. Here the column headings are the same as
with reference to Table A.6.2. The DC electrical
characteristics are shown with reference to Table A.6.4 and
carry the same column headings as depicted in Tables A.6.2
and A.6.3.
15. MPI R~AD TIMING
The AC characteristics of the MPI read timing diagrams
are shown with reference to Figure 54. Each line of the
Figure is labelled with a corresponding signal name and the
timing is given in nano-seconds. The full microprocessor
interface read timing characteristics are shown with
reference to Table A.6.5. The column entitled Number is
used to indicate the signal corresponding to the name of
that signal as set forth in the characteristic column. The
columns identified by MIN and MAX provide the minimum
length of time that the signal is present the maximum
amount of time that this signal is available. The Units
column gives the units of measurement used to describe the
signals.
16 . MPI ~IRIT~3 TIMING
The general description of the MPI write timing diagrams
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139
are shown with reference to Figure 54. This Figure shows
each individual signal name a~ associated with the MPI
write timing. The name, the characteristic of the signal,
and other various physical characteristics are shown with
reference to Table 6.6.
17. ~-~OL~ A~nr~r LOCATION8
In the present invention, certain less frequently
accessed memory map locations have been placed behind
keyhole registers. A keyhole register has two registers
associated with it. The first register is a keyhole
address register and the second register is a keyhole data
register. The keyhole address specifies a location within
a extended address space. A read or a write operation to a
keyhole data register accesses the locations specified by
the keyhole address register. After accessing a keyhole
data register, the associated keyhole address register
increments. Random access within the extended address
space is only possible by writing in a new value to the
keyhole address register for each access. A circuit within
the present invention may have more than one keyhole memory
maps. Nonetheless, there is no interaction between the
different keyholes.
18. PICTUR~-~ND
Referring again to Figure 11, there is shown a
general block diagram of the Spatial Decoder used in the
present invention. It is through the use of this block
diagram that the function of PICTURE_END will be described.
The PICTURE_END function has the multi-standard advantage
of being able to handle H.261 encoded picture information,
MPEG and JPEG signals.
As previously described, the system of Figure 11
is interconnected by the two wire interface previously
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140
described. Each of the functional block~ is arranged to
operate according to the state machine configuration shown
with reference to Figure 10.
In general, the PICTURE_END function in accordance with
the invention begins at the Start Code Detector which
generates a PICTURE_END control token. The PICTURE_END
control token is passed unaltered through the start-up
control circuit to the DRAM interface. Here it is used to
flush out the write swing buffers in the DRAM interface.
Recall, that the contents of a swing buffer are only
written to RAM when the buffer is full. However, a picture
may end at a point where the buffer is not full, therefore,
causing the picture data to become stuck. The PICTURE_END
token forces the data out of the swing buffer.
Since the present invention is a multi-standard machine,
the machine operates differently for each compression
standard. More particularly, the machine is fully
described as operating pursuant to machine-dependent action
cycles. For each compression standard, a certain number of
the total available action cycles can be selected by a
combination of control tokens and/or output signals from
the MPU or they can be selected by the design of the
control tokens themselves. In this regard, the present
invention is organized so as to delay the information from
going into subsequent blocks until all of the information
has been collected in an upstream block. The system waits
until the data has been prepared for passing to the next
stage. In this way, the PICTURE_END signal is applied to
the coded data buffer, and the control portion of the
PICTURE_END signal causes the contents of the data buffers
to be read and applied to the Huffman decoder and video
demultiplexor circuit.
Another advantage of the PICTURE END control token is
to identify, for the use by the Huffman decoder
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141
demultiDlexor, the end of picture even though it has not
had the typically expected full range andtor number of
signals applied to the Huffman decoder and video
demultiplexor circuit. In this situation, the information
held in the coded data buffer is applied to the Huffman
decoder and video demultiplexor as a total picture. In
this way, the state machine of the Huffman decoder and
video demultiplexor can still handle the data according to
system design.
Another advantage of the PICTURE_END control token is
its ability to completely empty the coded data buffer so
that no stray information will inadvertently remain in the
off chip DRAM or in the swing buffers.
Yet another advantage of the PICTURE_END function is
its use in error recovery. For example, assume the amount
of data being held in the coded data buffer is less than is
typically used for describing the spatial information with
reference to a single picture. Accordingly, the last
picture will be held in the data buffer until a full swing
buffer, but, by definition, the buffer will never fill. At
some point, the machine will determine that an error
condition exits. Hence, to the extent that a PICTURE_END
token is decoded and forces the data in the coded data
buffers to be applied to the Huffman decoder and video
demultiplexor, the final picture can be decoded and the
information emptied from the buffers. Consequently, the
machine will not go into error recovery mode and will
successfully continue to process the coded data.
A still further advantage of the use of a PICTURE_ END
token is that the serial pipeline processor will continue
the processing of uninterrupted data. Through the use of a
PICTURE END token, the serial pipeline processor is
configured to handle less than the expected amount of data
and, therefore, continues processing. Typically, a prior
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142
art machine would stop it~elf because of an error
condition. As previously described, the coded data buffer
counts macroblocks as they come into its storage area. In
addition, the Huffman Decoder and Video Demultiplexor
generally know the amount of information expected for
decoding each picture, i.e., the state machine portion of
the Huffman decode and Video Demultiplexor know the number
of blocks that it will process during each picture recovery
cycle. When the correct number of blocks do not arrive
from the coded data buffer, typically an error recovery
routine would result. However, with the PICTURE END
control token having reconfigured the Huffman Decoder and
Video Demultiplexor, it can continue to function because
the reconfiguration tells the Huffman Decoder and Video
Demultiplexor that it is, indeed, handling the proper
amount of information.
Referring again to Figure 10, the Token Decoder
portion of the Buffer Manager detects the PICTURE_END
control token generated by the Start Code Detector. Under
normal operations, the buffer registers fill up and are
emptied, as previously described with reference to the
normal operation of the swing buffers. Again, a swing
buffer which is partially full of data will not empty until
it is totally filled and/or it knows that it is time to
empty. The PICTURE_END control token is decoded in the
Token Decoder portion of the Buffer Manager, and it forces
the partially full swing buffer to empty itself into the
coded data buffer. This is ultimately passed to the
Huffman Decoder and Video Demultiplexor either directly or
through the DRAM interface.
19. FLU8~ING OPERATION
Another advantage of the PICTURE END control token is
its function in connection with a FLUSH token. The FLUSH
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143
token is not associated with either controlling the
reconfiguration of the state machine or in providing data
for the system. Rather, it completea prior partial signals
for handling by the machine-dependent state machines. Each
S of the state machines recognizes a FLUSH control token as
information not to be processed. Accordingly, the FLUSH
token is used to fill up all of the remaining empty parts
of the coded data buffers and to allow a full set of
information to be sent to the Huffman Decoder and Video
Demultiplexor. In this way, the FLUSH token is like
padding for buffers.
The Token Decoder in the Huffman circuit recognizes
the FLUSH token and ignores the pseudo data that the FLUSH
token has forced into it. The Huffman Decoder then operates
only on the data contents of the last picture buffer as it
existed prior to the arrival of the PICTURE END token and
FLUSH token. A further advantage of the use of the
PICTURE END token alone or in combination with a FLUSH
token is the reconfiguration and/or reorganization of the
Huffman Decoder circuit. With the arrival of the
PICTURE END token, the Huffman Decoder circuit knows that
it will have less information than normally expected to
decode the last picture. The Huffman decode circuit
finishes processing the information contained in the last
picture, and outputs this information through the DRAM
interface into the Inverse Modeller. Upon the
identification of the last picture, the Huffman Decoder
goes into its cleanup mode and readjusts for the arrival of
the next picture information.
20. FLU8H FUNCTION
The FLUSH token, in accordance with the present
invention, is used to pass through the entire pipeline
processor and to ensure that the buffers are emptied and
that other circuits are reconfigured to await the arrival
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of new data. More specifically, the precent invention
comprises a combination of a PICTURE_END token, a padding
word and a FLUSH token indicating to the serial pipeline
processor that the picture processing for the current
picture form is completed. Thereafter, the various state
machines need reconfiguring to await the arrival of new
data for new handling. Note also that the FLUSH Token acts
as a special reset for the system. The FLUSH token resets
each stage as it passes through, but-allows subsequent
stages to continue processing. This prevents a loss of
data. In other words, the FLUSH token is a variable reset,
as opposed to, an absolute reset.
2l. 8TOP-AFTER PICT~RE
The STOP_AFTER PICTURE function is employed to shut
down the processing of the serial pipeline decompressing
circuit at a logical point in its operation. At this
point, a PICTURE END token is generated indicating that
data is finished coming in from the data input line, and
the padding operation has been completed. The padding
function fills partially empty DATA tokens. A FLUSH token
is then generated which passes through the serial pipeline
system and pushes all the information out of the registers
and forces the registers back into their neutral stand-by
condition. The STOP_AFTER_PICTURE event is then generated
and no more input is accepted until either the user or the
system clears this state. In other words, while a
PICTURE_END token signals the end of a picture, the
STOP_AFTER PICTURE operation signals the end of all current
processing.
3 0 2 2 . MtJLTI -8TANDARD - 8EARCH ~IOD~3
Another feature of the present invention is the use of
a SEARCH_MODE control token which is used to reconfigure
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the input to the serial pipeline processor to look at the
incoming bit stream. When the search mode is set, the
Start Code Detector searches only for a specific start code
or marker used in any one of the compression standards. It
S will be appreciated, however, that, other images from other
data bitstreams can be used for this purpose. Accordingly,
these images can be used throughout this present invention
to change it to another embodiment which is capable of
using the combination of control tokens, and DATA tokens
along with the reconfiguration circuits, to provide similar
processing.
The use of search mode in the present invention is
convenient in many situations including 1) if a break in
the data bit stream occurs; 2) when the user breaks the
data bit stream by purposely changing channels, e.g., data
arriving, by a cable carrying compressed digital video, or
3) by user activation of fast forward or reverse from a
controllable data source such as an optical disc or video
disc. In general, a search mode is convenient when the
user interrupts the normal processing of the serial
pipeline at a point where the machine does not expect such
an interruption.
When any of the search modes are set, the Start Code
Detector looks for incoming start images which are suitable
for creating the machine independent tokens. All data
coming into the Start Code Detector prior to the
identification of standard-dependent start images is
discarded as meaningless and the machine stands in an
idling condition as it waits this information.
The Start Code Detector can assume any one of a number
of configurations. For example, one of these
configurations allows a search for a group of pictures or
higher start codes. This pattern causes the Start Code
Detector to discard all its input and look for the
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146
group start stA~rd image. When ~uch an image is
identified, the Start Code Detector generates a GROUP START
token and the search mode is reset automatically.
It is important to note that a single circuit, the
Huffman Decoder and Video Demultiplex circuit, is operating
with a combination of input signals including the standard-
independent set-up signals, as well as, the CODING_STANDARD
signals. The CODING STANDARD signals are conveying
information directly from the incoming bit stream as
required by the Huffman Decoder and Video Demultiplex
circuit. Nevertheless, while the functioning of the
Huffman Decoder and Video Demultiplex circuit is under the
operation of the standard independent sequence of signals.
This mode of operation has been selected because it
is the most efficient and could have been designed wherein
special control tokens are employed for conveying the
standard-dependent input to the Huffman Decoder and Video
Demultiplexer instead of conveying the actual signals
themselves.
23. INVER8E MODELLER
Inverse modeling is a feature of all three standards,
and is the same for all three standards. In general, DATA
tokens in the token buffer contain information about the
values of the quantized coefficients, and about the number
of zeros between the coefficients that are represented (a
form of run length coding). The Inverse Modeller of the
present invention has been adapted for use with tokens and
simply expands the information about runs of zeros so that
each DATA Token contains the requisite 64 values.
Thereafter, the values in the DATA Tokens are quantized
coefficients which can be used by the Inverse Quantizer.
24. INVER8E Q~ANTIZER
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The Inverse Quantizer of the present invention is a
required element in the decoding sequence, but has been
implemented in such away to allow the entire IC set to
handle multi-standard data. In addition, the Inverse
Quantizer has been adapted for use with tokens. The
Inverse Quantizer lies between the Inverse modeller and
inverse DCT (IDCT).
For example, in the present invention, an adder in the
Inverse Quantizer is used to add a constant to the pel
decode number before the data moves on to the IDCT.
The IDCT uses the pel decode number, which will vary
according to each standard used to encode the information.
In order for the information to be properly decoded, a
value of 1024 is added to the decode number by the Inverse
Quantizer before the data continues on to the IDCT.
Using adders, already present in the Inverse
Quantizer, to standardize the data prior to it reaching the
IDCT, eliminates the need for additional circuitry or
software in the IC, for handling data compressed by the
various standards. Other operations allowing for multi-
standard operation are performed during a "post
quantization function" and are discussed below.
The control tokens accompanying the data are decoded
and the various standardization routines that need to be
performed by the Inverse Quantizer are identified in detail
below. These "post quantization" functions are all
implemented to avoid duplicate circuitry and to allow the
IC to handle multi-standard encoded data.
2 5 . nu~llAN DECODER AND PAR8ER
Referring again to Figures 11 and 27, the Spatial
Decoder includes a Huffman Decoder for decoding the data
that the various compression standards have Huffman-
encoded. While each of the standards, JPEG, MPEG and
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H.261, require certain data to be Huffman encoded, the
Huffman decoding required by each 6tA~ d differs in some
significant ways. In the Spatial Decoder of the present
invention, rather than de~ign and fabricate three separate
Huffman decoders, one for each standard, the present
invention saves valuable die space by identifying common
aspects of each Huffman Decoder, and fabricating these
common aspects only once. Moreover, a clever multi-part
algorithm is used that makes common more aspects of each
Huffman Decoder common to the other standards as well than
would otherwise be the case.
In brief, the Huffman Decoder 321 works in
conjunction with the other units shown in Figure 27. These
other units are the Parser State Machine 322, the inshifter
323, the Index to Data unit 324, the ALU 325, and the Token
Formatter 326. As described previously, connection between
these blocks is governed by a two wire interface. A more
detailed description of how these units function is
subsequently described herein in greater detail, the focus
here is on particular aspects of the Huffman Decoder, in
accordance with the present invention, that support multi-
standard operation.
The Parser State Machine of the present invention, is a
programmable state machine that acts to coordinate the
operation of the other blocks of the Video Parser. In
response to data, the Parser State Machine controls the
other system blocks by generating a control word which is
passed to the other blocks, side by side with the data,
upon which this control word acts. Passing the control
word alongside the associated data is not only useful, it
is essential, since these blocks are connected via a two-
wire interface. In this way, both data and control arrive
at the same time. The passing of the control word is
indicated in Figure 27 by a control line 327 that runs
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149
beneath the data line 328 that connects the blocks. Among
other things, this code word identifie~ the particular
standard that is being decoded.
The Huffman decoder 321 also performs certain control
functions. In particular, the Huffman Decoder 321 contains
a state machine that can control certain functions of the
Index to Data 324 and ALU 325. Control of these units by
the Huffman Decoder is necessary for proper decoding of
block-level information. Having the-Parser State Machine
322 make these decisions would take too much time.
An important aspect of the Huffman Decoder of the
present invention, is the ability to invert the coded data
bits as they are read into the Huffman Decoder. This is-
needed to decode H.261 style Huffman codes, since the
particular type of Huffman code used by H.261 (and
substantially by MPEG) has the opposite polarity then the
codes used by JPEG. The use of an inverter, thereby,
allows substantially the same table to be used by the
Huffman Decoder for all three standards. Other aspects of
how the Huffman Decoder implements all three standards are
discussed in further detail in the "More Detailed
Description of the Invention" section.
The Index to Data unit 324 performs the second part of
the multi-part algorithm. This unit contains a look up
table that provides the actual Huffman decoded data.
Entries in the table are organized based on the index
numbers generated by the Huffman Decoder.
The ALU 325 implements the remaining parts of the
multi-part algorithm. In particular, the ALU handles sign-
extension. The ALU also includes a register file whichholds vector predictions and DC predictions, the use of
which is described in the sections related to prediction
filters. The ALU, further, includes counters that count
through the structure of the picture being decoded by the
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Spatial D~roAer. In particular, the dimensions of the
picture are programmed into registers associated with the
counters, which facilitates detection of "start of
picture, n and start of macroblock codes.
In accordance with the present invention, the Token
Formatter 326 (TF) assembles decoded data into DATA tokens
that are then passed onto the remaining stages or blocks in
the Spatial Decoder.
In the present invention, the in shifter 323 receives
data from a FIFO that buffers the data passing throuqh the
Start Code Detector. The data received by the inshifter is
generally of two types: DATA tokens, and start codes which
the Start Code Detector has replaced with their respective
tokens, as discussed further in the token section. Note
that most of the data will be DATA tokens that require
decoding.
The ln shifter 323 serially passes data to the Huffman
Decoder 321. On the other hand, it passes control tokens
in parallel. In the Huffman decoder, the Huffman encoded
data is decoded in accordance with the first part of the
multi-part algorithm. In particular, the particular
Huffman code is identified, and then replaced with an index
number.
The Huffman Decoder 321 also identifies certain data
that requires special handling by the other blocks shown in
Figure 27. This data includes end of block and escape. In
the present invention, time is saved by detecting these in
the Huffman Decoder 321, rather than in the Index to Data
unit 324.
This index number is then passed to the Index to Data
unit 324. In essence, the Index to Data unit is a look-up
table. In accordance with one aspect of the algorithm, the
look-up table is little more than the Huffman code table
specified by JPEG. Generally, it is in the condensed data
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151
format that JPEG specifies for tranæferring an alternate
JPEG table.
From the Index to Data unit 324, the decoded index
number or other data is passed, together with the
accompanying control word, to the ALU 325, which performs
the operations previously described.
From the ALU 325, the data and control word is passed
to the Token Formatter 326 (TF). In the Token Formatter,
the data is combined as needed with the control word to
form tokens. The tokens are then conveyed to the next
stages of the Spatial Decoder. Note that at this point,
there are as many tokens as will be used by the system.
26. INVBR8E DI8CR~TE CO8INE TRAN8FOR~
The Inverse Discrete Cosine Transform (IDCT), in
lS accordance with the present invention, decompresses data
related to the frequency of the DC component of the
picture. When a particular picture is being compressed,
the frequency of the light in the picture is quantized,
reducing the overall amount of information needed to be
stored. The IDCT takes this quantized data and
decompresses it back into frequency information.
The IDCT operates on a portion of the picture which is
8x8 pixels in size. The math which performed on this data
is largely governed by the particular standard used to
encode the data. However, in the present invention,
significant use is made of common mathematical functions
between the standards to avoid unnecessary duplication of
circuitry.
Using a particular scaling order, the symmetry between
the upper and lower portions of the algorithms is
increased, thus common mathematical functions can be reused
which eliminates the need for additional circuitry.
`-- 2145~24
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The I~CT responds to a number of multi-standard tokens.
The first portion of the IDCT checks the entering data to
ensure that the DATA tokens are of the correct size for
processing. In fact, the token stream can be corrected in
some situations if the error is not too large.
27. BUFFER MANAGER
The Buffer Manager of the present invention, receives
incoming video information and supplies the address
generators with information on the timing of the datas
arrival, display and frame rate. Multiple buffers are used
to allow changes in both the presentation and display
rates. Presentation and display rates will typically vary
in accordance with the data that was encoded and the
monitor on which the information is being displayed. Data
lS arrival rates will generally vary according to errors in
encoding, decoding or the source material used to create
the data. When information arrives at the Buffer Manager,
it is decompressed. However, the data is in an order that
is useful for the decompression circuits, but not for the
particular display unit being used. When a block of data
enters the Buffer Manager, the Buffer Manager supplies
information to the address generator so that the block of
data can be placed in the order that the display device can
use. In doing this, the Buffer Manager takes into account
the frame rate conversion necessary to adjust the incoming
data blocks so they are presentable on the particular
display device being used.
In the present invention, the Buffer Mnager primarily
supplies information to the address generators.
Nevertheless~ it is also required to interface with other
elements of the system. For example, there is an interface
with an input FIFO which transfers tokens to the Buffer
Manager which, in turn, passes these tokens on to the write
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address generators.
The Buffer Manager also interfaces with the display
address generators, receiving information on whether the
display device is ready to display new data. The Buffer
Manager also confirms that the display address generators
have cleared information from a buffer for display.
The Buffer Manager of the present invention keeps track
of whether a particular buffer is empty, full, ready for
use or in use. It also keeps track of the presentation
number associated with the particular data in each buffer.
In this way, the Buffer Manager determines the states of
the buffers, in part, by making only one buffer at a time
ready for display. Once a buffer is displayed, the buffer
is in a "vacant" state. When the Buffer Manager receives a
PICTURE_START, FLUSH, valid or access token, it determines
the status of each buffer and its readiness to accept new
data. For example, the PICTURE START token causes the
Buffer Manager to cycle through each buffer to find one
which is capable of accepting the new data.
The Buffer Manager can also be configured to handle the
multi-standard requirements dictated by the tokens it
receives. For example, in the H.261 standard, data maybe
skipped during display. If such a token arrives at the
Buffer Mnager, the data to be skipped will be flushed from
the buffer in which it is stored.
Thus, by managing the buffers, data can be effectively
displayed according to the compression standard used to
encode the data, the rate at which the data is decoded and
the particular type of display device being used.
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154
The foregoing description is believed to
adequately describe the overall concepts, system
implementation and operation of the various aspects of the
invention in sufficient detail to enable one of ordinary
skill in the art to make and practice the invention with
all of its attendant features, objects and advantages.
However, in order to facilitate a further, more detailed in
depth understanding of the invention,- and additional
details in connection with even more specific, commercial
implementation of various embodiments of the invention, the
following further description and explanation is pr~ferred.
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This is a more detailed description for a multi-standard
video decoder chip-set. It is divided into three main
sections: A, B and C.
Again, for purposes of organization, clarity and
convenience of explanation, this additional disclosure is
set forth in the following sections.
Description of features common to chips in the
chip-set:
Tokens
Two wire interfaces
DRAM interface
Microprocessor interface
Clocks
Description of the Spatial Decoder chip
Description of the Temporal Decoder chip
SECIION A.l
The first description section covers the majority of
the electrical design issues associated with using the
chip-set.
A.1.1 ~yo~.aphic conv-ntions
A small set of typographic conventions is used to
emphasize some classes of information:
NAME8_OF_TO~ENB
wire_name active high signal
wire_name active low signal
register_name
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156
SECTI`O~ A.2 Video Decoder Family
30 MHz operation
Decodes MPEG, JPEG & H.261
Coded data rates to 25 Mb/s
Video data rates to 21 MB/s
MPEG resolutions up to 704 x 480, 30 Hz, 4:2:0
Flexible chroma sampling formats
Full JPEG baseline decoding
Glue-less page mode DRAM interface
208 pin PQFP package
Independent coded data and decoder clocks
Re-orders MPEG picture sequence
The Video decoder family provides a low chip count
solution for implementing high resolution digital video
decoders. The chip-set is currently configurable to
support three different video and picture coding systems:
JPEG, MPEG and H.261.
Full JPEG baseline picture decoding is supported.
720 x 480, 30 Hz, 4:2:2 JPEG encoded video can be decoded
in real-time.
CIF (Common Interchange Format) and QCIF H.261 video can
be decoded. Full feature MPEG video with formats up to 740
x 480, 30 Hz, 4:2:0 can be decoded.
Note: The above values are merely illustrative, by way
of example and not necessarily by way of limitation, of one
embodiment of the present invention. Accordingly, it will
be appreciated that other values and/or ranges may be used.
A.2.1 System configurations
A.2.1.1 Output formatting
In each of the examples given below, some form of output
formatter will be required to take the data presented at
the outpu~ of the Spatial Decoder or Temporal Decoder and
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re-format it for a computer or display system. The details
of this formatting will vary between applications. In a
simple case, all that is required is an address generator
to take the block formatted data output by the decoder chip
and write it into memory in a raster order.
The Image Formatter is a single chip VLSI device
providing a wide range of output formatting functions.
A.2.1.2 JPEG still picture decoding
A single Spatial Decoder, with no-off-chip DRAM, can
rapidly decode baseline JPEG images. The Spatial Decoder
will support all features of baseline JPEG. However, the
image size that can be decoded may be limited by the size
of the output buffer provided by the user. The
characteristics of the output formatter may limit the
chroma sampling formats and color spaces that can be
supported.
A.2.1.3 JPEG video decoding
Adding off-chip DRAMs to the Spatial Decoder allows it
to decode JPEG encoded video pictures in real-time. The
size and speed of the required buffers will depend on the
video and coded data rates. The Temporal Decoder is not
required to decode JPEG encoded video. However, if a
Temporal Decoder is present in a multi-standard decoder
chip-set, it will merely pass the data through the Temporal
Decoder without alteration or modification when the system
is configured for JPEG operation.
A.2.1.4 H.261 decoding
The Spatial Decoder and the Temporal Decoder are both
required to implement an H.261 video decoder. The DRAM
interfaces on both devices are configurable to allow the
quantity of DRAM required for proper operation to be
reduced when working with small picture formats and at low
coded data rates. Typically, a single 4Mb (e.g. 512k x .3)
DRAM will be required by each of the Spatial Decoder and
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the Temp~ral Decoder.
A.2.1.5 MPEG decoding
The configuration required for MPEG operation is the
same as for H.261. However, as will be appreciated by one
of ordinary skill in the art, larger DRAM buffers may be
required to support the larger picture formats possible
with MPEG.
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159
SECTION A.3 Tokens
a. 3.1 To~ or~t
In accordance with the present invention, tokens provide
an extensible format for communicating information through
the decoder chip-set. While in the present invention, each
word of a Token is a minimum of 8 bits wide, one of
ordinary skill in the art will appreciate that tokens can
be of any width. Furthermore, a single Token can be spread
over one or more words; this is accomplished using an
extension bit in each word. The formats for the tokens are
summarized in Table A.3.1.
The extension bit indicates whether a Token continues
into another word. It is set to 1 in all words of a Token
except the last one. If the first word of a Token has an
extension bit of 0, this indicates that the Token is only
one word long.
Each Token is identified by an Address Field that starts
in bit 7 of the first word of the Token. The Address Field
is of variable length and can potentially extend over
multiple words (in the current chips no address is more
than 8 bits long, however, one of ordinary skill in the art
will again appreciate that addresses can be of any length).
Some interfaces transfer more than 8 bits of data. For
example, the output of the Spatial Decoder is 9 bits wide
(10 bits including the extension bit). The only Token that
takes advantage of these extra bits is the DATA Token. The
DATA Token can have as many bits as are necessary for
carrying out processing at a particular place in the
system. All other Tokens ignore the extra bits.
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A.3.2 Th~ DATA Token
The DATA Token carries data from one processing stage to
the next. Consequently, the characteristics of this Token
change as it passes through the decoder. Furthermore, the
meaning of the data carried by the DATA Token varies
depending on where the DATA Token is within the system,
i.e., the data is position dependent. In this regard, the
data may be either frequency domain or Pel domain data
depending on where the DATA Token is within the Spatial
Decoder. For example, at the input of the Spatial Decoder,
DATA Tokens carry bit serial coded video data packed into 8
bit words. At this point, there is no limit to the length
of each Token. In contrast, however, at the output of the
Spatial Decoder each DATA Token carries exactly 64 words
and each word is 9 bits wide.
A.3.3 Using Token formatted data
In some applications, it may be necessary for the
circuitry that connect directly to the input or output of
the Decoder or chip set. In most cases it will be
sufficient to collect DATA Tokens and to detect a few
Tokens that provide synchronization information (such as
PICTURE_START). In this regard, see subsequent sections
A.16, "Connecting to the output of Spatial Decoder", and
A.19, "Connecting to the output of the Temporal Decoder".
As discussed above, it is sufficient to observe activity
on the extension bit to identify when each new Token
starts. Again, the extension bit signals the last word of
the current token. In addition, the Address field can be
tested to identify the Token. Unwanted or unrecognized
Tokens can be consumed (and discarded) without knowledge of
their content. However, a recognized token causes an
appropriate action to occur.
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Furt~e~more, the data input to the Spatial Decoder can
either be supplied as bytes of coded data, or in DATA
Tokens (see Section A.10, "Coded data input"). Supplying
Tokens via the coded data port or via the microprocessor
interface allows many of the features of the decoder chip
set to be configured from the data stream. This provides
an alternative to doing the configuration via the micro
processor interface.
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Z ~ 6 _ 5 4 3 2 1 0 Token Name Relerexe
o o l QUANT_SCALE
c ~ o PREDICTION_MODE
O 1 1 (rese-ved)
o o MVD_FORWARDS
~ o 1 MVD_BACKWARDS
a' o o o 1 QUANT_TABLE
, 0 o o o 1 DATA
~ l l o o o o COMPONENT_NAME
1 l o o o 1 DEFINE_SAMPLING
1 l o o l o JPEG_TABLE_SELECT
1 1 o o 1 1 MPEG_TASLE_SELECT
o 1 o o TEMPORAL_REFERENCE
o l o 1 MPEG_DCH_TABLE
1, l 0 1 1 0 (reserved)
1 l O l l 1 (reserved)
O O O O (reserved) SAVE_STATE
O O 0 1 (reserved) RESTORE_STATE
o o 1 o TIME_CODE
1 1 1 1 0 0 1 1 (reserved)
l o o o o NULL
o O O O O O O l (reserved)
o ¦ O O O O 0 1 0 (reserved)
O ' O O O O 0 1 1 (reserved)
o o o 1 o o o o SEQUENCE_START
o o o 1 o o o 1 GROUP_START
o; o o 1 o o 1 o PICTURE_START
o~ o o l o o l 1 SLICE_START
o I o o l o 1 o o SEQUENCE_END
o o o ~ o ~ o 1 CODING_STANDARD
o. o o, o ~ l o PICTURE_END
o' o o 1 o 1 l l FLUS~
o ~ o o l l o o o FIELD_INFO
Table A.3.1 Summary ot Tokens
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7 6 5 l 4 3 2 1 0 ~ Token Natne F~e~erence
o o -o 1 1 0 o 1 MAX_COMP_ID
o o o 1 1 o 1 o EXTENSION_DATA
o o o 1 1 o 1 1 USER_DATA
o o o 1 1 1 o o DHT_MARKER
o o o 1 1 1 o 1 DQT_MARKER
o o 0 1 1 1 1 0 (reset~ed) DNL_MARKER
o o 0 1 1 1 1 1 ~re5erved) DRI_MARKER
1 1 1 o 1 0 0 0 (resetved)
0 1 0 0 ~ (reserved)
1 j 1 1 0 1 0 l O ~reser~ed)
1 1 1 0 1 0 1 1 (reserved)
o 1 1 o o BIT_RATE
o 1 1 o 1 VBV_BUFFER_SIZE
o 1 1 1 o V8V_DELAY
o 1 1 1 1 PICTURE_TYPE
1 o o o o PICTURE_RATE
o o o 1 PEL_ASPECT
o o 1 o HORIZONTAL_SIZE
o o 1 1 VERTICAL_SIZE
o 1 o o BROKEN_CLOSED
o 1 o 1 CONSTRAINED
1 1 1 1 o 1 1 o (reser~ed)SPECTRAL_LlMlT
o 1 1 1 DEFINE_MAX_SAMPLING
1 1 0 0 0 (reserved)
1 1 0 0 1 (reserved)
1 l l 1 1 0 1 0 (reserved)
l 1 1 l 0 1 1 (reserved)
' 1 1 1 1 1 o o HORIZONTAL_MBS
1 1 1 1 o 1 VERTICAL_MBS
l 1 1 1 1 0 (reserved)
,, 1 1 j 1 l l l (reserved)
Table A.3.1 Summary of Tokens ~contd)
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a. 3.~ D--crlption of Tok-n-
This section document~ the Tokens which are implemented
in the Spatial DeroADr and the Temporal Decoder chips in
accordance with the ~L~ sQnt invention; see Table A.3.2.
Note:
."r~ signifies bits that are currently reserved and carry
the value O
.unless indicated all integers are unsigned
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165
E 7 1 6 S 4 3 i 2 1 0 Descriplion
1 ! 1 j 1 o 1 1 0 0 BIT_RATE testinloonly
r r t r r r D b
Carries the MPEG bit rate parameter R. Genera:ed by ihe Hullman
b b b b b b b b decoder when decoding an MPEG bi~s~ream
b an 19 bit integer as defined by MP'G
1 f 1 1 1 o 1 o o BROKEN_CLOSED
r r r r r r c b
Carries two MPEG Itags bits:
c - closed_gop
b broken_link
o f o o 1 o 1 o 1 CODING_STANDARD
s s s s s s s s
s an 8 bit integer indicating the current coding s!andard. The
values currently assigned are
O - H.26 1
1 JPEG
2 MPEG
1 ! 1 0 o o o c c COMPONENT_NAME
n n j n n n n n n
Communicates the relation5h", between a co."ponent ID and the
co",yo"_"t name. See also ...
c 2 bit co,l",onent ID
n - 8 bit cG",~onrnt name'
j 1 ~ 1 1 o 1 o j 1 CONSTRAINED
r i r i r r r r r C
c - carnes the consl,~,,r,rd_parame~ers_nag decoded trom ~n
MPEG bitstream.
Table A.3.2 Tokens implemented in the Spatial
Decoder and Temporal Decoder (Sheet 1 of 9)
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E 7 6 1 5 4 3 2 10 Descriplion
0 0 1 0 0 0 1 c c DATA
d d I d d d d d d
Carries oata through the decoder chi~set.
O d d d d d d d d C - a 2 bit integer C~~~?Gn-nt lD (see A~3.5 1 j, This field
is not defined tor Tokens that carry coded data (r2!her t.'lan pixel
infv, " ,ation).
1 1 1 1 1 0 1 1 1 DEFINE_MAX_SAMPLING
1 r r r r r r h h
Max. Honzontal and Venical sampling numbers. rnese descnbe
O r r r r r r v v
the maximum number of blocks ho"~o, ~ yhr rt cally in any
~r,",t,onont of a n k~ bl~. See A.3.5.2
h - 2 bit horizontal sampling number.
v - 2 bit vertical sampling number.
1 1 1 0 0 0 1 c C DEFlNE_SAMPLlf~JG
1 r r r r r r h h
Horizontal and Vertical samDling numt~ers lor a panicular colour
O r r r r r r v v
culll?ontnL See A.3.52
c 2 bit cu, I ,ponont 10.
h - 2 bit horizontal sampling numoer.
v - 2 bit vertical sampling number.
O O O 0 1 1 1 0 0 Df~lT_MARKER
This Token informs the Vdeo Demux that the DATA Token ttlat
follows contains the st~g ifiCa~;On 01 a Huftman tat~le described
using the JPEG 'defne Hutfman table segment' syntax. This Token
is only valid when the coding standard is confi5ured as JPEG.
This Token is generated by the stan code detec~r Curing JPEG
decoding when a DHT marker has been encoun:ered in t~e r~ata
stream,
Table A.3.2 Tokens implemented in the Spatial
Decoder and Temporal Decoder (Sheet 2 of 9)
_ ` 214542~
167
E 7 6 1 5 4 3 2 1 1 0 - D~scrip~ion
o o ol o 1 1 1 1 o DNL_MARKER
This Token inforrns the Video Demux that the DATA Token ~.~al
lollows contains Ihe JPEG parameter NL which specifies the
number ol lines in a Irame.
This Token is generated by the s~art code detector during JPE5
decoding when a DNL marker has been encountered in the data
stream.
o o o o 1 1 1 o 1 DOT_MARKER
This Token in~orms the Video Demux that Ihe DATA Token that
tollows contains the sF ! fi~ 1 01 a quantisation table descrit~ed
using the JPEG 'define quantisation table segmenr syntax. This
Token is only valid when the coding standard is configured as
JPEG. The Video Demux generates a OUANT_TABLE To~en
containing the new quantisation table ;"lo" "ation.
This Token is generated by the start code detector dunng JPEG
decoding when a DaT marker has t~een encountered in the Ca a
stream.
o o o o 1 1 1 1 1 DRI_MARKER
This Token intorms the Video Demux that the DATA Token that
lollows contains the JPEG parameter Ri which specifies the
'~ number ot minimum coding units ~etween restart markers.
This Token is generated by the start code detector during JPE5
decoding when a DRI marker has ~een encounte-ed in the cata
stream.
Table A.3.2 Tokens implemented in the Spatial
Decoder and Temporal Decoder ~Sheet 3 of 9)
`- 2145~2~
168
E ~ ~--6 ~i 4 3 2 1 0 Description
o o o 1 1 o 1 o EXTENSION_DATA JPEG
O v v v v v v v v
This Token informs the Video ~emux that the DATA Token tha~
follows contains extension data. See A. 11.3, ~Conversion of stan
codes to Tokens-, and A.14.6, 'Recerving User and
Extension data',
During JPEG operation the 8 bil field ~ carries the JPEG market
value. This allows bhe class of extension da~a to be identified.
o o o o 1 ~ o 1 o EXTENSION_DATA MPEG
This Token informs the Video Demux that the DATA Token that
follows contains xtension data. See A.11.3, 'Conversion of start
codes to Tokens', and A.14.6, 'Receiving User and
Extension data',
1 o o o 1 1 o o o FIELD_INFO
o r r r t p ~ ~ ~
Carries i.lfu ", ~' , about the picture following to aid its display.
This funcbon is not signalled by any existing coding standard.
t - if the picfure is an interlaced frame this bit inCicates if the upper
field is first (t=O) or second.
p . it pictures are fields this indicates if the next picture is upper
- (p~O) or lower in the frame.
f - a 3 bit number indlcating position of the field in the 8 field PAL
sequence.
o o o o 1 o 1 1 1 FLUSH
Used to indicate the end of the current coded data and to pusn tne
end ot the data stream through the decoder.
o o o o 1 o o o 1 GROUP_START
Generated when the grouC of pictures start code is found when
decoding MPEG or the frame mar~ter is found wnen deco~ing
JPEG.
Table A.3.2 Tokens implemented in the Spatial Decoder and Temporal Decoder (Sheet 1 of
214~424 `
169
E 7 6 5 4 3 2 1 o D ~ vt
1 1 1 1 1 1 1 o o HORIZONTAL_MBS
1 r r r h h h h h
h a 13 bit number integer indicating the hori20ntal width ol the
0 h h h h h h h h
picture in Illacroblo 1~,.
1 1 1 1 1 o o 1 o HORIZONTAL_SIZE
h h h h h h h h
h 16 bit number integer indicating the hori~ontal width of the
h h h h h h h h
picture in pixels. This can be any integer value.
1 1 o o 1 o c c JPEG_TABLE_SELECT
r r r r r r t ~
Inlorms the inverse quantiser which quan~isation table ~o use on
the specified colour co" ,pono"~
c - 2 bit co, . ~v~ ,en~ ID (see A.3.5. 1
t - 2 bit integer table number.
1 o o o 1 1 o o 1 MAX_COMP_ID
r r r r r r m m
m - 2 bit integer indicating the maximum value ot component ID
(#e A.3.5.1 ) that will be used in the next picture.
o l l o 1 o 1 c c MPEG_DCH_TABLE
r r r r r r t t
Configures which DC coefficient Hutfman table should be used 'or
colour co""~or,_.,t cc.
c - 2 bit con,?ono.,t ID (see A.3.5.1
t 2 bit integer table number.
0 1 1 0 0 1 1 d n MPEG_TABLE_SELECT
Inlorms the inverse quantiser whether to use the delault or user
defined quantisation table lor intra or non-intra in~ormation.
n - 0 indicates intra in~o""ation 1 non-intra.
d 0 indicales delault table. 1 user defined.
Table A.3.2 Tokens implemented in the Spatial
Decoder and Temporal Decoder (Sheet 5 of 9)
214542~t
110
E 7 ¦ 6 5 4 3 2 1 0 Deso-iplion
0 1 d v v v v MVD_BACICWARDS
V V V V V V V V
Carries one co..~..-~.,l (rf~fither vertical or horizontal) o( the
bac~c,~ motion vector.
d - 0 indicales x co..,pone"l, 1 the y con,ponent
v -12 bit two's co..,v!~.,.ant number. The LSB provices ha~ pixel
resolution.
1 1 0 0 d v v v v MVD_FORWARDS
V V V V V V V V
Carries one ,r,",~r~n~ (eithet vertical or horizontal) ol the
~orvvard5 rr~otion vector.
d O indicatas x .,o",~n_.,l, 1 the y componenl
v .12 bit tv~o's co."ple."~.~t number. The LSB proviC~ hal~ pixel
resolution.
o o o o o o o o o NULL
Does nothing.
o o o 1 PEL_ASPECT
p - a 4 bit integer as defined by MPEG.
o o o o 1 o 1 1 o PICTURE_END
Inserted by the stan code detrector to indicate the end ol ;he cunent .
picture.
~ 1 1 1 1 o o o o PICTURE_RATE
r . r . p p p p
p a 4 bit integer as defined by MPEG.
o o o 1 o o 1 o PICTURE_START
r r r r n n n n
Indicates the start o~ a new picture.
n - a 4 bit picture rr.dex allocated to the picture by the s;art coCe
detector.
Table A.3.2 Tokencf implemented in the Spatial
Decoder and Temporal Decoder (Sheet 6 of 9)
~ 214~ 929
171
E 7 6 ~'5 ~ 3 2 1 0 D ~v~
o 1 1 1 1 PICTURE_TYPEMPEG
O r r r r r r p p
p a 2 bit integer indicating Ihe picture coding tyCe ol the picture
thal ~ollows:
O - Intra
1 - Predicted
2 - Bid,.~ nally Predicted
3 - DC Intra
o 1 1 1 1 PICTURE_TYPE H.261
1 r r r r r r O 1
Indicales various H.26 1 opbons are on (1 ) or 0n (0). These options
0 r r s d ~ q 1 1
are ah~ays 0n ~or MPEG and JPEG:
s Split Screen Indicator
d Document Camera
- Freeze Picture Flelease
Source picture tormat:
q = 0 - OCIF
q= 1 -CIF
0 0 1 0 h y x b ~ PREDICTION_MODE
A set o~ nag bits that indicate the prediction mode ~or the
,,,a. ,ubl~l~a that ~ollow
- forward predic0on
b backward prediction
x - reset torward vector predictor
y reset backward vector predictor
h enable H.261 loop filter
c o o 1 s s s s s OUANT_SCALE
Informs the inverse quantiser oi a new scale ~actor
s - S bit integer in range 1 ... 31. The value 0 is reserved.
Table A.3.2 Tokens implemented in the Spatial Decoder and Temporal Decoder (Sheet 7 of
~ 2145 12~
E 7 1 51 4 3 2 ~¦ Descnp~ion
1 o o o o 1 r t I t QUANt_TA3LE
1 q q rl q q q qi q
Loads the specified inverse quantiser tahle with 64 8 bit unsigned
integers. The values are in zig-~ag order.
0 q q q q q q q q
t - 2 bit integer specitying the inverse cuantiser lable ts be 10aded.
O O O O 1 0 1 0 o SEaUENCE_END
The MPEG se~uence_end_code and the JPEG EOI marker cause
this Token to be generated.
o o o o 1 o o o o SEQUENCE_START
Generated by the MPEG sequence_start start code.
o o o 1 o o 1 1 SLICE_START
ossssssss
Co. ~perrl- tû the MPEG slice_start the H.261 GOa a-d Ihe
JPEG resync interval The interpretation of 6 bit integer s ciffers
between coding standards:
MPEG Slice Vertical Position -1.
H.261 Group o~ Blocks Number -1.
JPEG res~ch,orl ~1 interval iden~ifica~ion (4 LSBs only).
1 1 1 o 1 o o t t TEMPORAL_REFERNCE
o t t t t t t t t
t - carries the temporal reterence. For MpEG this is a 10 bit intege .
For H261 only the 5 LSBs are used. the MSas will always be zero.
1 1 1 1 0 0 1 0 d TIME_CODE
1 r r r h h h h h
The MPEG time_code:
1 r r m m m m m m
d - Drop Irame nag
1 r r s s s s s s
h - 5 bit integer specitying hours
0 r r p p p p p p
m - 6 t~it integer SDecitying minutes
s 6 bit inleger specitying seconds
p 6 bit integer speci~ying pictures
Table A.3.2 Tokens implemented in the Spatial Decoder and Temporal Decoder (Sheet 8 of
2145~24
173
_L ~
E 7 1 6 I S 1 4 1 3 1 2 l O Descnption
01 I ~ 1 o 1, 1 USER_DATAJPEG
o V . V V V V V V: V
This Token informs '~he Vdeo Demux '~at the DATA Token rhat
follows contains user data. See A.11.3, '`onverslcn of s`art c~ces
~o Tokens', and A.14.6, 'Receiving User ana
Extension data',
During JPEG operation the 8 bit 'ield ~ carr:es the JP--G ,-arker
value, This allows ;he class ot user cata to be ider ;l'ied.
o o o i o 1 1 o 1 1 USER_DATA MPEG
rhis Token informs the Vdeo Demux that tne DATA loken ~nat
follows contains user data. See A.l 1.3, ~Conversion of stan coces
to Tokens', and A.14.6, 'Receivins User and
Extension data',
o 1 1 o j 1 VBV_BUFFER_SIZE
r ' r r r r r s s
s ~ a l O bit ir teger as defined by MPEG.
O s i s s s s s s s
o 1 1 1 o VBV_DELAY
b, b b b b b b j b
b ~ a 16 bit integer as dehned by MpEG~
G b b b b b b bl b
1 ~ 1 1 j 1 1 1 o 1 VERTiCAL_MBS
1 r ~ r r I v v v v v
v - a 13 bn integer indkating the vertical size of the picture in
O v, v v, v v v v v
I "~c- ~)tjlo..~s.
1, 1 o o 1 1 1 VERTICAL_SIZE
V I V I V I V V V V V
v - a 16 bit integer indicating the venical size of the plcrJre in Dixe~s.
O v v I v I v v I v v v
This can be any integer va~ue,
Table A.3.2 Tokens implemented in the Spatial
Decoder and Temporal Decoder (Sheet 9 of 9)
214542g
174
a. 3.5 ~umb-r- ig~all-d in Tok-n-
A.3.5.1 Co~pon-nt I~-ntification numb-r
In accordance with the present invention, the Component
ID number is a 2 bit integer specifying a color component.
This 2 bit field is typically located as part of the Header
in the DATA Token. With MPEG and H.261 the relationship is
set forth in Table A.3.3.
Component ID - MPEG or H.261 colour co."~ncn~
O Luminance (Y)
91ue di~erence signal (Ct~ / U)
2 Red dinerence signal (Cr t V)
3 Never used
T~bl- A.3.3 Component ID for ~PEG ~nd H.261
-
2145~24
175
With JPEG the situation is more complex as JPEG does not
limit the color components that can be used. The decoder
chips permit up to 4 different color components in each
scan. The IDs are allocated sequentially as the
specification of color components arrive at the decoder.
a.3.s.2 ~ori~ont~l ~nd V-rtical -mpling n~mher~
For each of the 4 color components, there is a
specification for the number of blocks arranged
horizontally and vertically in a macroblock. This
specification comprises a two bit integer which is one less
than the number of blocks.
For example, in MPEG (or H.261) with 4:2:0 chroma
sampling (Figure 36) and component IDs allocated as per
Table A.3.4.
Honzontal Venical
Component IDsampling Width in blocks sampling Height in blocks
number number
O 1 2 1 2
0 1 0
2 0 1 0
3 Not usedNot usedNot usedNot used
T~bl- A.3.~ 8umpling numb~rs for ~:2:0/MPEG
- 21~5424
176
With JPEG and 4:2:2 chroma sampling (allocation of
component to component ID will vary between applications.
See A.3.5.1. Note: JPEG requires a 2:1:1 structure for its
macroblocks when processing 4:2:2 data. See Table A.3.5.
Hon20n~1 Vertlcal
Cct-scren~ IDsampling Wid~ n ~locks samsbn9 He!5,~ 'n blocks
number numbet
Y 1 2 0
U O 1 0
v o 1 1 0
Tabl- A.3.5 8ampling numb-rs for ~:2:2 JPgG
1 2 ~
177
A.3.6 ~p-cial Token formats
In accordance with the present invention, tokens such as
the DATA Token and the QUANT TABLE Token are used in their
"extended form" within the decoder chip-set. In the
extended form the Token includes some data. In the case of
DATA Tokens, they can contain coded data or pixel data. In
the case of QUANT TABLE tokens, they contain quantizer
table information.
Furthermore, "non-extended form" of these Tokens is
defined in the present invention as "empty". This Token
format provides a place in the Token stream that can be
subsequently filled by an extended version of the same
Token. This format is mainly applicable to encoders and,
therefore, it is not documented further here.
Token Name MPEG JPEG H26
BIT_RATE
~ROKEN_CLOSED
CODING_STANDARD
COMPONENT_NAME
CONSTRAINED
DATA
DEFINE_MAX_SAMPLING
DEFINE_SAMPLING
DtlT_MARKER
DNL_MARKER
DQT_MARKER
DRI_MARKER
Table A.3.6 tokens for different standards
`- 2145~24
78
~ Tokcn Name MPEG JPEG H261
EXTENSION_DATA
FIELD_INFO
FLUSH
GROUP_START
HORIZONTAL_MBS
HORIZONTAL_SIZE
JPEG_TABLE_SELECT
MAX_COMP_ID
MPEG_DCH_TABLE
MPEG_TABLE_SELECT
MVD_BACKWARDS
MVD_FORWARDS
NULL .
PEL_ASPECT
PICTURE_END
PICTURE_RATE
PICTURE_START
PICTURE_TYPE
PREDICTION_MODE
OU ANT_SCALE
QUANT_TABLE
SEQUENCE_END
SEaUENCE_START
SLICE_START ~ ~ ~
TEMPORAL_REFERENCE ~ f
TIME_CODE
USER_DATA
VBV_BUFFER_SIZE
VBV_DELAY
VERTICAL_MRS
VERTICAL_SIZE
Tab~e A.3.6 Tokens for dir~etent standards (contd)
~1~5Q2Q
~79
A.3.7 Us- of Token~ for different standard~
Each standard uses a different ~ub-set of the defined
Tokens in accordance with the present invention; ss Table
A.3.6.
2145424
180
SECTION A.4 The two wire interface
a. ~ o ~ lr- $~t-rf~c-- ~nd th- To~-~ Port
A simple two-wire valid/accept protocol is used at all
levels in the chip-set to control the flow of information.
Data is only transferred between blocks when both the
sender and receiver are observed to be ready when the clock
rises.
l)Data transfer
2)Receiver not ready
3)Sender not ready
If the sender is not ready (as in 3 Sender not ready
above) the input of the receiver must wait. If the
receiver is not ready (as in 2 Receiver not ready above)
the sender will continue to present the same data on its
output until it is accepted by the receiver.
When Token information is transferred between blocks the
two-wire interface between the blocks is referred to as a
Token Port.
a. ~ . 2 ~h-r- us-d
The decoder chip-set, in accordance with the present
invention, uses two-wire interfaces to connect the three
chips. In addition, the coded data input to the Spatial
Decoder is also a two-wire interface.
A.~.3 Bu- ig~
The width of the data word transferred by the two-wire
interface varies depending upon the needs of the interface
concerned (See Figure 35, "Tokens on interfaces wider than
8 bits". For example, 12 bit coefficients are input to the
Inverse Discrete Cosine Transform (IDCT), but only 9 bits
are output.
_ ` 214S~2~
181
IntertaceData WiCth (bits)
Coaed data inpu~ ~o SpaDal Decode- ~
Out~u~ pon o~ Spatia~ Oecoder g
Input pon o~ Tempora~ Oecoder g
Output port o~ Tempor~ Decoder 8
Input por~ ol Image Fonnalter 8
Table A.4.1 Two wire interface data width
In addition to the data siqnals there are three other
signals transmitted via the two-wire interface:
.valid
.accept
.extension
A.4.3.1 The ext-nsion signal
The extension signal corresponds to the Token extension
bit previously described.
i 10 A.4.4 Design consideration~
The two wire interface is intended for short range,
point to point communication between chips.
The decoder chips should be placed adjacent to each
other, so as to minimize the length of the PCB tracks
1~ between chips. Where possible, track lengths should be
kept below 25 mm. The PCB track capacitance should be kept
to a minimum.
`- 2145~2~
182
The clock distribution should be designed to minimize
the clock slew between chip~. If there is any clock slew,
it should be arranged so that "receiving chips" see the
clock before "sending chips".l
All chips communicating via two wire interfaces should
operate from the same digital power supply.
a. ~ . 5 Int-rfac- ti-i~g
30 MH2 Note'
Num. Characterist~ Unit
Min. Ma~
InDutsignal set-up bme S ns
2 Input slgnal hold ~ime 0 ns
3 Output signal drive ome 23 ns
Ou~putsignæ hold ~me 2 ns
Tabl- A.~.2 T~o wir- int-rfac- timing
a. Figures in Table A.4.2 may vary in accordance with
design variations
b. Maximum signal loading is approximately 20 pF
' Note: Figure 38 shows the two-wire interface between the
system de-mux chip and the coded data port of the Spatial
Decoder operating from the main decoder clock. This is
optional as this two wire interface can work from the coded
data clock which can be asynchronous to the decoder clock.
See Section A.10.5, "Coded data clock". Similarly the display
interface of the Image Formatter can operate from a clock that
is asynchronous to the main decoder clock.
~_`` 2145!12~1t
83
A.4.6~_S~gnal level~
The two-wire interface uses CMOS inputs and output.
V~Hm,n is approx. 70% of V,,~, and V~LmJ~ is approx. 30% of VDD.
The values shown in Table A.4.3 are those for VIH and VIL at
their respective worst case VDn. V~ =5.0+0.25V.
Symool Parameter Min. Max. Unlts
Vly Input loglc '1' voltage 3.68VOO ~ 0.5 V
VIL Input log~c 'O' voltaÇe G~O - C.S l .43 V
VO~ Output loglc ' 1 ' voltageVOo ~ O. l
Voo 4 I V~
VO~ Out~ut )oÇlC 'O' voltage O.l V '
0.4
Input leakage current :10 ~A
Table A.4.3 DC electrical characteristics
a. 10H5 lmA
b. 1(IH< 4~
c. 1l~,clmA
lo d. 10l~4mA
~ ~145~2~1
184
A.4.7 Cpntrol clock
In general, the clock controlling the transfers across
the two wire interface is the chip's decoder_clock. The
exception is the coded data port input to the Spatial
Decoder. This is controlled by coded_clock. The clock
signals are further described herein.
~_ 2145~2~
185
SECTlON A.5 DRAM Interface
A.5.1 The DRAM interface
A single high performance, configurable, DRAM interface
is used on each of the video decoder chips. In general,
S the DRAM interface on each chip is substantially the same;
however, the interfaces differ from one another in how they
handle channel priorities. The interface is designed to
directly drive the DRAM used by each of the decoder chips.
Typically, no external logic, buffers or components will be
necessary to connect the DRAM interface to the DRAMs in
most systems.
A.5.2 Interface signals
Inpu~ /
Signal Narne Oescrip~ion
Output
DRAM_data(31:01 1/0 The 32 bi~ wide DRAM data Ous. Opbonally ~lis bus
can be configured ~o be 16 or 8 bils wide. See
section A.5.8
ORAM_addr~10:0] The 22 bit wide DRAM in~ertace address is tlme
mul~iplexed over ~his 11 ~it wide bus.
O The CRAM Row Address StroOe signal
~[3 Ol O The t~RAM Column Address Strooe slgnai. One
signal is provided per byte ot the interface~s data
bus. Alt the CAS signals are driven simu:taneousl;.
WE O The DRAM Write EnaOle signal
i5~ o rhe DRAM Output EnaOle signal
DR~M_enable I This inpu~ signal, when low, n^aKes all tne output
signals on the intertace go high i"lpeda,lce.
Note: on chip data process;ng is not s;opped when
tne ORAM intertace is high impedance. So, errcrs
will Occur i~ the chip attempts ~o access ORAM wni~e
ORAM_enable is low.
Table A.5.1 DRAM inter~ace signals
- 2145~24
186
In ~cordance with the present invention, the interface
is configurable in two ways:
.The detail timing of the interface can be
configured to accommodate a variety of
different DRAM types
.The "width" of the DRAM interface can be
configured to provide a cost/performance
trade-off in different applications.
A.5.3 Configuring the DRAM interface
o Generally, there are three groups of registers
associated with the DRAM interface: interface timing
configuration registers, interface bus configuration
registers and refresh configuration registers. The refresh
configuration registers (registers in Table A.5.4) should
be configured last.
A.5.3.1 Conditions after reset
After reset, the DRAM interface, in accordance with the
present invention, starts operation with a set of default
timing parameters (that correspond to the slowest mode of
operation). Initially, the DRAM interface will continually
execute refresh cycles (excluding all other transfers).
This will continue until a value is written into
refresh interval. The DRAM interface will then be able to
perform other types of transfer between refresh cycles.
A.5.3.2 Bus configuration
Bus configuration (registers in Table A.5.3) should only
be done when no data transfers are being attempted by the
interface. The interface is placed in this condition
immediately after reset, and before a value is written into
refresh_interval. The interface can be re-configured
later, if required, only when no transfers are being
attempted. See the Temporal Decoder chip access register
(A.18.3.1) and the Spatial Decoder buffer_manager_acCeS5
register (A.13.1.1).
21~5424
187
A.5.3.~ Interface timing configuration
In accordance with the present invention, modifications
to the interface timing configuration information are
controlled by the interface_timing_access register.
Writing 1 to this register allows the interface timing
registers (in Table A.5.2) to be modified. While
interface_timing_access = 1, the DRAM interface continues
operation with its previous configuration. After writing
1, the user should wait until 1 can be read back from the
interface_timing_access before writing to any of the
interface timing registers.
When configuration is compete, 0 should be written to
the interface_timing_access. The new configuration will
then be transferred to the DRAM interface.
A.5.3.4 Refresh configuration
The refresh interval of the DRAM interface of the
present invention can only be configured once following
reset. Until refresh_interval is configured, the interface
continually executes refresh cycles. This prevents any
other data transfers. Data transfers can start after a
value is written to refresh_interval.
As is well known in the art, DRAMs typically require a
"pause" of between 100 ~s and 500 JIS after power is first
applied, followed by a number of refresh cycles before
normal operation is possible. Accordingly, these DRAM
start-up requirements should be satisfied before writing a
value to refresh_interval.
A.5.3.5 Read acces~ to configuration registers
All the DRAM interface registers of the present
invention can be read at any time.
A.5.4 Interface timing tticks)
2145424
188
The DR~M interface timing is derived from a Clock which
is running at four times the input Clock rate of the device
(decoder_clock). This clock is generated by an on-chip
PLL.
S For brevity, periods of this high speed clock are
referred to as ticks.
21 l5424
189
A. 5 . 5 =~~ I~terface regi~ter~
Register name ~ ~ DescnDtion
in~ertace_timing_acCess 1 O This luncIIon enable reSIs;er allcws access to
bit ;he ORAh~t intertace tlmlng ccntigl,,a~on
registers. rhe configuration reSIsters should nct
rw be modified while this register hol~s the value
0. Writing a one to this resister re~ues~s access
to modifiy bhe configurabon registers. At er a O
has been wntten to this register bhe GRA,~1
intertace will start to use the new valLes in the
timing configuration registers.
page_start_length S O Specifies the length ot the access s-ar; in acks.
bit rhe minimum value that can be tssed is 4
(meaning 4 acks). 0 selec's the maximum
~w length ot 32 acks.
transter_cycle_length 4 O Specifies bhe length ot '~he tast paSe read or
bit write cycle in ticks. The minimum value that can
be used is 4 (meaning 4 bcks). 0 selec~s ahe
rw maximum length ot 16 bc!~s.
refresh_c~ycle_length 4 O Specifies the length of the relresh cycle in ticks.
bit The minimum value that can be ~sed is 4
(meaning 4 ticks). 0 selec~s the maxlmur
rw lensth ot 16 ticks.
RAS_talling 4 Specifies the numoer ol ticks atter ~he s;art o~
bit the access start that F~ lalls. The mir,im.um
value that can be used is 4 (meanins 4 ticks). Q
rw selec~s ~,he maximum len5th ot 16 tcks.
CAS_talling 4 8 Specifies the numher ol ticks atter :he s:art ot a
read cycle, write cycle or access s~ar ;ha~ CAS
talls. rhe minimum value that can 'ae used is t
rw (meaning 1 ock). O selec'5 the rna~imum lenç~
Ol 16 ticks.
Table A.~.2 Intetface timing configuration re9isters
~145~24
190
ai
Register name ~ ~D Description
i,i
DRAM_dau_width 2 0 Speclfies the numD of bits used on ~e DRA!,~
bit interface data bus DRAM_daut~ 0]. See
A.5.8
rv~
row_adaress_t~its 2 0 Speclfies the numOer of bits used for the row
bil address portion of the DRAM interface aCcress
bus. See A.5.10
rw
DRAM_enaDle 1 1 Wriong the value 0 in to tnis register lorces the
bit DRAM interface into a high i~ xJ~ncr, state.
0 will be read from this register if either ~he
rw DRAM_enabl- signal is low or 0 has been
written to the register.
CAS_strength 3 6 Th~ thr-- bit rerJisters configure the output
RAS_strength bit drive strength of DRAM interlace 5ignals.
addr_strength
This attows th- interface to De configured ~or
DRAM_dau_strength
rw various ditferent loads.
OEWE_strength
See A.5.13
Table A.5.3 Interface bu~ configuration regi~ter~
-- 21 15~24
191
A.5.6 I~terface op-ration
The DRAM interface uses fast page mode. Three different
types of access are supported:
.Read
.Write
.Refresh
Each read or write access transfers a burst of 1 to 64
bytes to a single DRAM page address. Read and write
transfers are not mixed within a single access and each
successive access is treated as a random access to a new
DRAM page.
Regisler name ~ ~¢n, Oescription
~n
retresh_interval 8 0 This value specifies ~he interval cetween
0it re~resh cycles in periods o~ 16 decoder_clock
cycles. Values in the range 1..255 can be
rw configured. The value 0 is automac~ally loaCed
aiter resel and torces the ORAM interlace :o
continuously execute re~re5h cycles untli a valid
re~resh interval is configured. It is
r~o.".,.en~ed that retresh_interval shculd ~e
configured ooly once a~ter each reset.
no_re~resh 1 0 Writing the value 1 to this register preven!s
bit execuoon o~ any rerresh cycles.
r~v
Table A.5.4 Refresh conf igUration registert3
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A.5.7 ACce~s structure
Each access ls composed of two parts:
.Access start
.Data transfer
In the present invention, each access begins with an
access start and is followed by one or more data transfer
cycles. In addition, there is a read, write and refresh
variant of both the access start and the data transfer
cycle.
Upon completion of the last data transfer for a
particular access, the interface enters its default state
(see A.5.7.3) and remains in this state until a new access
is ready to begin. If a new access is ready to
~ 21~5924
193
begin when the last access has finished, then the new
access will begin immediately.
A.5.7.1 Acc~s ~tar~
The access start provides the page address for the read
or write transfers and establishes some initial signal
conditions. In accordance with the present invention,
there are three different access starts:
.Start of read
.Start of write
lo .Start of refresh
Num. Cha. - ;st~ Min.Max. Unit Notes
RAS precharge period set ~y register 4 16 tick
RAS_talling
6 Access stan duraOon sel by register 4 32
page_stan_tength
7 CAS precharge length set by register 1 16
CAS_hlllng.
8 Fast page read or write cycle length set by 4 16
the register tr nster_cycle_tength.
9 Re~resh cycle length set by the register 4 16
retresh_cycle.
Table A.5.5 DRAM Interface timing parameters
a. This value must be less than RAS_falling to ensure
~ before RAS refresh occurs.
214542 1
194
In each case, the timing of RAS and the row address is
controlled by the registers RAS_falling and
page_start_length. The ~t~te of OE and DRAM_data[31:0] is
held from the end of the previous data transfer until **RAS
falls. The three different access start types only vary in
how they drive OE and DRAM datat31:0] when RAS falls. See
Figure 43.
a. S.7.2 D~t~ tr~n~f-r
In the present invention, there are different types of
data transfer cycles:
.Fast page read cycle
.Fast page late write cycle
.Refresh cycle
A start of refresh can only be followed by a single
refresh cycle. A start of read (or write) can be followed
by one or more fast page read (or write) cycles. At the
start of the read cycle CAS is driven high and the new
column address is driven.
Furthermore, an early write cycle is used. WE is driven
low at the start of the first write transfer and remains
low until the end of the last write transfer. The output
data is driven with the address.
As a CAS before RAS refresh cycle is initiated by the
start of refresh cycle, there is no interface signal
activity during the refresh cycle. The purpose of the
refresh cycle is to meet the minimum RAS low period
required by the DRAM.
A.S.7.3 Int-rf~c- d-f~ult stat-
The interface signals in the present invention enter a
default state at the end of an access:
RAS, CAS and WE high
*data and OE remain in their previous state
.addr remains stable
A.S.8 Data bus width
~` 2145924
195
The two bit register, DRAM_data_width, allows the widthof the DRAM interface's data path to be configured. This
allows the DRAM cost to be minimized when working with
small picture formats.
DRAM_data_wi dth
0' 8 bit wide aata bus on DRAM_data~31 :Z4]a.
t 16 bitwide data bus on DRAM_data(31:16j`al.
2 32 bil wide data bus on DRAM_datal31 :l
Table A.5.6 Configuring DRAM_data width
a. Default after reset.
b. Unused signals are held high impedance.
A.5.9 row address width
The number of bits that are taken from the middle
section of the 24 bit internal address in order to provide
the row address is configured by the register,
row_address_bits.
row_address_Oits Width o~ row address
10 oits on DRAM_addr~9:0]
2 11 t~its on DRAM_addr~10:0]
Table A.5.7 Configuring row_address_bit~
~` 214592~
196
A.5.1~ Ad~ress bits
On-chip, a 24 bit address is generated. How this
address is used to form the row and column addresses
depends on the width of the data bus and the number of bits
selected for the row address. Some configurations do not
permit all the internal address bits to be used and,
therefore, produce "hidden bits)".
Similarly, the row address is extracted from the middle
portion of the address. Accordingly, this maximizes the
rate at which the DRAM is naturally refreshed.
rowrow address
data buscolumn address translaaon
addresstransla~on
widthinl~rnal O external
widthinternal O external
9~14:6] O ~8:0~ ô ~19:151 ~ ~10:61 15:0l ~ [5:0]
1 6 [20: 1 51 ~ [1 0:51 ~5: 1 1 :~ [4:01
32 ~21:151 ~10:41 [5 21 ~3:01
10~15:61O[9:01 8 ~19:161~10:61 ~5:0~ 5:01
16 ~20:161 0 ~10:51 [5:11 :~ t4:0l
32 ~21:1610~10:41 ~s:21~[3-:0
11[16:61 0 [10:01 ~ 119:17] ~ [1o:6l [5:01 O [
16 [20:17~c\ [~0:51 ~S:ll~ [4:0
32 [21:l7l0[l0:41 ~52~:~[3:01
Table A.5.8 M~pping between internal and external addresses
~_,' 2145g2~
197
A.5.10.1 Low order column address bits
The least significant 4 to 6 bits of the column address
are used to provide addresses for fast page mode transfers
of up to ~4 bytes. The number of address bits required to
control these transfers will depend on the width of the
data bus (see A.5.8).
A.5.10.2 Decoding row addres~ to access more DRAM bank~4
Where only a single bank of DRAM is used, the width of
the row address used will depend on the type of DRAM used.
lo Applications that require more memory than can be typically
provided by a single DRAM bank, can configure a wider row
address and then decode some row address bits to select a
single DRAM bank.
NOTE: The row address is extracted from the middle of
the internal address. If some bits of the row address are
decoded to select banks of DRAM, then all possible values
of these "bank select bits" must select a bank of DRAM.
Otherwise, holes will be left in the address space.
A.5.11 DRAM Interface enable
In the present invention, there are two ways to make all
the output signals on the DRAM interface become high
impedance, i.e., by setting the DRAM_enable register and
the DRAM-enable signal. Both the register and the signal
must be at a logic 1 in order for the drivers on the DRAM
interface to operate. If either is low then the interface
is taken to high impedance.
Note: on-chip data processing is not terminated when
the DRAM interface is at high impedance. Therefore, errors
will occur if the chip attempts to access DRAM while the
interface is at high impedance.
In accordance with the present invention, the ability to
take the DRAM interface to high impedance is provided to
allow other devices to test or use the DRAM controlled by
the Spatial Decoder (or the Temporal Decoder) when the
214542~
~,
198
Spatial Decoder (or the Temporal Decoder) is not in use.
It is not intended to allow other devices to share the
memory during normal operation.
A.5.12 Refresh
Unless disabled by writing to the register, no refresh,
the DRAM interface will automatically refresh the DRAM
using a~C~ before KAS refresh cycle at an interval
determined by the register, refresh_interval.
The value in refresh_interval specifies the interval
between refresh cycles in periods of 16 decoder_clock
cycles. Values in the range 1.255 can be configured. The
value 0 is automatically loaded after reset and forces the
DRAM interface to continuously execute refresh cycles (once
enabled) until a valid refresh interval is configured. It
is recommended that refresh_interval should be configured
only once after each reset.
While reset is asserted, the DRAM interface is unable to
refresh the DRAM. However, the reset time required by the
decoder chips is sufficiently short, so that it should be
possible to reset them and then to re-configure the DRAM
interface before the DRAM contents decay.
A.5.13 Signal strengths
The drive strength of the outputs of the DRAM interface
can be configured by the user using the 3 bit registers,
CAS_strength, RAS_strength, addr_strength,
DRAM_data_strength, and OEWE_strength. The MSB of this 3
bit value selects either a fast or slow edge rate. The two
less significant bits configure the output for different
load capacitances.
The default strength after reset is 6 and this
configures the outputs to take approximately 10ns to drive
a signal between GND and VDD if loaded with 24pF.
424
199
stren~th value Drive cha,a.l~ ,isli.s
o Approx. 4 nsN into 6 pf load
Approx. 4 nsN into 12 p~ load
2 Approx. 4 nsN into 24 p~ load
3 Approx. 4 nsN into 48 pi load
4 Approx. 2 nsN inlo 6 p~ load
Approx. 2 nsN into 12 p~ load
6- Approx. 2 nsN into 24 p~ load
7 Approx. 2 nsN into 4B p~ load
Table A.5.9 Output strength configuration~
a. Default after reset
When an output is configured appropriately for the load
it is driving, it will meet the AC electrical
characteristics specified in Tables A.5.13 to A.5.16. When
appropriately configured, each output is approximately
matched to its load and, therefore, minimal overshoot will
occur after a signal transition.
A.5.14 Electrical ~pecifications
All information provided in this section is merely
illustrative of one embodiment of the present invention and
is included by example and not necessarily by way of
limitation.
,
4 2 ~
200
Symbol Parametet Min. Max. Units
VDO SUPPIY vol~age relathe to GN0 -0.5 6.5 V
Vl" Inpu~ voltage on any pin GND Q5 VDO, O S V
TA OperaDng temperature 40 185 C
Ts Storasetem~erature 55 , 150 C
Table A.5.10 Maximum Ratingsa
Table A.5.10 sets forth maximum ratings for the
illustrative embodiment only. For this particular
embodiment stresses below those listed in this table should
be used to ensure reliability of operation.
Symbol Parameter Min. Max. Units
V00 Supply voltage relathe to GN0 4.75 5.25 v
GND Ground 0 0 V
V~ Input logic '1' voltage 2.0 v00 ~ 0.5 v
V~L Input logic '0' voltage GN0 - 0.5 0.6 V
TA Operaang temperature 0 70 C-
Table A.5.11 DC Operating conditions
a. With TBA linear ft/min transverse airflow
~ 2145~24
201
SymDol Farameter Min. Ma1~. Units
VOL Output logic '0' volUge 0.4 V '
VOt~ Output logic '1~ voltage 2.8 V
Output current ~ 100 ~ D
10z Output On state leakage current ~ 20 ilA
llz Inputl akagecurrent ~10 ~IA
IX RMS powersupply current 500 mA
CIN Input caDa~ nce S pF
COL~ Output / lO cdD~cit~nce S pF
Table A.5.12 DC Electrical characteri~tic~
a. AC parameters are specified using VoLma~ = 0.8V
as the measurement level.
b. This is the steady state drive capability of
the interface.
Transient currents may be much greater.
-- 2145~24
202
A.5.14.1 AC characteristics
Num. Parameter Min.Max.Unit Note '
Cycle time -2 ~2 ns
I l Cycle time 2 +2 ns
12 High pulse -5 ~2 ns
13 Low puLse 11 12 ns
11 Cycletime 9 ~2 ns
Table A.5.13 Differences from nominal valu-s for a strobe
a. As will be appreciated by one of ordinary skill in
the art, the driver strength of the signal must be
5configured appropriately for its load.
Num. Parameter Min.Max.Unit Note '
Strobe to strobe delay 3 +3 ns
16 Low hold time -13 ~3 ns
17 Strobe tc strobe precharge e.g. tCRP, -9 ~3 ns
tRCS, tRCH, tRRH, tRPC
precharge pulse between any two -5 +2 ns
~signals on wide DRAMs e.g. tCP, or
between 1~ rising and ~ ialling e.g.
. tRPC
18 Precharge oe~ore disable 12 t3 ns
Table A.5.14 Differences from nominal
values between two strobes
a. The driver strength of the two signals must be
configured appropriately for their loads.
21~5~24
203
Num. Pafameter Min. Max. Unit Note'
19 Setup3mo 12 l~ ns
Hold ome 12 ~3 n5
I Address access time -12 ~3 r5
22 Next valid aher slroCe -12 ~3 rs
Table A.5.15 Differences from nominal
betweQn a bus and a strobQ
a. The driver strength of the bus and the strobe must
be configured appropriately for their loads.
Num~ Parameter Min.Max.Unit Note
23 Read dala set-up amo Ceiore ~ signa~ 0 rs
slarts to rise
24 Read data hold time aher ~ signal n5
slarts to go high
S Table A.5.16 Difference~ from nominal
between a bus and a strobe
When reading from DRAM, the DRAM interface samples
DRAM_data[31:0] as the ~ signals rise.
2145~24
2D~
parameter parameter parameter
name numDer name number name number
tPC 10 tRSH16 tRHCP 18
tCPRH
tRC 11 tCSH ~SR 19
~RP 12 IRWL tASC
tCP tCWL tDS
tCPN tRAC tRAH20
tRAS 13 tOACltOE tCAH
tCAS tCHR tOH
tCAC tCRP 17 tAR
tWP tRCS tAA 21
tRASP tRCH tRAL
tRASC tRRH tRAD22
tACPnCPA 14 tRPC
tRCD 15 tCP
tCSR tRPC
Table A.5.17 Cross-reference ~etween "st~ndard" DRAM
p~rameter names and timing par~meter numbers
S l24
205
SECT101~ A.6 Microprocessor interface (MPI)
A standard byte wide microprocessor interface (MPI) is
used on all chips in the video decoder chip-set. However,
one of ordinary skill in the art will appreciate that
microprocessor interfaces of other widths may also be used.
The MPI operates synchronously to various decoder chip
clocks.
A.6.1 MPI si~nals
Input /
Signal Name Oescnption
OUtDUt
enaOle[~ :O] Input Two active low chlp enables. Both must ~e low lo
enaDle accesses via the MPI.
rw Input Hi5h indicates that a aevice wishes to read values
trom the video chip.
This signal should be stable while the C.lip is
enabled.
addr(n:OI Input Addtess specifies one ot 2" locations in ~he chip s
memory map.
This signal should be stable while Ihe chip is
enabled.
data~7:0l Output ~ bit wide data 1/O port. These pirls are high
""peJance jl either enable signal is hign.
Output An acuve low, open collector, interrupt request
signal.
Table A.6.1 MPI interface signals
~- 2145~2~
206
A.6.2 MPI electrical specifications
Symbol Parameter Min. Max. Units
V00 Supply vo~tage relathve to GND -0.5 6.5 V
V~ Inputvoltageon anypin GND 0 5 VOD I 5 V
T,~ Operanng temperature 10 , 85 C
Ts Storage lemperalure -S; ~ I S0 'C
Table A.6.2 Absolute Maximum Ratings-
Sym~ol Parameter Min. Max. Units
V~0 Supply voltage relathe to GND 4.75 5.25 V
G,~lD Ground 0 0 V
VIH Input logic 'I' vottage 2.0 V00 ~ 0.5 V '
VIL Input logic ~0' voltage GNO - 0.5 0.8 v (-J
T~ Operating ta,~ e 0 70 C~
Table A.6.3 DC Operating conditions
a. AC input parameters are measured at a 1.4
measurement level.
b. With TBA linear ft/min transverse airflow.
--` 21~5424
207
Syrnbol Pararneter Min. Max. Units
VOL OUtPUt 109;C 'O' voltag- 0.4 V
Vo~x Open collector output logic '0 0.4 V'
voltage
vc~ Output logic '1' voltage 2.4 V
lo Outputcurrent + 100
loOc Open collr~ctor output current 4.0 8.0 r~ '
loz Output ofl state leakage current ~ 20 ~A
l!N Inputlealcagecurrenl ~ lO ~LA
loo RMS power supp/y curr-nt 500 r~
C,!~ Inpul capa.lt~e S pF
Co~,r Output /10 c~pd~itcl~e 5 ~;
T~ble A.6.4 DC Electrical characteristics
a. lo<lo~m~
b. This is the steady state drive capability of
the interface. Transient currents may be
much greater.
c. When asserted the open collector lrq output
pulls down with an impedance of 1oon or less.
`-- 2145424
208
A.6.2.~ AC characteristics
Notes
Num. Cha,d.,l~rl,t~ Min. Ma~o Unit
Enable low penod 100 ns
26 Enable hish perioC 50 ns
27 Address or rw set~up to chip enable O ns
28 Address or r.v hold trom chip disable O ns
29 OUtDUt turn-on time 20 ns
Read dataaccess time 70 ns b
3 I Read data hold time 5 ns
32 Read da!a tur~o~ bmo 20
Table A.6.5 Microprocessor interface read timing
a. The choice, in this example, of ena~le[0]
to start the cycle and enable[1] to end it
is arbitrary. These signal are of equal
status.
b. The access time is specified for a maximum
load of 50 pF on each of the data[7.o].
Larger loads may increase the access time.
Num. Chd~5~ ;st~ Min. Max. Unit Notes
33 Write aata set-uP time 15 ns
3.~ Wri~edata hotd Ome O ns
Table A.6.6 Microprocessor interface write timing
a. The choice, in this example, of ena~le[0]
to start the cycle and ena~le~l] to end
it is arbitrary. These signal are of equal
status.
-- 21~5424
209
A.6.3 Interrupts
In accordance with the present invention, "event" is the
term used to describe an on-chip condition that a user
might want to observe. An event can indicate an error or
it can be informative to the user's software.
There are two single bit registers associated with each
interrupt or "event". These are the condition event
register and the condition mask register.
A.6.3.1 condition event register
The condition event register is a one bit read/write
register whose value is set to one by a condition occurring
within the circuit. The register is set to one even if the
condition was merely transient and has now gone away. The
register is then guaranteed to remain set to one until the
user's software resets it (or the entire chip is reset).
The register is set to zero by writing the
value one
Writing zero to the register leaves the register
unaltered.
The register must be set to zero by user
software
before another occurrence of this condition can
be observed.
The register will be reset to zero on reset.
A.6.3.2 Condition ma~k register
The condition mask register is one bit read/write
register which enables the generation of an interrupt
request if the corresponding condition event register(s)
is(are) set. If the condition event is already set when 1
is written to the condition mask register, an interrupt
request will be issued immediately.
The value 1 enables interrupts.
The register clears to zero on reset.
Unless stated otherwise a block will stop operation
-- 2145424
210
after geQerating an interrupt request and will re-start
operation after either the condition event or the condition
mask register is cleared.
A. 6 . 3 . 3 Event and mask bits
Event bits and mask bits are always grouped into
corresponding bit positions in consecutive bytes in the
memory map (see Table A.9.6 and Table A.17.6). This allows
interrupt service software to use the value read from the
mask registers as a mask for the value in the event
registers to identify which event generated the interrupt.
A. 6. 3 . 4 The chip event and mask
Each chip has a single "global" event bit that
summarizes the event activity on the chip. The chip event
register presents the OR of all the on-chip events that
have 1 in their mask bit.
A 1 in the chip mask bit allows the chip to generate
interrupts. A 0 in the chip mask bit prevents any on-chip
events from generating interrupt requests.
Writing 1 to 0 to the chip event has no effect. It will
only clear when all the events (enabled by a 1 in their
mask bit) have been cleared.
A. 6 . 3 . 5 The irq signal
The irq signal is asserted if both the chip event bit
and the chip event mask are set.
The irq signal is an active low, "open collector" output
which requires an off-chip pull-up resistor. When active
the irq output is pulled down by an impedance of loon or
less.
I will be appreciated that pull-up resistor of
approximately 4kn should be suitable for most applications.
A. 6 . 4 Accessing registers
A. 6. 4 .1 Stopping circuits to enable access
In the present invention, most registers can only
2145g2~
211
uodifi-d if the block wit~ which they are associated is
stopped. Therefore, groups of register~ will normally be
as~ociated with an access register.
The value O in an acce~s register indicates that the
group of registers associated with that access register
should not be modified. Writing 1 to an access register
reguests that a block be stopped. However, the block may
not stop immediately and block's accesc register will hold
the value O until it is stopped.
Accordingly, user software should wait (after writing 1
to request access) until 1 is read from the access
register. If the user writes a value to a configuration
register while its access register is set to 0, the results
are undefined.
A.6.~.2 R-gist-r- holding int-g-r-
The least significant bit of any byte in the memory mapis that associated with the signal data[O].
Registers that hold integers values greater than 8 bits
are split over either 2 or 4 consecutive byte locations in
the memory map. The byte ordering is "big endian" as shown
in Figure 55. However, no assumptions are made about the
order in which bytes are written into multi-byte
registers.
Unused bits in the memory map will return a O when read
except for unused bits in registers holding signed
integers. In this case, the most significant bit of the
register will be sign extended. For example, a 12 bit
signed register will be sign extended to fill a 16 bit
memory map location (two bytes). A 16 bit memory map
location holding a 12 bit unsigned integer will return a O
from its most significant bits.
A.6.4.3 ~-y~ol-d ~ddr-ss loc~tions
In the present invention, certain less frequently
accessed memory map locations have been placed behind
- 2145424
212
''keyhOl~ ". A "keyhole" has two registers associated with
it, a keyhol e address register and a keyhol e data register.
The keyhole address specifies a location within an
extended address space. A read or a write operation to the
keyhole data register accesses the location specified by
the keyhole address register.
After accessing a keyhole data register the associated
keyhole address register increments. Random access within
the extended address space is only possible by writing a
new value to the keyhole address register for each access.
A chip in accordance with the present invention, may
have more than one "keyholed" memory map. There is no
interaction between the different keyholes.
A.6.5 Special registers
A.6.5.1 Unused registers
Registers or bits described as "not used" are locations
in the memory map that have not been used in the current
implementation of the device. In general, the value 0 can
be read from these locations. Writing O to these locations
will have no effect.
As will be appreciated by one of ordinary skill in the
art, in order to maintain compatibility with future
variants of these products, it is recommended that the
user's software should not depend upon values read from the
unused locations. Similarly, when configuring the device,
these locations should either be avoided or set to the
value 0.
A.6.5.2 Reserved regi ters
Similarly, registers or bits described as "reserved" in
the present invention have un-documented effects on the
behavior of the device and should not be accessed.
A.6.5.3 Test registers
Furthermore, registers or bits described as "test
registers~' control various aspects of the device's
,~_ 211S42~
213
testab;,lity. Therefore, these registers have no
application in the normal use of the devices and need not
be accessed by normal device configuration and control
software.
2145429
214
SECTION A.7 Clocks
In accordance wit~ the present inventions, many
different clock~ can be identified in the video decoder
system. Examples of clocks are illustrated in Figure 56.
As data passe~ between different clock regimes within
the video decoder chip-set, it it~ resynchronized (on-chip)
to each new clock. In the present invention, the maximum
frequency of any input clock is 30 ~ . However, one of
ordinary skill in the art will appreciate that other
freguencies, including those greater than 30MHz, may also
be used. On each chip, the microprocessor interface (MPI)
operates asynchronously to the chip clocks. In addition,
the Image ~ormatter can generate a low frequency audio
clock which is synchronous to the decoded video's picture
rate. Accordingly, this clock can be used to provide
audio/video synchronization.
A.7.1 8patial D-cod-r clock ~ignalJ
The Spatial Decoder has two different (and potentially
asynchronous) clock inputs:
Input /
Signal ~arne Descnp~ion
Output
coaed-clock Input Thls c'oct~ conlrols cata ;ranster 'n ;o tne codeC rJata
port ol the Spatial Decoder.
On-chip this clock conuols tne proce,si-,g ol rhe
coder~ r~ata until it reaches the coCed data bu~er.
decoder_clock Input The Cecocter ciock corlrols the malonr.~ ot ~e
processing lunctions cn Ihe Spatlal Decocer.
The oecooer clock also controls the trarster ol data
ou~ o~ 'he Spatial Dec~oer through Its OUtDUt ~ort.
Tabl- A.7.1 Spatial D-cod-r clocks
2145~24
215
A.7.2 Temporal Decoder clock signals
The Temporal Decoder has only one clock input:
Input /
Signal Name Oescription
Output
rlecoCer_clock Input The deco~er clocl~ controls all o~ the processing
functions on the Temporal Decoder.
The decoder clock also controls ;ransfer of data in to
the Temporal Decoder through its input port and out
via it5 output port
Table A.7.2 Temporal Decoder clockfs
A.7.3 Electrical specificationf3
30 MH2
Num. Characturistic Unit Note
Min. Ma~r.
35 Clock period 33 ns
36 Clock high period 13 ns
37 Clock low period 13 ns
Table A.7.3 Input clock requirements
~ 2145924
216
Symbol Paramelet Min. Max. Units
V~ Input logic 'I' voltage 3.65 VOO + 0.5 V
V~L Input logic 'O' voltage GNo - O.S 1.43 V
loz Inputleakagecurrent + 10 ~LA
Table A.7.4 Clock input conditions
A.7.3.1 CMOS leVels
The clock input signals are CMOS inputs. VIHmin is
approx. 70% of Vl)D and V~Lma~ is approx. 30% of VDD. The
values shown in Table A.7.4 are those for VIH and VIL at
their respective worst case VDD. VDD=5. 0+0. 25V.
A.7.3.2 Stability of clocks
In the present invention, clocks used to drive the DRAM
interface and the chip-to-chip interfaces are derived from
the input clock signals. The timing specifications for
these interfaces assume that the input clock timing is
stable to within + 100 ps.
21~5424
.
217
SECT10~ A.8 JTAG
As circuit boards become more densely populated, it is
increasingly difficult to verify the connections between
components by traditional means, such as in-circuit testing
using a bed-of-nails approach. In an attempt to resolve
the access problem and standardize on a methodology, the
Joint Test Action Group (JTAG) was formed. The work of
this group culminated in the "Standard Test Access Port and
Boundary Scan Architecture", now adopted by the IEEE as
standard 1149.1. The Spatial Decoder and Temporal Decoder
comply with this standard.
The standard utilizes a boundary scan chain which
serially connects each digital signal pin on the device.
The test circuitry is transparent in normal operation, but
in test mode the boundary scan chain allows test patterns
to be shifted in, and applied to the pins of the device.
The resultant signals appearing on the circuit board at the
inputs to the JTAG device, may be scanned out and checked
by relatively simple test equipment. By this means, the
inter-component connections can be tested, as can areas of
logic on the circuit board.
All JTAG operations are performed via the Test Access
Port (TAP), which consists of five pins. The trst (Test
Reset) pin resets the JTAG circuitry, to ensure that the
device doesn't power-up in test mode. The tck (Test Clock)
pin is used to clock serial test patterns into the tdi
(Test Data Input) pin, and out of the tdo (Test Data
Output) pin. Lastly, the operational mode of the JTAG
circuitry is set by clocking the appropriate sequence of
bits into the tms (Test Mode Select) pin.
The JTAG standard is extensible to provide for
additional features at the discretion of the chip
manufacturer. On the Spatial Decoder and Temporal Decoder,
2145429
218
there are 9 user instructions, including three JTAG
mandatory instructions. The extra instructions allow a
degree of internal device testing to be performed, and
provide additional external teet flexibility. For example,
all device outputs may be made to float by a simple JTAG
sequence.
For full details of the facilities available and
instructions on how to use the JTAG port, refer to the
following JTAG Applications Notes. --
a.8.l Conn-ction of JTAa pins i~ non-JTAa y-t---
Signal Oirecllon Descnption
trst lnDut This pin has an intemal pull-up. Du~ musl De laken
low at power-up even i~ the JTAG ~ea~ures are not
Deing used. This may De achieved Dy ccnnecting
tr5t in common ~vith the chiD reset pin reseL
tai Input These pirls have interna~ pull-ups. ancl ,.-~y De left
tms d-sconne_'.d i~ bhe JTAG circui'~y is not ~eing used.
tck Input This pin does not have a pull-up, anc sncuid De tled
to ground it the JTAG circuitry is not used.
t~o Curput High impedance excepl Curing JTAG scan
operabons. Ii JTAG is nol Deing used. ~.is pin may
~e len d.~:onne_le~.
Tabl- A.8.1 ~ow to connect JTAG input~
~ 214542~
219
A.8.2 ~evel of Conformance to IEEE 11~9.1
A.8.2.1 Rul~s
All rules are adhered to, although the following should
be noted:
Aules Oescription
3.1.1 (b) The trst pin is provided.
3.5.1(b) Guaranteed tor all public instrucDons (see IEE_ 1149.1
5.2.1 (c)).
5.2.1 (c) Guaranleed ~or all public instrucUons. For some private
instrucoons, the TOO pin may be acDve during any o~ the
states Capture-OR, E~it1-DR, Exit-2-OR ~ Pause-DR.
5.3.1(a) Power on-reset is achieved by us o~ the tirst pin.
62.1 (e.~ A code lor the BYPASS instrucDon is loaded in t~e Tes~-Logic-
Reset state.
7.1.1(d) Un-allocated instrucDon codes are equivalent to 3YPASS.
7.2.1 (c) There is no device lO register.
Table A.8.2 JTAG Rule~
2145421
220
Rul s Oescription
7.9.1(b) Single-step operatlon reCuires external conUol of the system
clock.
7 9 1(~) There is no RUNalST lacility.
7.11.1(.. ) There is no IOCOOE insUuction.
7.12.1(---) There is no USERCOOEinsuuctlon.
8.1.1(b) There is no device ,dc"I,hCation register.
8.2.1 Ic) Guaran~eed ~or all puhlic instructions. The apparent !ength oi
the path ~rom tdi to tdo may change under certain
circumstances while private instruction codes are :oaded.
8.3.1(d-i) Guaranteed tor all public instrucoons. Oata may t)e loaded at
times other than on the rising edge of tck wh!le Frivate
instrucoons codes are loaded.
10 4 1 (e) Ouring INTEST, the system dcck pin must be ConJolled
externally.
10.6.1 (c) Ouring INTEsT~ output pins are controlled by data shlned in via
tdi.
Table A.8.2 JTAG Rule~
A.8.2.2 Recommendation~
Ftec~,.u,,, '; ~ Oescription
3.2.1 (b) tck is a high i~llv-Jdnce CMOS input
3.3.1(C) tms has a high ;~v ddn~e pull-up.
3.6.1 (d) (Applies to use ot chip).
3.7.1(a) (Applies to use oi chip).
6.1.1 (e) The SAMPLE/PRELOAD instruction code is Icadeo cunng
Capture-lR.
7.2.1 (f) The INTEST instrucaon is supported.
7.7.1(9) Zeros are loaded at system output pins dunng EXTES 1.
7.7.2(h) All system outputs may be set high-,-"~,eJ~c6.
.8.1(~) Zeros are loadect at system input pins dunng INTEST~
8.1.1(d e) Oesign-speciFic test data registers are not put~licly a~cese ble
Table A.8.3 Re~ommendations met
~_ 21454~4
221
n~
10.4. 1 (~ During EXTEST, the signal driven into the on-chp logic trom
th syslem clock pin is that supplied e~temally.
Table A.8.4 Recommendations not implemented
A.8.2.3 Permissions
P.. " ,;s~,ons Description
3.2.1(c) Guaranteed lor alt public insuucoons.
6.1.'(') The instrucoon register is not usea to capture des:gn-specific
" ~.
7.2.1(9) Several aC~itionat pubtic instnJctions are provided.
7.3.1(a) Several private instruct~on codes are allocated.
7 3.1 (c) (Rute?) Such instructions codes are documented.
7.4.1(~ Additional codes pertorm identically to EYPASS.
10.1.1 (i) Each output pin has its own 3-state conuol.
10.3. 1 (h) A parallel latch is provid~d.
10.3.1 (i,j) Ouring EXTEST, input pins are controlled by data shitted in via
tdt.
10.6.1 (d,e) 3-state cells are not lorced inactive in the Test-Logic-~eset
state.
Table A.8.5 Permi~ions met
21~5424
222
SECT101~ A.9 Spatial Decoder
30 MH, operation
Decodes MPEG, JPEG & H.261
Coded data rates to 25 Mb/s
Video data rates to 21 MB/s
Flexible chroma sampling formats
Full JPEG baseline decoding
Glue-less DRAM interface
Single +5V supply
208 pin PQFP package
Max. power dissipation 2.5W
Independent coded data and decoder clocks
Uses standard page mode DRAM
The Spatial Decoder is a configurable VLSI decoder chip
for use in a variety of JPEG, MPEG and H.261 picture and
video decoding applications.
In a minimum configuration, with no off-chip DRAM, the
Spatial Decoder is a single chip, high speed JPEG decoder.
Adding DRAM allows the Spatial Decoder to decode JPEG
encoded video pictures. 720x480, 30Hz, 4:2:2 "JPEG video"
can be decoded in real-time.
With the Temporal Decoder Temporal Decoder the Spatial
Decoder can be used to decode H.261 and MPEG (as well as
JPEG). 704x480, 30Hz, 4:2:0 MPEG video can be decoded.
Again, the above values are merely illustrative, by way
of example and not necessarily by way of limitation, of
typical values for one embodiment in accordance with the
present invention. Accordingly, those of ordinary skill in
the art will appreciate that other values and/or ranges may
be used.
~ 214542~
223
A. 9 .1 Spatial Decoder Signals
SignaJ Name UO Pin Number C L
coCed_clock I 182 Coded Oata Po~ Used to supply
coded Cata~7:0] 1 172 171 169 168 167 166 164
coded data or Tokers to th~ Spalial
1 63 Oecoder.
coCed_e~n I 174
See secbor~s A10.1 ar,d
, coded_valid 1 162
coCed_accept O 161 A.4.1
bySe_mode I 176
enaOle~1:0] 1 126,127 MiaoProcessorlntertace(MPI).
1 25
addr~6:01 1 136,135,133,132,131,130,128
Cata(7:0] 0 152,151,149,147, 145,143 141 SeesecSonA61
140
r~ 0 154
DRAM_data[31:0] UO 15, 17, 19, 20, 22, 25, 27, 30, 31, MAM Interlace.
33, 35, 38, 39, 42, 44, 47, 49, 57,
59,61,63,66,68,70,72,74,76,
See secbon A52
79,81,83,84,85
ORAM_addr~10:01 0 184, 186,188, 189, 192, 193,195,
197, 199, 200, 203
RAS O 11
CASf3:0] 0 2, 4, 6, 8
WE O 12
O E 0 204
DRAM_enat~le I 112
oul_Casat8:0] 0 88, 89, 90, 92. 93. 94, 95, 97, 98 Output Port.
out_e~sn 0 87
See secSon A4.1
out_valid 99
out_accept 1 100
tck 1 115 JTAG po~
~i I 116
See section A8
!~o O 120
~ms 1 11
trst 1 121
Table A.9.1 Sp2ttial Decode~ signals
2I4542~
224
S;gna~ Narne UO Pin Number DescriFtion
decoder_clock 1 177 The main deco~er clock. See section
A.~
res t 1 160 Reset.
Table A.9.1 Spatial Decoder signals (contd)
Signal Narne UO Pin Num. Oe~r;ption
tphOish I 1~ l~ overrid- 1 then tphOish and tph1ish are
tph1ish 1 123 inputs lor the on-chip two phasa clock.
override 1 110
For nomlal operaaon set override = O.
tphOish and tph1ish are ignored (so connecl
to GND or VUD~
chiptest 1 111 Set chiptest = O lor normal operation.
tloop 1 114 Connect to GND or VOO duing normal
oPerabon~
ramtest 1 109 It ramtfft = 1 test ol the on~hip RAMs is
ena.Oted.
Set ramtfft = O ~or normal operaOon.
pllsetect 1 178 If pllxbct = O the on-chip phase locked
loops ar disabbd.
Set pllsetect = 1 lor nom~al operation.
ti 1 180 Two clocks requireo t~y the CRAM interface
tq 1 179 during test opertbon.
Connect to G~D or VS~D duing normal
operation.
pdout 207 These two pins are .on.~tio.~s ior an
pdin 1 206 e~ternat filter lo- the phase lock loop.
Tab~e A.9.2 Spatial Decoder Test signals
21~5424
225
Signal Nam _ Pi~ Signal Name Pin Sir~nal Name ~in Signal Name Pln
nc 208 nc 156 nc 104 nc 52
lest pin 207 nc 155 nc 103 nc Sl
les: pin 206 irq 154 nc 102 nc SO
GNO 205 nc 153 VDD 101 ORAM_data(ls~ 43
OE 204 data~7] 152 out_accept 100 nc 4-3
DRAM_addr(O] 203 data~6] lSl out_valid 99 DRAM_data(161 47
VDD 202 nc 150 out_data[O] sa nc 46
nc 201 data[Sl 149 out_data[11 97 GND 45
DRAM_addr[1] 200 nc 148 GND 96 DRAM_data[17~ 44
DRAM_addr~2] 199 data[4] 147 out_datal2J 9S nc 43
GND 198 GNo 146 out_data[31 94 DRAM_data[181 42
DRAM_addr[3] 197 data[31 145 out_datat4l 93 VDD 41
nc 196 nc 144 out_data~S] 92 nc 40
DRAM_addr~4~ 195 data~21 143 VDD 91 DRAM_data[19] 39
VDD 194 nc 142 out_data[61 90 DRAM_data[20] 3a
DRAM_addr~S] 193 datal11 141 out_data~71 89 nc 37
DRAM_addr[6j 192 datalOl 140 out_data~8] 88 GND 36
nc 191 nc 139 out_extn 87 DRAM-data[21l 3i
GNo 190 VDD 132 GND 86 nc 34
DRAM_addr~7] 189 nc 137 DRAM_data~O] 85 DRAM_data(221 33
ORAM_addr(8] 188 addr~61 136 DRAM_datall] 84 VDD 32
VDD 187 addr~5] 135 DRAM_data~21 83 DRAM_data[231 31
DRAM_addrl9] 186 GND 134 VDD 82 DRAM_data[24l 30
nc 185 addr~4] 133 DRAM_datat3] 81 nc 29
ORAM_addr~10] 184 addr~3] 132 nc 80 GND 28
GND 183 addr~21 131 DRAM_data[41 79 ORAM_data(25] 27
codeC_clock 182 addr(l l 130 GND 78 nc 26
VOO 181 VOO 129 nc 77 ORAM_data[26~ 25
test pin 180 addr~O] 128 DRAM_datalSl 76 nc 24
lest pin 179 enaDle~O] 127 nc 7; VDD 23
test pin 178 enaDle[ll 126 DRAM_data[6l 74 DRAM_data(27l 22
decoder_clock 177 rw 125 VOO 73 nc 21
by~e_mode176 GND 124 DRAM datar7j 72 DRAM_data(28] 20
GND 175 test pin 123 nc 71 DRAM_data(29] 19
coaect_e~tn 174 test pin 122 DRAM_data[8l 70 GND 18
Tabie A.g.3 Spatial Decoder Pin Assignments
21~542~
226
Slgrul Name Pin Signal Na~ Pin Signal Name Pln S~nal Name Pin
-
nc 208 nc 156 nc 104 nc 52
tesl pin 207 nc 155 nc 103 nc 51
test pin 206 aq 154 nc t 02 nc 50
GND 205 nc 153 VOO 10t ORAM_datat15j 49
OE 204 datat71 152 out_accept 100 nc 48
DRAM_addr[0l 203 data~6] 151 out_valid g9 0RAM-data[16i 47
VD0 202 nc 150 out_data[01 98 nc 46
nc 201 data~S; 149 out_data(1] 97 GND 45
DRAM_addr~11 200 nc 14t GN0 96 ORAM_dataf17] 44
DRAM_addr~2] 1g9 data~4] 147 out_data~2] 9S nc 43
GNO 198 GND 146 out_da~a(31 94 0RAM_data~181 42
DRAM_addrl3l 197 data~3j 145 out_data~41 93 VDD 41
nc 196 nc 144 out_Cata~il 92 nc 40
DRAM_addr~4] 195 data~2] 143 VOD 91 ORAM_data~19] 39
VOD 194 nc 142 ou~data[6] 90 ORAM_data[20] 38
DRAM_addrlS~ 193 dataf1] 141 out_data,7] eg nc 37
ORAM_addr~6] 192 data~0] 140 out_data~8] 88 GNO 36
nc 191 nc 139 ou~extn 87 0RAM_data~21] 35
GNO 190 VOD 138 GNO 86 nc 34
ORAM_addf~71 189 nc 137 DRAM_datat0] 85 DRAM_data~22] 33
ORAM_addr~tl 1 t8 addr~61 136 DRAM_datal1 l a4 VDO 32
VOO 187 addr~S] 135 DRAM_data~2] a3 DRAM_dataf231 31
DFtAM_addr~9] 1t6 GNO 134 VOO 82 DRAM_datat24] 30
nc 185 addt~4] 133 ORAM_data~31 81 nc 29
DRAM_addr[10] 184 addf(31 132 nc 80 GND 28
GNO 183 addrl2~ 131 DRAM_data~4] 79 DRAM_dataj25] 27
coded_dock 182 addr~11 130 GND 78 nc 26
VOO . 1t1 VOO 129 nc 77 DRAM_data[26] 25
test pin 1t0 addr~'01 12t ORAM_datalS] 76 nc 24
test pin 179 enable~01 127 nc 75 VOD 23
test pin 178 ena,~e(1~ 126 ORAM_data,'6] 74 DRAM_datat27] 22
deccdef_clcck 177 rw 125 VOO 73 nc 21
t~yte_mode 176 GND 124 ORAM_data,f7~ 72 ORAM_data[29] 20
GND 175 testpin 123 nc 71 DRAM_data,291 15
cs~ded_estn 174 testpin 122 ORAM_data~8] 70 GND
Tab~e A.9.3 Spatial Decoder Pin Assignments
- 2145424
227
Sigral Nam~ P~n S;gnal Name Pin Signal Narne ~in S~gna~ Narne Pin
nc 173 trst 12t GND 69 DRAM_data(301 17
CoCed_data(7 172 tdo 120 O~M_data~91 68 nc 16
coded_data(61 171 nc 119 nc 67 CRAM_da~a(311 l5
vOO 170 VOO 118 DRAM_data[101 66 ~/D0 14
coded-datatsl 169 ttTU 117 VO0 6i nc 13
coded_catat43 168 tdi 116 x 64 ~E 12
c~ced-datat3l 167 tc~ 115 ORAM_data~ 63 ~ 11coded_Cata[21 166 tcstpin 114 nc 62 nc lO
GN0 165 GN0 113 ORAM_~ata~12] 61 GN0 9
coded_da;at l 1 164 OR~M_~nat~le 112 GN0 60 ~[1 8
:oded_data(OI 163 test pin 111 O~M_data~131 S9 nc 7
~oded_valid 162 test pin 110 nc SS ~tll 6
~ded_acceot 161 test pin 109 DFiAM_data[141 57 VD0 5
reset 160 nc 10B VOO j6 ~;21
vOO 159 nc 107 nc SS nc 3
nc 158 nc 106 ne 54 ~[31 2
nc 157 nc 105 nc i3 nc
Table A.9.3 Spatial Decoder Pin Assignments (contd)
A.9.1.1 "nc" no connect pins
The pins labeled nc in Table A.9.3 are not currently
used these pins should be left unconnected.
A.9.1.2 Vt~ and GND pins
As will be appreciated by one of ordinary skill in the
art, all the V,,,, and GND pins provided should be connected
to the appropriate power supply. Correct device operation
~` 2145424
228
cannot ke ensured unless all the V~ and GND pins are
correctly used.
A. 9 .1. 3 Test pin connections for normal operation
Nine pins on the Spatial Decoder are reserved for
internal test use.
Pin numtxt Connectlon
Connect ~o GNO tot norrnal operabon
Connect to VOO tor normal oCeration
~eave Open Grcuit lor morrnal overation
Table A. 9 . 4 Default test pin connections
A.9.1.4 JTAG pins for normal operation
See section A.8.1.
2145424
229
A. 9 . 2 Bp/atial Decoder memory map
Addr (hex) RegisSff Name See tat~le
OxO0 Ox03 InterruDt #rvice area A 9 6
OxO4 Ox07 Input circuit registers A 9 7
Ox08 OxOF SSancoded bctorregisters
Ox~0 Ox15 BunersSarl-upconSrolregisters A98
Ox16 Ox17 Not used
Ox18 Ox23 DRAM intcrtac configuration registers A 9 9
0~4 Ox26 Bu~er rnanag r ~s5 and keyhole registers A 9 1 C
Ox27 Not used
0~28 Ox2F Hunman decoderregisters A 9 13
Ox30 Ox39 Inverse qu ntiser registers A 9 14
Ox3A Ox3B Not used
Ox3C Reservcd
Ox30 0~3F Not uscd
Ox40 Ox7F Test registers
Tab~e A.9.5 Ovc. ~;c-: of Spatial Decoder memory map
2145~24
230
Addr sa
~ -- Aeg~ter Nan~ Page relerences
the~ num
OxOO 7 chip_ vent CEO_EVEN7 0
6 not used
5 Illegal_length_count_event
SCO_ILLEGAL_LENGTH COUNT
4 reserved mty read 1 or 0
SCO_JPEG_OVERLAPF~lNG_STAflT
3 C ~e~ br r ~9_St n_eVellt
SCD-NoN-JpEG-ovERuf~plNG-sTAf1T
2 Ln;e;~ iseJ_start_ev nt
SCO_UNF1ECOGNlSED_SrAl~T
stop_atter_picture_event
SCO_STOP_Af TER_PICTVf1E
0 non_allgned_sUrt_event
SCO_NON ALlGNEO_STAf'~T
0~01 7 chTp_rnask CED_MASI~_0
6 nol used
5 Illegal_length_count_mask
4 reserved wrile 0 to this location
SCO_JPEG_OV~flUPPlNG_STAf1T
3 nonJpeg_ ~ ! 1, r' g_st rt_n~sk
2 L~r~ ~31~ _st rt_mask
stop_aner_plctu-e_mask
O non_aligned_start_m~sk
Ox02 7 Idct_too_lew_event IOCT DEFF NUM
6 idct_too_rn ny_event IDCT SUPER_NUM
5 accept_enahle_event BS_STREAM_ENO_EVENT
4 arget_n et_event Bs-TAJ~GET-MET-EvENr
3 counter_flusheo_too_ea 1y_ewnt
ES_FLVSH BEFof~fE TAFiGEJ_MET EVEM
2 counter_flusl ed_event 55_fLUStl_EVENT
parser_event OEMUX_EVENT
O huttrnan_event HUFfMAN_f VENT
Table A.9.6 Interrupt service area registers
~ 21~5~24
23
Ar~r ~n
Register Name Page .~ r_o.e.s
(he~) num
0~03 7 ~da_too_~ew_mask
6 idct_too_many_mask
accept_enable_mask
4 target_met_mask
3 eounter_~lush-d_too_carly_mask
2 counter_~lushed_mask
parser_mask
O hu~man_mask
Table A.9.6 Interrupt service area registers (contd)
21~5~24
232
AddrBa
Register Name Page ,~lo;onces
(hex~ num
OxO4 7 coded_busy
6 enabl_mpl_lnput
5 coded_estn
4 0 ~ot uset
OxO57 0 coded_daU
Ox06 7 0 not used
Ox07 7 0 not used
OxO~ 7 1 not used
0 surt_code_d~bcto_acc~
also input-clrcuit-accffs
CEO_SCO_ACCESS
oYO9 7:4 nolu#d c~o-sco-co~rFloL
3 stop_~tter_pictu~-
2 disc rd_e~ension_daU
dlscard_user_daU
0 Ignore_non_aligned
OxOA 7:5 nolused C~O_SCD_STATUS
4 insert_sequenoe_start
3 discard_all_d Sa
2 0 surt-code-#arch
Tab~e A.9.7 Start code detector and input circuit registers
2145~24
233
AdCr. ait
Regist Name Pa9e ~E~ ncei
(hex) num
Ox087 0 Tesl regist iengt~l_count
OxOC7:0
OxO~7 2 not used
1 0 start_code_detector_coding_standard
OxOE7 0 start_value
OxOF7 4 nol used
3 0 plcture_number
Table A.9.7 Start code det~,_tor and input circuit registers (contd)
Addr Bit
Regist Name Page re~erences
(hex) num
oxlo 71 notused
0 startup_acces CEO_BS_ACCESS
Ox 11 7 3 not used
2 0 bit_count_presr;al- CEO_ES_P~ESCALE
Ox12 7 0 bit_count_brg~t CEO_BS_rAF1~ET
Ox13 7 0 bit_count CEO_SS_COUNT
0X14 7 1 not used
0 o~chip_qwue CEO_BS_OUEUE
ox ~ 5 71 not used
O enab~_stream CEO BS_ENABLE_NXT snu
Table A.9.8 Buffer start-up regi~ers
-- 214542~
234
Addr. Bit
Register r ame Page r~k.tn.,e
(hex~ num.
Ox l 8 7:5 no~ used
4:0 page_sUrt_kngth
C~D_lT PAGE SrA~r LENGJH
Oxl9 7:4 not used
3:0 read_cyck_kngth
OxlA 7:4 nol usod
3:0 write_cycb_bngth
TableA.9.9 DRAMin'~ I :econf7gurationr~gist~.s
214542~
235
AddrBit
Re~gister Name Page relerences
(hex) num
Ox1~7 4 nol t~d
3 0 re~resh_cych_kngth
Ox1C?4 notused
3 0 CAS_lalling
Ox107 4 not U#d
3 0 RASplling
Ox1E71 notus d
0 Interhce_tlming_access
OxlF70 ret~sh_lnter,val
Ox20 7 not used
6 4 Dn~M_addr_strength~2 0
3 1 CAS_str~ngth[2 0]
O RAS_st . ~ t2
Ox217 6 RAS_ trengthl1 0
5 3 OEWE_-t J~12 0
2 0 DRAM_d ta_strent~ 2:01
Ox22 7 ACCEssbit~orp~dstr~thelt ?not
usedCED_DRAM_CONFlGVRE
6 ~ero_butlers
S DRAM_enabh
4 no_re1r sh
32 row_address_bltsl1 0]
10 DRAbl_d U_wldth~l:O]
Ox23 7 0 Test registers CED_PLLAES_CONflG
Table A.9.9 DRAM i"t~ 20e configuration registe, s (contd)
Addn 5it
Register Narne Page relerences
(hex) nurr~
Ox24 71 no~
O but~er_rnan ger_access
Ox25 7 6 not used
5:0 buner rnanager_ke~1hole_address
ox26 7 0 butter_rr nager_xe~hole_da~a
Table A.9.10 3uffer manager access and keyhole registers
~145~2~
236
~adt ~it
_ ~ t~eg~st rNarne Pagereterences
(hex) num
OxO0 7 0 not u#d
OxOl ~ 2
1 0 cdb_~se
Ox02 ~ 0
Ox03 7 0
Ox04 7 0 not used
Ox05 ~ 2
1 0 cdb_kngth
Ox06 ~ 0
OxO~ ~:0
Ox08 7 0 not used
OxO9 7 0 cdb_read
OxOA 7 0
OxOS 7:0
OxOC 7 0 not used
OxOD 7 0 crdb_numb r
OxOE 7 0
OxOF 7 0
Ox l 0 7 0 not u#d
Oxll 70 sb_ba#
Ox12 7 0
Ox13 7D
Oxl4 7 0 nol used
Ox15 7 0 tb_bngU
Oxl6 7 0
Ox17 7:0
Ox18 7 0 not used
Ox19 70 tb_r ard
Ox1 A 7 0
Ox1 ~ ~:0
Ox1C 7 O not used
Ox13 7 0 Sb_number
ox1E 70
Ox1F 7o
Table A.9.11 Buffer manager extended address s~ace
~145~24
237
~ddr_. Ba
Regisler Narne Page reletences
th s) num.
Os~O 7 0 nol used
Ox21 7 O but~er_limit
Ox22 7 O
Ox23 7 O
Ox24 7:4 nol used
3 cdb_~ull
2 cdb_empty
tb_full
O tb_empty
Table A.9.11 Buffer --anager extended address space (contd)
Add-. Bit
Regisler Narne Page relerences
(hex)nun~
Ox28 7 demux_acces~ C~O_H CrRL~7
6:4huttman_e~or_code 2:01 CED_I-l_CTRL~fi41
3:0 prrva~ huttrrun control bhs t31 #lects s?ecial
CBP t21 sdects 4/8 bit fixed length CEP
OS29 7:0 p r#r_error_code CEO_H_OMUX_ERR
Os2A 7:4 nol us~d
30 rJ mux_~eyhok_address
Ox2B 7~ CED H KEYHOLE_AOOR
O~C 7.0 rJemux_~ob_tata CEO_~_KEY~OLE
Os2D 7 dummy_bst_plcture CED_~_ALV_REG0,
r dumny ~s~rame_bit
6 ~ield_lnto cEo-~-ALu-R~Go~t-reld-in~o-bn
5:1 nol used
o contlnu- CEO_H ALU_REG0,r_conbnue on
O~E 7:0 rom_r~v~lon CED_~ ALV_REGl
Ox2F 7:0 prr~ale regisler
Table A.9.12 Video demux registers
~ ~145424
238
Addr. Bit
R gisler Name Page r~ _x~;
(tle~) num.
O~F 7 CED_H_TRACE_VENT write 1 to single step. one
will t~ read when the step has been completed
6 CED_H_TRACE_MASK set to one to enter single
step mode
S CED_H_TRACE_RST partial reset when sequenced
1,0
4:0 not u#d
Table A.9.12 Video demux regi~ters (contd)
-
2145~29
.
239
ACdt. Bit
Regis;er Name Page relerences
(hex) num.
Oxoo 7:0 not used
OxOF
OxlO 7:0 hork_pels r honvck
Ox1 1 7:0
Ox12 7:0 vert_pels r_verLpets
Ox 1 3 7:0
ox 14 7 2 nol used
1:0 bufler_size r b~tter_sizs
OxlS 7:0
Ox16 7:4 not used
3:0 pel_aspect r Del ast~ect
Ox 17 7:2 not used
1 0 bit_rate r_bi~ah
Ox18 7:0
Ox19 7:0
Ox 1 A 7:4 not us~d
3:0 pic_r te r oic_rate
Ox1B 7:1 notused
O c ~r ~ r-cLJl ~a~
OxlC 7:0 picture_type
Oxl D 7:0 h261_pic_type
Table A.9.13 Video demux extended address space (Sheet 1 of ô)
2145424
240
Addr8it
Regist rN~ Page ele~ ee
(hex) num~
Ox1 E 7 2 nol us d
1 0 ho~en_closed
Ox1F7 5 not used
40 p ~t ~ ~_mode
Ox207 0 vbv_delay
7:0
oX227 0 private regisler MPEG full_oel_fwd JPEG
pendin~ frarne_chanqo
Ox2370 privateregisterMPEGfull_oel_bwd JPEG
rcstart_index
OX247 0 prrvate register horiz_mb_copy
Ox257 0 plc_number
Ox2671 not used
1 0 rnax_h
Ox2771 not used
1 :0 rnax_v
Ox287 0 priva~e regisler scratch1
Q~ 7 0 pnvab register scratch2
Ox2A7 0 private register scratch3
Ox287 0 f!n MPEG unused1 H261 ingob
ox2C' pnvate regist r MPEG ~Irs~7roup JPEG first_sc~
Ox2D7 0 private register MPEG in~re
Ox2E 7 durnmy_bst_picture r rom_con~l
6 rleld_lnto
5 1 not used
O conlinue
0~2F7:0 rom_revklon
ox~o7~ notus d
1 :0 dc_hun_O
Ox317 ~ not used
1 0 dc_hutt 1
Ox327 ~ notused
1 0 dc_hut~_2
Taf~le A.9.13 Video demux extended address SpaCe (Sheet 2 of 8)
~ 214542~
241
Addr. Bit
~ Regisler Name Page re~erences
(h~x) nurrL
0~33 7 2 not used
1 :0 dc_hutl_3
Ox3`4 7 2 not usfft
1 O aC-hutt-o
Ox35 7~ not used
1:0 ac-hun-1 !
Ox36 7 2 not used
1 0 ac_hun_2
Ox37 7 2 not used
1.0 ac_hun_3
Ox38 7 2 not used
1:o tQort~O
Ox39 7:2 not used
1:0 t~_1 r tQ 1
Ox3A 7 '7 not used
1 o t~_2 r to 2
Ox39 7 ~ nct used
1:0 t~_3 r t~3
Ox3C 7.0 c p 2 ~ ~ . _name_0 r_c_0
Ox30 7:0 :~-F-~- I_n me_1 r c_1
Ox3E 7 0 c , ~ _name_2 r_c_2
Ox3F 7 0 ~ _n~rne_3 r c_3
Ox40 7:0 pnvat regis~ers
Ox63
Ox40 7 0 r_dc_Dred_0
Ox41 7.0
Ox42 7uO r_dc_ored_1
Ox43 7:0
Ox44 7:0 r_dc_prcd_2
Ox45 7 o
Ox46 7 0 r_dc~Dred_3
Ox4~ 7:0
Ox48 7:0 not use~
Ox4F
Tab~e A.g.13 Video demux extended address space (Sheet 3 of 8)
~_ 214542~
242
Addr. Bit
Register Name Page relerertce5
(hex) num.
Ox50 7 0 r_prev_mh~
OxS1 7:0
OxS2 7.0 r_prev_mv~
OxS3 7 0
OxS4 7:0 r_prev_mhb
OxSi 7 0
OxS6 7:0 r_prev_mvb
OxS7 7:0
OXSf3 7.~ nol used
OxSF
Ox60 7.0 r_horiz_mbcnl
Ox6 l 7:0
Ox62 7:0 r_ver~mbent
Ox63 7.0
Ox64 7:0 hork_,~c~ k ' ' r_hork_mbs
Ox65 7:0
Ox66 70 vert_~..acl,b': :' r_vert_mbs
Ox67 7:0
Ox6a 7:0 private regis;er r_restar~_cnt
Ox69 7:0
Ox6A 7:0 rffsart_lnbnral r_restatt_int
Ox68 7:0
Ox6C 7:0 private register r_blk_h_cnt
Ox6D 7:0 private regista r_blk_v_cnt
Ox6E 7:0 prrvate register r_compid
Ox6F 7 0 rrux_c:--F~n~ .t_id r_max_compid
Ox70 7:0 coding_sUndard r_codin std
Ox71 7:0 prrvale regista r_pattem
Ox72 7 0 pttvate tegist r_twd_t_size
Ox73 7:0 private register r_bwd_r_size
Ox74 7:0 not used
Ox77
Ox78 7 2 not utsed
1:0 blocks_h_0 r_blk_h_0
Tab~e A.9.13 Video demux ext~nded address s3ace (Sheet 4 of 8)
` 214542g
243
ACdr~ a I
Register ame Page reterenc
(hex) nurr~
Ox79 7 2 not used
1 0 blocks_h_1 r_blk_h_1
Ox7A 7 2 not llsed
1:0 blocks_h_2 r_blk_h_2
Ox7a 7 2 not used
1:0 blocks_h_3 r_blk_h_3
Ox7C 7 ~ not used
1:0 blccks_v_O t_blk_vQ
Ox7D 7 2 not used
1:0 blocks_v_1 r_blk_v_1
Ox7E 7:2 not used
1:0 btocks_v_2 r_blk_v_2
Ox7F 7:2 not used
1:0 blocks_v_3 _blk_v_3
Ox7F 7:0 not used
OxFF
Ox100 7:0 dc_bits_Ot15:01 CED_H_KEY_DC_CPBO
Ox1 OF
OxllO 7:0 dc_bits_1t15:0]CED_H_KEY_DC_CPB1
Ox11F
ox120 7:0 not used
Ox13F
Ox140 7:0 ac_bits_O[15:01 CED_H_KEY-Ac-cpBo
Ox1 4F
Ox150 7:0 ac_bits_1~15:0~ CED_H_KEY_AC_CPB1
Ox 1 5F
Ox160 7:0 not used
Ox1 7F
Ox180 7:0 dc_~sss_OCED_H_KEY_ZSSSS_lNDEX0
Ox181 7:0 dc_ ssss_1 CED_H_KEY_ZSSSS_INDEX1
Ox182 7:0 not used
0~187
Ox188 7:0 c_eob_O CED_H_KEY_EOa_lNDEXO
Tab~e A.9.13 Video demux e~nde~ address space (Sheet S ot 8)
214542~
244
Addr, Bn
Regis~er Name Pase reference5
(I ex) num.
0x189 7:0 ~c_eob_1 CED-H-KEy-EoB-lNDEx1
0x1 8A 7 0 not used
OX1eB
0x18C 7:0 ac_zrl_0 CED_H_KEY_ZRL_INOEX0
0x180 7:0 c_zrt_1 CED_H_KEY_ZRL_INDEXl
0x18E 7:0 nol used
0x1 FF
0x200 7:0 ~c_huthal_0[161:0] CED-H-KEy-Ac-lToo-o
0x2AF
0x2B0 7 0 dc-hu~tval-o~11:o~ CED_H_KEY_DC_lTOD_o
0x2BF
0x2C0 7:0 no~ used
0x2FF
0x300 7:0 ~c_hutfval_1[161:0~ CED_H_KEY_AC_ITOO_l
0x3AF
0x3B0 7:0 oc_huttval_1t11:0~ CED_H_KEY_DC_ITOO_l
0x3BF
0x3C0 7:0 nol used
0x7FF
0x800 7:0 priv teregisters
0xAC
F
0x800 7:0 CED_KEY_TCOEFF_CPB
0x80F
0x810 7:0 CED_KEY_CBP_CPB
0x81 F
0x820 7:0 CED_KEY_MBA_CP3
0x82F
0x830 7:0 CED_KEY_MVD_CP9
0x83F
oxa40 7:0 CED_KEY_MTYPE_I_CPB
0x84F
Taf~e A.9.13 Video demuX extended address space (Sheet 6 o~ 8)
2145424
Addr. 8rt
Reç~ta Name Pasercl~
~x) nu~
0~850 7:0 CED_KEY_MrYpE-p-cpB
0~85F
0~860 7:0 CED_KEY_MTYPE_B_CPB
0x86F
0~870 7:0 CED_KEY_MTYPE_H26t_CP8
OY88F
OY880 7:0 notu#d
Ox900
0~01 7:0 CED_KEY_HDSTROM_0
0~02 7:0 CED_KEY_HDSTPOM_1
0~03 7:0 CED_KEY_HDSTROM_2
a~OF
0~10 7:0 notu~d
0xAB
F
~C 7:0 CED_KEY_DMX_WORD_0
o
OxAC 7:0 CED_KEY_DMX_WORD_1
OxAC 7:0 CED_KEY_OMX_WORD_2
OxAC 7:0 CED_KEY_DMX_WORO_3
0xAC 7:0 CED_KEY_DMX_WORD_4
OxAC 7:0 CED_KEY_DMX_WORD_S
.
OYAC 7:0 CED_KEY_DMX_WORD_6
~AC 7:0 CED_KEY_DMX_WORD_7
Tab~e A.9.13 Video demuxe~cndcd address s~ace(Sheet7 ot8)
~145424
246
ACdr. Bit
Regist Name Page relerences
(hex) num.
OXAC 7:0 CED_KEY_DMX_WORD_8
a
OxAC 7:0 CED_KEY_DMX_WORD_9
OxAC 7:0 nct used
A
OxAC
OxAC 7:0 CED_KEY_DMX_AINCR
C
OxAC 7:0
D
OxAC 7:0 CED_KEY_DMX_CC
E
O~AC 7:0
F
Table A.9.13 Video demux extended address space (Sheet 8 Ot 8)
Addr. Bit
Rqister Narne Page relerences
(hex) nurn.
7:1 nol used
Ox30 7:1 not used
O IQaccess
Ox3l 7 2 not U#C
1 :O Iq coding_sanCard
Ox32 7:5 not u#d
4:0 tcst register io scale
ox33 7 ~ notu#d
1:0 tes~ register iq_co~ . r s
ox34 7 o not u#d
1:0 test regisler inverse_r~uantiser_r~redic5ion_mod~
Ox3s 7:0 l~st reg~slerlpeg ;.. '' ~_U.~,~
Table A.9.14 ~nverse qUantiser registers
219542~
247
Accr. Ba
Regisler Narne Pase rele~ences
(hex) num.
Ox36 7 2 nolused
1:0 test register m~eg_indi,cotion
Ox37 7:û not used
Ox38- 7:0 iQt!able_keyhole_acdress
Ox39 7:0 Iq_tabl~_keyhole_dat~a
Table A.9.14 Inverse quantizer regi~ter~ (contd)
AdCr.
Register Name Pa5e references
(hex)
OxOO:Ox3F JPEG Inverse quantlsaDon table 0
MPEG delault intrt table
Ox40:0x7F JPEG Inverse quantlsanon table 1
MPEG delault non-intra table
Ox80:0xgf JPEG Inverse quantisation table 2
MPEG down-loaded intra table
OxCO:OxFF JPEG Inverse quanosation table 3
MPEG down-loaded non-intra table
Table A.9.15 Iq table extended addres~ ~pace
~145424
248
SECTION A.10 Coded data input
The system in accordance with the present invention,
must know what video standard is being input for
processing. Thereafter, the system can accept either pre-
existing Tokens or raw byte data which is then placed intoTokens by the Start Code Detector.
Consequently, coded data and configuration Tokens can be
supplied to the Spatial Decoder via two routes:
The coded data input port
The microprocessor interface (MPI)
The choice over which route(s) to use will depend upon
the application and system environment. For example, at
low data rates it might be possible to use a single
microprocessor to both control the decoder chip-set and to
do the system bitstream de-multiplexing. In this case, it
may be possible to do the coded data input via the MPI.
Alternatively, a high coded data rate might require that
coded data be supplied via the coded data port.
In some applications it may be appropriate to employee a
mixture of MPI and coded data port input.
~14542`4
249
A.lo. -~he coded data port
Input /
Signal Narne Oexription
OUtPtJt
coded_clockInput A clock operating at up lo 30 MHz controlling tt^,e
op-ration o~ the input cirwit
coded_data[7 01 Input Th- stuldard 11 wires required to implement a
cod-d_estn Input Token Pon t,~ " 'I ,i"g 8 bit dala values See sect on
cod-d valldInput
A 4 ~or an electrical desc,ivt)on o~ this
coded_accept O~JtPUt
intertace
Circuits otl-chip must pac~age ~e coded data into
Tokens
byte_mod- Input When high this signal indicales that iniorrnation is to
be t~dn ' ,.d across the coded data port in ~yTe
mode rather than roken mode.
Table A.10.1 Coded data port ~ignals
~145~24
-
250
The ~coded data port in accordance with the present
invention, can be operated in two modes: Token mode and
byte mode.
A. ~0.1.1 Token mode
In the present invention, if byte_mode is low, then the
coded data port operates as a Token Port in the normal way
and accepts Tokens under the control of coded_valid and
coded_accept. See section A.4 for details of the
electrical operation of this interface.
The signal byte_mode is sampled at the same time as data
[7:0~, coded_extn and coded_valid, i.e., on the rising edge
of coded_clock.
A. 10 . 1 . 2 Byte mode
If, however, byte_mode is high, then a byte of data is
transferred on data[7:0] under the control of the two wire
interface control signals coded_valid and coded_accept. In
this case, coded_extn is ignored. The bytes are
subsequently assembled on-chip into DATA Tokens until the
input mode is changed.
l)First word ("Head") of Token supplied in token mode.
2)Last word of Token supplied (coded_extn goes low).
3)First byte of data supplied in byte mode. A new
DATA Token is automatically created on-chip.
A. 10 . 2 Supplying data via the MPI
Tokens can be supplied to the Spatial decoder via the
MPI by accessing the coded data input registers.
A.lO.2.l Writing Tokens via the MPI
The coded data registers of the present invention are
grouped into two bytes in the memory map to allow for
efficient data transfer. The 8 data bits, coded_data~7:01,
are in one location and the control registers, coded_busy,
enable_mpi_input and coded_extn are in a second location.
2145424
251
(Se~Table A.9.7).
When configured for Token input via the MPI, the current
Token is extended with the current value of coded_extn each
time a value is written into coded_data[7:0]. Software is
responsible for setting coded_extn to 0 before the last
word of any Token is written to coded_data[7:0].
For example, a DATA Token is started by writing 1 into
coded_extn and then Ox04 into coded_data[7:0]. The start
of this new DATA Token then passes into the Spatial Decoder
for processing.
Each time a new 8 bit value is written to
coded_data[7:0j, the current Token is extended. Coded_extn
need only be accessed again when terminating the current
Token, e.g. to introduce another Token. The last word of
the current Token is indicated by writing 0 to coded_extn
followed by writing the last word of the current Token into
coded data~7:0].
Regis~er name ~ ", Oescription
~r.i
coaea-e~tn 1 ~ Tokens can be SuDpliea ~o Ihe Scatlal Oecocer
rw via the MPI oy wriong to these reglstets
cocea_aat~al7 0] 3
w
coaea-busy 1 1 rne state ot this reglSters Inclcales ~M~e
r Spatial Decoder is aole to accep~ Tokens
written into cod~d_daLa~7 0
~he value l indicates that Lhe interlace is bus
and unable to accept data Behaviour is
undefined it the user tnes to write lo
coded_dat~ 0l when codea_busy = l
enable_mpl_input l û The value in this tunction enable reglsters
rw controls wh-ther coded data input ;o the Soaba!
Oecoder is via the codea daLa pon ~o) or via~e
MPI (1)
Table A.10.2 Coded data input registers
-- ~14~424
252
Eacb time before writing to coded_data[7:0~, coded_busy
should be inspected to see if the interface is ready to
accept more data.
A.10.3 Switching between input modes
Provided suitable precautions are observed, it is
possible to dynamically change the data input mode. In
general, the transfer of a Token via any one route should
be completed before switching modes.
Previous mode Next Moae 9ehaviour
9yte Token The on~hip circuitry will use the last byte suppiieC ;n
MPI input byte mode as the last byte ot the DATA Token t,'a:
i~ was constructing (i.e. the extn bit wlll be set ~o ~).
9efore accepting the ne~t Token.
Table A.10.3 Switching data input modes
-- 2145424
253
P-evlots mo~e Next Mode aehaviour
,oken 3~ he On~hlp clrcultry sUDplying ~e ,o~en In Token
mo~e is ~r 5pcn5~0'e lor comDie; rs: e T oken (i e.
wlth t~le e~tn t~,( o~ ~he last Oy-~e o~ ;n~r~atlcn set 'o
O) ~efore selec~:ng t~yte mo~e.
MPI In~ut Access ;o input vla the MPI Wlll nct ~e ~ran~e~ ii.e.
c~ed_busy ~11 emaln se, ;o 1) ~,nil the On~!:D
circuitry suDDlxins :he Token in ~en--oCe ~as
comp~eled the To~en (i.e. With :he e~t,~ '~It of Ule !as~
byte o~ i"t~",~ion se~ to 0).
MPI input 8yte ~he conUof so~a o musl have ~srr.~le'ec ~e
MPI input Token ~i.e. ~th the extn bit o~ the la5~ by~e ~
,~lo,~,...tion set to O) be~ore enable_mpi_inp~t is set
to 0.
Table A.10.3 switching data input modes (contd)
The first byte supplied in byte mode causes a DATA Token
header to be generated on-chip. Any further bytes
transferred in byte mode are thereafter appended to this
5 DATA Token until the input mode changes. Recall, DATA
Tokens can contain as many bits as are necessary.
The MPI register bit, coded busy, and the signal,
coded_accept, indicate on which interface the Spatial
decoder is willing to accept data. Correct observation of
these signals ensures that no data is lost.
A.10.4 Rate of accepting coded data
In the present invention, the input circuit passes
Tokens to the Start Code Detector (see section A.ll). The
Start code Detector analyses data in the DATA Tokens bit
serially. The Detector's normal rate of
2145421
254
processii~g is one bit per clock cycle (of coded_clock).
Accordingly, it will typically decode a byte of coded data
every 8 cycles of coded_clock. However, extra processing
cycles are occasionally required, e.g., when a non-DATA
Token is supplied or when a start code is encountered in
the coded data. When such an event occurs, the Start Code
Detector will, for a short time, be unable to accept more
information.
After the Start Code Detector, data passes into a first
logical coded data buffer. If this buffer fills, then the
Start Code Detector will be unable to accept more
information.
Consequently, no more coded data tor other Tokens) will
be accepted on either the coded data port, or via the MPI,
while the Start Code Detector is unable to accept more
information. This will be indicated by the state of the
signal coded_accept and the register coded_busy.
By using coded_accept and/or coded_busy,the user is
guaranteed that no coded information will be lost.
However, as will be appreciated by one of ordinary skill in
the art, the system must either be able to buffer newly
arriving coded data (or stop new data for arriving) if the
Spatial decoder is unable to accept data.
A.10.5 Coded data cloc~
In accordance with the present invention, the coded data
port, the input circuit and other functions in the Spatial
Decoder are controlled by coded_clock. Furthermore, this
clock can be asynchronous to the main decoder_clock. Data
transfer is synchronized to decoder_clock on-chip.
_ ~145~24
255
SECTION A.ll Start code detector
A.11.1 Start codes
As is well known in the art, MPEG and H.261 coded video
streams contain identifiable bit patterns called start
codes. A similar function is served in JPEG by marker
codes. Start/marker codes identify significant parts of
the syntax of the coded data stream. The analysis of
start/marker codes performed by the Start Code Detector is
the first stage in parsing the coded data. The Start Code
Detector is the first block on the Spatial Decoder
following the input circuit.
The start/marker code patterns are designed so that they
can be identified without decoding the entire bitstream.
Thus, they can be used in accordance with the present
invention, to help with error recovery and decoder start-
up. The Start Code Detector provides facilities to detect
errors in the coded data construction and to assist the
start-up of the decoder.
A.11.2 Start code detector registers
As previously discussed, many of the Start Code Detector
registers are in constant use by the Start Code Detector.
So, accessing these registers will be unreliable if the
Start Code Detector is processing data. The user is
responsible for ensuring that the Start Code Detector is
halted before accessing its registers.
The register start_code_detector_access is used to halt
the Start Code Detector and so allow access to its
registers. The Start Code Detector will halt after it
generates an interrupt.
There are further constraints on when the start code
search and discard all data modes can be initiated. These
are described in A.11.8 and A.11.5.1.
~ 21i~5-424
256
Register name ~ c, Descr p~ion
start_corJe_d-t~ctor_access 1 0 Writing 1 to this regls;er requests ;hat the s;an
rw code detector 5tOp tO allo~-v access to i;s
registers. ' he user snould walt un~il ~e value t
can be read ~rom U~.is rec,ister indicating ...at
oDeration has stoDped and access is possibie.
Ta~le A.11.1 Start code detector
registers (Sheet 1 of s)
~ 2145~2~
257
Register name Q O Oescnption
illegal_lengtn_count_event 1 0 An illegal length count event wlll occur ~ wn ie
rw decoding JPEG data a length co-;nt fie~d :s
illegal_length_count_rnask 1 O lound carrymg a value less than 2. ~his Should
only occur as the result ol an error in the JPEG
data.
Il Ihe mask register is set to 1 then an interruFt
can be generated and the start code Cetec:or
will stop. 8ehaviour lollowing an error is not
pr~: t e il this error is suppressed (mas~
register set to O). See A. 11 .4.1
jpeg_o.erlapping_stan_event 1 0 If the coding standard is JPEG and the
rw sequence 0xfF 0xFF is lound while looking lor
jpeg_o.erlapping_start_rtus~ 1 o a marker code this event will occur.
rw This sequence is a legal stumng secuence.
It the mask register is set to 1 then an interrupt
can be generated and the start eode detector
will stop. See A.11.4.2
ovellapp;ng_start_event 1 O If the coding standard is ~1PEG or H 751 andrw an o. o. Iapp;n4 start code is tound while looking
o.e.iapp ~g_start_rnask 1 o ~orastartcodethiseventwiUoccur.l~themasY
rw register is sel to 1 then an inte~upt can De
generated and the start code detector Wlll StcD.
See A11.4.2
Table A.11.1 Start code detector registers (Sheet 2 of 5)
214S424
258
.. ..
Register name ~ c~ DescnD~Ion
i~i tr
unrc~3 ~ std_start_event 1 0 ll an unrecognlsed s;an coCe Is encountereC
rv~ this event wlll occur. Il t~.e ma5k reglster is set
unr cosn sed_sUn_mask 1 0 to 1 Ihen an internuD~ can be generated and the
rw stan code de~ector wil~ stOp.
stan_value 3 x The stan code value read Irom the tits.ream ;s
ro available in the register start_value wnile :he
s~an coCe detector is halted. See A.11.4.3
During normal operation start_value csntains
the value ol the most recently decoCed star~
marker code.
Only Uhe 4 LSBs ot stan_value are used during
H.261 operabon. The 4 ~1Sa5 will se zero.
stop_atter_picture_event 1 0 ll the registe! stop_after_picture is set to 1
rw then a StD aner picture event will se generated
stop_aner_plcture_mask 1 0 anet the end ol a picture has passed through
rw the stan code deteclor.
stop_aner_pictur- 1 0 11 the mask register is set to 1 then an interrupt
rw can be generated and the start code Cetec or
will stop. See A.11.5.1
stop_atter_picture Coes not reset to 0 atter
the end ol a p~cture has seen detec!ed so
should be cleared CirecUy.
Table A.11.1 Statrt code detector registers (Sheet 3 of 5)
'~ 2145424
259
Register name ~ ~D O - "~tion
u~ c
non_afigned_stan_event 1 0 When ignore_non_aligned is set to 1, s:an
rw codes that are not byte aligned are igroreo
non_allgned_start_mask 1 0 ~Lreated as normal data).
rw When ignore_non_aligned is set to 0, H.251
ignore_non_aligned l O and MPEG stan codes will be delec:ed
rw roga~.'e o~ byte alignment and ;he non
aligned stan event will be generated.
I~ the mask register is set to l then the event
will cause an interrupt and the stan coCe
detector will stop. See A.11.6
l~ the coding standud is configured as 'PEG
Ignore_non_aligned is ignored and t~e non-
aligned stan event Will never be generated.
discard_e~tension_data 1 1 When Ulese registers are set to 1 ex~ension or
rw user data that cannot be decoded by the
discard_user_data 1 1 SpatiaJ Decoder is disarded by the stan code
rw detector. Se- A. 11.3.3
discard_all_data 1 0 When #t to 1 all data and Tokens are
rw discarded by the stan code detector. This
connnues until a FLUSH Token is supplied or
the register is set to O direcUy.
The FLUSH Token Uhat resets this regis~er is
disarded and not output t)y the stan coCe
detector. See A.11.5.
in#rt_sequence_start 1 1 See A.11.7
rw
Table A.11.1 S~art code detector registers tSheet 4 of 5)
~ 214~424
260
P~egister narne ~ ~ Oescriptlon
sun-code-#arctl 3 5 When this register is set ~o 0 the star; :_Ce
n,v deteclor operates normalll. When set :o a
~igher value the star: coCe Cetec:or C scarcs
data until the specified type of star- cxe Is
detected. When the spec ~e~ sta, t cxe s
detected the registet is set :o C and . r r. "al
operation tollows. See A. 11.3
start_code_detector_coding_sUndard 2 0 This register configures the cocling s~anC2rd
rw used by the stan code de!ec~or. The reg ster
can be loaded direct/y or by us;ng a
CODING_STANDARD Token.
Whenever the start code Cetector ;erera;es a
CODING_STANDARD Token (see
A.11.7.4 H t ca,7ies its current
coding s~andard configura~cn. I his ,cken will
then configure the coding s~andard usec 5y all
other parts ot the decoder chip-set. See A.21.1
~nd A. 11.7
pictur-_numoer 4 0 Each bme the start coded Cetec:or de!ec:s a
~w picture stan code in the Cata stream (or the
H.261 or JPEG e~uivalent) a
PICTURE_START Token is gener2;ed
which carries the current value ot
piCture_number, This register then
inc,~. "o~ ,ts.
Table A.11.1 Start code detector registers (Sheet 5 of '5)
214S424
261
F~egister name ~ ~ ~)escnplion
leng~_co~lnt l 6 0 This regisler contains Ul~ currenl value of Ihe
rO JPEG leng~ counl. Ths register ~ modined
under the con~ol o~ the coded data c!oc~ and
should only be read via ~e MPI ~en ~e stan
code del~clor is slopped.
Table A.11.2 Start code detector test registers
A.11.3 Conversion of start codes to Tokens
In normal operation the function of the Start Code
Detector is to identify start codes in the data stream and
to then convert them to the appropriate start code Token.
In the simplest case, data is supplied to the Start code
Detector in a single long DATA Token. The output of the
Start Code Detector is a number of shorter DATA Tokens
interleaved with start code Tokens.
Alternatively, in accordance with the present invention,
the input data to the Start Code Detector could be divided
up into a number of shorter DATA Tokens. There is no
restriction on how the coded data is divided into DATA
Tokens other than that each DATA Token must contain 8 x n
bits where n is an integer.
Other Tokens can be supplied directly to the input of
the Start Code DeteCtor. In this case, the Tokens are
passed through the Start Code Detector with no processing
- 214~q2'1
262
to oth~ 6tages of the Spatial Decoder. These Tokens can
only be inserted just before the location of a start code
in the coded data.
A.11.3.1 Start cod- form~ts
Three different start code formats are recognized by the
Start Code Detector of the present invention. This is
configured via the register,
start_code_detector_coding_standard.
Coding StanCard Start Code ~an-m ~he~) Size of s~an eode value
MP~G OxOO 0~00 OxO1 cvalue~ 8 bit
JPEG O~FF <value~ B bit
H.261 OxOO O~Ot ~value~ 4 bit
T~ble A.11.3 8tart code formats
A.11.3.2 Start code Token eguiv~lents
Having detected a start code, the Start Code Detector
studies the value associated with the start code and
generates an appropriate Token. In general, the Tokens are
named after the relevant MPEG syntax. However, one of
ordinary skill in the art will appreciate that the Tokens
can follow additional naming formats. The coding standard
currently selected configures the relationship between
start code value and the Token generated. This
relationship is shown in Table A.11.4.
`- 21gt5~2~
263
S~an Co~e Value
Surt coce Token generate~t MPEG H.261 JPEG JPE5
Ihex) (~ex) (~ex~ (name
PICTURE_START ox00 ox00 0xDA SGS
SLICE_START ' 0x01 to oxol to oxoo to RS ~ 3 to
0xAF 0xCC 0x07 ~tS 1,
SEOUENCE_START 0x33 0xD8 SOI
SEQUENCE_END 0xB7 0xO9 _CI
GROUP_START 0xB8 0xC0 SOFo~
USER_DATA Ox92 0xE0 to APPo to
0xEF APPF
0xf_ COM
EXTENSION_DATA 0xBS 0xC8 'PG
0xF0 to J?G~ :o
0xFD JPGD
0x02 to RES
0xBF
0xC1 to SOF~ to
0xCB SOF"
OxCC OAC
DHT_MARKER 0xC4 DHT
DNL_MARKER 0xDC DNL
DQT_MARKER 0xOB DaT
DRI_MARKER oxOO ~RI
Table A.11.4 Tokens from start code values
a. This Token contains an 8 bit data field which is
loaded with a value deter~ined by the start code
value.
b. Indicates start of baseline DCT encoded data.
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264
A.11.3 3 Extended features of the coding standards
The coding standards provide a number of mechanisms to
allow data to be embedded in the data stream whose use is
not currently defined by the coding standard. This might
be application specific "user data" that provides extra
facilities for a particular manufacturer. Alternatively,
it might be "extension data". The coding standards
authorities reserved the right to use the extension data to
add features to the coding standard in the future.
Two dlstinct mechanisms are employed. JPEG precedes
blocks of user and extension data with marker codes.
However, H.261 inserts "extra information" indicated by an
extra information bit in the coded data. MPEG can use both
these techniques.
In accordance with the present invention, MPEG/JPEG
blocks of user and extension data preceded by start/marker
codes can be detected by the Start Code Detector.
H.261/MPEG "extra information" is detected by the Huffman
decoder of the present invention. See A.14.7, "Receiving
Extra Information".
The registers, discard_extension_data and
discard_user_data, allow the Start Code Detector to be
configured to discard user data and extension data. If
this data is not discarded at the Start Code Detector it
can be accessed when it reaches the Video Demux see A.14.6,
"Receiving User and Extension data".
The Spatial Decoder of the present invention supports
the baseline features of JPEG. The non-baseline features
of JPEG are viewed as extension data by the Spatial
Decoder. So, all JPEG marker codes that precede data for
non-baseline JPEG are treated as extension data.
21~5~24
265
A.~l.3.~ JP W S~bl- d-~ tio~-
JPEG ~upporta down loaded Huffm~n and quantizer tables.
In JPEG data, the definition of these tables is preceded by
the marker codes DN~ and DQT. The Start Code Detector
generate~ the Tokens DHT MARXER and DQT MARKER when these
marker codes are detected. The~e Tokens indicate to the
Video Demux that the DATA Token which follow~ contains
coded data describing Huffman or guantizer table (using the
formats described in JPEG). ---
o a. ~ Error d-t-ctio~
The Start Code Detector can detect certain errors in the
coded data and provides some facilities to allow the
decoder to recover after an error i~ detected (see A.11.8,
"Start code searching").
A.11.~.1 Ill-gal JPE~ l-~gth ¢ou~t
Most JPEG marker codes have a 16 bit length count field
associated with them. This field indicates how much data
is associated with this marker code. ~ength counts of 0
and 1 are illegal. An illegal length should only occur
following a data error. In the present invention, this
will generate an interrupt if illegal_length_count mask is
set to 1.
Recovery from errors in JPEG data is likely to require
additional application specific data due to the difficulty
of searching for start codes in JPEG data (see A.11.8.1).
A.l~.~.2 Ov-rlapping tart/mar~-r cod-s
In the present invention, overlapping start codes should
only occur following a data error. An MPEG, byte aligned,
overlapping start code is illustrated in Figure 64. Here,
the Start Code Detector first sees a pattern that looks
like a picture start code. Next the start Code Detector
sees that this picture start code is overlapped with a
group start. Accordingly, the Start Code Detector
~14S~2~
-
266
generate~ a overlapping ~tart event. Furthermore, the
Start Code Detector will generate an interrupt and stop if
overlapping start mask i~ set to 1.
It is impo~sibl- to tell which of the two start codes is
S the correct one ~nd which was caused by a data error.
However, the Start Code Detector in accordance with the
present invention, di~cards the first start code and will
p~ee~ ~Co~ing the ~ n~ ~tart code ~as if it is
correct" after the overlapping start--code event has been
serviced. If there are a series of overlapped start codes,
the Start Code Detector will discard all but the last
(generating an event for each overlapping start code).
Similar errors are pos~ible in non byte-aligned system~
(H.261 or possibly MPEG). In this case, the state of
ignore non aligned must also be considered. Figure 65
illustrates an example where the first start code found is
byte aligned, but it overlaps a non-aligned start code. If
ignore non aligned is set to 1, then the second overlapping
start code will be treated as data by the Start Code
Detector and, therefore no overlapping start code event
will occur. This conceals a possible data communications
error. If ignore non aligned is set to 0, however the
Start Code Detector will see the second, non aligned, start
code and will see that it overlaps the first start code.
a. 1l . 4.3 ~n~ iz-d tart cod--
The Start Code Detector can generate an interrupt whenan unrecognized start code is detected (if
unrecognized start mask z 1). The value of the start code
that caused this interrupt can be read from the register
start value.
The start code value OxB4 (sequence error) is used in
MPEG decoder systems to indicate a channel or media error.
For example, this start code may be inserted into the data
by an ECC circuit if it detects an error that it was unable
- 2145424
267
to cor~ect.
A.11.4.4 Sequence of event generation
In the present invention, certain coded data patterns
(probably indicating an error condition) will cause more
than one of the above error conditions to occur within a
short space of time. Consequently, the sequence in which
the Start Code Detector examines the coded data for error
conditions is:
l)Non-aligned start codes
2)Overlapping start codes
3)Unrecognized start codes
Thus, if a non-aligned start code overlaps another,
later, start code, the first event generated will be
associated with the non-aligned start code. After this
event has been serviced, the Start Code Detector's
operation will proceed, detecting the overlapped start code
a short time later.
The Start Code Detector only attempts to recognize the
start code after all tests for non-aligned and overlapping
start codes are complete.
A.11.5 Decoder start-up and shutdown
The Start Code Detector provides facilities to allow the
current decoding task to be completed cleanly and for a new
task to be started.
There are limitations on using these techniques with
JPEG coded video as data segments can contain values that
emulate marker codes (see A.11.8.1).
A.11.5.1 Clean end to decoding
The Start Code Detector can be configured to generate an
interrupt and stop once the data for the current picture is
cor~plete. This is done by setting stop after picture = 1
and stop_after_picture_mask = 1.
Once the end of a picture passes through the Start Code
Detector, a FLUSH Token is generated (A.11.7.2),
2145~24
268
an in~ur~upt is generated, and the Start Code Detector
stops. Note that the picture just completed will be
decoded in the normal way. In some applications, however,
it may be appropriate to detect the FLUSH arriving at the
output of the decoder chip-set as this will indicate the
end of the current video sequence. For example, the
display could freeze on the last picture output.
When the Start Code Detector stops, there may be data
from the "old" video sequence "trapped" in user implemented
buffers between the media and the decode chips. Setting
the register, discard_all_data, will cause the Spatial
Decoder to consume and discard this data. This will
continue until a FLUSH Token reaches the Start Code
Detector or discard_all_data is reset via the
microprocessor interface.
Having discarded any data from the "old" sequence the
decoder is now ready to start work on a new sequence.
A.11.5.2 When to start discard all mode
The discard all mode will start immediately after a 1 is
written into the discard_all_data register. The result
will be unpredictable if this is done when the Start Code
Detector is actively processing data.
Discard all mode can be safely initiated after any of
the Start Code Detector events (non-aligned start event
etc.) has generated an interrupt.
A.11.5.3 Starting a new sequence
If it is not known where the start of a new coded video
sequence is within some coded data, then the start code
search mechanism can be used. This discards any unwanted
data that precedes the start of the sequence. See A.11.8.
A.11.5.4 Jumping between sequences
This section illustrates an applicatiOn of some of the
technique5 described above. The objective is to "jump"
~ 2145424
269
from one part of one coded video sequence to another. In
this example, the filing system only allows access to
"blocks" of data. This block structure might be derived
from the sector size of a disc or a block error correction
system. So, the position of entry and exit points in the
coded video data may not be related to the filing system
block structure.
The stop_after_picture and discard_all data mechanisms
allow unwanted data from the old video sequence to be
discarded. Inserting a FLUSH Token after the end of the
last filing system data block resets the discard_all_data
mode. The start code search mode can then be used to
discard any data in the next data block that precedes a
suitable entry point.
A.11.6 Byte alignment
As is well known in the art, the different coding
schemes have quite different views about byte alignment of
start/marker codes in the data stream.
For example, H.261 views communications as being bit
serial. Thus, there is no concept of byte alignment of
start codes. By setting ignore_non_aligned = O the Start
Code Detector is able to detect start codes with any bit
alignment. By setting non-aligned_start_mask = O, the
. start code non-alignment interrupt is suppressed.
In contrast, however, JPEG was designed for a computer
environment where byte alignment is guaranteed. Therefore,
marker codes should only be detected when byte aligned.
When the coding standard is configured as JPEG, the
register ignore_non_aligned is ignored and the non-aligned
start event will never be generated. However, setting
ignore_non_aligned = 1 and non-aligned-start-mask = O is
recommended to ensure compatibility with future products.
MPEG, on the other hand, was designed to meet the needs
of both communications (bit serial) and computer (byte
,_ 2145424
270
oriented)-systems. Start codes in MPEG data should
normally be byte aligned. However, the standard is
designed to be allow bit serial searching for start codes
(no MPEG bit pattern, with any bit alignment, will look
like a start code, unless it is a start code). So, an MPEG
decoder can be designed that will tolerate loss of byte
alignment in serial data communications.
If a non-aligned start code is found, it will normally
indicate that a communication error has previously
occurred. If the error is a "bit-slip" in a bit-serial
communications system, then data containing this error will
have already been passed to the decoder. This error is
likely to cause other errors within the decoder. However,
new data arriving at the Start Code Detector can continue
to be decoded after this loss of byte alignment.
By setting ignore_non_aligned = 0 and
non_aligned_start_mask = 1, an interrupt can be generated
if a non-aligned start code is detected. The response will
depend upon the application. All subsequent start codes
will be non-aligned (until byte alignment is restored).
Accordingly, setting non_aligned start_mask = 0 after byte
alignment has been lost may be appropriate.
MPEG JPEG H.261
ignore_non_aligned 0 1 0
non_aligned_start_nusk 1 0 0
Table A.11.5 Configuring for byte alignment
~1~512~
271
A.11.7 autO~tic To~-~ g-~-r~t$o~
~ n the present invention, most of the Tokens output by
the Start Code Detector directly reflect syntactic elements
of the various picture and video coding standards. In
addition to these "~atural" Tokens,some useful "invented"
Tokens are generated. Examples of these proprietary tokens
are PICTURE_END and CODING_STANDARD. Tokens are also
introduced to remove some of the syntactic differences
between the coding standards and to ~tidy up" under error
conditions.
This automatic Token generation is done after the serial
analysis of the coded data (see Figure 61, "The Start Code
Detector"). Therefore the system responds equally to
Tokens that have been supplied directly to the input of the
Spatial Decoder via the Start Code Detector and to Tokens
that have been generated by the Start Code Detector
following the detection of start codes in the coded data.
A.11.7.1 Indic~ting th- nd of a pictur-
In general, the coding standards don't explicitly signal
the end of a picture. However, the Start Code Detector ofthe present invention generates a PICTURE END Token when it
detects information that indicates that the current picture
has been completed.
The Tokens that cause PICTURE END to be generated are:
SEQUENCE START, GROUP START, PICTURE START, SEQUENCE END
and FLUSH.
A.11.7.2 8top aft-r pictur- nd option
If the register stop after picture is set, then the
Start Code Detector will stop after a PICTURE END Token has
passed through. However, a FLUSH Token is inserted after
the PICTURE END to "push" the tail end of the coded data
through the decoder and to reset the system. See A. 11. 5.1.
214542~
272
A.11.7.3 Introducing sequence start for H.261
H.261 does not have a syntactic element equivalent to
sequence start (see Table A.11.4). If the register
insert_sequence_start is set, then the Start Code Detector
will ensure that there is one SEQUENCE_START Token before
the next PICTURE_START, i.e., if the Start Code Detector
does not see a SEQUENCE_START before a PICTURE_START, one
will be introduced. No SEQUENCE_START will be introduced
if one is already present.
This function should not be used with MP~G or JP~G.
A.11.7.4 Setting coding standard for each sequence
All SEQUENCE_START Tokens leaving the Start Code
Detector are always preceded by a CODING_STANDARD Token.
This Token is loaded with the Start Code Detector's current
coding standard. This sets the coding standard for the
entire decoder chip set for each new video sequence.
A.11.8 Start code searching
The Start Code Detector in accordance with the
invention, can be used to search through a coded data
stream for a specified type of start code. This allows the
decoder to re-commence decoding from a specified level
within the syntax of some coded data (after discarding any
data that precedes it). Applications for this include:
start-up of a decoder after jumping into a coded data
file at an unknown position (e.g., random accessing).
to seek to a known point in the data to assist recovery
after a data error.
For example, Table A.11.6 shows the MPEG start codes
searched, for different configurations of
start_code_search. The equivalent H.261 and JPEG
start/marker codes can be seen in Table A.11.4.
2145q2~
273
_start_codc_search Slan codes searched ~or . . .
o Normal opera~lon
Reserved (Will ~enave ~e discard Ca~a)
3 sccuence start
sUrt_cod-_search Slan codes #archcd ~or
g-oup or sequence stan
5 ~ picnJre. group or sequence stan
6 slice. p~ture. group or sequence stan
7 Ihe next stan or marker code
Table A.11.6 Start code search modes
a. A FLUSH Token places the Start Code Detector
in this search mode.
b. This is the default mode after reset.
When a non-zero value is written into the
start_code_search register, the Start Code Detector will
start to discard all incoming data until the specified
start code is detected. The start_code_search register
will then reset to 0 and normal operation will continue.
The start code search will start immediately after a
non-zero value is written into the start_code_search
register. The result will be unpredictable if this is done
when the Start Code Detector is actively processing data.
So, before initiating a start code search, the Start Code
Detector should be stopped so no data is being processed.
The Start Code Detector is always in this condition if any
of the Start Code Detector events (non-aligned start event
etc.) has just generated an interrupt.
A.11.8.1 LimitatiOns on using ~tart code search with JPEG
2145~
274
Most-~PEG marker codes have a 16 bit length count field
associated with them. This field indicates the length of a
data segment associated with the marker code. This segment
may contain values that emulate marker codes. In normal
S operation, the Start Code Detector doesn't look for start
codes in these segments of data.
If a random access into some JPEG coded data "lands" in
such a segment, the start code search mechanism cannot be
used reliably. In general, JPEG coded video will require
additional external information to identify entry points
for random access.
214~424
275
SECTl~ A.12 Decoder start-up control
A.12.1 Overview of decoder start-up
In a decoder, video display will normally be delayed a
short time after coded data is first available. During
this delay, coded data accumulates in the buffers in the
decoder. This pre-filling of the buffers ensures that the
buffers never empty during decoding and, this, therefore
ensures that the decoder is able to decode new pictures at
regular intervals.
Generally, two facilities are required to correctly
start-up a decoder. First, there must be a mechanism to
measure how much data has been provided to the decoder.
Second, there must be a mechanism to prevent the display of
a new video stream. The Spatial Decoder of the invention
provides a bit counter near its input to measure how much
data has arrived and an output gate near its output to
prevent the start of new video stream being output.
There are three levels of complexity for the control of
these facilities:
Output gate always open
Basic control
Advanced control
With the output gate always open, picture output will
start as soon as possible after coded data starts to arrive
at the decoder. This is appropriate for still picture
decoding or where display is being delayed by some other
mechanism.
The difference between basic and advanced control
relates to how many short video streams can be accommodated
in the decoder's buffers at any time. Basic control is
sufficient for most applications. However, advanced
control allows user software to help the decoder manage the
start-up of several very short video streams.
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276
A.12.2 ~PEG video buffer verifier
MPEG describes a "video buffer verifier" (VBV) for
constant data rate systems. Using the VBV information
allows the decoder to pre-fill its buffers before it starts
to display pictures. Again, this pre-filling ensures that
the decoder's buffers never empty during decoding.
In summary, each MPEG picture carries a vbv_delay
parameter. This parameter specifies how long the coded
data buffer of an "ideal decoder" should fill with coded
data before the first picture is decoded. Having observed
the start-up delay for the first picture, the requirements
of all subsequent pictures will be met automatically.
MPEG, therefore, specifies the start-up requirements as
a delay. However, in a constant bit rate system this delay
can readily be converted to a bit count. This is the basis
on which the start-up control of the Spatial Decoder of the
present invention operates.
A.12.3 Definition of a stream
In this application, the term stream is used to avoid
confusion with the MPEG term sequence. Stream therefore
means a quantity of video data that is "interesting" to an
application. Hence, a stream could be many MPEG sequences
or it could be a single picture.
The decoder start-up facilities described in this
chapter relate to meeting the VBV requirements of the first
picture in a stream. The requirements of subsequent
pictures in that stream are met automatically.
-- 214S424
277
A.12.4 Start-up control register~
Regis;er rame ~ Cescn~tlon
ir.i o
startup_access 1 0 Wnting I to tnis re ,is~er ,eques;s ;r~a; ~~.e ~1;
CED_3S_ACCESS rw counter ano ga~e opening logic S;OD to allow
access to their configuraoon regis;ers.
bit_count 3 0 This bit countems Incrementeo as coce~ _a;a
CED_35_COUNr rw ~eaves the start ccde cetec:or. The rur.. cer c~
bit_count_prescale 3 0 bits requiredo to ircreT:ent bit_count ^nce .s
rv~ approx 2(bl~-r~unt~r~ ) x ~i12
CED_3S_PRESCALE
The bit counter stars counting bits atter a
FLUSH Token ~asses ;hrouçn the bi; coun:er.
It is reset to zero and ;hen stops increr"en~Jrg
a~ter the bit count tatge; has been me;.
bit_count_t~arget 3 x This register specifies :.he bit coun; ;arçet. A
CED_3S_TARGET rw target met event is senerated wrenever the
lollowing condition becomes true:
bit_count ~= bit_count_t~trget
target_met_event 1 0 When the bit count ;arget is met ~his even; w
3S_TARGET MET_EVENT rw be generateo. It the mask regis;e mS se; ;o 1
target_m-t_mas~t 1 0 then an interruDt can be generated. however,
rw the bit counter will ~'OT stop p~ocessing data.
This event will occur when ;he bi; ;ounter
irlcre.,.c.lb to its ;arget. It will also oc_ut ;' a
target value is written which is less ;'~an ^r
equal to the current value ol the C~; cr un ed
Writing û to bit_count_t~rget wiil a~watS
genera;e a target me; event.
Table A.12.1 Decoder start-up registers
~- 21~5429
o
Register name j~ ~ iDesctiption
counter_llush-d_event 1 0 When a FLUSH To~en passes throusn the Clt
BS_FLUSI/_c'VENT r,v count circuit this evenl will occur It the mask
counter_tlushed_mask 1 0 register is set to 1 then an interrupl can be
r~t generated and the bit counter ,viil s~op
counter_llushed_too_early_ event 1 0 l~ a FLUSH Token passes throush ~he hlt
BS_;LUS~_BEEO~E_TA~GET_MET_EVEhT rv,~ count clrcuit and the Clt count target has ~ot
Counter_tlushed_too_early_mask 1 0 been met this event wll occur It the mask
w register is set to 1 then an interrupt can be
gen-rat-d and the ol~ counter will s;op
SeeA1210
ottchip_queue 1 0 Settingthisregisterto l conngures hesate
CED_9S_OUEUE rw opening logic to reCuire m~lupr~L~u,
sùppon When this regiSter is set to 0 he OUt"
gate control logic wiil au~omaacally ccntrol he
operaSon ot the output gate
See secSons A 12 6 and A 12 7
enahle_stream 1 0 When an o~-chip queue is in use writlng ;o
rw enaole stream conuols the behaviour oi the
CE3_BS__NABLE_NXT STM
output gate atter the end oi a sUeam ~asses
through it
A one in this register enahles the cu ~ul o,a e to
open.
The register will t~e reset when an
accep~_enahle interruct is genera!e
Ta~leA.12.1 i~ecoderstart-upregisters (contd)
~ 2145424
279
Regisbr name ~ . C)escnption
accept_enable_event 1 0 This event indicates that a FLUSH Token has
rw passed through ~re output gate (caus;ng it to
BS_STf~AM_END_EVENT
accept_enable_mask 1 0 close) and that an enat~le was available to allow
rw the gate to open
1~ the mask register is set to 1 then an interrupt
can ~e generated and the register
enable_stream will t~e reset See A 12 71
i
Table A.12.1 Decoder start-up regi~ter~ (contd)
~ 214542~
280
A.12.~ Output gate always open
The output gate can be configured to remain open. This
configuration is appropriate where still pictures are being
decoded, or when some other mechanism is available to
manage the start-up of the video decoder.
The following configurations are required after reset
(having gained access to the start-up control logic by
writing l to startup_access):
set offchip_queue = 1
set enable_stream = 1
ensure that all the decoder start-up event mask
registers are set to 0 disabling their interrupts
(this is the default state after reset).
(See A.12.7.1 for an explanation of why this holds the
output gate open.)
A.12.6 Basic operation
In the present invention, basic control of the start-up
logic is sufficient for the majority of MPEG video
applications. In this mode, the bit counter communicates
directly with the output gate. The output gate will close
automatically as the end of a video stream passes through
it as indicated by a FLUSH Token. The gate will remain
closed until an enable is provided by the bit counter
circuitry when a stream has attained its start-up bit
count.
The following configurations are required after reset
(having gained access to the start-up control logic by
writing 1 to startup_access):
set bit_count_prescale approximately for the expected
range of coded data rates
set counter_flushed_too_early_mask = 1 to enable this
error condition to be detected
Two interrupt service routines are required:
Video Demux service to obtain the value of
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281
~bv-delay for the first picture in each new
stream
Counter flushed too early service to react to
this condition
The video demux (also known as the video parser) can
generate an interrupt when it decodes the vbv_delay for a
new video stream (i.e., the first picture to arrive at the
video demux after a FLUSH). The interrupt service routine
should compute an appropriate value for bit_count_target
and write it. When the bit counter reaches this target, it
will insert an enable into a short queue between the bit
counter and the output gate. When the output gate opens it
removes an enable from this queue.
- ~145921
282
A.~2.~.1 8t~rtiug ~ tr-u~ hortly ~ft-r ~oth-r
f~
As an example, the MPEG stream which iQ about to finish
i6 called A and the MPEG stream about to start is called B.
A FLUSH Token should be inserted after the end of A. This
pushes the last of its coded data through the decoder and
alerts the various sections of the decoder to expect a new
stream.
Normally, the bit counter will have reset to zero, A
having already met its start-up conditions. After the
FLUSH, the bit counter will start counting the bits in
stream B. When the Video Demux has decoded the vbv_delay
from the first picture in stream B, an interrupt will be-
generated allowing the bit counter to be configured.
As the FLUSH marking the end of stream A passes through
the output gate, the gate will close. The gate will remain
closed until B meets its start-up conditions. Depending on
a number of factors such as: the start-up delay for stream
B and the depth of the buffers, it is possible that B will
have already met its start-up conditions when the output
gate closes. In this case, there will be an enable waiting
in the queue and the output gate will immediately open.
Otherwise, stream B will have to wait until it meets its
start-up requirements.
A.~2.6.2 a ~ucc-s~ion of ~hort Jtr-amJ
The capacity of the queue located between the bit
counter and the output gate is sufficient to allow 3
separate video streams to have met their start-up
conditions and to be waiting for a previous stream to
finish being decoded. In the present invention, this
situation will only occur if very short streams are being
decoded or if the off-chip buffers are very large as
compared to the picture format being decoded).
In Figure 69 stream A is being decoded and the
~145~21
283
output gate is open). Streams B and C have met their
start-up conditions and are entirely contained within the
buffers managed by the Spatial Decoder. Stream D is still
arrlving at the input of the Spatial Decoder.
Enables for streams B and C are in the queue. So, when
stream A is completed B will be able to start immediately.
Similarly C can follow immediately behind B.
If A is still passing through the output gate when D
meets its start-up target an enable will be added to the
queue, filling the queue. If no enables have been removed
from the queue by the time the end of D passes the bit
counter (i.e., A is still passing through the output gate)
no new stream will be able to start through the bit
counter. Therefore, coded data will be held up at the
input until A completes and an enable is removed from the
queue as the output gate is opened to allow B to pass
through.
A.12.7 Advanced operation
In accordance with the present invention, advanced
control of the start-up logic allows user software to
infinitely extend the length of the enable queue described
in A.12.6, "Basic operation". This level of control will
only be required where the video decoder must accommodate a
series of short video streams longer than that described in
A.12.6.2, "A succession of short streams".
In addition to the configuration required for Basic
operation of the system, the following configurations are
required after reset (having gained access to the start-up
control logic by writing 1 to start_up access):
set offchip_queue = 1
set accept_enable_mask = 1 to enable interrupts
when an enable has been removed from the queue
set target_met_mask = 1 to enable interrupts
when a stream's bit count target is met
- ~145424
284
Twa additional interrupt service routines are
required:
accept enable interrupt
Target met interrupt
When a target met interrupt occurs, the service routine
should add an enable to its off-chip enable queue.
A.12.7.1 Output gate logic behavior
Writing a 1 to the enable_stream register loads an
enable into a short queue.
When a FLUSH (marking the end of a stream) passes
through the output gate the gate will close. If there is
an enable available at the end of the queue, the gate will
open and generate an accept enable_event. If
accept_enable_mask is set to one, an interrupt can be
generated and an enable is removed from the end of the
queue (the register enable_stream is reset~.
However, if accept_enable_mask is set to zero, no
interrupt is generated following the accept_enable_event
and the enable is ~OT removed from the end of the queue.
This mechanism can be used to keep the output gate open as
described in A.12.5.
A.12.8 Bit counting
The bit counter starts counting after a FLUSH Token
passes through it. This FLUSH Token indicates the end of
the current video stream. In this regard, the bit counter
continues counting until it meets the bit count target set
in the bit_count_target register. A target met event is
then generated and the bit counter resets to zero and waits
for the next FLUSH Token.
The bit counter will also stop incrementing when it
reaches it maximum count (255).
A.12.s Bit count prescale
In the present invention, 2i~ 'ounl-prc~ x 512 bits are
~ 214592~
285
required to increment the bit counter once. Furthermore,
bit count_prescale is a 3 bit register than can hold a
value between O and 7.
n Range (bits) n~s~ (bits)
0 0 to 262144 1024
0 to 5242~8 2048
7 o to 31457280 1~880
Table A.12.2 Example bit counter ranges
The bit count is approximate, as some elements of the
video stream wlll already have been Tokenized (e.g., the
start codes) and, therefore includes non-data Tokens.
A.12.10 Counter flushed too early
If a FLUSH token arrives at the bit counter before the
bit count target is attained, an event is generated which
can cause an interrupt (if counter_flushed_too_early_mask =
1). If the interrupt is generated, then the bit counter
circuit will stop, preventing further data input. It is
the responsibility of the user's software to decide when to
open the output gate after this event has occurred. The
output gate can be made to open by writing O as the bit
count target. These circumstances should only arise when
trying to decode video streams that last only a few
pictures.
-- 2145~24
286
SECT~ A. 13 Buffer Management
The Spatial Decoder manages two logical data buffers:
the coded data buffer (CDB) and the Token buffer (TB).
The CDB buffers coded data between the Start Code
Detector and the input of the Huffman decoder. This
provides buffering for low data rate coded video data. The
TB buffers data between the output of the Huffman decoder
and the input of the spatial video decoding circuits
(inverse modeler, quantizer and DCT). This second logical
lo buffer allows processing time to include a spread so as to
accommodate processing pictures having varying amounts of
data.
Both buffers are physically held in a single off-chip
DRAM array. The addresses for these buffers are generated
by the buffer manager.
A.13.1 Buffer manager registers
The Spatial Decoder buffer manager is intended to be
configured once immediately after the device is reset. In
normal operation, there is no requirement to reconfigure
the buffer manager.
After reset is removed from the Spatial Decoder, the
buffer manager is halted (with its access register,
buffer_manager_access, set to 1) awaiting configuration.
. After the registers have been configured,
2S buffer_manager_access can be set to O and decoding can
commence.
Most of the registers used in the buffer manager cannot
be accessed reliably while the buffer manager is operating.
Before any of the buffer manager registers are accessed
buffer_manager_access must be set to 1. This makes it
essential to observe the protocol of waiting until the
value 1 can be read from buffer_manager_access. The time
taken to obtain and release access should be taken into
2145424
-
287
consider~ion when polling such registers as cdb_full and
cdb_empty to monitor buffer conditions.
Register name C Descripfion
butler_manager_access 1 1 This access ba stops the operaD:n - -a;e butler rr.anaget so thal 5
rw various registers can be accessed reliably. See A.6.4.1
Note: this access register is unusual as its de~ault state atter reset s
1. I.e. atter reset the buner manager is halted awa~ting cor, -,Lra; oi-
via the ",~- ,pror,~r intenace.
Register name ~ n Des.cription
tl~ ~
buffer_manager_keyhole_address 6 x Keyhole access to the extendec accress space used icr s~e cui er
rw manager registers shown below. See A.6.4.3 cir rr,ore
but~er_manager_keyhole_dau 8 x ;r,~u.,,,at;on about accesising registers throus;n a keyhoie
rw
butter_limlt 18 x This specifies the overall size o' ~ne ~ 3rti~, attac.nec to !re
rw Spatial Decoder.Allbuneraddressesarr i c~ ed i`.lCD ~nlsi~UI er
size and so will wrap round within the 0~ tovided.
~db_base 18 x These registers point to the base o~ the . -I o drtta (cob) and Tcken
tb_base ~w (tb) buHers.
cdb_tength 18 x These ~r~i~ ~e~ ~ speci~y the lenc~h (i.e. size) o' the codeo Ca;a ~CCb)
tb_length rw and Tolr (tb) buners.
cdb_read 18 x These registe~s hold an of ~set Irom the bu' - m,ase and inclcale
tb_read 'O whers data -~ill be read ~rom next.
cdb_numt~er 18 x These ~q sters show how much data 1< ~ u~ntly held in tne -ut!ers.
tb_number ro
cdb_tull 1 x Ther , ~ iters will be set to 1 i~ th~ - gd oata (ccb) cr o-~er ,:5i
tb_tull ~0 bu
cdb_empty 1 x Trr ~gisters will be set to 1 i~ tne ~,oded data (cdb) cr oi~en '5
tb_empty ~ 'O b .rier empties.
Table A.13.1 Buffer manager registers (contd)
~145~24
288
A.13.~.1 Buffer manager pointer values
Typically, data is transferred between the Spatial
Decoder and the off_chip DRAM in 64 byte bursts (using the
DRAM's fast page mode). All the buffer pointers and length
5 registers refer to these 64 byte (512 bit) blocks of data.
So, the buffer manager's 18 bit registers describe a 256 k
block linear address space (i.e., 128 Mb).
The 64 byte transfer is independent of the width (8, 16
or 32 bits) of the DRAM interface.
10 A.13.2 Use of the buffer manager registers
The Spatial Decoder buffer manager has two sets of
registers that define two similar buffers. The buffer
limit register (buffer_limit) defines the physical upper
limit of the memory space. All addresses are calculated
15 modulo this number.
Within the limits of the available memory, the extent of
each buffer is defined by two registers: the buffer base
(cdb_base and tb_base) and the buffer length (cdb_length
and tb_length). All the registers described thus far must
20 be configured before the buffers can be used.
The current status of each buffer is visible in 4
registers. The buffer read register (cdb_read and tb_read)
indicates an offset from the buffer base from which data
will be read next. The buffer number registers (cdb_number
2:, and tb_number) indicate the amount of data currently held
by buffers. The status bits cdb_full, tb_full, cdb_empty
and tb_empty indicate if the buffers are full or empty.
As stated in A.13.1.1, the unit for all the above
mentioned registers is a 512 bit block of data.
30 Accordingly, the value read from cdb_number should be
multiplied by 512 to obtain the number of bits in the coded
data buffer.
A.13.3 Zero buffers
Still picture applications (e.g., using JPEG) that do
2145424
289
not h4ve a "real-time" requirement will not need the large
off-chip buffers supported by the buffer manager. In this
case, the DRAM interface can be configured (by writing 1 to
the zero_buffers register) to ignore the buffer manager to
provide a 128 bit stream on-chip FIFO for the coded data
buffer and the Token buffers.
The zero buffers option may also be appropriate for
applications which operate working at low data rates and
with small picture formats.
Note: the zero_buffers register is part of the DRAM
interface and, therefore, should be set only during the
post-reset configuration of the DRAM interface.
A.13.4 Buffer operation
The data transfer through the buffers is controlled by a
handshake Protocol. Hence, it is guaranteed that no data
errors will occur if the buffer fills or empties. If a
buffer is filled, then the circuits trying to send data to
the buffer will be halted until there is space in the
buffer. If a buffer continues to be full, more processing
stages "up steam" of the buffer will halt until the Spatial
Decoder is unable to accept data on its input port.
Similarly, if a buffer empties, then the circuits trying to
remove data from the buffer will halt until data is
available.
As described in A.13.2, the position and size of the
coded data and Token buffer are specified by the buffer
base and length registers. The user is responsible for
configuring these registers and for ensuring that there is
no conflict in memory usage between the two buffers.
~145~24
290
SECTlOI~ A.14 Video Demux
The Video Demux or Vldeo parser as it is also called,
completes the task of converting coded data into Tokens
started by the Start Code Detector. There are four main
processing blocks in the Video Demux: Parser State Machine,
Huffman decoder (including an ITOD), Macroblock counter and
ALU.
The Parser or state machine follows the syntax of the
coded video data and instructs the other units. The
Huffman decoder converts variable length coded (VLC) data
into integers. The Macroblock counter keeps track of which
section of a picture is being decoded. The ALU performs
the necessary arithmetic calculations.
A.14.1 Video Demux registers
~n 1
Regis~er name ~ ~ Description
~ ¢
demux_access 1 0 This access bit stops the operaDon of Ihe Video Cemux so ~,a~ ~t's
CED-H-cT~L~7J rw vanous registerscan be acce~sed reliably. See A.6.4.1
huttman_error_code 3 Wh-n the.Video Oemux stops following the gr neration ot a
C~O_H_CTftL,~6:4~ ro hunman_event intetrupt request this 3 0it register holds a val~e inCicating
why the interrupt was grr._. ~ See A.14.5.1
parser_error_code 8 When the Vid-o Demux stops tollowing the generation ot a ~arser_event
CED_H_OhtUX_ERFt ro interrupt re~uest this 8 bit register holds a value indicating why the
internupt was g-. ~ ' See A.14.5.2 .
demux_keyhole_address 12 x Keyhole access to the v'ideo Demux's extrtnded address sDace. See
C~O_H_KEYHOLE_ADOft rw A.6.4.3 ~or more ir,~u,,,,~tion about accessing regls:e~s
demux_keynole_data 8 x through a keyhole.
CEo-H-KEyHoLE rw Tables A.14.2, A.~4.3 and A.14.4 describe the regiSters ~hat ^an ~e
acc-ssed via the keyhole.
Table A.14.1 Top level Video Demux registers
2145424
2 9 1
Re_ .1? .. _ ~D -- Desc~lplion
~i tD
dummy_last_picture 1 0 When ttlis reglstems set ;o 1 the Vdeo ~emux ~ll genera:e informaoon
CeO_~_ALU_RE5~ rw lor a 'dummy' Intra plcture as the lasl plc'ure ol an MPEG sequence.
r_rom_control This funcbon is use~ul ~hen the Temporal Oecor!ems configured tor
automatic picture re-ordering (see A.18.3.5. 'Pic'ure sequence re-
r_dummy_las~frame_oit
ordering'. to nush the last P or I ~icture out o~ the Temporal
Oecoder.
No 'dummy' picture is required it:
the Temporal Decoder is not configured /or re-ordering
another MpEG sequence will De decoded immediately (as ~Lhls Will also
nush out the last picture)
the coding standard is nol MPEG
field_in~o 1 0 When this register is set to 1 the first Dyte ot any MPEG
CEO_H_ALU_REGO rw extra_i"~o""aa'on_picture is placed in the FIELD_INFO Token. See
A.14.7.1
r_rom_con~rol
r_fie/d_in/o_bit
continue 1 0 This register allows user so/tware to control how mucn extra. user or
CEO_H_ALU_REGO rw extension data it wants to receive when is it is cetected by the decoder.
See A.14.6 . and A.14 7
r_rom_control
r_continue_oit
rom_revision 6 Immediately lollowing reset t~is holos a copy o~ e mierocor~e RCM
Ce-D-H-ALu-REG1 revision numDer.
This register is also used :o present :o control so~tware data vaiues read
r !cm_rev1sJon
irom the coded data. See A.14.6, 'Receiving User and Extension da:a'
and A.14.7. 'Receiving Extra Inforrna:ion',
Table A.14.1 Top level Video Demux registers (contd)
2145424
Register name ~ ~ Oescription
ir-.i c
hunman-eve~lt 1 0 A Huffman evenl is generated it an efror is found in the coded Ca;a. See
_ ~ I
rw A.14.5.1 for a de~.:,ti~n ot these events.
hutfman_mask 1 0
li the mask register is set to 1 then an interrupt can be generated and the
rw Video Demux will stop. It th- mask register is set to 0 then no interruD~ s
generated and the Vdeo Cemux will anempt~o recover trom the e~rcr.
parser_event 1 0 A Parser event can oe in responce to errors in the coce~ ~ata cmo :~e
rw arrival ot ;"f~ at the Video Demux that reCuires software
parser_mask 1 0 ;n~e~c.,tian. See A.14.52 for a Ce~nption of trese events.
If the mask register is set to 1 then an interrupt can be generateC arC :he
Vldeo Demux wifl stop. I~ th- mask register is set to û then no interru~t is
generated and the Video Demux ~vill attempt to continue.
Table A.14.1 Top level Video Demux regi~ter~ ~contd)
Register name a~ ~2 Description
~n
co."pon~ ~t_name_0 8 x During JPE~ operation the register CG",pOnC.,t_name_n holds an 8 t~it value
co",?on~nt_name_1 rw indicating (to an ' ~ ) which colour cr,",~no.,~ has the col,lponent ID n.
co",ponLnt_name_2
cG",ponent_name_3
horiz_pels 16 x These registers hold the horizonul and verticaf dl",e.,a.or~s o~ the video oeing
rw decoded in pixels.
vert_Dels 1 6 x
See secbon A14.2
rw
hori2_".aC, JO~ ' 16 x These registers hold the honzontal and venicaf d;ll.ensions of the viceo aelrS
rw decoded in ."~,,oOI~.
ven_ma., . ~ ~c: 16 x
rw See section A14.2
Table A.14.2 video demux picture
construction registers
2145421
-
Reglsler name ~ u~ Oescription
rn tr
max_n 2 x These reglsters hold the ,-Gc~otil~c~ wldth ancl heignl In blocks (3 xa pl:~e!sl.
rw rhe values 0 to 3 indicate a ~ id ~ e ~hl ot 1 lo 4 blocks.
max v 2 x
See section A.14.2
r~
max_co..,ponr nl_id 2 x rhe values O to 3 indicate that 1 to 4 difterenl video co~Coner.:s a. e --r en ~l
rw ~eing decoded.
See seclion A.14.2
Nt 8 x Ouring JPEG operation thi5 register holds the Darame~er ,!~jl (nur-.Der ol image
rw co."?onr.. ,ts in trame~.
blocks_h_0 2 x For each ot the 4 cohur co-,-?oncnl~ the reglsters blocks_h_n and
blocks_h_1 rw blocks_v_n hold the number ot blocks horizontally and vertica,ly in a
blocks_h_2 ",a~ ~ubl~ tor the colour co--,poncnt with co-,lvonent 10 n.
blocks_h_3 See secbon A.14.2
blocks_v_0 2 x
blocks_v_1 rv~
blocks_v_2
blocks_v_3
to_0 2 x The tvvo bit value held by Ihe register tq_n descnt~es whicn Inverse
tq_1 rv~ Cuantisation table is to be used when decoding da:a with componen; iD r,.
tr~ 2
tQ_3
Ta~le A.14.2 Video demux picture
construction registers (contd)
al4s424
294
A.1~ .1 Register loading and Token generation
Many of the registers in the Video Demux hold values
that relate directly to parameters normally communicated in
the coded picture/video data. For example, the horiz_pels
register corresponds to the MPEG sequence header
information, horizontal_size, and the JPEG frame header
parameter, X. These registers are loaded by the Video
Demux when the appropriate coded data is decoded. These
registers are also associated with a Token. For example,
the register, horiz_pels, is associated with Token,
HORIZONTAL_SIZE. The Token is generated by the Video Demux
when (or soon after) the coded data is decoded. The Token
can also be supplied directly to the input of the Spatial
Decoder. In this case, the value carried by the Token will
configure the Video Demux register associated with it.
214S~2~
295
- Oescription
~n
dc_huH_0 2 The two bit value held by the register dc_hun_n ~escrloes whlch Hu~man
dc_hutt_1 rw decoding table is to be used when decocing the DC coe~cients ol ~ata wlth
dc_hutt_2 co,-"~onCnt ID n.
dc_hut~_3 Similarly ac_hutt_n desCnDes the table to be used when c'ecocirg AC
ac_hun_0 2
coc~
ac_hutt_1 ~v~
Baseline JPE5 reCuires up to two Hunman tables per scan. The or iy ~a~!es
ac_hutt_2
? O l~_nted are O and 1.
ac_hutt_3
dc_bits_0l15:0] 8 Each ol these is a ~able oi 16, eight bit values. rhey ;rovsde the Bl I S
dc_bits_1[15:01 rw in~ullllaliull (see JPEG Huflman table sDe~ fi~ on) which ~orm par; ol the
ac_bits_0l15:0] 8 de~,i~tion o~ two DC and two AC Huttman tables.
aC_bits 1[15:0] rw
See section A. 14.3.1
dc_huttval_0[11:0] 8 Each o~ these is a table oi 12, eight brt values. They provide the HU;~VAL
dc_huttval_1(11:0] rw ;-,f~""~tion (see JPEG Huttman table 5~ ;rcation) which ~omm pa,-t o~ ,he
de~,;~tiu,, o~ two DC Huffman tables.
See seCtion A.14.3.1
ac_huttval_0t161:0] 8 Each o~ these is a table o~ 162, eight bit values. They provide the hUFi-VAL
ac_hu~val_1~161:0] n~ ;ntulllldtion (see JPEG Hut~man table s~ Sion) which ~orm part ol he
d~, i~JtiOI ~ o~ two AC Huttman tables.
See seCtion A.14.3.1
dc_zssss_0 8 These 8 bit registers hold values that are 'special cased' to acce~erate ;~e
dc_2ssss_1 rw decoding ol certain ~reguently used JPEG VLCs.
ac_eob_0 dc_ssss - magnitude of DC coetffcient is 0
ac_eob_1 rw
ac_eob - end o~ block
ac_zr~_0 8
ac_zrl - run ol 16 zeros
ac_~rl_1 rw
Table A.14.3 Video demux Huffman tiable registers
~145424
296
Regisl-r name ~ ~ Descriplion
i~i
buner-size 10 This register i5 loaded when drcoding MPEG data wlt;h a value Inclcaong ~he
rw size ot V~V but~er required in an ideal decoder.
This value is not used by the decoder chips. However the valLe it hoits mal
be usetul to user sottware when configuring the coCed Cata bu~er slze and :3
detemine whether the decoder is capable ot decoding a pan cular .~ a a
file.
pel_aspect 4 This register is ioaded when decoding MPEG da~a v~;h a value Inc:ca;;ng ~e
rw pel aspect rabo. The value is a 4 bit integer that is used as an inde~ into a
table defined by MPEG.
See the MPEG standard tor a definition ot this table.
This value is no~ used by bhe decoder chips. Howevet the value it holCs may
be useiul to user sottware when configuring a display or output dev ce.
bit_rate 18 This register is loaded when dr~coding MpEG da~a Wi~h a value inticating~2e
rw coded data rate.
See the MPEG standard tor a definibon ol this value
This value is not used by the decoder chips. However the value a holds may
be usehl to user sottware when configuring the decoder sun-up recis:ers.
pic_rate 4 This register is baded when decoding MPEG data Wlth a va:ue indicating the
rw picture rate.
See the MPEG standa d tor a definiOon of this value.
This value is not used by the decoder chips. However the value it ho!cs r~ay
be usetul to user sott~re when configuring a display or output dev-ce.
consl.. ;nr d 1 This register is loaded when decoding MPEG data to indicate it the coced o a a
rw meets MPEG'sc.or,,t) ~cd pc~ t. a.
See the MPEG standard lor a definition ol this nag.
This value is not used by the decoder chips. However .r.e value ~t holds -ay
be usetul to user sottware to detemine whether the decoder is ca able ot
decoding a particular MPEG data file.
Table A.14.4 Other Video Demux rer~listers
2145424
~ . .
Register name ~ ~ ~escnption
picture_typ- 2 During MPEG oPeratlon this reglster holds the plcture type of the cic:ure being
nv decoded.
h_261_pic_type 8 This register is loaded when Cecoding H.261 data. It bolds inforna~on abou~
rw the picture formaL
17161514131211101
¦ r ¦ r ¦ s ¦ d ¦ ~ ¦ r~ I r ¦ r ¦
Fiags:
s - Split Screen Indicator
d - Document Camera
~- Freeze Picture Release
This value is not used by the decoder chips. However the informaGon should
be used when configuring horiz_p-ls, vert_pels and the display or cutput
device.
broken_closed 2 ~)uring MPEÇi operalion this register holds the broken_link ano c'osedsop
rw i,,f~,,,,,ction ior the group of pictures being decoded.
71615141312j 1101
¦ r ¦ r ¦ r r ¦ r ¦ r ¦ c ¦ b ¦
Flags:
c - c~osed~;op
Table A.14.4 other Video Demux r-gisters (contd)
~ ` 2145424
298
_ ~, . _j
Regisler nam
tr
pre- lction_rnode 5 During MPEG and H.2610peration this register holds the current value o~
rw prediclion mode.
6 1 5 1 4 1 3 1 2 1 1 1 û I
¦ ~ ¦ r ¦ t ¦ h ¦ y ¦ x ¦ b ¦ ~ ¦
F!ags:
h enab~e H.26 1 loop filter
y resel backward vector prediction
vbv_delay 16 This register is load d when decoding MPEG data with a value indica~ing the
rw minimum start-up delay betore decoding should start.
See the MPEG standard tor a definibon oi this value.
This value is not used by tho decoder chips. However ~e value it holds may
be usetul to user sottware when configuring the decoder start-up regiSterS~
pic_number ~ This register holds ~e picture number ~or tne pictures that is currently ~elng
rw decoded by the Video Demux. This number was generated by the start code
detector when thiS picturs arrived there.
See Table A. 112 ~or a d ~b ~n ot the picture number.
dummy_last_olctur- 1 0 These registers are also visbl- at the top bvel. See Table A. 14.1
rw
tield_lnto ~
rw
continu- 1 0
rv~
rom_reviSion 8
rw
codin9-s~andard 2 This register is loaded by t~e CODING_STANDARD Token to conf5ure
ro the Vdeo Demux s mode oi operabon.
See section A.21.1
Table A.14.4 Other Video Demux resiat~rs (contd)
;~ 2145~24
299
Registu name ~ vt Oescription
~n rr
restart_interval ô Tnis register is loaded w~en decoding JPEG data wlttl a value Indica~lng ~e
rw minimum stan-up delay before decooing should s;an.
See the MPEG standard lor a definibon o~ this value
Table A.14.4 other Video Demux regi~ter~ ~contd)
register Tokenstandard comment
CG . poncr.~_name_n COMPONENT_NAME JPEG in cooed data.
MPE5 not used in standard.
H.261
horiz_pels HORIZONTAL_SIZE MpEG in coded data.
ven_pels VEFITICAL_SIZEJPEG
H.261 aulomatica.ly derived rcm picture
type.
nori~_ ac.o~ o HORIZONTAL_MBS MPEG control sottware must denve Irom
ven_.. ~ ~t - VERTICAL_MBS JPEG horizontal and vertical plcture size.
H.261 aulu,l,at,c..lly derived trsm pic~ure
type.
max_n DEFlNE_MAX_SAMPLlN~i MPEG control sottware must configure.
max_v Sampfing structure is fixed by
standard.
JPEG in coded data.
H.261 automatically configure~ lor 4:2.
video.
Table A.14.5 Register to Token cro~ reference
~_ 21ilS~24
300
reglster Tok-n standud comment
ma~t-cG~ oncnt-ld MAX_COMP_ID MPEG conUol so~tware must configure.
Sampling sUucture is fixed by
standard.
JPEG in coded data.
H.261 automatically configured lor 4:2:0
video~
tq_0 JPEG_TABLE_SELECT JPEG in coded data.
tq_1 MPEG nol used in standard.
H.261
tq_2
tq_3
blocks_h_0 DEFINE_SAMPLING MPEG conUol so~are must configure.
blocks_h_1 Samoling SUucture is fixed by
blocks_h_2 standard.
blocks_h_3 JPEG incoded data.
H.261 auto."atica'.y configured ~or 4:2:0
blocks_v_0
video.
blocks_v_1
blocks_v_2
blocks_v_3
dc-hun-o in san header data JPEG in coded data.
dc hun 1 MPEG_DCH_TABLE MPEG conuolsoftwaremustconfigure.
H.261 not used in standard.
dc_hutt_2
dc_hutt_3
ac_hutl_0 in san header data JPEG in coded data.
ac_hu~r_1 MPEG not used in standard.
H.261
ac_hut~_2
ac_hutr_3
Table A.14.5 Register to Token cro~
reference (contd)
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