Note: Descriptions are shown in the official language in which they were submitted.
2167189
LOW FREQUENCY SQUARE WAVE ~T~CTRONIC R~r~T~A~T
FOR GAS DISCHARGE DEVI OES
BACgGROUND OF 1~ INVENTION
1. Field of the Invention
The present invention relates to a low frequency power
converter and specifically to low frequency electronic ballasts
for gas discharge devices. More specifically, the present
invention relates to a low frequency square wave electronic
ballast for high pressure sodium lamps.
2. Prior Art
An important application for high frequency switchmode
power converters is supplying power to gas discharge devices,
especially high pressure sodium (HPS) lamps. In the case of high
frequency powering of gas discharge lamps, the high frequency
h~ t and the gas discharge lamp have a higher level of
interaction than that which exists between a conventional low
frequency ballast and gas discharge lamp. High frequency
ballasts suffer from acoustic resonance which can cause various
problems such as instability, high output fluctuation, or, in the
worst case, cracked arc tubes. Therefore, an optimum solution
to this problem is the use of a high frequency DC-to-DC switch-
mode as a controlled current source connected to a low frequency
DC-to-AC square wave inverter supplying the gas discharge lamp.
Due to its lessened weight, higher efficiency and the nonexis-
tence of acoustic resonances, this novel high frequency ballast
-~ with a low frequency output has significant advantages when
compared with either the conventional low frequency ballasts and
the usual high frequency electronic ballast. Additionally, a
new, high sophisticated electronic ballast generation can be
introduced to provide several special features, such as, for
example, automatic or controlled ~; mm; ng.
Therefore, the essential design targets for a highly
sophisticated, high efficiency, low frequency electronic ballast
supplying gas discharge lamps would be the following:
(a) very high efficiency (s 95%), energy saving
and low temperature rise of critical components;
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(b) low frequency square wave lamp current (crest
factor is unit). Since the instantaneous lamp power is constant
(no flickering), no acoustic resonance can occur;
(c) high reliability and long life time (lower
power loss, no electrolytic capacitors);
(d) fully controlled lamp power, elimin~ting the
effects of line voltage fluctuation and lamp aging;
(e) programmed and/or controlled~immlngproviding
essential energy saving;
(f) automatic switching off when the lamp has
- reached the end of its life time (programmed in advance);
(g) automatic light switching and high temperature
protection; and
(h) power factor correction (PF 2 95%) and EMI
filtering.
The prior art is replete with many known circuits
providing high frequency ballast for gas discharge lamps. For
instance, high efficient electronic ballast which can be used
with HPS (HID) lamps are discussed in U.S. Patent No. 5,097,183
entitled "Master-Slave Half-bridge DC-to-AC Switchmode Power
Converter" and U.S. Patent Application Serial No. 883,762, filed
May 15, 1992, entitled "Self-Symmetrizing and Self-Oscillating
Half-Bridge Power Inverter" assigned to the assignee of the
present invention.
- 25 SUMMARY OF THE INVENTION
It is an object of the present invention to provide a
power controlled and current limited current source implementing
the ideal ballast curve for HPS (HID) lamps.
A second object of the present invention is to provide
a power controlled current source, wherein the power can be
selected and/or continuously changed.
A further object of the present invention is to provide
a high frequency DC-to-DC converter as a power controlled current
source, wherein no electrolytic capacitors are used.
21 671 89
.
Another object of the present invention is to provide
a high frequency buck converter configuration which has a
substantially improved efficiency, wherein the control circuit
is floating together with the main switching transistor.
A further object of the present invention is to provide
a circuit, especially for a buck converter configuration,
implementing the inversion of output voltage and zero current
sensing.
Another object of the present invention is to provide
a high efficiency square wave full-bridge inverter operation in
a very wide frequency range including DC operation.
A further object of the present invention is to provide
a logic control circuit controlling a square wave full-bridge
inverter implementing programmed transition between the high (or
zero) and the low frequency operations.
Another object of the present invention is to provide
a low power stabilized logic supply voltage source connected to
main voltage, wherein no electrolytic capacitors are used.
A further object of the present invention is to provide
a low power stabilized logic supply voltage source connected to
main voltage, wherein no electrolytic capacitors are used.
BRIEF DESCRIPTION OF Tn~ DRAWINGS
FIG. 1 illustrates a schematic diagram of the preferred
- electronic ballast for gas discharge devices including six basic
units;
FIG. 2A, 2B and 2C show the voltage and current
waveforms with respect to the schematic diagram of FIG. 1;
FIG. 3A illustrates the ballast curve as a diagram of
lamp power versus lamp voltage realized by the preferred
electronic ballast of the present invention;
FIG. 3B shows the diagram of lamp current versus lamp
voltage;
2 1 6 7 1 89
FIG. 4 shows the circuit diagram of a high power factor
preregulator designated as UNIT-1 in FIG. 1;
FIG. 5A shows the circuit diagram of a power control
converter designated as UNIT-2 in FIG. 1;
5FIG. 5B illustrates a diagram of the inductor current
with respect to UNIT-2;
FIG. 5C illustrates a diagram of the functional
relationship between output and control voltages;
FIG. 6A shows the circuit diagram of a controlled full-
bridge inverter and ignitor circuit designated as UNIT-3 and
UNIT-4 in FIG. 1;
FIG. 6B illustrates the four output control signals of
a logic drive unit designated as LD-3 in FIG. 1;
FIG. 6C illustrates a timing diagram with respect to
UNIT-3 under no load condition;
FIG. 6D illustrates a timing diagram with respect to
UNIT-3 under loaded condition; and
- FIG. 7 shows the circuit diagram of a logic supply and
a monitor unit designated as UNIT-5 and UNIT-6 in FIG. 1.
20DETATr.~n DESCRIPTION OF THE lNV~N'llON
FIG. 1 illustrates a schematic diagram of the preferred
electronic ballast for gas discharge devices including:
a high power factor preregulator designated as UNIT-1
including a boost converter (PU-1), a MOSFET driver (MD-1) and
a control unit (CU-1);
a power controlled DC current source designated as
UNIT-2 including a buck converter (PU-2), a MOSFET driver (MD-2)
and a control unit (CU-2);
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a low-frequency square wave DC-to-AC converter
designated as UNIT-3 including a full-bridge square wave inverter
(PU-3), four MOSFET drivers (MD-3), a logic driver (LD-3) and a
frequency control unit (CU-3);
a high voltage ignitor circuit designated as UNIT-4;
a stabilized logic supply voltage source designated as
UNIT-5 including a low power half-bridge square wave inverter
(B) and five linear regulators (LR-1, LR-2, LR-3, LR-4 and LR-
5);
a monitor unit designated as UNIT-6 including an input
voltage, a temperature and a light sensing circuit; and
a gas discharge device, especially a high pressure
sodium lamp designated as HID lamp.
FIG. 2A, 2B and 2C show some characteristic voltage and
current waveforms of the preferred electronic ballast with
respect to schematic diagram of FIG. 1. Particularly, FIG. 2A
shows the nearly sinusoidal input current (Ii) of the high power
factor preregulator. Furthermore, FIG. 2B shows the input (V1)
and output (VO) voltages of the power controlled DC current
source. FIG. 2C shows the lamp voltage (VL = + VO) and lamp
current (IL) waveforms in the normal, low frequency mode. This
figure illustrates that an instantaneous lamp power can be
obtained.
FIG. 3A illustrates the ballast curve as a diagram of
the functional relationship between the lamp power (PL) and the
-~ lamp voltage (VL). Furthermore, FIG. 3B shows the diagram of
lamp current (IL) versus lamp voltage (VL). Three different
ranges can be distinguished, depending on the lamp voltage as it
is shown in FIG. 3A and 3B, namely;
a constant lamp current range in the warming up period
(05Vr.~VL(min) );
a constant lamp power range is a certain range of lamp
voltage (VL(~) <VL~VL(~) ); and
a forbidden range ( VL> Vr (~) ), if the lamp voltage
reaches V~ ) the ballast will automatically switch off.
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Two different nom;n~l lamp power levels can be selected
by the preferred ballast, for instance 200W or 250W. Further-
more, the lamp power can be continuously changed providing
~lmm;ng capability which can be significant from an energy saving
viewpoint.
The six basic units of the present invention will now
be explained.
UNIT-1 includes an input filter F10 and is shown in
FIG. 4. The circuit is based on a st~n~rd boost converter
configuration including a bridge rectifier B10, an inductor L10,
a power MOSFET M10, a fast rectifier D10 and an output capacitor
C10. Controlled on-time and zero current switching on techniques
are applied. Therefore, the peak and average inductor current
is sinusoidal as is the input voltage. The MOSFET driver
designated as MD-1 in FIG. 1 is implemented by MOSFETs M11 and
M12, the inputs of which are connected to the outputs of dual
input NAND Schmitt-triggers IC10 and IC11, respectively.
The control unit designated as CU-1 in FIG. 1 includes:
an error amplifier IC15;
a saw-tooth generator implemented by a resistor R11,
a capacitor C11, a MOSFET M13 and a NAND Schmitt-trigger IC13;
a pulse width modulated (PWM) comparator IC14; and
a zero current sensing comparator IC12 connected to a
shunt resistor R10.
An essential difference between the preferred high
- power factor preregulator of the present invention and standard
regulators, is the position of the shunt resistor R10. In this
case, the voltage drop (which is proportional to the inductor
current) on R10 is positive when compared to the zero level of
the control unit providing sensitivity and less loss. This
m~;m~l on-time and the m~lm~l inductor current is limited by
Zener diode Z10. This solution is effective if the main switch
M10 is switched on at zero inductor current level as in the
preferred embodiment. A further difference between the preferred
high power factor preregulator and standard regulators, is the
utilization in the present invention, of a relatively small value
film capacitor C10 instead of employing a large value electro-
2 ~ 67l 89
-
lytic capacitor as the output capacitor. In the case, the
fluctuation (120Hz) of the output voltage V1 is large as can be
seen in FIG. 2B.
UNIT-2, which is connected to the output capacitor C10
of UNIT-1 is shown in FIG. 5A. The power unit designated as PU-2
in FIG. 1 is based upon a standard buck converter configuration
including a power MOSFET M20, a fast rectifier D20, an inductor
L20 and an output (film) capacitor C20. The MOSFET driver
designated as MD-2 in FIG. 1 is implemented by MOSFETs M21 and
M22 controlled by dual input NAND Schmitt-triggers IC20 and IC21.
The control unit designated as CU-2 in FIG. 1 is much different
from the standard control methods. This control circuit will be
described as follows:
a) Floating control: The control unit is connected
directly to the MOSFET-driver MD-2 (M21 and M22) and therefore
to the main switch M20.
b) Zero current sensing employing rectifiers: A fast
rectifier D21 connected in series with a Schottky-rectifier D22
are connected in parallel to the main rectifier D20. If the main
switch M20 is OFF, the main rectifier D20 is ON and an approxi-
mately 200mV voltage drop occurs across the Schottky-rectifier
D22. This voltage controls a voltage comparator IC22 connected
to the first inputs of NAND Schmitt-triggers IC20 and IC21, which
forces M20 OFF, implementing the only possibility of switching
on M20 at zero inductor current. FIG. 5B illustrates the diagram
- of inductor current iL(t).
c) Control of inductor current: Assuming the ON-state
of M20 and a discharged initial condition for capacitor C21, its
voltage Vc(t) can be calculated as follows:
V,--V
V ( t) = o t
where t is the time with respect to an ON time interval, R =
R20 + R21 (the effect of R22 and R23 are neglected), C = C21 and
Vi and VO are the input and output voltages. Since the inductor
current iL ( t) is also proportional to Vi-VO we obtain:
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, j
iL(t) = RLCVC(t)
where L is the inductance of inductor L20. Using a voltage
compArator IC23 connected to the second inputs of dual input NAND
Schmitt-triggers IC20 and IC21, the peak inductor current can be
derived as follows:
IP= RL vr ( 1 )
where Ip is the peak inductor current and Vr=l2-Vf is a given
reference voltage as it is shown in FIG. 5A. Therefore the peak
inductor current as well as the average inductor current Ia=Ip/2
can be directly controlled by a reference voltage Vr. To achieve
the discharging of the capacitor C21, a low power P channel
MOSFET M23 is connected to the output of the voltage comparator
IC22, with c^apacitor C21 connected in parallel with the source
and drain of this MOSFET.
d) Control of output power: Assuming that the reference
voltage is proportional to the inverse value of output voltage
VO:
V~=12-V~= V ~ VO(min)SV~V(m~) (2)
O
.
and substituting (2) into (1) we obtain:
p IpVo RC
2 2L
where PA is the average output power.
Therefore, the control of a fixed output power is
solved in a certain range of output voltage, assuming an
electronic realization of equation ( 2) which will now be
described.
21 671 89
e) Electronic realization of the functional relation-
ship Vl=/VO: The output voltage VO is boosted to the floating
control level by employing a rectifier D23 and a smoothing
capacitor C22. This is essentially the flyback method especially
for a buck converter configuration without applying a secondary
winding on inductor L20. Applying voltage divider resistors R24
and R25 and Zener diodes Z20 and Z21 connected in series with
resistors R26 and R27 respectively, a sufficient (~1%) approxi-
mation of function Vr=/VO (in a certain range of output voltage)
can be achieved, as it is illustrated in FIG. 5C. If VO<Vo(~n),
Vr and therefore Ip (Ia) is limited to an appropriate value by a
zener diode z22 as it is also shown in FIG. 5A.
To achieve discharging capacitor C21, a low power P
channel MOSFET M23 is connected to the output of the voltage
comparator IC22, with capacitor C21 connected in parallel with
the source and drain of this MOSFET.
For HPS lamps assuming 100V nominal lamp voltage,
Vo(~)z80V, Vo(~z160V and I~ z3amperes. The output voltage
can be limited by applying a Zener diode Z23(Vz=160~ connected
in series with a current limiting resistor R28 and an optocoupler
OC20 (connected also to IC22) providing OFF-state for the main
switch M20. The output power can be changed by changing the
value of resistor R21. For instance if R=R20=R21, the output
power can be 250W and if R=R20 (R21 = 0), the output power is
'- 25 200W. Furthermore, a continuous ~lmmlng of the output power
- (lamp power) can be achieved by a continuous decrease of the
value of resistor R21, which can be advantageous from an energy
saving consideration.
UNIT-3, which is connected to the output capacitor of
UNIT-2 is shown in FIG. 6A. The power unit designated as PU-3
in FIG. 1 is based on a full-bridge configuration including
MOSFETs M31, M32, M33 and M34. The MOSFET drivers designated as
MD-3 in FIG. 1 are implemented by four complementary MOSFETs
CM31, CM32, CM33 and CM34. Furthermore, complementary MOSFETs
CM33 and CM34 are driven by optoisolators OC33 and OC34,
respectively, providing isolation from the control level. The
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`
logic driver designated as LD-3 in FIG. 1 provides four logic
signals Q " Q2, Q3 and Q4 controlling the MOSFET driver MD-3.
The logic driver signal waveforms for Q " 72~ 73 and 74 are
shown in FIG. 6B. The logic driver signals contain appropriate
deadtimes avoiding cross conductions of the main switches. The
symmetrical input logic signal Q is shifted with ~tz5~s by a
dual comparator IC32/2 and IC32/1, and an RC circuit (R31, C31)
resulting in signals Qg and 75. The non-inverting input of
IC32/l and the inverting input of IC32/2 are connected to the
common point of the RC circuit containing R31 and C31. The
inverting input of IC32/1 and the non-inverting input of IC32/2
are connected to the common point of a voltage divider pair
including resistors R32 and R33. Using dual input NAND gates
IC31/l, IC31/2, IC31/3 and IC31/4, the four logic driver signals
15 can be derived from the upper MOSFET driver as:
73 = Q Ps~ Q4 =
and for the lower MOSFET drivers as:
Q1 = QgX, Q2 = QgX
where X is an inhibition signal (if X=O, the lower MOSFETs M31
and M32 are switched off).
The logic control unit designated as CU-3 in FIG. 1
20 implements a time programmed starting and restarting process
including the control of ignitor unit (UNIT-4), a low frequency
symmetrical logic signal (Q) to control the logic driver in the
normal operating (X=1), and an automatic switching off feature
under no load or lamp failure conditions or in the case of an old
25 lamp.
The control unit CU-3 including the following function-
al circuits:
a first voltage comparator (IC33/1) with a comparator
level V1, where V, is somewhat smaller than VO(~;
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.
1 1
a second voltage comparator (IC33/2) with a comparator
level V2, where V2 is somewhat smaller than V1;
a first timer (IC34) having a timing period of tlzlOs;
a second timer including a digital counter IC35 and a
digital oscillator IC36 having a timing period of t2z120s;
a low frequency digital oscillator IC37 where thefrequency fiz25Hz and the duty cycle is arbitrary;
a high frequency digital oscillator IC38 having a
frequency f2z20kHz and the duty cycle being smaller than 0.5;
a T flip-flop implemented by a D flip-flop IC39 having
a clock input and a SET input providing the symmetrical signal
Q; and
two AND gates IC40/1 and IC40/2, as well as two
inverters whose functions are obvious from FIG. 6A.
FIG. 6C shows the timing diagram under no load
condition including the case of an unsuccessful ignition. FIG.
6D shows the timing diagram in the case of a successful ignition
(normal operation). The ignited lamp operating quickly in a
complicated plasma physical process (including the glow dis-
charge) achieves the state of arc discharge, assuming that a
sufficient high voltage and high current are provided. After
achieving arc discharge, an important task of the circuit of the
present invention is to stabilize the lamp in the arc discharge
state. Since the discharge tube is cold, any slow zero current
_ 25 crossing can cause an extinction of arc discharge.
Therefore, there are two different short term starting
methods for avoiding extinction as applying a high frequency
current pulse operation, or a DC operation.
The time period of short term starting operation is
implemented by the first timer (tlzlOs). After the short term
starting period, the discharge becomes a normal low frequency
(z50Hz) symmetrical square wave operation. The different
starting operations can be selected by a switch S as it is shown
in FIG. 6A, which switches between the high frequency (HF) or
direct current (DC) mode. In the case of DC starting operation,
the control circuit can be obviously simplified. For HPS lamps,
2 1 67 1 8~
12
the simpler DC starting method can be satisfactory. The square
wave full-bridge PU-3 can be completed with one of the standard
current limiting methods connected together with the control unit
which is not shown in FIG. 6A.
UNIT-4, which is connected to the output of UNIT-3 is
also shown in FIG. 6A. Additionally, resistor R42 is connected
to the output capacitor C10 of the preregulator unit. UNIT-4
implements an ignitor for HID lamps providing high voltage
(z3500~ ignition signals. The circuit is based on a pulse
transformer configuration including a pulse transformer L41, a
thyristor Th41, a capacitor C41 and an RC circuit (R41 and C42)
connected to the gate of thyristor Th41. The capacitor C41 is
charged by a resistor R42 connected to the output capacitor of
UNIT-1. The capacitor C41 is discharged periodically by
thyristor Th41 which is controlled by the digital counter of unit
CU-3 with a repetition frequency of 2Hz. The voltage of the
fully charged capacitor C41 (~450~ is increased by a transform-
er including windings N~ and N2 where Nl/N2=8. In normal
operation the thyristor Th41 is switched off and the pulse
transformer implemented by a gapped core lnductor acting as a
filter element. Furthermore, inductor L41 provides a continuous
current flow through the lamp when the unit PU-3 changes the
polarity of lamp voltage containing deadtimes.
UNIT-5, which is connected to the sinusoidal AC power
supply (more precisely to the common mode filter of UNIT-1) is
- shown in FIG. 7. UNIT-5, acting as a stabilized voltage source,
includes a low power half-bridge square wave inverter designated
as HB and five linear regulators designated as LR-1, LR-2, LR-3,
LR-4 and LR-5. The low power self-oscillating half-bridge
inverter (square wave oscillator) includes a rectifier bridge
B51, an energy storage (film) capacitor C51, connected to the DC
output of B51, two transistors T51 and T52 acting as controlled
switches, two voltage divider capacitors C52 and C53 and a
transformer L51 acting as a high frequency half-bridge square
wave oscillator.
The transformer has a primary winding N~, two feedback
windings Nf~ and Nf2, and five secondary windings Ns1, Ns2' Ns3~ Ns4
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13
and Nss providing appropriate (non-stabilized) voltage sources
for the five linear regulators. The feedback windings, connected
in series with RC circuits (R51, C54 and R52, C55), are connected
to the bases of transistors T51 and T52, providing decreasing
base (diode) currents and therefore alternating switched ON or
OFF states for the transistors. The self-oscillating feature is
realized by the polarity change in the windings caused by the
switched off magnetizing current of transformer L51. Further-
more, the circuit includes a self-switching off starter circuit
implemented by a continuously charged capacitor C65, a DIAC S51
and a transistor T53 controlled by winding Nf1. The rectified
output voltages are essentially DC voltages from a high frequency
viewpoint. Therefore, only small value film capacitors can be
used as smoothing elements. Stabilized output voltages (1 2V) can
be obtained by the use of any standard linear regulation methods.
UNIT-6 operates as a monitor unit including four
Schmitt-triggers is also shown in FIG. 7. The Schmitt-triggers
ST-1, ST-2, ST-3 and ST-4 (see FIG. 1) are implemented by four
voltage comparators designated as IC61, IC62, IC63 and IC64. The
first Schmitt-trigger (IC61) is controlled by a photoresistor
(PH) implementing a light controlled switch. The second Schmitt-
trigger ( IC62) is controlled by a thermistor (TH) implementing
a temperature controlled switch. The third and fourth Schmitt-
trigger (IC63 and IC64) are controlled by a voltage Vx which is
proportional to the input voltage implementing a window compara-
- tor. Transistor T61 is controlled by the common outputs of
comparators (AND connection) resulting the monitor unit. The
output (M) of transistor T61 controls UNIT-1 and UNIT-2 imple-
menting ON or OFF states for them as M=0 or M=1 (-12~ .
Thus, while preferred embodiments of the present
invention have been shown and described in detail, it is to be
understood that such adaptations and modifications as occur to
those skilled in the art may be employed without departing from
the spirit and scope of the invention, as set forth in the
claims.
