Note: Descriptions are shown in the official language in which they were submitted.
21 84q84 ~
MT~THOD ANn APPARATUS FOR THT~ T~NT ARcT~MT~NT OF TR~ RT~'A('~T
OF TITT~` TRANSMTSSION ~ITANNT~T B~TWT`T`N FUNCTIONAT GROUPS
OF AN I~nN--USER TNTT~RFACE
The invention relates to a method and apparatus for
s the enlargement of the reach of the transmission channel
between functional groups of an ISDN-User interface with
reference to one or more equivalent ISDN interfaces, as they
are for example standardized according to CCITT I. 400 - ISDN
user network interface and I.430 - basic user network
10 interface. With this invention it is possible to transmit the
many faceted ISDN services over great distances.
The ISDN (Integrated Services Digital Network),
which allows, in addition to speech transmission, the rapid
transmission of data, text, and pictures also allows for the
lS possibility of the connection of NT and TE apparatus, as well
as other distribution nets.
For the functional separation of the elements which
are used in a participant connection, it is useful to consider
the reference configuration with the CCITT. Fig. 3 shows the
20 reference configuration for the ISDN-participant connection
with the reference points R, S, T, U and V.
The functional units in accordance with Figure 3
describe each unit:
ET, exchange termination: transfer point of the net which
transmits a user signaling
identity to the net side;
2s LT, line termination: line termination which terminates
the transfer on the net side of
the connection from the transfer
point to the user interface. It
is sometimes regarded as part of
the ET exchange termination and
not specifically represented.
NT 1, network termination 1: this is the termination from LT
to the user interface, can be
2 1 84~84
controlled by the network
provider and isolates the end
system connection from the
transmission technology of the
user interf ace .
NT 2, network termination 2: if present, the conveyance, i.e.
concentration f unction in the
realization of a PBX private
branch exchange.
TE 1, tPrmin~l equipment corresponds to the ISDN
type 1: interfaces and works directly
with NT 1, or NT 2.
TE 2, t~rrnin;~l equipment is a conventional end apparatus
s type 2: with an analog interface and for
the feeding from the ISDN a
terminal adaptor, TA is necessary
to establish the access to the
I SDN .
This use reference configuration identifies the
ne,P~Ary functions ;nrlF.r~nrl~ntly of technical details and
establishes their relative position to one another. Between
these functional groups, certain reference points are defined,
o which separate the functional groups from one another. The
reference point V is located between the conveyance point and
connection termination, the reference point U is located
between line termination and network termination, the
reference point T is located between network termination 1 and
2, the ref erence point S is located between network
termination and an end system type 1 and the ref erence point R
is located between the t~r~in~l adaptor TA and an end system
type 2. For the reference point U national standards exist
and for the reference points S and T there are international
20 standards.
-- 2 --
2t84984
At the interfaces of the ISDN participant
connections there is a multiplicity of functions which have to
be realized. An SO - interface, for example, must fulfill the
following functions:
s - For each transmission direction 2 lines
( copper );
- A gross transmission rate of the AMI coded
signals in each direction of 192 Kbit/s;
- A net data rate (2B -h~nn~l ~ plus lD channel)
lo which equals 144 Kbit/s (48 Kbit/s for
synchronization and control);
- Step timing: derived from the bit stream which
occurs at 192 Kbit/s;
- Octet timing: derived from 192 Kbit/s which
equals 8kHz (for speech coding);
- Frame synchronization: realized through
deliberate code violations for purposes of
recovery of the time division f~h~nn~
-- D/echo channel: serves the orderly attachment
of the TE device to the D channel;
- Activation and de-activation (the changeover
between utilization and rest conditions).
Frame build-up and coding of the transmitted bytes
are subject to a rigorous rule. In accordance with the rules
2s of the EIDLC, the information to be transported is built in to
one or more frames which always begin and end with a special
bit sequence. According to established rules, procedures such
as frame synchronization, super frame control, connection
control, remote feed, and activation and de-activation are
30 realized.
Regardless of a net side connection of ISDN t~rm;n~l
equipment or network terminations it is an advantage to extend
the reach of the transmission channel between functional
~ groups of the ISDN participant connection (with reference to
3s one or more ISDN basic connections SO, or other interfaces), to
transmit the information from a net over a longer distance.
-- 3 --
~ 2t~4~84
However, the achievable reach with conventional apparatus is
signif icantly restricted because of the electrical properties
of the ISDN interfaces and connection ways. For example,
heretofore, it has not been possible to drive a S0 interface
s over more than 1000m (point to point connection) or an Uk0
interface without intervening connections of amplifiers, over
more than 6 kilometers. That means that the reach of the
transmission way between functional groups of the ISDN
participant connection to one or more ISDN interfaces is
0 limited.
In accordance with GB-A-2249927 it is Icnown to
convert information of a lower data density into information
of a higher data density. In accordance with this process the
conventional pulse code modulation process according to ISDN
is utilized and data of several rh~nnPl ~ are transmitted in a
bundled form over a primary multiplex process. The ISDN
typical timing relationships are maintained. When extended
transmission distances are required, the establishment of
connections break apart and no communications can arise. From
ICC '84, LINKS FOR TIIE FUTURE, vol. 2, Amsterdam 1984, it is
known to transfer from a U interface to several different S
interfaces. The transfer function requires a Corr~cpfln~;n~
address scheme and the active utilization of the D channel and
hence a utilization of the layer 2 information. Various
2s transfer functions are based on the typical ISDN data
structure but the utilized time multiplex process is not
suitable for large tr~ncmif:s~on distances.
In accordance with standard CCITT I. 400 the signal
travel tsignal delay) time, for example between the functional
units NT and TE, and back, is standardized between a minimum
of 10 microseconds and a maximum of 14 microseconds. This is
primarily caused by the 2-bit frame shift which is necessary
for time recovery (frame shift equals code displacement as a
signal for the beginning o~ a frame).
3s To detect a collision, the frame beginning (2-bit)
must be detected within 709~ of the signal transfer time
period .
-- 4 --
2~ 849~4
-- For 2-bit this equals 10.416666 microseconds
and,
- with return answer, equals 3 . 6458331
microseconds .
s Under the assumption of a wave attenuation of 7. 6 dB
per kilometer (for copper) the signal transfer time delay
T = 9 microseconds per km. From this relationship
g~ls/~m
one can determine the maximum extension of the
sO connection. This calculation is valid for case of point to
o many point configurations. The calculation for the point-to-
point configuration (no collision recognition) analogously
yields 1 kilometer.
The timing relationships f or the transmission over a
satellite channel do not change with respect to the collision
recognition. However, the signal transit time over a
connection via a geo-stationary satellite (approximately
36,000 kilometers) changes. The signal transit time is 220 ms
in one direction, and with reply, 440 ms. These timing
relationships show that a direct extension of the reach of the
transmission channels between functional entities of the ISDN
network connection are impossible from a basic interface sO.
An object of the invention is to create a process
and apparatus which allow the extension of the reach of the
transmission channel between functional entities of the ISDN
2s user network. This is achieved by the maintenance of all ISDN
typical characteristics, such as:
- maintenance of the network timing
-- multiple acces6 to the inter3~ace bus
- activation and deactivation of the interf ace .
In accordance with the invention the object of the
extension of the reach of the transmission channel between
functional entities of the ISDN network relative to one or
-- 5 --
21 84984
more similar ISDN interface6 is solved in a process in which:
a) the data transmission from the net side occurs
in such a manner that the data arriving at the
respective ISDN interfaces tcoded in ISDN
s specific format) are converted by way of a code
converter into binary coded data, separated in
accordance with B and D channel information,
b) the arriving binary coded data, of the B&D
~-h;~nnPl c: are grouped into data blocks (by way
o of a buffer arrangement), and then are
augmented with the address of a particular ISDN
interface, and thereafter, are sequentially
delivered to transmission means with a timing
derived from the ISDN interface timing and are
transmitted by the transmission means to the
receiver side with bit timing derived either
from an independently produced bit timing or a
bit timing derived from the ISDN specific
timing,
c) on the tPrmin~1 side, the required ISDN
specific timings, required for communication
between sender and receiver, are derived from a
timing recovery process which occurs either
through the arrival sequence of the received
2s data blocks or the sequence of the transmitted
data bits, and
d) the received data blocks are stored in a buffer
in accordance with their addresses, and
transferred to the respective ISDN interface,
wherein the B channel information, and the D
channel information, if any, is provided to a
code converter in accordance with the Le~uv~:Led
timing information where the binary coded data
-- 6 --
~ 2184984
is converted to ISDN specif ic coded data, and
e) on the t~rm;n~l side the data transmission
occurs in a fashion analogous to process steps
a) and b) wherein the ISDN specific timing
s mentioned in step b) is the timing which is
derived or recovered in accordance with the
process step c), and
f) the data blocks received on the net side are
o allocated and transmitted, in accordance with
the buffer apparatus, to their respective ISDN
interfaces where, through a code conversion
process, the data is converted f rom the binary
coded form into ISDN specific coded form in
1S accordance with the timing for the ISDN
specif ic timing of the net side.
Preferably, the block formation in accordance with
step b) of the process occurs in such a manner that the blocks
have equal lengths and the B and the D channel data exhibit a
partition which corresponds to the capacities of the B and the
D <-h;~nnf~l ~ of the ISDN interface.
For those times in which the D channel carries no
information, the block formation occurs in equal length
without D channel data.
2s For those times, in which the ISDN interface n is
not active, block formation occurs in such a fashion that
equal length blocks of a fixed length are formed. These
blocks carry no relevant information as they serve only for
the maintenance of the communication ability between net and
t~rm;n;~l side.
An active intervention in the D channel
signalization occurs for those cases in which the signal delay
of the D channel signalization is too large for the utilized
transmission channel. In these cases, the activating
3s participant is advised that the connection has not been
-- 7 --
~ 21 84984
established .
The length of the blocks built in accordance with
process step b) is dependent on the capacity of the processing
units required for the coding, transmission, and uncoding of
s the ISDN interface information as well as the ISDN speciflc
channel capacities.
The blocks formed at the receiver side are bit timed
either with an independently produced timing signal or with a
timing signal derived from the ISDN specif ic timing for
lo transmission over transmission over satellite or other
transmission rh2~nn~
In accordance with CCITT I.400, to ensure the
accurate distinction of the flags (0111110) in the
transmission of the information bytes in the blocks, a "O" is
5 inserted in the bit stream wherever more than 5 "ones" follow
successively. As a result, the real nP~cs~ry bit rate
increases. To reduce the probability for this occurrence,
preferably the blocks are connected with an exclusive OR
before and after transmission. For this purpose pre-defined
20 bytes, with changing bit value, are used.
Timing recovery in accordance with step c) of the
process, when the transmission system determines the
transmission timing, occurs in such a f orm that a comparison
timing is derived from the time-spaced arrival of the received
2s data blocks, from which, in accordance with known principles,
a base timing is produced in a phase locked loop (PLL) from
which the timing for the ISDN n interfaces is provided on the
tPr~; n~ 1 S ide .
When the bit timing for the tr~n~:mi~ion system can
30 be provided with a process in accordance to the invention,
this base timing for the ISDN interfaces is preferably derived
from the bit transmission rate by way of a PLL.
Both the t~rrnin~l and net side code conversion of
the ISDN-specific coded data into binary form occurs through
3s known principles by way of a code converter, preferably an
ISDN subscriber access controller.
In accordance with the invention, the realization of
-- 8 --
~ 21 84984
the process ~or the enlargement of the reach o~ the
transmi6sion channel between functional entities of several
ISDN participant connections occurs through an arrangement
which comprises on both terminal and net sides an arrangement
s for protocol conversion and means appropriate for the
transmission channel.
The transmission channel comprises transmis5ion
arrangements which are per se known and which are adapted to
the medium utilized, for example a satellite channel with the
appropriate sending and receiving arrangements as well as the
required modems.
The arrangements for protocol conversion communicate
with one another over the particular transmission channel and
are preferably formed in the same way and can function both in
master mode as well as slave mode wherein the arrangement
connected to the net side functions in master mode and the
arrangement on the tPrmin~l side functions in slave mode. But
it is also possible to achieve the arrangement of a protocol
converter exclusively in master or slave mode wherein an
arrangement at the net side comprises an arrangement working
in master mode and the arrangement on the tPrm;nAl side
functions in slave mode.
The assembly for protocol conversion consists
essentially of:
zs A number of interface modules (1) corresponding to
the number n of the ISDN interfaces to be connected
A microcomputer (66), and
An interface module (2) for the transmission channel
X
A module f or timing ( 3 )
One PIO (92),
A mode switch (5)
A power supply (4)
as well as the corresponding electrical connections
3s and a bus for the addres6 and data exchange.
The microcomputer 66 is connected over a bus b with
the ISDN interface modules 1, and over the bus b, with the
_ g _
21 8498~
parallel input-output-building block PIO 92 as well as with
the interface module 2 for the connection to the tr~nRmi ~cion
channel X.
The module (3) for timing generation is connected,
s via bus b, with the interface module 1 and with the interface
module 2 for the connection to the transmission channel X as
well as with the PIO block 92 with microcomputer 66.
The switch 5 for the mode setting (master/slave)
functions on power supply 4, on the interface module 1 and on
0 the module 3 for timing generation.
The power supply 4 supplies a switch with voltage
and produces, when the protocol converter works in 81ave mode,
the 6upply voltage for the tPrm;nAl equipment which i8
independent of the net.
1S Every ISDN interface module 1 converts the ISDN
interface into a binary coded form. The binary data as well
as the required control information are exchanged, via bus b,
between the interface module 1, the microcomputer 66, the PIO
92 and the interface module 2. The interface module 1 is
20 comprised on an ISDN interface and a circuit for the
conversion of the ISDN-specifically coded data into binary
data, for example an ISDN-subscriber access controller. The
interface module 2 for the transmission on the X channel
comprises a interface and a serial input-output building block
2s SIO.
The microconputer 66 comprises a microprocessor, a
ROM for the storage of the program code, a RAM as working
memory and a bus. The microcomputer 66 is connected with the
parallel input-output block PIO 92 and with the ISAC circuit
30 in interface module 1 as well with the serial input-output
building block SIO over a bus. The processor in microcomputer
66 controls the function of the building blocks PIO 92, the
ISAC circuit in interface module 1 and SIO in interface module
2 in a known manner through appropriate adjustment of the
3s registers provided therefor in these building blocks.
In case of the realization of the arrangements for
protocol conversion exclusively in slave or in master mode,
-- 10--
~1 84984
these elements consist of almost the same building blocks as
described above. The switch for mode selection 5 i5
eliminated. The other building blocks are switched so that
they achieve the functions in slave, or, master mode as
s described above.
On the net side the system for protocol conversion
functions in master mode as follows:
in the interface module 1 there is a conversion of
the signal levels existing at the ISDN interface to
the signal levels required by the ISAC circuit.
The mode switch 5 switches the ISAC building blocks
in all interface modules 1 into the TE mode-t~rminAl mode. In
such a mode the ISAC produces a timing signal of 512kHz at the
output DCL. When the ISDN interface is active, the timing
15 signal of 512kHz is synchronously derived from the bit timing
of the ISDN interface.
The timing signal of 512kHz of every interface
module is transmitted to the module 3 for timing signal
generation. The processor of the microprocessor 66 designates
20 the lowest logical address in the interface module which
corresponds to the ISDN interface which is active. The timing
signal of 512kHz of the ISAC circuit of exactly this ISDN
interface is used in the module 3 for timing generation timing
module (all as controlled by the processor in microcomputer
2s 66, to produce a symmetrical timing signal). Such timing
signal is provided to a port of the PIO 92 of the
microcomputer 66.
The ISAC circuit in the particular interface module
1 converts the ternary coded B and D channel signals of an
30 ISDN interface, insofar as it is active, into binary coded
signals and stores these, by byte, in its registers. In
reverse, the circuit converts the binary coded B and D channel
data from the processor into ternary signals and transmits
these data to the interface of the corresponding interface
3s module 1 for transmission to the ISDN interface n.
The ISAC circuit signals, through a register, that
it is prepared for the reception of new B1 and B2 channel
2184984
bytes and, simultaneously, for a complete Bl and s2 channel
byte, through the processing microcomputer 66. The processor
in microcomputer 66 periodically interrogates the signal
register of the ISAC circuit and accepts, or transmits, the
s completed B channel bytes in its working memory.
Through a further register, the ISAC circuit also
signals when a D channel frame from a particular ISDN
interf ace has been received . The processor in microcomputer
66 also interrogates this register periodically and reads the
o signal bytes and receives, in the appropriate case, the D
channel frames in its working memory.
When the processor in microcomputer 66 has received
a D channel frame, it, in turn, transmits these bytes to the
ISAC circuit for further delivery to the ISDN interface.
From the bytes transmitted from the ISAC circuit the
proces60r f orms blocks and stores these in the RAM of
microcomputer 66 in the interim.
The processor in microcomputer 66 will always
receive an interrupt signal from the PIO 92 when the signal
levels change upon receipt of the timing signal. At every
such signal, the first part of a new block is delivered to the
SIO in the interface module 2 and a control register is set in
the SIO to make this building block responsible to commence
the transmission of this block. The SIO designates in its
2s register, when the next portion of the block has to be
delivered so that the delivery is not interrupted. The
processor in microcomputer 66 interrogates this register
repeatedly and delivers to the SIO in interface module 2 the
corresponding further portions of the block.
The processor delivers to the SIO in interf ace
module 2 successively received data blocks corresponding to
the cyclically repeated logical addresses of the ISDN
interfaces n. All ISDN interfaces operate synchronously on
the basis of the central system timing of the ISDN so that the
3s blocks are also produced synchronously.
In the reverse direction, the SIO in the interface
module 2 receives data bit serially over the interface in
-- 12--
- 2 1 8~ 9~4
.
interface module 2. When the first portion of a new blook or
a further portion of a block is received in the SIO,
appropriate signalization bites are set in a register in the
SIO. The processor of the microcomputer 66 periodically
s interrogates this register. When the receipt of a block is
indicated, the processor receives this block in its working
memory RAM. The blocks are stored in accordance with the
logical address stored in the control bytes. Several recently
received blocks are stored in accordance with the logical
address.
Internal registers within the SIO in interface
module 2 signal that a B channel byte is to be delivered to
the ISAC circuit for transmission to the ISDN interface n.
The processor of microcomputer 66 interrogates these registers
of all ISAC circuits repeatedly and delivers the corresponding
B bytes to the relevant ISAC circuit.
The D channel bytes of the blocks received in
interface module 2 are delivered to the known D channel
registers in the ISAC circuit in interface module 1.
On the ~Prm;n~l side, the arrangement for protocol
conversion in slave mode functions as follows:
in the interface module l a conversion occurs at the
interface from the signal levels of the respective
ISDN interfaces n to the signal levels required by
the ISAC circuits.
The ISAC circuits in interface module 1 is switched
to the network tPrm;n;31 mode by the mode adjuster 5. In such
mode, the ISAC circuit requires syn. IILU~IUUS timing signals at
its inputs DCL of 512kHz, and 8kHz on FSC 1 and FSC 2. From
these signals, the ISAC circuit delivers the same
synchronization and bit synchronization timing signals for the
ISDN interf ace .
Module 3 for timing signal generation derives a
timing signal from the arrival times of the blocks from the
3s master apparatus. From this timing signal, module 3 produces,
in accordance with the well known working principles of a PLL,
a timing signal 512kHz and therefrom, through division, a
-- 13 --
2 1 849~4
timing signal of 8kHz. These timing signals are delivered to
the corresponding inputs of the ISAC circuit of all interface
modules 1.
From the 8kHz signal a further symmetrical timing
s signal is generated in module 3 and delivered to one input of
PI0 92.
Microcomputer 66, ISAC switching network in
interface module 1, and the SI0 in interface module 2,
function in a similar manner as in the master apparatus
o together in the further transfer of the B and D channel data
between the ISDN interface and the X channel.
Advantageously, arrangements for protocol conversion
can be constructed from discretely elements as well as an
interf ace module 1 or with several interf ace modules 1. A
mode switch 5 then supplies an additional switching function
for the operation of signal arrangements for protocol
conversion autonomously or the allocation and the common
operation of selected arrangements for protocol conversion.
In accordance with the process and apparatus of the
invention it is possible to transmit the many faceted services
of the ISDN over the appropriate interfaces, parallel in
accordance with the ISDN rh~nn~ , over large distances
without transf er to another net . Thus it is pos6ible to
remain in the utilized ISDN net whereby the quality of the
2s transfer services is not af~ected.
Further exemplary embodiments of the invention are
illustrated in the attached drawings. Thereby shown
Fig. l shows a functional block diagram of an
arrangement for protocol conversion
Fig. 2 shows and arrangement for the extension of
the reach of a transfer channel between functional groups of
an ISDN user interface.
Fig. 1 shows a block diagram of one arrangement for
protocol conversion.
3s Microcomputer 66 is comprised of a microprocessor
-- 14 --
' ~ 2184q84
(realized as an N80C188XL-20), a ROM for the storage of the
program code, a RAM as working memory and a bus.
The microcomputer i8 connected with an SIO circuit
(configured as a SAB82532) in interface module 2, with a PIO
s building element functionally created within SAB 82532, as
well as with an ISAC circuit (realized as a PEB 2086) within
interface module 1. The processor in microcomputer 66
controls the circuits PIO 92, PEB 2086 and SAB82532 through
appropriate switching of the registers provided for these
purposes in these building blocks. At the same time the
processor interrogates these building blocks over these
registers about the condition of them and exchanges data with
them .
The activation/de-activation of the ISDN interface
is controlled through PEB 2086 and interface module 1. The
condition of each ISDN interface can be read from the
registers of PEB 2086. The processor in mi~L.,c _Ler 66
periodically interrogates the registers of PEB 2086 to note
the condition of the respective ISDN interface.
The arrangement in Figure 1 functions in master mode
on the net side as follows:
Interface module 1 converts, in each direction, the
signal levels of the ISDN interface to the levels required by
circuit PEB 2086.
2s By way of the mode switch 5 the building blocks PEB
2086 of all interface module 1 are switched into the t~rm;n~l
mode. In this mode, PEB 2086 produces a timing signal of 512
kHz at its output DCL. When the ISDN interface is active, the
timing signal of 512kHz is derived synchronously from the bit
timing of the ISDN interface. The timing signal of 512 kHz of
every interface module is provided to the module 3 for timing
signal generation. The processor of microcomputer 66
de~rm; n~fi the interface module 1 with the lowest logical
address of the ISDN interface which is active. The timing
3s signal 512kHz from PEB 2086 of exactly this ISDN interface is
utilized, through control of the microcompressor, in the
-- 15 --
2 1 84984
module 3 for timing generation to achieve, through division, a
symmetrical timing signal of 500Hz.
The 500Hz signal is delivered to a port of PI0 92 of
microcomputer 66.
s PEB 2086 in interface module converts the ternary
coded B and D channel signals of the ISDN interface (insofar
a6 it is active), into binary coded signals and stores these,
byte by byte, in its registers. In the reverse direction, PEB
2086 converts the incoming binary coded B and D channel
lo signals from microcomputer 66 into ternary signals and sends
these data to the interface of the interface module 1 for
delivery to the appropriate ISDN interface.
Through a register PEB 2086 indicates that it is
ready for the transfer of a new B1 and B2 channel bytes and
simultaneously a complete B1 and B2 channel byte from the
processor. The processor of microcomputer 66 periodically
interrogates the signaling register of PEB 2086 and either
receives, or delivers, the formed B channel bytes in its
working register.
Through a further register, PEB 2086 signals when a
D channel frame has been received from the ISDN interface.
The processor periodically interrogates these signaling bytes
and accepts the D channel frame in its working memory.
If the processor has received a D channel frame from
2s its opposite part, it transmits these bytes to PEB 2086 for
further delivery to the ISDN interface.
The processor of microcomputer 66 builds blocks from
the bytes received from PEB 2086 and stores these in its
working RAM.
The processor in microcomputer 66 will always
received an interrupt signal from PIo 92 when the timing input
500Hz of PI0 92 changes its signal value. With every such
signal, the first part of a new block is transmitted to the
SAB82532 in interface module 2 and then a control register in
3s SAB82532 is set whereby this building block is directed to
begin the transfer of this block. SAB82532 indicates in a
known register when the next part of the block must be
-- 16 --
21 84q84
transmitted so that the transmission does not break off. The
processor periodically interrogates this register and delivers
the further sections of the block to SAB82532.
The processor in microcomputer 66 transmits to SAB
s 82532 in interface module 2 blocks in a continuing sequence
corresponding to the cyclically read logical addresses of the
ISDN interfaces. All active ISDN interfaces operate
synchronously on the basis of the central timing of the ISDN
so that the blocks are also produced synchronously.
lo When the ISDN interface is not active, the processor
in microcomputer 66 builds equal blocks of f ixed length and
transmits these instead of the data blocks.
In the opposite direction, SAB 82532 in interface
module 2 receives bit serial data over the interface in
interface module 2. When a first portion of a new block, or a
further portion of a block are received in SAB82532,
appropriate signaling bits are set in a register of SAB82532.
The processor of microcomputer 66 periodically interrogates
this register. When the receipt of a block is indicated, the
processor accepts this block in sections in its working 3~AM.
The blocks are ordered and stored in accordance with the
logical address coded into the control bytes. The two most
recently received blocks are temporarily stored per logical
address .
2s The B channel bytes in the stored blocks are
delivered with an average delay of (2xn x 16~ bytes, with
reference to the time of their arrival, to the PEB 2086 in
interface module 1 corresponding to the designated logical
address of the blocks and the interface module.
PEB 2086 in interface module signals over internal
registers that a s channel byte is ready for transfer to PEs
2086 for transmission to the ISDN interface. The processor of
microcomputer 66 periodically interrogates the registers of
all PEB 2086 units and then transfers the corresponding B-
3s bytes to PEB 2086.
The D channel bytes of the blocks received by
interface module 2 are transferred to the known D channel
- 17--
2 1 849~4
registers of PEB 2086 in interface module 1.
When the D channel frame is complete or a section of
32 D channel bytes i8 transferred, the processor arranges the
transfer of the bytes through PEB 2086 to the ISDN interface
s by setting a proper register in PEB 2086.
On the tPrm;nAl side the arrangement of Figure 1
operates in slave mode as follows:
The conversion in either direction of the signal
levels from the ISDN interface to the signal levels needed by
10 building block PEB 2086 occurs in the interface module 1 at
the ISDN interface.
The mode switch 5 switches building block PEB 2086
in interface module 1 into the network tPrminAl mode. In this
mode, PEB 2086 requires synchronous timing signals at the
input DCL of 512kHz, and 8kHz at FSC 1 and FSC 2. From these,
PEB 2086 delivers the frame and bit synchronization signals
for the ISDN interface.
Module 3 for timing signal generation derives a
timing signal of lkHz from the sequence of arrival of the
20 blocks from the master unit. From this timing signal, module
3, working in accordance with known principles of a phase
locked loop, produces a timing signal of 512kHz and therefrom
through division, a timing signal of 8kHz. These timing
signals are delivered to the corresponding inputs of the PEB
2s 2086 of all interface modules 1.
From the 8kHz signal module 3 further delivers a
timing signal of 500Hz and delivers it one of the inputs of
PIO 92.
Microcomputer 66, PEB 2086 in the interface module
30 1, and SAB82532 in the interface module 2 function in similar
ways as in the master unit in the further transfer of the B
and D channel data between the ISDN interface and the X
channel .
The power supply for the apparatus produces for a
3s connected TE without its own power supply a DC voltage of 40
volts which is transferred over the ISDN inter~ace to the TE.
-- 18 --
2 1 84~84
The blocks formed by the processor in microcomputer
66 have the following structure:
In the arrangement for protocol conversion every
interface module 1 utilizes a switching network of PEB 2086
s for the coupling between the ISDN interface (S/T-reference
point) and bus (b).
At every active ISDN interface there are sent, as
well as received, four frames of 48 bits per millisecond at a
bit transmission rate of 192kHz. Four frames contain:
64 bits channel B1
64 bits channel B2
16 bits channel D.
These data are stored in corresponding internal
registers of PEB 2086 in interface module by byte and sorted
in accordance with the chAnnPl c so that they can be read by
micLu,~ er 66 over the bus (b).
On the D channel of the ISDN, HDLC f rames are
transmitted. PEB 2086 stores only those D channel bytes which
have been received within a D channel frame.
Por transmission over the X channel, microcomputer
66 forms a block in n milliseconds in parallel (time
multiplex) for every interface module 1 and stores these in
the working register (RAM) . Per m~ l l l f~prnntl ~ a block is
created of 8 B1 bytes and 8 B2 bytes.
2s For example:
Bl.l¦B2.1¦Bl.2¦B2.2¦Bl.3¦B2.3¦Bl.4¦B2.4¦Bl.5¦B2.5¦
Bl.6¦B2.6¦Bl.7¦B2.7¦Bl.8¦B2.8
These blocks (hereafter characterized as GB) are
sequentially, arranged in accordance with the number n of the
30 interface modules 1 utilized and an c-nh~n~!~d, insofar as
available, by 2xn D bytes. Preceding is a control byte S in
which the logical channel and the possible beginning of a D
channel frame is encoded.
Block structure:
3s S¦GBl¦GB2¦GB3 ¦ . . . ¦GBn¦D1. . . ¦Di¦Di+1¦ . . . IDj
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2l 84984
The number i + j of the D bytes is r~Y;r~l ly 2 x n
and greater than 0, when D frames are to be transmitted. S is
a steering byte in which the logical address of the interface
module l, as well as the value i, is encoded so that it shows
s that Di is the last byte of the preceding D frame and Di + 1
the first byte of a following new D frame.
Flags (at least one flag) is transmitted between the
blocks as separators. Thus, the X channel must have a
transmission rate in both directions of at least
o [18 x n + l] x 8 kBits/s.
In the arrangement connected to the net side every
PEB 2086 is programed in the TE mode and thus delivers a
timing signal of 512kHz which is derived synchronously from
the bit transmission rate of the ISDN interface and
synchronously for the system timing of the ISDN. From one
these timing signals the control module derives a synchronous
timing signal of
1 kHz and n x 160 kHz.
The data blocks are delivered on the X channel to
the units connected on the participants side synchronously
with the lkHz timing signal.
The transmission can occur either
a) with a bit timing signal from the transmission
arrangement or
2s b) with a timing signal of nxl60kHz arranged in
the unit. This can be det/~rmin~d by a switch.
In the arrangement on the participant's side for the
protocol conversion, every PEB 2086 is pLCIyL ?1 in the NT
mode and thus requires therewith synchronous timing signals of
512kHz and 8kHz. These timing signals can be derived either
from the time spaced succession of the blocks or, insofar one
works with the bit transmission timing in accordance with (b),
-- 20--
2l84984
.
derived from the received bit timing by way of a PLL. These
timing signals are synchronous with the 512kHz timing signals
in the arrangement connected to the net side. PEB 2086 forms
from these signals the ISDN frame timing signal of 4kHz at a
s bit timing of 192kHz. Thus, the synchronicity of the ISDN
units on the participant ' s side with the ISDN is assured.
The data blocks of the above described structure are
transmitted on the modem channel in both directions in
accordance with the sequence of their formation. The received
o blocks are stored in the working memory. The B and D channel
bytes of the blocks are transmitted in accordance with logical
number of the blocks from the storage to the register provided
therefor in PEB 2086 of the appropriate interface module 1.
PEB 2086 transfers these data to the ISDN interface in
15 accordance with the timing and frame structure.
When the ISDN interface is not active, the processor
in microcomputer 66 forms equal length blocks of a fixed
length with the following structure:
S-Byte ( Channel) ¦ ISAC-S-Condition Byte ¦ ISAC-S-
Condition Byte¦ . . ¦ . . ¦ . . ¦ . . ¦ . . ¦ . . ¦
The S-byte signif ies the logical channel . The
condition byte is delivered from the circuit of PEB 2086 and
indicates the condition of the ISDN interface. The condition
byte is repeated in the example and the block is filled out
2s with 9 bytes. The 6 bytes for filling do not carry any
relevant inf ormation .
To assure the certain differentiation of the flags
(Ollllllo), during block transfer, from the information bytes,
a "O" is inserted in the bit stream where more than five "1"
follow one another. This results in an increase in the real
required bit rate. To reduce the probability of this
occurrence the blocks are connected, prior to transmission,
through an exclusive OR with the bytes sequence O x 55,
O X AA,
3s Figure 2 shows an arrangement for the enlargement of
the reach between functional units of ISDN participant
connections, with reference to an SO interface. Emitting from
-- 21 --
~ 1 84984
.
an ISDN network, over an interf ace Uko to a network termination
NT, a protocol converter is arranged on the net side at the SO
interface which communicates over the transmission channel
with an arrangement for protocol conversion on the t~rmin~l
s side and which prepares the interface SO on the tPrm; n~l side.
On the terminal side one can drive an NT 2 unit or TE units
directly .
The apparatus connected to the SO interface on the
net side functions in master mode and the apparatus connected
10 to SO interface on the t~rm;n;ll side functions in slave mode.
The unit operating in master mode behaves, with respect to the
ISDN net, like a t~rm;n~l equipment TE and the unit working in
slave mode appears as an NT network termination.
Between the two units connected over the
5 transmission channel for protocol conversion (PW) the data
exchange proceeds by way of bit serial synchronous
transmission of data blocks of 16B channel bytes plus, at
most, 2D channel bytes.
The arrangement for protocol conversion PW in master
20 mode activates the SO interf ace always when it is not active .
It transmits blocks only when the SO interface is active.
The arrangement for protocol conversion PW in slave
mode activates the SO interface when this interface is not
active and the unit receives data blocks at the same time from
2s the master unit. The arrangement de-activates the SO interface
when no blocks have been received from the master unit for one
second .
-- 22 --
