TRACE-PAD INTERFACE FOR IMPROVED SIGNAL QUALITY

INTERFACE RESEAU-PLAQUETTE POUR QUALITE AMELIOREE DE SIGNAUX

English Abstract

A method of routing or laying out signal traces on printed wire or circuit board in order to improve signal transmission quality. The method comprises routing a given signal trace such that it is electrically connected to a rectangular corner of a substantially wider component pin pad and forms an angle of approximately 135 degrees with the proximate sides of the pad, thereby minimizing the impedance discontinuity at the interface or junction of the signal trace and pad and hence minimizing the reflection of the digital signal at the interface or junction.

French Abstract

Une méthode d'acheminement ou de conception de traces de signaux sur une carte de circuits ou de connexions imprimés permet d'améliorer la qualité de la transmission du signal. La méthode comprend l'acheminement d'une trace de signal donnée qui est connecté électriquement à un coin rectangulaire d'un réseau de connexions substantiellement plus grand à un angle d'environ 135 degrés avec les côtés proximaux du réseau, minimisant ainsi la discontinuité d'impédance à l'interface ou à la jonction de la trace de signal et du réseau et minimisant donc la réflexion du signal numérique à l'interface ou à la jonction.

Claims

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THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE PROPERTY
OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. An apparatus for a signal-triggered digital circuit of a memory system
device, said
apparatus comprising:
a memory controller signal source for generating a digital control signal;
an input receiver located within said memory device, said input receiver
receiving
said digital signal for said digital circuit and being responsive to
triggering induced by
said digital signal;
a conducting interface;
a conducting signal path, said conducting signal path being electrically
connected
to said conducting interface at a corner thereof, said conducting interface
being
electrically connected to said input receiver, said signal path carrying said
digital signal
thereover, said conducting signal path having a length which is at least 1/6th
of a
transition electrical length of said digital signal carried thereover, said
transition electrical
length constituting a transient time of said digital signal multiplied by a
propagation
speed of said digital signal over said conducting signal path, said transient
time of the
said digital signal being selected from a group comprising a rise time thereof
and a fall
time thereof; and
wherein said conducting interface is substantially rectangular in planar view
and
said conducting signal path connected thereto as aforesaid has a longitudinal
centerline
axis which forms an angle in a range of 110 to 160 degrees with respect to a
side of said
conducting interface to which said conducting signal path is connected to
thereby
produce a reduced reflection of said digital signal at said connection between
said
conducting interface and said conducting signal path when compared to a
connection
wherein said angle has a value of 90 degrees.
2. An apparatus according to claim 1, wherein said conducting signal path has
a length
which is at least said transition electrical length of said digital signal
carried thereover.
3. An apparatus according to claim 1, wherein said angle in a range of 110 to
160 degrees is

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an angle of 135 degrees.
4. An apparatus according to claim 3, further comprising a circuit substrate,
wherein said
conducting interface and said conducting signal path are located on said
circuit substrate.
5. An apparatus according to claim 4, wherein said circuit substrate comprises
a printed
circuit board and wherein said conducting interface is a pad and said
conducting signal path is a
trace.
6. An apparatus according to claim 5, wherein said pad is substantially square
in planar
view.
7. An apparatus according to claim 5, wherein said trace has a width which is
1/5th of a
width of said pad to which said trace is connected.
8. An apparatus according to claim 5, wherein when said input receiver is
mounted to said
pad, said trace has a thickness which is in a range of 1/5th to 1/6th of a
thickness of said pad to
which said trace is connected.
9. An apparatus according to claim 5, wherein when said input receiver is
mounted to said
pad, said pad has a width of 22 mils and a thickness in a range of 6 mils to 7
mils, and wherein
said trace has a width of 4 mils and a thickness of 1.2 mils.
10. An apparatus according to claim 4, wherein said circuit substrate further
comprises a slot
and wherein said memory system further comprises a memory module on which said
memory
device is located, said memory module being a dual in-line memory module
(DIMM) comprising
an edge connector, said DIMM being connected to said memory controller by said
edge
connector connecting to said slot.
11. A circuit substrate for a signal-triggered memory device digital circuit,
said circuit
substrate comprising:

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a conducting interface, substantially rectangular in planar view, for
electrical
connection to an input receiver of the memory device, said input receiver
receiving a
digital control signal over said digital circuit and being responsive to
triggering induced
by said digital control signal;
a conducting signal path having a width which is 1/5th of a width of said
conducting interface, said conducting signal path being connected to said
conducting
interface, said signal path carrying said digital control signal thereover,
said conducting
signal path having a thickness which is in the range of 1/5th to 1/6th of a
thickness of the
conducting interface to which said conducting signal path is connected; and
wherein said conducting path connected to said conducting interface has a
longitudinal centerline axis which forms an angle in a range of 110 to 160
degrees with
respect to a side of the conducting interface to which said path is connected
to thereby
produce a reduced reflection of said digital control signal at said connection
between said
conducting interface and said conducting path when compared to a connection
wherein
said angle has a value of 90 degrees.
12. A circuit substrate according to claim 11, wherein said conducting
interface is
substantially square in planar view.
13. A circuit substrate according to claim 11, wherein when said input
receiver is mounted to
said conducting interface, said conducting interface has a width of 22 mils
and a thickness in a
range of 6 mils to 7 mils, and wherein said conducting signal path has a width
of 4 mils and a
thickness of 1.2 mils.
14. A circuit substrate according to claim 11, wherein said conducting signal
path is
connected to the conducting interface at a corner thereof.
15. A circuit substrate according to claim 14, wherein said conducting signal
path has a
length which is at least 1/6th of a transition electrical length of said
digital signal carried
thereover, said transition electrical length constituting a transient time of
said digital signal
multiplied by a propagation speed of said digital signal over said conducting
signal path, and

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wherein said transient time of said digital signal is selected from a group
comprising a rise time
thereof and a fall time thereof.
16. A circuit substrate according to claim 15, wherein said conducting signal
path has a
length which is at least said transition electrical length of said digital
signal carried thereover.
17. A circuit substrate according to claim 14, wherein said angle in a range
of 110 to 160
degrees is an angle of 135 degrees.
18. A circuit substrate according to claim 17, wherein said circuit substrate
comprises a
printed circuit board, said conducting interface is a pad and said conducting
signal path is a trace.
19. A circuit substrate according to claim 18, said circuit substrate further
comprising a
signal source for generating said digital control signal.
20. A circuit substrate according to claim 19, wherein said circuit substrate
further comprises
a slot and wherein said memory device further comprises a memory module on
which said
memory device is located, said memory module being a dual in-line memory
module (DIMM)
comprising an edge connector, said DIMM being connected to said memory
controller by said
edge connector connecting to said slot.
21. An apparatus for a signal-triggered digital circuit, said apparatus
comprising:
a signal source for generating a digital signal;
an input receiver, said input receiver receiving said digital signal for said
digital circuit
and being responsive to triggering induced by said digital signal;
a conducting interface;
a conducting signal path, said conducting signal path being electrically
connected to said
conducting interface at a corner thereof, said conducting interface being
electrically connected to
said input receiver, said signal path carrying said digital signal thereover,
said conducting signal
path having a length which is at least 1/6th of a transition electrical length
of said digital signal
carried thereover, said transition electrical length constituting a transient
time of said digital

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signal multiplied by a propagation speed of said digital signal over said
conducting signal path,
said transient time of the said digital signal being selected from a group
comprising a rise time
thereof and a fall time thereof, and
wherein said conducting interface is substantially rectangular in planar view
and said
conducting signal path connected thereto as aforesaid has a longitudinal
centerline axis which
forms an angle in a range of 110 to 160 degrees with respect to a side of said
conducting
interface to which said conducting signal path is connected to thereby produce
a reduced
reflection of said digital signal at said connection between said conducting
interface and said
conducting signal path when compared to a connection wherein said angle has a
value of 90
degrees.
22. An apparatus according to claim 21, wherein said conducting signal path
has a length
which is at least said transition electrical length of said digital signal
carried thereover.
23. An apparatus according to claim 21, wherein said angle in a range of I 10
to 160 degrees
is an angle of 135 degrees.
24. An apparatus according to claim 23, further comprising a circuit
substrate, wherein said
input receiver and said conducting interface are located on said circuit
substrate.
25. An apparatus according to claim 24, wherein said circuit substrate
comprises a printed
circuit board and wherein said conducting interface is a pad and said
conducting signal path is a
trace.
26. An apparatus according to claim 25, wherein said pad is substantially
square in planar
view.
27. An apparatus according to claim 25, wherein said trace has a width which
is 1/5th of a
width of said pad to which said trace is connected.
28. An apparatus according to claim 25, wherein when said input receiver is
mounted to said

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pad, said trace has a thickness which is in a range of 1/5th to 1/6th of a
thickness of said pad to
which said trace is connected.
29. An apparatus according to claim 25, wherein when said input receiver is
mounted to said
pad, said pad has a width of 22 mils and a thickness in a range of 6 mils to 7
mils, and wherein
said trace has a width of 4 mils and a thickness of 1.2 mils.
30. An apparatus according to claim 25, wherein the apparatus is a memory
system which
further comprises a memory device, wherein said signal source is a memory
controller which
generates digital signals in the form of control signals carried by said
trace, and wherein said
input receiver is located within said memory device.
31. An apparatus according to claim 30, wherein said circuit substrate further
comprises a
slot and wherein said memory system further comprises a memory module on which
said
memory device is located, said memory module being a dual in-line memory
module (DIMM)
comprising an edge connector, said DIMM being connected to said memory
controller by said
edge connector connecting to said slot.
32. A circuit substrate for a signal-triggered digital circuit, said circuit
substrate comprising:
a conducting interface, substantially rectangular in planar view, for
electrical connection
to an input receiver, said input receiver receiving a digital signal over said
digital circuit and
being responsive to triggering induced by said digital signal;
a conducting signal path having a width which is 1/5th of a width of said
conducting
interface, said conducting signal path being connected to said conducting
interface at a corner
thereof, said signal path carrying said digital signal thereover, said
conducting signal path has a
length which is at least 1/6th of a transition electrical length of said
digital signal carried
thereover, said transition electrical length constituting a transient time of
said digital signal
multiplied by a propagation speed of said digital signal over said conducting
signal path, and
wherein said transient time of said digital signal is selected from a group
comprising a rise time
thereof and a fall time thereof, and

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wherein said conducting path connected to said conducting interface has a
longitudinal
centerline axis which forms an angle in a range of 110 to 160 degrees with
respect to a side of
the conducting interface to which said path is connected to thereby produce a
reduced reflection
of said digital signal at said connection between said conducting interface
and said conducting
path when compared to a connection wherein said angle has a value of 90
degrees.
33. A circuit substrate according to claim 32, wherein said conducting
interface is
substantially square in planar view.
34. A circuit substrate according to claim 32, wherein said conducting signal
path has a
thickness which is in a range of 1/5th to 1/6th of a thickness of the
conducting interface to which
said conducting signal path is connected.
35. A circuit substrate according to claim 32, wherein when said input
receiver is mounted to
said conducting interface, said conducting interface has a width of 22 mils
and a thickness in a
range of 6 mils to 7 mils, and wherein said conducting signal path has a width
of 4 mils and a
thickness of 1.2 mils.
36. A circuit substrate according to claim 32, wherein said conducting signal
path has a
length which is at least said transition electrical length of said digital
signal carried thereover.
37. A circuit substrate according to claim 36, wherein said angle in a range
of 110 to 160
degrees is an angle of 135 degrees.
38. A circuit substrate according to claim 37, wherein said circuit substrate
comprises a
printed circuit board, said conducting interface is a pad and said conducting
signal path is a trace.
39. A circuit substrate according to claim 38, said circuit substrate further
comprising an
input receiver and a signal source for generating said digital signal.
40. A circuit substrate according to claim 39, said circuit substrate further
comprising a

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memory device, wherein said signal source is a memory controller which
generates digital
signals in the form of control signals carried by said trace, and wherein said
input receiver is
located within said memory device.
41. A circuit substrate according to claim 40, wherein said circuit substrate
further comprises
a slot and wherein said memory system further comprises a memory module on
which said
memory device is located, said memory module being a dual in-line memory
module (DIMM)
comprising an edge connector, said DIMM being connected to said memory
controller by said
edge connector connecting to said slot.

Description

CA 02218575 1997-10-16
TRACE-PAD INTERFACE FOR IMPROVED SIGNAL QUALITY
Field of Invention
The invention relates generally to an interconnect
structure for use in the construction of a printed circuit or
wire board. More specifically, the invention relates to an
improved interconnection interface between a relatively thin
signal trace and a relatively wide component pin pad on the
surface of a printed wire board in order to better accommodate
high speed signals which are conducted along or through such an
interface.
Background of Invention
Integrated circuit devices and other types of electronic
components having multiple pinouts or leads are often mounted
onto the surface of a printed wire board such that each pin or
lead of the electronic component is mounted or soldered to a
typically rectangularly-shaped deposit of copper (i.e. "pad")
present on the surface of the printed wire board. (The means
for mounting electronic components directly onto the surface or
a printed wiring board is commonly referred to as "surface
mount technology".) The many component pin pads which
typically exist on the surface of the printed wiring board are
interconnected together in a predetermined configuration by
thin copper signal lines (i.e. "traces"). Conventionally, as
is shown in Fig. 1, the practice in the industry has been to
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lay out a signal trace 10 so that it intersects one of the
sides of the pad 12 at approximately the middle thereof.
Typically too, the layout practice dictates that the trace 10
be orientated to intersect the side of the pad at a
substantially ninety degree angle as shown.
As the internal operating speed of integrated circuits
(IC's) such a microprocessors and memories increase with
improving semiconductor process technology, the digital signals
which travel along the printed circuit board between the
various components thereof also have to reach their
destinations, i.e. trigger their input receivers, more quickly
in order to take advantage of the increased IC operating speed.
For example, in order to decrease memory access time in a
computer, the control signals produced by a memory controller
must reach the memory more quickly and at a greater frequency.
Fig. 2A shows a typical digital binary signal 15 which
goes from a low, or binary 0, state to a high, or binary 1,
state. Since the transition of the signal from the low state
to the high state or vice versa cannot be accomplished
instantaneously, there exists a rise time tr and a fall time tf
which respectively results in a sloping leading edge 16 and a
sloping trailing edge 18. In order to make a control signal
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reach or trigger an input receiver faster, it is necessary to
(a) minimize the rise and/or fall time, and (b) increase the
frequency at which control signals are sent. In the present
art, the rise/fall time has fallen to below one nanosecond,
with signal frequency at 66 MHz.
Fig. 2B shows the binary digital signal 15 represented in
the frequency domain. It will be noted that each frequency
component i of the digital signal has a voltage vo(i)
associated therewith (phase information is not shown in Fig.
2B).
On a printed circuit board, the junction between a signal
trace and a component pin pad, such as the prior art interface
shown in Fig. 1, represents an impedance discontinuity since
(a) the width of the conducting path suddenly drastically
increases at the pad and (b) the cross-sectional area or
thickness of the conducting path increases due to solder
present on the pad. When a digital signal such as that shown
in Fig. 2 travels across an impedance discontinuity, the
voltage or power of the signal is split at the trace-pad
junction so that a portion vo(i)/xl(i) of each frequency
component i of the signal travels back in the opposite
direction of the wave front. The remaining portion vo(i)/x2(i)
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of each frequency component i of the signal travels in the
original or forward direction. The values xl(i) and x2(i) are
greater than or equal to one. The greater the ratio of the
larger impedance to the smaller impedance at the discontinuity,
the more the voltage of the signal components will be affected
by the discontinuity, i.e., the smaller the value of xl(i).
The portions vo (i )/xl (i ) of each frequency component of
the signal which travel in the opposite direction will
similarly reflect at the next impedance discontinuity in their
path, and the same will happen to the frequency components
vo(i)/x2(i) which travel in the forward direction. The
reflected portions of the signal will recombine with the
wavefront and modify its appearance. In the frequency domain,
this will be visible as a change in voltage associated with
each frequency component. In the time domain, this will appear
as one or more "glitches" or "inflection points". An example of
one such glitch caused by a single discontinuity is shown in
idealized form in the time domain diagram of Fig. 3 where at
time/position to the forward portion Y_vo (i) /x2 (i) of the signal
travels across the impedance discontinuity presented by the
prior art trace-pad junction and a short time t1 later the
reflected and rebounded portion Y_vo(i)/x1(i) of the signal
recombines.
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The physical size of electronic components mounted on a
printed circuit board means that the components have to be
distributed across the board in such a way that relatively long
signal traces cannot be avoided. Inflection points or glitches
on the signal will be produced by the impedance discontinuities
along the conduction path the signal travels. These non-
monotonic wave forms appear as multiple rising (or falling)
edges where only one rising (or falling) edge was desired. One
or a combination of the glitches or inflection points may
produce false triggers at input receivers. The invention seeks
to reduce the tendency of this phenomenon.
Summary of Invention
In a broad sense, the invention provides an interconnect
structure for connecting together a relatively narrow printed
wire board signal trace and a substantially wider component pin
pad in a manner which reduces the amount of signal reflection
at the trace-pad junction. The reduced signal reflection thus
reduces the tendency to produce false triggers at input
receivers. This objective is accomplished by routing or laying
out a given signal trace so that it is electrically connected
to a substantially rectangularly shaped corner of the pad to
form an angle in the range of 110 to 160 degrees, and
preferably approximately 135 degrees, with proximate sides of
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the component pin pad. This topology results in a gradual
increase in the width of the conducting path thereby reducing
the impedance mismatch between the signal trace and the
component pin pad. The above described signal layout practice
provides the advantage of not adversely affecting the
manufacture of a printed circuit board, particularly the
process of reflow soldering, as explained in greater detail
below.
According to one aspect of the invention, there is
provided a method of improving the transmission quality of a
digital signal on a printed wire board wherein the digital
signal travels along a conduction path comprising a relatively
narrow signal trace which interfaces with a substantially
wider, component pin pad having at least one substantially
rectangularly shaped corner. The method includes the step of
electrically connecting the signal trace to the substantially
rectangular corner of the component pin pad such that the
signal trace forms an angle of approximately 135 degrees to
proximate sides of the component pin pad.
According to another aspect of the invention, there is
provided a method for improving the signal transmission quality
of a printed wire board comprising relatively narrow signal
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traces electrically connected to substantially wider component
pin pads each having at least one corner of substantially
rectangular shape. The method comprises the step of routing or
laying out the signal traces such that they are electrically
connected to the substantially rectangular corners of the pads
to form angles of approximately 135 degrees to proximate sides
of the respective pads.
Other details of the invention will become more apparent
from the following detailed description and drawings wherein
like reference numerals depict like elements.
Brief Description of Drawings
Fig. 1 is a diagram illustrating a typical junction
between a printed wire board signal trace and a component pin
pad as conventionally laid out in the prior art;
Fig. 2A is a diagram of a portion of a binary digital
signal as represented in the time domain;
Fig. 2B is a diagram of the signal shown in Fig. 2A as
represented in the frequency domain;
Fig. 3 is an idealized diagram of a portion of a noisy
digital signal in the time domain which features multiple
rising edges caused by an impedance discontinuity at the
junction between a trace and a pad;
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Fig. 4 is a diagram illustrating an interface between a
printed wire board signal trace and a component pin pad in
accordance with a preferred embodiment of the invention;
Fig. 5 is a diagram of the junction of Fig. 4 illustrating
a gradually increasing conductive path width;
Fig. 6 is a diagram illustrating an interface between two
signal traces and a component pin pad in accordance with a
preferred embodiment of the invention;
Fig. 7 is a block diagram of a memory system;
Fig. 8 is an illustration of one example of a portion of a
mass produced printed wire board constructed in accordance with
the principles of the invention.
Detailed Description of Preferred Embodiments
Fig. 4 illustrates an interconnect structure 20 for
connecting together a relatively narrow printed wire board
signal trace 22 and a substantially wider, substantially
rectangular, component pin or lead pad 24 in accordance with
the preferred embodiment of the invention. The trace 22 has a
width of about 4 mils (thousands of an inch) and each side 26
of pad 24 has a width of about 22 mils. The trace 22 has a
cross-section or thickness of about 1.2 mils, and, due
partially to the solder typically placed on the pad 24 for
mounting the IC component pin, the pad 24 has a cross-section
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CA 02218575 1997-10-16
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or thickness in the range of about 6 to 7 mils. These
dimensions are typical of the present art. However, unlike the
prior art, it will be noted that trace 22 is electrically
connected to a substantially rectangular corner 28 of pad 24
and routed or laid out to form an angle 6 in the range of about
110 to 160 degrees with proximate sides 26a and 26b of the pad
24, with the most preferred angle A being about 135 degrees.
As illustrated in Figs. 4 and 5, the topology of
interconnect structure 20 permits a gradual increase in the
width of the electrically conductive path between the signal
trace 22 and component pin or lead. The gradual increase
results in smaller impedance changes or graduations along the
conductive path (as represented in Fig. 5) compared to the
prior art interconnect structure topology shown in Fig. 1.
Reflections will still occur, but since the reflection
coefficient R at any given frequency w is related to the ratio
of the change in impedance Z at the boundary, i.e.,
R c,~ Zz(c))-Zl(W)
~ )- Z2(W)+Z1((O),
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where Z1 is the impedance at the near side of the boundary and
ZZ is the impedance at the far side of the boundary, the signal
crossing from the near side to the far side of the boundary.
The reflections will be smaller in amplitude as compared
to the prior art trace-pad interface shown in Fig.l.
The invention is preferably utilized in circumstances
where the signal trace is sufficiently long so as to act like a
transmission line. This is generally believed to occur when
the length of the signal trace is approximately at least 1/6th
of the "transition electrical length" of the digital signal,
i.e., the rise or fall time of the signal multiplied by the
propagation speed of the signal along the signal trace (which
is typically about 1/2 the speed of light for FR4 type board).
The invention is particularly useful when the length of the
signal trace approaches or exceeds the transition electrical
length of the digital signal since in such circumstances,
assuming no other impedance discontinuities along the
conduction path, reflections caused by the trace-pad interface
have a greater likelihood of not recombining within the rise or
fall time of the signal.
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When it is desired to couple two signal traces to a
component pin pad, it is preferred to connect the signal
traces 22 to opposite, substantially rectangularly shaped,
corners of the component pin pad as shown in Fig. 6. This will
ensure the most gradual impedance gradient in the event a
digital signal has to flow from trace 22a, through the pad 24,
to trace 22b.
It may also be thought desirable to gradually increase or
flare the width of the signal traces as they approach component
pin pads on printed wire boards in order to further reduce the
impedance graduations along the conductor path. However, this
approach leads to two particular disadvantages which are not
conducive to the mass manufacture of printed circuit boards.
One such disadvantage relates to the wire density of the
printed wire board; flaring or widening the signal traces means
that the board will accommodate a lower density of signal
traces, which is contrary to the continuing trend towards ever
greater miniaturization. Another disadvantage relates to the
process by which printed circuit boards are assembled using
surface mount technology assembly techniques. The assembly
process generally includes a reflow soldering stage wherein
electronic components are soldered en masse to their respective
component pin pads on the printed wire board. Flaring the ends
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of the signal traces effectively results in increasing the mass
of the component pin pads which will then not be able to
accumulate enough heat in the conventional reflow soldering
process to form a good joint with the associated component pins
or leads. This condition is commonly termed a "cold solder
joint" and results in printed circuit boards of poor signal
transmission quality. In contrast, the preferred embodiment of
the invention described above does not interfere with the
conventional reflow soldering process nor is the wire or trace
density of the printed wire board unduly compromised.
The assignee of the instant application has developed a
mass production printed circuit dual-in-line-memory-module
(DIMM) utilizing the design layout principles of the invention.
Fig. 7 shows a block diagram of a memory system 38 which
employs the DIMM. The system 38 comprises a memory controller
40 which controls the flow of thirty three bit Control 42 ,
seventy two bit Data 44, and twelve bit Address 46 signals to
each of a plurality of DR.AM DIMM slots 48. A processor, not
shown, sends the Data 44 and Address 46 lines to the memory
controller 40. Each of the DIMM slots 48 is a hardware
connector into which DRAM DIMMs can be inserted. The system 38
is designed such that the controller 40 resides on one printed
circuit board while the DRAM DIMMS reside on another circuit
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board. The system 38 utilizes digital signals having a
rise/fall time of below 1 nanosecond and the maximum frequency
of the Control signals 42 is up to 66 MHz. Using a
commercially available simulation software package
("simulator"), it was noted that the DIMM, as notionally
assembled onto a conventionally laid out printed circuit board,
occasionally exhibited errant behaviour due to false triggering
of the DIMM memory. However, when the DIMM was modelled using
a printed wire board wherein certain signal traces carrying
critical control signals were connected to the corners of the
pads at 135 degree angles as described above, the simulator
showed that the preferred embodiment of the invention improved
upon the errant behaviour of the originally modelled DIMM
memory. Fig. 8 shows an example of a portion of one surface of
such a DINM printed circuit board which was constructed and
mass produced.
Those skilled in the art will appreciate that other
modifications and variations may be made to the preferred
embodiments disclosed herein whilst keeping within the spirit
and scope of the invention as defined by the claims which
follow:
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Representative Drawing