Note: Descriptions are shown in the official language in which they were submitted.
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High Voltage Generating Circuit for Volatile Semiconductor Memories
This invention relates to a high voltage generating circuit for use in random
access
memories.
Background of the Invention
Semiconductor devices such as Dynamic Random Access Memories (DRAMS),
synchronous DRAMs (SDRAMs) or other types of volatile memories generally
utilize CMOS
semiconductor devices. Power for these devices is provided by a standard
voltage supply having
a positive voltage VDD relative to a ground voltage Vss. As is well known,
data bits having
either logic high state or logic low state are stored in memory cell
locations. The high logic level
stored in a memory cell generally corresponds to a voltage equivalent to VDD
while the low logic
level corresponds to the ground voltage Vss.
Specifically in dynamic memories, the data bit is stored in a capacitor, which
is charged
or discharged through a memory cell access transistor. Typically, n-channel
Metal-Oxide
semiconductor Field-Effect Transistor (NMOS Transistor) devices have been used
in the
memory cell array since they take up a smaller layout area, and are thus
better suited for higher
integration. Using an NMOS access transistor however, requires providing a
voltage higher than
VDD to the gate of the memory cell access transistor in order to fully turn it
on and avoid any
threshold voltage drop. The requirement for generation of a voltage supply,
which is higher than
Vpp thus, arises. Various circuits have been devised for generating such high
voltages for use in
volatile memories. Generally, this boosted supply voltage level is referred to
symbolically as
Vpp. This naming convention traces its origins to nonvolatile memories such as
EEPROMs and
Flash EPROMs wherein programming voltages are generated for cell programming.
Although
some similarities exist, the generation of VPP in volatile memories has
different design goals and
approaches than generating VPP in nonvolatile memories.
A conventional prior art circuit for generating a VPP voltage level from VDD
is described
with reference to figure 1. The circuit illustrated in figure 1 employs a
conventional r ng
oscillator (not shown) to generate a VDD level oscillating signal OSC PUMP,
the output of
which is connected to an NMOS capacitor C1 for functioning as a charge pump. A
second
NMOS device T2, with its source-drain path connected between VDD and the
charge pump
CA 02243375 2004-05-27
capacitor C 1 at node 1, is used for pre-charging the capacitor C 1.
Furthermore, a main driving
P-channel Metal-Oxide Semiconductor Field-Effect transistor (PMOS transistor)
pass transistor
T3 is connected between the charge pump capacitor C 1 at node 1 and a VPP
output.
In operation, the ring oscillator 1 generates an oscillating signal OSC PUMP
with a
constant period Tosc and an amplitude of the source supply voltage VDD which
is provided to
one plate of the charge pumping capacitor C 1. The other plate of C 1 is
cyclically precharged by
transistor T2 which in turn also receives a VDD level oscillating signal OSC
PRECHARGE at its
gate.
When the oscillating signal OSC PUMP is at the ground voltage VSS, the voltage
across
the C1 is VDD-V~, where V~ is a threshold voltage loss of the NMOS transistor
T2. When the
oscillator voltage changes from Vss to VDD, the voltage at the node 1 will
also rise from a voltage
VDD-V~ to a voltage of approximately 2VDD-V~, due to the capacitive coupling
effect of
capacitor C1. The voltage is transferred to the output VPP when the PMOS pass
transistor T:3 is
turned on. The voltage VPP may be charged into a load capacitor CL (not
shown). The oscillation
is continued to maintain the VPP potential. Optionally, a level detector and
regulator may be
included to pause the pumping action during periods requiring little power.
A disadvantage of this NMOS precharge, PMOS pass generating circuit is that
there is
always a threshold voltage V~ loss at a boost node 1. Thus, when VDO is low,
for example
during power-up, or at less than 2V~, the circuit will not work.
A cross-coupled charge pump circuit using a two-phase charge pump shown in
figure 2
has been implemented as an improvement over the circuit of figure 1. This
circuit is capable of
compensating for the threshold voltage loss at the boost node due to the
bootstrap action of the
precharge devices. However, this circuit still has the disadvantage of having
a threshold voltage
loss in the diode-type NMOS devices T4 at the output stage.
An alternate to the cross-coupled charge pump configuration of figure 2 was
proposed in
United States Patent No. 5,196,996. The circuit shown in figure 3 comprises a
clamping circuit,
a charge pump circuit and a charge transfer circuit. The clamping circuit is
provided with an
NMOS capacitor C4 having one of its plates connected to a first
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precharging oscillating signal OSC PRECHARGE. A diode-type NMOS device TS is
also provided having its gate and drain coupled to a source supply voltage VDD
and its
source connected to the gate of an NMOS transistor T6 and the other plate of
capacitor C4.
The charge pump circuit is provided with an NMOS capacitor CS having one of
its
plates coupled to a second main pump oscillating signal OSC PUMP. The other
plate of
capacitor CS and the drain of the NMOS transistor T6 are coupled via a PMOS
pass
transistor T7 to the output Vpp.
Since the gate of the precharging transistor T6 is cyclically boosted above
VDD by
the prechaxging capacitor C4, a full VDD is provided to the drain of
transistor T6, thus
overcoming the threshold voltage loss in the output stage. However, the
circuit has the
disadvantage in that VDD must be at least greater than twice the threshold
voltage, i.e. VDD
>_ 2V~. Thus, although this circuit solves the problem of the V~ loss in
generating VPP, it
still has the problem that for low VDD, i.e. close to 2V~, the circuit will
not work.
Essentially, if an NMOS precharge circuit is used the low VDD problem will
always be
present. The reason why many designs choose to live with this problem is that
by using
NMOS precharge the greater problem of device latch-up is avoided.
It would therefore be advantageous to develop a high voltage generating
circuit
which provides the constant VPp output without any threshold voltage drop and
which is
capable of operating efficiently at low values of VDD.
Summary of the Invention
This invention seeks to provide a high voltage generating circuit for use in
random
access memories in which the output, VPP, makes efficient use of a source
supply voltage
VDD, is able to maintain its efficiency at low values of VoD and does not
suffer from the
dangers of latch-up.
In accordance with this invention there is provided a voltage boosting circuit
for
providing a boosted voltage VPP at an output node, from a supply voltage VoD,
the circuit
comprising:
a precharge transistor element responsive to a precharge clock signal for
transferring the supply voltage VDD to a boost node for precharging the boost
node to the
full supply voltage VDDi
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a capacitive element connected between the boost node and a pump node, the
capacitive element pumping the boost node in response to a pump voltage signal
applied to
the pump node; and
a switching element connected between the boost node and the output node, for
transferring charge from the capacitive element to the output node to provide
the boosted
voltage VPP.
In accordance with a further aspect of the invention the precharge transistor
element is an PMOS transistor.
An advantage of the present invention is that no threshold voltage drop is
experienced in the precharge section of an embodiment of the present invention
as would
be experienced in conventional NMOS precharge or NMOS pass type pump circuits
since
a PMOS precharge system is employed. Another advantage of the present
invention is the
elimination of the latch-up problem conventionally experienced in PMOS
precharge
systems. A further advantage of the present invention is significant power
savings are
achieved through the use of a self biasing current comparator which monitors
the value of
the output voltage Vpp.
Brief Description of the Drawings
A better understanding of the invention will be obtained by reference to the
detailed
description below in conjunction with the following drawings in which:
Figure 1 is a circuit diagram of a single phase conventional NMOS precharge,
PMOS pass
VPP voltage generating circuit;
Figure 2 is a circuit diagram of a two-phase conventional NMOS precharge, NMOS
pass
VPP voltage generating circuit using diode connected NMOS pass transistors;
Figure 3 is a circuit diagram of a conventional VPP voltage generating circuit
for
eliminating threshold voltage loss in the output;
Figure 4 is a circuit diagram of a VPP voltage generating circuit in
accordance with the
present invention;
Figure 5(a) and (b) are waveform diagrams of representative components in
figure 4; and
Figure 6 is a circuit diagram of a comparator shown in Figure 4.
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Detailed Description of Preferred Embodiments
Referring to figure 4, an embodiment of a voltage boost circuit in accordance
with
the present invention is shown generally by numeral 40. The voltage boost
circuit includes
a voltage pump section 42, an initial charge circuit 48 and a substrate
biasing section 43,
which in turn includes a substrate switching section 44 and a voltage
comparator circuit 46.
The voltage boost circuit 40 also includes a power-up pre-conditioning device
50. In
addition, the voltage pump section 42 consists of a first and second identical
charge pump
circuits 54 and 56, respectively.
The voltage boost circuit 40 is provided with an external power supply having
a
source supply voltage VDD 58. The circuit 40 is controlled by signals that
include: a first
and second oscillator pre-charge signals OSC PRE1 60 and OSC PRE2 62,
respectively; a
charge pump signal OSC PUMP1 64 and OSC PUMP2 66, respectively; and first and
second charge transfer signals OSC TRANS 1 68 and OSC TRANS2 70, respectively.
These signals control the generation of the VPP voltage 72 in a manner to be
described
below.
Considering firstly, the first charge pump circuit 54 (the second charge pump
circuit 56 is identical) which includes a precharge PMOS transistor P 1 having
its source
connected to VDD and its drain connected to a charge pumping capacitor C1 at a
boost node
74. The charge pumping capacitor C 1 is an NMOS device with its source and
drain
connected together at a pump node 64 which in turn is fed by the first charge
pump signal
OSC PUMP1 64. The gate 76 of the pre-charge transistor P1 is fed by the first
precharge
oscillator clock signal OSC PRE1 60. A PMOS pass transistor P2 provides a
controllable
charge transfer from the boost node 74 of capacitor C 1 to the output node VPP
72. The gate
78 of the PMOS transistor P2 is controlled by the first charge transfer signal
OSC TRANS 1 68.
A problem with PMOS transistors is the potential for latch-up. The PMOS
devices
reside in an n-well, which must be biased to a positive voltage level in order
to avoid
forward biasing the p-n regions formed by the source/drain implants (or
diffusions), and
the channel region located in the n-type material of the n-well. Such a
forward bias would
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constitute the first step to causing CMOS latch-up. Since a PMOS device will
have its
body (or more commonly referred to as substrate) connected to the output VPP
to ensure
that the n-well is at the highest potential available, clearly, when VDD is
low, VPP is even
lower and this forward biasing problem becomes a significant threat.
The PMOS transistors P1 and P2 are formed in n-wells as is well known to
persons
skilled in the art. The n-wells are connected to the biasing node which is
held at a voltage
VPP_SUB 80. The region underneath the gate oxide where the channel is formed
consists
of the n-type material of the n-well. Traditionally, well contacts have
loosely been referred
to as substrate contacts in the art. In fact, n-wells act as a localized
substrate for the PMOS
devices. For this reason, the voltage biasing the well is referred to as VPP
SUB, (local)
substrate connection for Vpp.
It should be noted that by using PMOS transistors for the precharge
transistors P1
and P1' which fully turn on when Vss is applied to their gates, there is no
threshold voltage
V~ loss during the precharging of the pump capacitor C1. Since the voltage at
the gate 76
of PMOS P1 is at ground level Vss, the PMOS device P1 is on.
In a PMOS device as previously mentioned, the n-well or local substrate must
be
connected to the most positive supply voltage in order to avoid forward
biasing the PN
junction formed between the p-type source/drain and the n-well. Thus, it may
be seen that
if the voltage VPP_SUB is less than VDD forward biasing of the aforementioned
junction
and eventual latch-up of the respective PMOS devices will occur, i.e. a large
current will
flow from VDD to VPP SUB through the device that will eventually cause damage
to the
device. Thus, during power-up of the device and throughout the rest of other
operation
conditions, whenever VDD and consequently VPP is low, it is necessary to
establish a
system whereby the forward biasing of the PN junction and hence latch-up of
the PMOS
transistors is avoided.
The substrate voltage switch circuit 44 includes a pair of PMOS transistors P3
and
P4 with their drains connected together at node 84 and the output taken from
this node to
the VPP SUB node 80. The respective source terminals 86 and 88 of the
transistors P3
and P4 are connected to VDD and VPP, respectively. The substrate of each of
these
transistors is also connected to VPP SUB in order to avoid undesired latch-up
of these
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devices. The respective gates 90 and 92 of transistors P3 and P4 are connected
to
complementary switching signals Voo _ H and VPp _ H , respectively.
The complementary switching signals VoD _ H and VPP _ H are derived from the
output 94 of a voltage comparator 95 which has VDD connected to its inverting
input 96
and VPP connected to its non-inverting input 98. A VDD level inverter 100 is
provided at
the output of the voltage comparator and inputs to the gate of transistor P4
as the
VpP _ H signal. A further VPP level inverter 102 is provided at the output of
inverter 100
and inputs to the gate of transistor P3 as the VDD _ H signal.
The operation of providing the optimum VPP SUB voltage to the VPP driving
transistors P1 and P1' will now be described. In order to ensure that VPP SUB,
i.e. the
well potential of the PMOS transistors is always at the most positive
potential, in
accordance with the embodiment of the present invention illustrated in figure
4, the n-well
contacts of the VPP generator, which are connected to the voltage VPP_SUB are
selectively
switched either to VDD or VPP by the substrate voltage switch circuit 44
according to
whichever is more positive at the time.
When VDD>Vpp, the output of the comparator 95 is low; this is passed through
the
level inverter 100 to set VPp _ H high and thus turning off transistor P4. As
a result,
transistor P3 is turned on, pulling VPP SUB to VDD. When Vpp>VDD, the output
of the
comparator 95 is high, driving the output of the level inverter 100 VpP _ H
low, therefore
turning on transistor P4 and connecting VPP_SUB to VPs. The level inverter 102
is
provided with a VPP supply voltage in order to assure that the transistor P3
is fully turned
off by applying VPP to its gate 90. Without this precaution, if only a VDD
level is provided
to node 90 when node 92 is low and VPP is higher than VpD, leakage current
will flow from
node 84 to VDD, thereby greatly reducing the efficiency of the pump.
A second capacitive element, namely, a PMOS transistor PS is connected as a
MOS
capacitor between VDD and VPP_SUB. The transistor PS is used to charge VPP_SUB
when VDD is very low, i.e. VDD<V~, by coupling the charge between VDD and VPP
SUB.
During this period, neither P3 nor P4 will turn on. Device PS also acts as a
reservoir
capacitor once VPP reaches its regulated level by damping sudden glitches in
the VPP line.
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Furthermore, an NMOS transistor N 1 has gate-drain terminals connected to the
VDD line and its source connected to Vpp. This transistor acts as a diode and
helps to
charge VPP during power-up by providing a direct and instantaneous current
path between
VDD and Vpp Whlle Vpp<VDD-V~.
Referring now to figures Sa and Sb, the actual VPP generating operation of the
circuit of figure 4 is described. The circuit operates in two phases, i.e. a
precharge phase
and a boost phase. Because the capacitor C1 in figure 4 is used to charge up
VPP in the
boost phase, two boost circuits 54 and 56 are provided, each of which are
driven by signals
that are 180° out of phase. Thus, while the capacitor C 1 in the first
boost circuit is being
precharged, the capacitor C1' is charging up VPP. This results in a higher
efficiency circuit.
Of further special importance are the levels of the oscillating signals. Both
OSC PUMP1 and OSC PUMP2 are VDD level oscillating signals. However, both
OSC PRE1 and OCS TRANS1 as well as OSC PRE2 and OSC TRANS2 are all VPP
level oscillating signals. The reason for the increased voltage level required
for these
oscillating signals is to ensure that when the boost nodes 74 and 74' are at
their high
voltage values, the precharge transistors P1 and P1' are fully turned off.
Only a VPP level
signal at the gate of these respective precharge transistors will shut them
off completely. A
VoD level at their gates will allow leakage current to flow between the boost
nodes and
VDD, resulting in significant power drain and a decrease in the pumping
efficiency. The
generation of the boosted level signals OSC PRE1, OCS TRANS1, OSC PRE2 and
OSC TRANS2 can be accomplished through the use of conventional level shift
circuits as
described in US patent 5,406,523 also assigned to the subject assignee.
Figure Sa illustrates the sections of precharge and boosting for the two
pumps. The
alternating effect of having the output supplied with pumped charge every half
oscillating
cycle greatly increases the efficiency of the overall VPP generating circuit.
Figure Sb illustrates the relative states of the VoD _ H and VPp _ H signals
and the
resulting VPP output.
Referring to figure 6, an embodiment of the voltage comparator 95, shown
schematically in figure 4, is described. The comparator 95 consists of two
symmetrical
circuits, corresponding to the inverting input 96 and the non-inverting input
98,
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respectively. The core of the comparator consists of transistors P 13, N 3 and
P 14, N4.
Transistors P13 and P14 are PMOS devices, whereas transistors N3 and N 4 are
NMOS
devices. The transistor P13 is connected in series with the transistor N3 and
the transistor
P14 is connected in series with the transistor N4. The input voltage VDD is
applied to the
source of P3 via a PMOS transistor P11, having its drain connected to the
source of P13
and its source connected to VDD. The input VPP 98 is applied directly to the
source of
PMOS transistor P 14. The gates of transistors P 13, N3 and P 14, N4 are
connected
together at node 110, i.e. VBIAS. Transistors N2 and N6 are connected in the
series path
between P 13, N3 and P 14, N4 respectively to provide protection against hot
electron
effects. The drains of transistors P 14 and N6 are connected together at node
112 providing
an output signal VCOMP. This output signal VCOMP is passed through a pair of
series
connected inverters 114 and 116 to provide an output signal VPP UP 118. The
output
signal VPP UP is fed back to the gate of the PMOS transistor P11 and the gate
of an
NMOS transistor N1 having its source and drain connected to the source and
gate of
transistor N3, respectively.
The circuit of figure 6, in operation, exhibits two significant features,
namely, a
quick set-up initialization at very low VDD and a no current drain or power
loss for values
of VpP greater than VDD~
Because of the symmetry between the two parts of the circuit and the mutual
connection of the four gates of devices P13, N3, P14, N4, the voltage VCOMP is
one half
the voltage VDD when Voo and VPP are equal. That is, the currents IP3 and IP4
through
transistors P13 and P14, respectively, are equal. When VPP is less than VDD,
the current IP4
is less than the current IP3 and, therefore, the current IN4 is greater than
the current IP4,
resulting in more current flowing to ground, thus driving VCOMP low. It may be
seen that
the current through the transistors N3 and N4 are equal since their gates are
connected
together and because of the symmetry between the circuits. When VCOMP is low,
VPP_UP is low, driving transistors P11 on and N1 off, thus causing VDD to
supply the
current for the VPP generator.
On the other hand, when VPP is greater than VDD, the current IP4 is greater
than the
current Ip3, therefore, IP4 is also greater than IN4. This drives VCOMP high.
When
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VCOMP is high, the voltage of VPP UP is also high. When applied to the gate of
transistor P11, VPP UP turns transistor P11 off. Since transistor P11 is off,
there is no
current flowing in the series branch made up of P11, P13, N2, and N3.
Furthermore, when
P11 is off, N1 is on and since this is an NMOS device with its drain connected
to VBIAS
and its source connected to ground, it drives VBIAS to ground. Since VBIAS is
also
applied to the gate of N4, this turns off transistor N4. By turning off N4,
there is now no
current flowing in the series branch made up of P14, N6 and N4. Therefore,
when VPP is
sufficiently high, there is no biasing current drawn from VPP or VDD. It may
thus be seen
that this provides a power saving feature for the high voltage generating
circuit.
In order to provide quick initialization of the circuit at low VDD, the
transistor P12
has its source connected to VDD, its gate connected to Vpp and its drain
connected to
VBIAS. On power-up when VDD rises from zero to Vpp, the voltage VPP is almost
zero,
thus the transistor P12 is on and VBIAS is then set equal to VDD. The voltage
VCOMP
will go low because the transistor N4 is on and thus, VPP UP is also driven
low. Thus
transistor P 12 initializes all the key voltages in the comparator circuit in
a stable manner on
power-up.
Furthermore, the substrate (n-well connection) of PMOS transistor P14 needs
only
be connected to VPP since P14 is maintained in an off state as long as VPP is
less than VDD~
As a result, the latch-up threat is not significant. Since the drain of a PMOS
transistor P!$
is connected to VCOMP which should not be grater than Vpp. As a result there
is little risk
of latch-up and no need to connect the local substrate contact to VPP_SUB.
As has been illustrated in an embodiment of the present invention, several
advantages over the prior art are accomplished with simple and robust
solutions.
Specifically, the latch-up problem experienced in conventional PMOS precharge
circuits
has been addressed. No threshold voltage drop experienced in conventional NMOS
precharge or NMOS pass type pump circuits exists since a PMOS precharge system
is
employed. Furthermore, power savings are achieved through the use of a self
biasing
current comparator which monitors the value of the output voltage Vpp.
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While the invention has been described in connection with a specific
embodiment
thereof and in a specific use, various modifications thereof will occur to
those skilled in the
art without departing from the spirit of the invention as set forth in the
appended claims.
The terms and expressions which have been employed in the specification are
used
as terms of description and not of limitations, there is no intention in the
use of such terms
and expressions to exclude any equivalents of the features shown and described
or portions
thereof, but it is recognized that various modifications are possible within
the scope of the
claims to the invention.
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