Note: Descriptions are shown in the official language in which they were submitted.
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SILICON CARBIDE CMOS AND METHOD OF FABRICATION
:.,
This invention was made with Government
support and the U.S. Government has certain rights in
r
this invention.
Field of the Invention
The present invention relates to
metal/polysilicon-oxide semiconductor (MOS) devices
formed in silicon carbide. More particularly the
present invention related to complementary
metal/polysilicon-oxide-semiconductor devices commonly
known as CMOS formed in silicon carbide.
Background of the Invention
Complimentary MOS (CMOS) integrated devices
are monolithically integrated p-channel and n-channel
transistors which are optionally interconnected in a
single device. CMOS devices provide the basis for many
integrated circuits such as operational amplifiers,
sensing devices, digital logic, memory devices, and
microprocessors. CMOS technology is readily adaptable
to mixed analog and digital applications. The
20, availability of active or current source loads makes it
possible to generate large voltage gains with
relatively small supply voltages and currents. CMOS
also provides for low power digital circuits. CMOS is
also attractive as a technology because lower power
supply voltage operation and reduced circuit design
complexity enhances reliability over all operating
- conditions.
To produce a CMOS device, a single substrate
or die must be capable of producing transistors of
complementary type.. Thus, a single die must support
-- both p-type and n-type regions to provide for the p
type and n-type channels of the complementary devices.
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Previous CMOS devices have been fabricated in silicon
but have not been produced using silicon carbide. The
difficulty in fabricating regions of opposite
conductivity silicon carbide suitable for producing
complementary transistors on a single die or wafer, in
addition to the general difficulty in producing a p-
channel silicon carbide MOS field effect transistor
have prevented production of CMOS in silicon carbide.
. Japanese Patent Application Publication No.
08088283 entitled SILICON CARBIDE COMPLEMENTARY TYPE
MOSFET describes a complementary MOSFET formed using an
epitaxial layer laminated to a substrate to provide two
transistors, one having a gate groove which extends
through the epitaxial layer to the substrate.
United States Patent No. 5,342,803 to Shimaji
describes a method for i.sol.ating circuit elements for
effectively isolating devices on a semiconductor
substrate. The patent describes such .met.hod with
respect to silicon devices and mentions silicon carbide
as a,possible substrate for one embodiment which .does
not include co~gle~nent.ary devices _ The Shimoj i
reference provides no information about how silicon
carbide could be used for the methods described in the
patent or to make complementary devi.ces_in silicon
carbide.
United Stat-e,s~ Patent ado . 3 , 84-9 , 216 t-o S-alters
describes a method of manufacturing a seiciiconductor
device. 'The Salters reference mentions silicon carbide
as a source material for forming an -i-nsulating region.
United States Patent No. 5,385,855 to Brown et aI.
describes a silicon carbide integrated circuit,
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however, the reference does not describe complementary
devices in an integrated circuit.
Because of the advantages that CMOS integrated
devices have over devices comprised solely of p-channel
or n-channel transistors, it is desirable to overcome
the barriers in silicon carbide to allow for~the
development of a CMOS silicon carbide integrated device
technology.
Summar~r of the Invention -
In view of the above, it is~ an object 'of an
aspect,of the present invention to provide a method of
fabrication of a monolithic silicon carbide integrated
device with a p-channel transistor and an n-channel
transistor on the same die or wafer. It is a further
object of an aspect of the present invention to provide a
CMOS device formed. in silicon carbide.
The methods and structures of the present
invention provide an integrated device formed of
silicon carbide . The .integrat.ed ,dezri.ce .has _a first
si.lican carbide MOS ffield -effect transistor formed in
silicon carbide. This first MOS device has a channel
region formed in p-'type conductivity silicon carbide.
Also in the integrated device is provided a second
silicon carbide MOS field effect transistor formed in
2S silicon carbide. This second MOS device has a channel
region formed in r~-type conductivity silicon carbide.
Optionally, the drain of the first silicon carbide MOS
field effect transistor is electrically connected to
the drain of the second silicon carbide MOS field
effect transistor.
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In accordance with one aspect of the present invention
there is provided an integrated silicon carbide device
comprising a first silicon carbide MOS field effect
transistor having a channel region formed in a first-type
conductivity silicon carbide and first source and drain
contacts, and a second silicon carbide MOS field effect
transistor integrated with said first transistor and having
a channel region formed in a second-type conductivity
silicon carbide of opposite type conductivity to said
first-type conductivity silicon carbide, and second source
and drain contacts, wherein the source and drain contacts
of both transistors are ohmic contacts formed of a same
contact metal.
In accordance with another aspect of the present
invention there is provided a method of forming a
monolithic complementary MOS integrated silicon carbide
device comprising the following steps:
forming a first silicon carbide MOS field effect
transistor, wherein the channel region of the first device
is formed in a first type conductivity silicon carbide; and
forming a second silicon carbide MOS field effect
transistor, the second silicon carbide MOS field effect
transistor being integrated with the first silicon carbide
MOS field effect transistor, wherein the channel of the
second transistor is formed in a second type conductivity
silicon carbide of opposite type conductivity to the first
type conductivity, forming first source and drain contacts
on the first type conductivity silicon carbide and forming
second source and drain contacts on the second type
conductivity silicon carbide, the source and drain contacts
of both transistors being ohmic contacts formed of a same
contact metal.
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In a preferred embodiment of the present
invention the drain and source contacts of the first
and second MOS field effect transistors are formed of
the same material. The preferred material for these
contacts is nickel.
Preferred structures provided by the present
invention include structures for a complementary MOS
integrated device which includes a layer of a first
conductivity type silicon carbide which may be a
substrate or an epitaxial layer. A well region of a
second conductivity type silicon carbide is formed in
the silicon carbide layer. A plurality of regions of
the second conductivity type silicon carbide are formed
in the silicon carbide layer to form a layer source
region and a layer drain region in the silicon carbide
layer. A plurality of regions of the first
conductivity type silicon carbide are formed in the
well region to form a well source region and a well
drain region in the well region. A gate dielectric
layer is formed between the layer source and the layer
drain regions and extending over at least a portion of
the layer drain and layer source regions. Likewise a
gate dielectric layer is formed between the well source
and the well drain regions and extending over at least
a portion of the well source and well drain regions. A
layer gate electrode is formed on the gate dielectric
layer formed between the layer source region and the
layer drain region so as to provide an active channel
region in the first conductivity type silicon carbide
layer between the layer source and the layer drain when
a bias is applied to the layer gate electrode. A well
gate electrode is also formed on the gate dielectric
layer formed between the well source region and the
well drain region so as to provide an active channel
region in the second conductivity type well region
between the well source and the well drain when a bias
is applied to the well gate electrode.
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A well source contact may also be formed on
the well source region and a well drain contact may be
formed on the well drain region. Similarlya layer
source contact may be formed on the layer source region
S and a layer drain contact formed on the layer drain
region.
In an alternate embodiment of the present
invention, a plurality of well channel stop regions are
formed in the well region. The stop regions are formed
of the second conductivity type silicon carbide and
have a higher carrier concentration than the well
region. The channel stops are positioned such that the
well source region and the well drain region are
displaced between the channel stop regions. A
plurality of layer stop regions may also be formed in
the silicon carbide layer adjacent the layer source and
the layer drain regions. The layer stop regions are
formed of the first conductivity type silicon carbide
and have a higher carrier concentration than the
silicon carbide layer. The layer stop regions are
formed such that the layer source and the layer drain
regions are displaced between the layer stop regions.
In addition to the formation of the basic
transistor devices, embodiments of the present
invention may include an isolation layer formed on the
silicon carbide layer, the well region, the well
source, gate and drain contacts and the layer source,
gate and drain contacts. This isolation layer allows
for interconnections of the various silicon carbide
devices. This interconnection may be achieved by a
plurality of metallization regions for selectively
providing connection to the well source, gate and drain
contacts and the layer source, gate and drain contacts
through connection windows formed in the isolation
layer.
In a further embodiment of the present
invention, a protective layer is formed on the exposed
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surfaces of the integrated device to protect the device
from environmental damage. Connection pads may be
formed in a connection pad window through the
a protective layer to allow for connection to any
underlying region such as the interconnecting
. metallization.
In a further alternate embodiment of the
present invention, at least one of the MOS devices has
a source and drain layer region that is self-aligned to
the gate electrode.
The method embodiments of the present
invention include a method of forming a complementary
MOS integrated device in silicon carbide. The method
includes the steps of forming a first silicon carbide
MOS field effect transistor in silicon carbide and
having a channel region formed in p-type conductivity
silicon carbide and forming a second silicon carbide
MOS field effect transistor in silicon carbide which
has a channel region formed in n-type conductivity
silicon carbide.
In a particular embodiment of the methods of
the present invention, the method of forming a silicon
carbide integrated device includes the steps of forming
a lightly doped silicon carbide layer of a first
conductivity type having highly doped source and drain
regions of a second conductivity type silicon carbide.
The second conductivity type is an opposite
conductivity type from the first conductivity type. A
lightly doped well of the second conductivity type is
formed in the lightly doped layer of the first
conductivity type. The lightly doped well has formed
in it highly doped source and drain regions of a first
conductivity type silicon carbide. Gate dielectric
layers are formed on the lightly doped silicon carbide
layer between the source and drain regions of the
lightly doped silicon carbide layer of the first
conductivity type and on the lightly doped well of the
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second conductivity type between the source and drain
regions in the lightly doped well.
In a preferred embodiment of the present
invention, the lightly doped well is formed by creating
a masking layer on a surface of the lightly doped
silicon carbide layer so as to create a window
corresponding to the region of the lightly doped well.
Ions are implanted into the lightly doped silicon
carbide layer through the window and the implanted well
is annealed to activate the ions implanted in the
lightly doped silicon carbide layer to create the
lightly doped well of a second conductivity type.
Preferably, the ions are implanted at a maximum implant
energy of greater than about 250 keV.
In a preferred embodiment of the method of
forming the drain and source regions, these regions are
formed by creating a masking layer on a surface of the
lightly doped silicon carbide layer so as to create a
window corresponding to the regions of the highly doped
source and drain regions of a second conductivity type.
Ions are implanted into the lightly doped silicon
carbide layer through the window and the implanted
regions are annealed to activate the ions implanted in
the lightly doped silicon carbide layer to create the
highly doped source and drain regions of a second
conductivity type. Preferably the highly doped source
and drain regions of the first conductivity type are
formed in the well region and activated in the same
manner utilizing an appropriate mask and ion.
In a preferred embodiment of the methods of
the present invention, the gate dielectric layers are
formed by depositing a gate dielectric layer on the
surface of the silicon carbide layer with exposed
portions of the lightly doped well of a second
conductivity type, the highly doped source and drain
regions of a first conductivity type and the highly
doped source and drain regions of a second conductivity
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type. The deposited dielectric layer is then heated in
an oxidizing ambient.
In a further embodiment of the present
invention, gate electrodes are formed on the gate
dielectric layers, source contacts are formed on the
source regions, and drain contacts are formed on the
drain regions. The source contacts and the drain
contacts are preferably formed by selective deposition
of nickel. The gate electrodes are preferably formed
by selective deposition of molybdenum. The formation
of the source and drain contacts for both device types
is preferably carried out simultaneously.
Stop regions may also be formed surrounding
the channel regions and/or source and drain regions by
adjusting the mask layer to allow ion implantation in
locations surrounding the channel and/or source and
drain regions of the device during implantation of the
source and drain regions of the complementary device.
In an alternative preferred embodiment an
interconnect isolation layer is formed over the gate,
source and drain contacts and any exposed gate
dielectric layer by deposition of an insulative
material. Connections to source, drain and gate
electrodes may be made by selectively opening vias in
the interconnect isolation layer for contact to the
underlying gate, source and drain contacts. A
metallization layer may be selectively formed- on the
interconnect isolation layer to selectively connect the
contacts or electrodes of the devices through the
opened vial. Successive interconnect isolation layers
with corresponding metallization layers and windows to
underlying interconnection layers may be formed to
provide a multi-layer interconnection system.
Contact pads may also be formed on the
metallization to allow contact to probes or wire bonds.
A contact pad may be formed by forming a platinum
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region on the metallization layer and forming a gold
layer on the platinum region.
A protective layer may also be formed on the
device to prevent environmental damage to the device.
In such a case windows are opened in the protective
layer to allow access to the contact pads.
The foregoing and other advantages, features
and objects of aspects
of the invention,
and the manner
in which the same are accomplished, will become more
readily apparent pon consideration of the following
u
detailed descripti on of the invention taken in.
conjunction with he accompanying drawings, which
t
illustrate preferr ed and exemplary embodiments, and
wherein:
Descriation of the DrawincLs
Figure 1 is a circuit diagram of a CMOS
integrated device according to the present invention;
Figure 2 is a cross-sectional view of a CMOS
integrated device according to the present invention;
Figure 3 is a flow diagram describing the
fabrication seque nce for a CMOS device such as that
shown in Figure ;
1
Figure 4 is a cross sectional view of an
intermediate step in the fabrication of a CMOS
integrated device according to the present invention;
~ Figure 5 is a cross sectional view of an
intermediate step in the fabrication of a CMOS
integrated device according to the present invention;
Figure 6 is a cross sectional view of an
intermediate step in the fabrication of a CMOS
integrated device according to the present invention;
Figure 7 is a cross sectional view of an
intermediate step in the fabrication of a CMOS
integrated device according to the present invention;
Figure 8 is a' cross sectional view of an
intermediate step iri the fabrication of a CMOS
integrated device according to the present invention;
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Figure 9 is a cross sectional view of an
intermediate step in the fabrication of a CMOS
integrated device according to the present invention;
Figure 10 is a circuit diagram of a silicon
carbide operational amplifier utilizing the present
invention;
Figure 11A is an I-V Characteristic Plot of
an n-channel device according to the present invention;
Figure 11B is an I-V Characteristic Plot of a
p-channel device according to the present invention;
Figure 12 is a plot of the DC transfer curve
of a CMOS operational amplifier according to the
present invention; and
Figure 13 is a plot of the implant profile of
an example of an n-type well according to the present
invention.
Detailed Description
The present invention now will be described
more fully hereinafter with reference to the
accompanying drawings, in which preferred embodiments
of the invention are shown. This invention may,
however, be embodied in many different forms and should
not be construed as limited to the embodiments set
forth herein; rather, these embodiments are provided so
that this disclosure will be thorough and complete, and
will fully convey the scope of the invention to those
skilled in the art. Like numbers refer to like
elements throughout.
Figure 1 illustrates the basic circuit
diagram of a CMOS device according to the present
invention. As seen in Figure 1, a p-channel MOSFET 20
and an n-channel MOSFET 22 are formed of silicon
carbide. These transistors are formed in a single
integrated device to create a CMOS integrated device.
The transistors shown in Figure 1 are illustrated with
the source/drain region of one device connected to the
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source/drain region of the complementary device. These
connections are optional as is the grounding of the
source/drain of one transistor and the connection of
the second transistor to a voltage source. By
connecting the two gate inputs of the transistors it is
possible to create a SIC CMOS invertor which is the
basic building block of many CMOS digital circuits.
The interconnection of the two transistors of Figure 1
is shown for illustration purposes only.
The complementary transistors of Figure 1
will now be described with reference to Figure 2 which
illustrates one possible cross section for a CMOS
silicon carbide integrated device according to the
present invention. As shown in Figure 2, a bulk single
crystal silicon carbide substrate 30 of a first
conductivity type has a lightly doped epitaxial layer
32 of the first conductivity type formed on its upper
surface. For purposes of illustration, the first
conductivity type may be p-type conductivity silicon
carbide, thus making the epitaxial layer 32 lightly
doped p-type (p-) conductivity silicon carbide.
Formed in the epitaxial layer 32 is a well
region 40 of a second conductivity type silicon
carbide. For purposes of illustration, the second
conductivity type may be n-type conductivity silicon
carbide, thus making the well region 40 lightly doped
n-type (n-)conductivity silicon carbide. ,
A plurality of regions of the second
conductivity type silicon carbide are formed in the
silicon carbide epitaxial layer 32 to form a layer
source region 36 and a layer drain region 38. These
source and drain regions are highly doped regions such
that, in the present example, they would be n' silicon
carbide. A plurality of highly doped second
conductivity type silicon carbide regions 44 are also
formed in the well region 40 to create well stop
regions. These regions in the present example would
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also be n' silicon carbide. Preferably, the channel
stop regions define the perimeter of the device,
however, the channel stop regions may only be formed to
confine the channel region of the device. Thus, for
example, as seen in Figure 2, the channel stop regions
may be formed only in a third dimension to the cross
section show in Figure 2 such that the channel stop
regions run perpendicular to the source and drain
regions to confine the channel to the regions between
the source and drain regions.
A plurality of regions of the first
conductivity type silicon carbide are formed in the
well region 40 to form a well source region 46 and a
well drain region 48. These source and drain regions
are highly doped regions such that, in the present
example, they would be pi silicon carbide. The well
source region 46 and well drain region 48 are formed
within the confines of the well channel stop regions
44. Preferably, the channel stop regions define the
perimeter of the device, however, the channel stop
regions may only be formed to confine the channel
region of the device. Thus, for example, as seen in
Figure 2, the channel stop regions may be formed only
in a third dimension to the cross section show in
Figure 2 such that the channel stop regions run
perpendicular to the source and drain regions to
confine the channel to the regions between the source
and drain regions. A plurality of highly doped first
conductivity type silicon carbide regions 34 are also
formed in the silicon carbide epitaxial layer 32 to
create layer stop regions. These regions in the
present example would also be p' silicon carbide. As
seen in Figure 2, the layer stop regions 34 are formed
outside the layer source region 36 and layer drain
region 38.
The use herein of the terms "layer" and
"well" as prefixes to a feature serves to distinguish
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the features of one transistor from the other,
complementary, transistor. For example, a well source
region would refer to a region which is associated with
the transistor formed in the second conductivity type
silicon carbide well. A layer source region refers to
a region which is formed in the first conductivity type
silicon carbide layer.
Furthermore, while the present invention uses
the term "well" to describe the region where the
complementary device is formed, as will be appreciated
by those of skill in the art, any shaped region of
opposite conductivity type silicon carbide may be
utilized as long as it is capable of having a
complementary silicon carbide device formed in the
region. Thus, for example, the "well" region 40 may
extend completely through the epitaxial layer 32 to
substrate 30 so as to form a contiguous region of
second conductivity type silicon carbide which
interrupts epitaxial layer 32. Accordingly, the use of
the term "well" is used to describe a region where a
complementary device may be formed, however that region
is created.
Also shown in Figure 2 is a gate dielectric
layer 49 which is formed on the surface of the
epitaxial layer 32 opposite the substrate 30. The gate
dielectric layer 49 is illustrated as being formed over
the entire upper surface of the epitaxial layer 32 with
windows opened in the gate dielectric layer 49 over the
source and drain regions 36, 38, 46, and 48. However,
the gate dielectric layer 49 need only be formed on the
epitaxial layer 32 between layer source region 36 and
layer drain region 38 and well source region 46 and
well drain region 48 with a suitable overlap of the
source and drain regions.
As is further illustrated in Figure 2, a
layer gate electrode 50 is formed on the gate
dielectric layer 49 between the layer source region 36
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and layer drain region 38. The layer gate electrode 50
provides an active channel region in the first
conductivity type silicon carbide layer between the
layer source and the layer drain when a bias is applied
to the layer gate electrode Likewise, a well gate
electrode 52 is formed on the gate dielectric layer 49
between well source region 46 and well drain region 48.
The well gate electrode 52 provides an active channel
region in the second conductivity type well region
between the well source and the well drain when a bias
is applied to the well gate electrode. While various
materials such as poly-silicon may be utilized for
forming the gate electrodes, molybdenum is preferred.
Figure 2 further illustrates a layer source
ohmic contact 54, a layer drain ohmic contact 56, a
well source ohmic contact 57 and a well drain ohmic
contact 55 formed on their respective source and drain
regions. A well body contact 53 is also shown in
Figure 2. These ohmic contacts are preferably formed
of the same material and more preferably formed of
nickel. However, as will be appreciated by one of
skill in the art, ohmic contacts formed on the various
conductivity type silicon carbide regions may be formed
of different contact materials. Accordingly, nickel
may be used to form ohmic contacts to n-type silicon
carbide regions and aluminum and/or titanium or
platinum may be utilized to form ohmic contacts to p-
type silicon carbide regions. Differing contact
materials, however, are not preferred because of the
increased complexity of fabrication.
Also shown is an ohmic contact 51 formed on
the surface of substrate 30 opposite epitaxial layer
32. This layer serves as the layer body contact of the
layer device and may be formed of any suitable material
for forming an ohmic contact with silicon carbide. In
the present example, platinum would be suitable for
forming the ohmic contact to the p-type substrate.
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Optionally, the layer body contact may be formed by
contacting the epitaxial layer 32 directly.
An interconnect isolation layer 58 is also
illustrated in Figure 2 and may optionally be formed on
the exposed surfaces of the integrated device. This
isolation layer 58 is formed on the silicon carbide
layer 32 to isolate the well region 40, the layer
source contact, gate electrode and drain contact 54, 50
and 56 and the well source contact, gate electrode,
drain and body contacts 57, 52, 55 and 53. A plurality
of metallization regions 59 may also be provided for
selective interconnection of the layer source contact,
gate electrode and drain contact 54, 50 and 56 and the
well source contact, gate electrode and drain and body
contacts 57, 52, 55 and 53 through connection windows
formed in the isolation layer 58. As shown in Figure
2, the drains of the two complementary transistors are
connected through a metallization region, however, such
is not required by the present invention.
Metallization formed of molybdenum is preferred for the
present invention, however, other materials such as
aluminum may be utilized.
A protective layer 60 may also be formed on
the exposed surfaces of the integrated device, such as
the metallization regions 59 and the isolation layer
58, to protect the device from environmental damage.
Connection pads may also be formed in a connection pad
window through the protective layer 60 where the
connection pad is selectively formed on the underlying
regions such as the metallization regions to provide
external contact to the underlying regions. A
connection pad is shown in Figure 2 as a layer of
platinum 61 formed on the metallization region 59 in a
connection pad window and a layer of gold 62 formed on
the layer of platinum 61.
In addition to the general structure above,
it is preferred that the gate overlap of the source and
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drain regions of the both device types be made as small
as possible while still allowing for formation of a
channel region between the source and the drain when a
bias is applied to the gate electrode. Furthermore,
the devices may have self aligned gates for one or both
of the devices. Methods of self aligning gates in 3C
silicon carbide have been discussed in Palmour et al.,
J. App. Phys., 64, p. 2168 et seq. (1988) which is
incorporated herein by reference as if set forth fully.
While the present invention is described
above with respect to the formation of the
complementary devices in an epitaxial layer formed on a
silicon carbide substrate, the present invention is not
limited to such a device. For example, the
complementary devices may be formed in a silicon
carbide substrate with no epitaxial layer.
Additionally, there may be additional layers
interspersed between a substrate and the silicon
carbide layer in which the complementary devices are
formed. Accordingly, as used herein the term silicon
carbide layer may refer to a layer of silicon carbide
formed on a substrate, to a layer of silicon carbide
formed on another layer or to a silicon carbide
substrate.
Also, the above device has been discussed
with reference to a p-type epitaxial layer and an n-
type well region, a device having an n-type epitaxial
layer and a p-type well region may also be utilized.-
In such a case the first conductivity type silicon
carbide would be n-type silicon carbide and the second
conductivity type silicon carbide would be p-type
silicon carbide. Alternatively, an epitaxial layer of
opposite conductivity to a substrate could be used
where devices of one channel type are formed in the
epitaxial layer and complementary devices formed in the
substrate.
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The method of fabrication of devices
according to the present invention will now be
described with reference to Figures 3 through 9.
Fabrication of CMOS in silicon carbide may be
accomplished through a nine step process which includes
ion implantation of the source and drain regions of
both device types and the well region for the
complementary device. Suitable methods for ion
implantation acording to the present invention include
the high temperature ion implantation methods of
commonly assigned United States Patent No. 5,087,576,
the disclosure of which is incorporated herein as if
set forth fully. These fabrication steps will now be
described with reference to fabrication of a silicon
carbide device on a p-type epitaxial layer formed on a
p-type silicon carbide substrate. However, as
described above, the present invention is not limited
to devices utilizing a p-type silicon carbide layer but
may also be used with n-type silicon carbide layers
with suitable substitutions of implantation ions and
fabrication techniques based upon the changes in
conductivity type. For example, a p-type well region
for fabrication of the complementary device could be
formed in an n-type silicon carbide layer through
implantation of boron ions in the n-type silicon
carbide layer.
Figure 4 illustrates the beginning steps of
forming a CMOS integrated device in silicon carbide.
After growth of an epitaxial layer on a lightly doped
p-type silicon carbide substrate, a mask layer 81 is
formed to expose the layer source and drain regions and
the well channel stops. The formation of the mask
layer is illustrated as block 102 of Figure 3. 6H
silicon carbide is the preferred polytype for the
present invention, however, other silicon carbide poly-
types, such as 3C, 4H, and 12H may also be utilized.
Preferred carrier concentrations for the p-type
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substrate range from about 1 X 1016 to about 1 X 1018 cm-
3, however, the doping level of the substrate as it is
used in the present example is not critical. Preferred
carrier concentrations for the p-type epitaxial layer
range from about 1 X 1015 to about 1 X 101' cm-3. The
mask layer may be formed of silicon dioxide (SiOz),
however, any suitable masking material may be utilized.
The masked wafer is implanted with nitrogen
ions to form the n' source and drain regions for the n-
channel device and the n' well channel stops for the p-
channel device. The implantation step is reflected in
block 104 of Figure 3. While nitrogen is the preferred
ion for implantation to form the n~ regions, other
suitable ions known to those of skill may also be
utilized. The nitrogen is preferably implanted at a
temperature of 650 °C, however, implantation
temperatures ranging from about room temperature to
about 1300 °C maybe utilized. The nitrogen is also
preferably implanted with multiple implant energies of
not greater than 135 keV with maximum implant energies
of less than about 200 keV being suitable. Suitable
carrier concentrations for the n' implanted regions are
from about 1 X 101' to about 1 X 10z° cm-3.
Figure 5 illustrates that after implantation
of the n' regions the wafer is recoated with polysilicon
82 which is patterned to form an opening in the
polysilicon and the underlying oxide mask. The
formation of the polysilicon mask is shown in block 106
of Figure 3 This opening corresponds to the n-type
well which provides the opposite conductivity region
for the n-channel device. After formation and
patterning of the polysilicon/oxide mask, nitrogen is
again implanted in the p-type epitaxial layer to form
the n- well region 40. Implantation of the well region
is illustrated in block 108 of Figure 3. Nitrogen is
the preferred ion for implantation to form the n- well
region. The nitrogen is preferably implanted at a
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temperature of 650 °C, however, implantation
temperatures ranging from about room temperature to
about 1300 °C maybe utilized. The nitrogen is also
preferably implanted multiple implant energies with a
maximum implant energy of about 380 keV. However,
maximum implant energies ranging from about 250 keV to
about 1 MeV may be suitable. Suitable carrier
concentrations for the n- well region is from about 1 X
1015 to about 1 X 101' cm-3. Because of the difficulty of
implanting deep wells in silicon carbide and the need
to support an application dependent reverse bias
voltage, the implant profile of the well region may be
tailored such that impurity concentration increases
with depth.
After implantation of the n-type well, the
wafers are stripped of the mask layers utilizing a wet
chemical solution such as hydrofluoric acid or other
suitable solutions. The stripping operation is
illustrated in block 110 of Figure 3. After stripping,
the wafers are annealed to remove damage from caused by
ion implantation and to activate the implanted dopants.
The wafer is preferably annealed at 1550 °C, however,
temperatures ranging from 1000 to about 1800 °C are
suitable. The annealing step is shown in block 112 of
Figure 3. Optionally, the wafer may be annealed after
multiple ion implantations are performed.
After annealing, a third mask layer 83 is
formed on the epitaxial layer to create the n-channel
stop regions 34 and the p-channel source 46 and drain
48 regions. This mask layer is illustrated in Figure
6. As with the first masking operation, silicon
dioxide or any other suitable masking material may be
utilized for the mask layer. The formation of the
third mask layer is illustrated in Figure 3 at block
114. Aluminum is then implanted to form the p' well
source and drain regions 46 and 48 and to form the
layer stop regions 34. The implantation step is
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reflected in block 116 of Figure 3. While aluminum is
the preferred ion for implantation to form the p'
regions, another suitable ion includes boron. The
aluminum is preferably implanted at a temperature of
about 1200 °C, however, implantation temperatures
ranging up to about 1300 °C maybe utilized. The
aluminum is also preferably implanted with multiple
implant energies of up to about 135 kev with a maximum
implant energy being dependent on the depth of the well
region. The source and drain region maximum implant
energy is limited such that when the source and drain
are reverse biased with respect to the well region, the
well region beneath the source and drain is not fully
depleted and the depletion region below the source and
drain does not extend into the substrate. Suitable
carrier concentrations for the p' implanted regions are
f rom about 1 X 101' to about 1 X 102° cm-3 .
After implantation of the p' regions, the
third mask is stripped as described above and the wafer
is again annealed as described above. This second
strip and anneal step is illustrated in block 118 of
Figure 3. After the second anneal, the wafers may
optionally be thermally oxidized to remove surface
damage and the resulting oxide again stripped.
After the formation of the n' and p+ regions,
the two devices are fabricated in the same manner. As
seen in Figure 7, the gate dielectric layer 49 is
deposited on the epitaxial layer 32 so as to cover the
channel regions of the two devices. This gate
dielectric layer is preferably silicon dioxide and is
deposited and then oxidized as described in commonly
assigned United States Patent No. 5,459,107 entitled
METHOD OF OBTAINING HIGH QUALITY SILICON DIOXIDE
PASSIVATION ON SILICON CARBIDE AND RESULTING PASSIVATED
STRUCTURES, and as described in copending and commonly
assigned U.S. Patent No. 5,972,801, entitled PROCESS FOR
REDUCING DEFECTS IN
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OXIDE LAYERS ON SILICON CARBIDE, filed November 8,
1995, the disclosures of which are incorporated herein
by reference as if set forth fully. Thus, after
deposition of a silicon dioxide layer, the wafers are
preferably placed in a furnace in an oxidizing ambient
for several hours prior to the deposition of gate metal
on the gate dielectric 49. This deposit and re-oxidize
step is illustrated in block 120 of Figure 3.
While deposition and reoxidation of the gate
dielectric layer is preferred, other methods of forming
the gate dielectric layer, such as thermally growth may
be utilized. The densified deposited oxide was chosen
as the gate insulator to strengthen the gate overlap
regions of the device where most MOSFET oxide
reliability failures occur. The deposited oxide
eliminates the step that develops at either end of the
lightly doped channel during the growth of a thermal
gate oxide. This step is the result of an enhanced
oxidation rate over the implanted source/drain regions.
The step can act as a field concentrator in the gate
overlap regions and stress the gate oxide. The
dielectric strength of an oxide which is grown on
heavily implanted SiC is poor, and additional stress
increases the likelihood of an oxide related failure in
the overlap region. This weakness may be attributed to
impurity incorporation, non-stoichiometric growth, or a
rough SiC-Si02 interface due to impurity segregation or
implant damage. A deposited oxide reduces these
concerns related to impurity incorporation and
segregation. The incorporation of aluminum in the gate
overlap regions of p-channel devices is a particular
problem because it creates a deleterious gate leakage
path at elevated temperatures. The oxidizing anneal
step is performed to ensure proper oxide stoichiometry
and to improve the SiC-Si02 interface.
After completion of the formation of the gate
dielectric layer 49, the gate metal, 50 and 52, is
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deposited and patterned. This operation is shown in
block 122 of Figure 3. As discussed above, the gate
material is preferably molybdenum, however, other
suitable gate materials include polysilicon or
aluminum.
After deposition of the gate material, an
isolation layer 58 is deposited on the wafer and vias
are etched through the isolation layer to expose
portions of the n' and p+ source and drain regions or
the well region or the epitaxial layer. The formation
of the isolation layer 58 is illustrated in Figure 8.
The isolation layer 58 is preferably formed of silicon
dioxide but may be formed of any suitable insulating
material such as silicon nitride. The isolation layer
serves to isolate the devices from an interconnect
metallization layer which is formed on the isolation
layer. The formation of the isolation layer is
reflected in block 124 of Figure 3.
After formation and etching of the isolation
layer 58, nickel or other suitable ohmic contact
material is deposited in the vial opened in the
isolation layer 58 to simultaneously create the source
and drain ohmic contacts 54, 56, 55 and 57 and the well
region contact 53. While the simultaneous creation of
contacts for both type devices is preferred, the p-type
contacts and the n-type contacts could be formed of
differing materials and formed in multiple fabrication
steps if desired. The contacts are preferably annealed
for about 2 minutes at about 825 °C, however, any time
and temperature combination sufficient to form the
metal-semiconductor contact may be utilized. The
contact formation steps are illustrated in block 126 of
Figure 3.
After formation of the contacts,
metallization 59 is selectively formed on the isolation
layer to selectively connect the devices sources,
drains, gates and epitaxial layer or well region. As
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an example, the drains of the two devices illustrated
in Figure 8 are interconnected by metallization formed
on the isolation layer. The metallization is
preferably formed of molybdenum, however, other
suitable metallization materials such as aluminum may
be utilized. The formation and patterning of the
interconnection metallization may be done by any
suitable technique known to those of skill in the art.
The formation of the interconnect metallization is
shown in block 128 of Figure 3.
An example of the final device is shown in
Figure 9. The final steps of fabrication of the device
include selectively forming contact pads by depositing
a platinum layer 61 and a gold layer 62 on the
metallization layer 59. The formation of the contact
pads is shown in block 130 of Figure 3 The entire
device is then covered with a protective layer 60 to
protect the device from the environment. The
protective layer 60 is patterned to open vial above the
contact pads to allow for probing or formation of wire
bond or other suitable external connections. The
protective layer 60 may be a deposited layer of silicon
dioxide or other suitable material such as silicon
nitride. The formation of the protective layer is
illustrated in block 132 of Figure 3.
Described above have been various formation
and patterning steps for the creation of masking or
isolation or protective layers. These steps may be
carried out using any suitable technique for formation
and patterning such as, for example, by chemical vapor
deposition or other techniques known to those of skill
in the art. Suitable equipment for the formation of
the devices utilizing the growth, deposition and
implantation techniques described above is commercially
available and known to those of skill in the art.
A CMOS silicon carbide integrated circuit has
been fabricated utilizing the present invention. The
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CMOS silicon carbide circuit is illustrated in Figure
and is an operational amplifier. The operational
amplifier was formed on a 6H p-type silicon carbide
substrate with a p-type epitaxial layer doped to a
5 carrier concentration of from about 2 X 1015 cm-3 to
about 2 X 1016 cm-3. The epitaxial layer had a
thickness of about 3 to 5 ~.m. The fabrication
techniques described above were carried out to create
the complementary devices required for the operational
10 amplifier of Figure 10.
The n-well for the p-channel device was
created with a 15 V power supply in mind. The high
temperature nitrogen implant energy was limited at the
time to 380 keV. The worst case condition is having the
drain of a p-channel device near ground (the substrate
potential) while the n-well is at VDD which puts 15 V of
reverse bias on the well from both directions. To
support this bias without punching through the n-wall,
the simulated profile shown in Figure 13 was
implemented. A higher implant energy and lower dose
may also be utilized to form a deeper and flatter
impurity profile which may accomplish the same reverse
bias capability. The reverse bias capability may also
be reduced to accommodate a VDp of 12 V, another common
supply voltage available in most systems. This would
reduce the total dose and energy required to form the
n-wells, and would reduce implant damage that occurs in
forming the n-well. The dual use of the source/drain
implants for channel stops was employed here to
simplify this process, however, separate implants with
lighter doses and lower energies may also be utilized.
The carrier concentrations of the n+ regions
of the device were approximately 1 X 1019 cm-3 and
carrier concentrations of the n- well are illustrated in
Figure 13. The carrier concentration of the p+ regions
was approximately 1 X 1018 cm-3. The n' and p' regions
were implanted to a depth of about 0.35 and 0.25 ~cm
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respectively and the source and drain regions had
dimensions of about 8 ~.m by 25 ~,m to about 100 ~,m. The
n-type wells were formed to a depth of approximately
0.7 ~.m in the p-type epitaxial layer. Gate widths of
approximately 25 to 200 ~,m and gate lengths of
approximately 2 to 8 ~m were utilized.
The I-V characteristics of the complementary
devices are shown in Figure 11A and Figure 11B. Figure
11A illustrates the operational characteristics of the
n-channel device formed in the well region. Figure 11B
illustrates the operational characteristics of the p-
channel devices formed in the epitaxial layer. The
threshold voltage of the n-channel devices was 2.5
volts and the threshold voltage of the p-channel
devices was about -15 to -17 volts.
Figure 12 is a graph of the DC transfer curve
for the silicon carbide CMOS operational amplifier of
Figure 10. The open loop operational gain of the
amplifier was about 109 or 80 db.
In the drawings and specification, there have
been disclosed typical preferred embodiments of the
invention and, although specific terms are employed,
they are used in a generic and descriptive sense only
and not for purposes of limitation, the scope of the
invention being set forth in the following claims.
