Note: Descriptions are shown in the official language in which they were submitted.
CA 022~76~8 1999-01-12
W093tt3~ PCT/US93/04361
ORRI8-ls
RESTRICTED INFORMATION
DISTRIBUTION SYSTEM APPARATUS AND ~TUons
~eld of the ~nvention
The ~ubject invention relates to the di6tribution of
information and, more particularly, for distributing this
information in a 6ecure and restricted manner to a plurality
of users.
Backaround of The Invention
Applicant and other related companies are in the business
of distributing realtime financial market information to
various clients who use thi6 informAtion to carry on their
business. When a client subscribes for this service, an
agreement is entered into in which the client indicates what
information i8 desired and how many video screens will be
displaying the information. Based on these parameters, a
fee is ACsec~~~ to the client and the information then is
transmitted to the client.
Typically, this fi~nciAl market information is
transmitted to clients as one or more pages or records thAt
may be displayed on a video 6creen, portions of which, from
time to time, are updated to reflect changes in the market
information. Various clients F~h-~ribe to view different
specific groups of these pages and/or records.
An early method of distributing market information was
~ based upon the transmi6sion of a single page of real time
digital information over a single telephone line. Page-
oriented information (ROW t, COL ~, rU~cTER STRING) wa6
6ent from the information vendor's computer over a telephone
network to a controller, provided by the information vendor,
located at the client 6ite. The page-oriented information
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was 6ubseguently ~G~-~e~ ~ed to video by a video generation
unit within the ~o..L~oller. The video o~L~- was then
connected to n video screen by a single coAxial cable.
Each full page was repeatedly transmitted in video at a
field rAte for realtime display, ~imilar to that of a
television transmission. However, once the video signal was
produced, there was nothing, except the personal integrity
of the client, to prevent the client from co~necting any
number of video screens to a video distribution amplifier
connected to the col.LLoller, driving a larger number of
video screens above and Leyond the number stated in the
-agreement. This practice dilutes the revenues to which the
information vendor would ordinarily be entitled.
This architecture was costly and unreliable because of
the lArge amount of hardware needed to place financiAl
information on a lArge number of trading desks. For
example, if A client~ trading room had thirty traders, each
trader needed his own single-user system resulting in thirty
keyboards, thirty controllers with thirty internal video
generation units, thirty telephone cables, thirty modems,
thirty coaxial video cables, and thirty video screens to
receive and display the reguired financial information.
This technology also limited the screen presentation
format to what was provided by the information vendor. When
2S traders were only interested in one or two fields of
information on a screen, they would have to display the
entire page of information. If they wanted to look at one
or more fields of information on A second screen at the same
time, an entire additional single-user system would be
required. Further, when two traders wanted to look at the
same page, they would either have to have two separate
single-user systems or the video information would be
redistributed to a ~slave~ video screen making it difficult
for the information vendor to know how many video screens
3s were connected to a given co.. LLoller and hence how many
people were viewing their information. This made billing
CA 022S76~8 1999-01-12
W093/23~8 PCT/US93/~ ~1
difficult and u~ually created a ~ of surpri6e client-
~ite visit6 that left both $nformation vendor and client
llnhArpy.
The development of multi-user sy6tems re~c~d the amount
of required hardware and enabled u~ers to share resources
and view common information. In multi-user sy~tems, each
trader had one keyboard and several video screen6. Through
the use of video switc~in7 t~rhn~ques, thirty traders could
chare perhap~ ten or fifteen c6.,L.oller6 and contend for
their use. Since many trader-c are part of a trading group
that uses essentially the same financial market information,
-the probability of blocking (not having a oG~ oller
available to fulfill a new page reque~t) was small.
Such multi-user sy6temg helped reduce costs by reducing
the number of controllers, keyboard~, and system cAbling,
but did not solv~ either the billing problems or allow the
user to customize screen presentation format~.
Later, single telephone line, multi-page distribution
systems were developed which reduced the required number of
telephone line~. The information syntax for these multi-
page sources was slightly modified to (PAGE ~, ROW ~, COL ~,
CHARACTER STRING). User~ of such ~ystems al~o could create
composite pages (fields from different pages displayed
simultaneously on one video screen) and calculate and insert
additional value-added information (e.g., bond yield to
maturity). By doing so, customized ou~p~1 di_play pages
could be created showing only the information and value-
added calculations the user wanted to see.
U_ers developing value-added applications based upon page
oriented data had to as~ign a symbolic name to an
'- information field located at a specific display location of
the input source page. When the information vendor changed
~' the presentation format of the information (i.e., the
location of a -cpecific data element), a~ often h~pr~nC when
financial instrument~ are either added or deleted, the
value-added application had to be modified. To overcome
CA 022~76~8 1999-01-12
W093/23 ~ PCT/US93~04361
this difficulty, and to supply basic information without
display parameter~, the information vendor created record-
oriented cources using the syntax (SYMBOLIC NAME, rU~RA~TER
STRING). Examples of ~uch a system are the Reuter~
Integrated Data Net~o~ and the Telerate TIQ Feed.
Despite the foregoing advance~ in the field of electronic
financial information distribution systems, ~u .,.~ sy~tems
still allow video ccreens to be added and/or moved freely
without either the information vendor's knowledge or
con-?nt. Further, each video screen must be connected by
its own single-video ~home-run~ cable, i.e., a cable that
-typically runs for hu.,dLeds of feet between the trading
floor where the video screen is located ~nd the eguipment
room where either a cGI~.oller~ video switch ou~uL, or a
host computer i6 located.
Summary Of The Invention
An object o. the present invention i8 to provide a system
capable of ~ecurely providing restricted information.
A further object of the present invention i5 to provide a
system which is capable of uniguely identifying each of the
video screens authorized to display information, to restrict
this information to only these individual video screens, to
identify which of the information these video screens are to
2S display, and to present only authorized information on each
and every video screen; unauthorized video screens would
only ~,esent unintelligible transmogrified ver~ions of the
information.
It also i~ a object of the present invention to provide a
financial information distribution ~ystem that is capable of
taking inputs simultaneously from both multiple information
page and/or record-oriented input ~ources (e.g. video,
digital and/or live television) and a multitude of
keyboards, to create a multitude of different GU~u~
displays for concurrent display on a multitude of video
screens all interconnected by a single cable, such that the
CA 022~76~8 1999-01-12
WOg3~g58 PCT/US93/~361
video S~l~ enC may contain different combinations of portions
of different input gou~ce3 of information.
It i~ a further object of the ~ ent invention to
provide a f~n~nc~l information di~tribution ~y~tem in which
each video ~creen has a unique display identification code
that is used to authorize viewing and/or to permis~ion what
input source information each individual video screen will
be capable of displ~ying at any given time.
It is a another object of the ~er~nt invention to
facilitate the ~bility to provide each user'g video
screen(g) with a customized o~u~ display.
- It is yet another object of the present invention to
reduce the cost of tr~nsmitting and displaying financial
market updates to numerous userg.
It is further object of the present invention to provide
a single host computer device to ~u~o~ a plurality of
users and an even larger plurality of video screens for
securely distributing restricted information to one or more
authorized video screens simult~n--o~ly. It is another
object to allow rapid ~e~ ~? to user reguests to view new
or additional ~ource of inf ormation.
It is another object to provide for distributing
information in a tile format whereby each user cAn assign a
loc~tion on that user's video screen for display of the
tile, and the same digplay information may be displayed on
different locations on different video screens and
simultaneougly updated- It is another object to DU~O~ ~ a
larger video ~creen to provide for displaying tiles from a
plurality of information input sou~es ~imultaneously.
Applicant has r~co~n~zed that usually only small portions
of the input page or record source information change over a
small time, for example, the time cG~le-pon~ng to one field
time of displayed video. It is, therefore, nec~sr-ry to
transmit only the information which is changing as update
data and then to store this update dat~, along with the
CA 022~7658 1999-01-12
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-6-
~ch~nged data, in a memory at the video screen for
subsequent display.
It is, therefore, another object to yLep~G~Fss video
signals to identify the changed display information to be
displayed prior to inputting the video information into a
display information distribution system, thereby minimizing
the amount of channel bandwidth nec~ssAry to distribute the
information.
It is another object of the invention to provide for
preprocessing digital and analog video signals for display
information including financial market information and
- television ~.o~Lam information signals. It is another
object to provide for preprocessing composite and non
composite video signals. It is yet another object to
provide a switchable device that can process information in
color and monochromatic video signals.
It is another object of the invention to provide a
modular residual video converter device that can be
constructed as a ~mall printed circuit assembly so that one
assembly is used for each source of video signals and
several assemblies can be combined onto a single printed
circuit board for ease of packaging and ~YpAnsion.
It is another object of the present invention to improve
the efficiency and messaging capacity of an information
distribution system by converting incoming video signals
having successive frames of display information to digital
video messages identifying the pixel changes from one frame
to the next.
Applicant also has recognized that users typically want
to view only a portion of a full page or record of source
information provided by the vendor and therefore use several
video screens displaying different sources of information so
that the information they wish to view is concurrently
displayed on multiple screens.
With these facts in mind, the above objects are achieved
in a system for securely providing restricted information,
CA 022~76~8 1999-01-12
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-7-
wherein the 6ystem includes an ~ncoA~r for ~ncoA~ng update
data for updating various tiles (i.e., portions of pages or
lcCu~dS) of displ~y information, and a plurality of ~PcoAPrs
for ~eco~ng said update data ~nd generating s~id v~rious
S ~uL~uL displays on video S~LeenSr characterized in that sai
enco~Pr comprises means for generating a fir~t data stream,
said first data stream including respective sets of one or
more unigue di~play identification codes identifying each
video screen and one or more information identification
codes for each of said tiles, said sets being indicative of
the tiles, i.e., each particular portion of di~play
information, each video screen of each client or user is
authorized to receive; means for generating a seguence of
recon~ data streams, each of said ~eCQn~ data streams
including one of said individual information identification
codes, coordinates of an area in a relevant video screen
that is to di~play update data for the portion of display
information, ~nd the respective upd~te data; and me~ns for
transmitting said first data ~tream followed by said
~equence of s~ -nA data streams; and in that e~ch of said
decoders comprises a video screen; means for identifying the
relevant video screen with one of said unigue di~play
identification codes; means for recognizing said one unique
display identification code and for storing the information
2S identification codes in the associated ~et with aid one
unique display identification code; means for retrieving
said display coordinates of the update data ~GL~e~l,o..ling to
each of said stored information identification codes; means
for storing said update data at the related coordinates for
subseguent display on the video screen; and means for
selectively displaying said stored updated display
information on the video screens.
-, In accordance with a preferred embodiment, the encoAer
(also referred to as a transmitter) is a mi~lu~ r--or
based device that transmits a high bandwidth digital and/or
analog signal over a single coaxial cable. The enco~Pr
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-8-
manages communications between a host computer and the
plurality of AecoA~rs (al~o referred to as receivers),
caches those particular portions of display information that
_re being viewed on video ~creens, _nd stores symbolic data
elements. All data changes and/or specific instructions
sent to any one or all of the AeCoAprc originates in _n
application r~nning on the host computer, and is transmitted
via a digital-video tDV) bus from the encoAer to the
decoAPr(s). A delta-modulation type of communication
protocol is used to greatly reduce the _mount of transmitted
information. Unl~e a video switch environment, in which
almost the same information is transmitted sixty times a
recon~, only display screen changes Are signaled.
Display chAnges are transmitted by tile messaging, i.e.,
transmitting the portion of the page or record of financial
market information that contains the changed financial
market information within a tile of horizontally and
vertically ccntiguous cells. Each tile is given an
information identification code and has corresronAing data
such that authorized users of the data are enabled with the
corresponAing information identification code as a symbolic
name or reception key for identi'ying the particular tile by
its symbolic name or reception key _nd receiving and
retrieving the update data. Further, the tile may be given
a default size and display location on a video screen, a
user-defined size and display location, or both, such that
the transmitted data is mapped into any user-defined
location as it is stored for display on the video screen.
Some of the transmitted data may not be stored or displayed
when the user-defined tile is smaller than the transmitted
tile.
The cost associated with transmitting the same data for
different tiles (pages or ~eco~ds) of information can be
greatly reduced in accordAnce with the ~ qnt invention, by
3s initializing the location of an individual data field,
through the use of a message identifying (i) the information
CA 022~76~8 1999-01-12
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identification code for a particul_r ~ource page or ,e~
of display information, (ii) the information identification
code for the specific information field tl~ou~}- the use of a
~ymbolic name of a tile contAin~ng the individu_l data
field, and (iii) a location in which the data of the data
field _re to appear on the particular tile. After this
initialization, the information identification code for the
symbolic name can be transmitted along with data, without
any display coordinate information, and each initl A 1 i zed
video ~creen that displayc the data as~ociated with the
cy~bolic name is updated simultA~eo~ly through the use of
:this single data message and previously provided display
coordinAtes .
Each AecoAer receives at least all transmitted messages
for it~ video 6creens and stores the inform_tion to be
displayed, i.e., the screen image, in an internal picture
~tore memory. Each AecoAPr selects out and ~s~ e~ only
those messages on the DV bus that are directed to its video
screens or to the decoAer. Thus, each AecoAer may have more
than one video ~creen and a unigue display identification
code for each video screen. Each video screen has a unique
identification code that supports permissioning of
restricted display information to be viewed and is capable
of displaying ~imultAnec~sly either color or monochromatic
text and/or pixel based graphics, as well a8 live TV
pictures. In addition, the decoAer can detect and directly
pass through unencoA~A video sign_ls to its video screens.
Commercially available keyboards and mice may be provided
to send information request signals via the ~coAPr to a
cGl.L.ol bus connecting the plurality of decoders to the
encoAer or host computer _nd to define tile size and display
locations. The keyboard optionally may include an internal
, LCD display.
A residual video converter (RVC) device allows both view-
only and interactive video souL~e- to be utilized on the
system. The RVC device accepts one or more video inputs,
CA 022~76~8 1999-01-12
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--10--
c~ e,~s them into _ DV bus messAge form_t con~n~ng only
video ~creen ch_nges ~uitable for transmission to the
~co~r~ over the DV bus, and directly interfaces with the
enGo~r. Thus, the encoA~r m_y transparently pass the RVC
ouL~ ignals at _~G~Liate times.
A television feed converter (TFC) device allows realtime
television sources to be utilized on the system. The TFC
device _ccepts one or more televi~ion inputs, cG..ve,~s them
into A format ~uitAble for transmission to the ~co~ers over
the DV bus, and directly interfaces with the enco~r. The
~nGo~er may transparently pas~ the television p~GyL~m
--information signals at appropri~te times.
In addition, financial market information may be brought
into the system via a commercially available Digital
~5 Interf_ce Board (DIB) device. On larger systems, the DIB
device _lso may be configured to manage the control bus.
The DIB device _lso allows for authorized indivi~llA~ to
gain remote _ccess to the sygtem, for example, by use of
passwords. ~or example, the information vendor may use the
interf_ce remotely to ~Authorize~ clients to use and/or view
predefined subsets of their source information (e.g., to
increase the number of authorized video screens). The
vendor also is able to gather utilization statistics from
each client site which is u~eful for marketing and/or
billing ~u~c~es. The operator of the system mAy use the
interface remotely to provide routine ~oftware mainten~nce
and upgrades, modification of existing composite page
def initions, downloading of new composite pages and periodic
monitoring of system performance. The client system
administrator may use the remote interface to log onto the
system from home or any other remote location.
One adYantage of the present invention is that it is
sufficiently flexible to adapt for use as any of a stand- -
alone system in a small system environment having only A
digital data feed which the ~nco~er distributes to A
plurality of decoders, an ~n~cement to an existing system
CA 022~76~8 1999-01-12
WOg3~23~ PCT/US93/~ ~1
having a video ~wi~h~ng system and user interface hardware
such thAt the ~ncoAPr ~uL~ i8 connected to a ~ingle shared
input and rAr6~ to one or more ouL~Ls on the video switch
to the plurality of user6, a work station, and a large
system including, for example, separate mach;~eF for
providing value-Added calculations.
Description Of The DrAw~ngs
With the above and additional objects and advantages in
mind as will hereinafter ApreAr, the invention will be
described with reference to the accompanying drawing~, in
.which:
FIG. 1 is a block diagram of a ~ystem according to the
invention;
FIG. 2 is a diagram ~e~L esenting the transmitted first
data stream and the ~equence of second data streams in a
first embodiment of the invention;
FIG. 3A ~hows a diagram .e~ nting a characteri~tic
first data ~tream, and FIGS. 3B-3F show diagrams
representing characteristic seql~enceF in the r_~o~d data
streams, all in the first embodiment of the invention;
FIG. 4 shows a video screen having a sample market
information page thereon in which a block of data to be
updated is ~hown in cross-hatc~;
FIG. 5 shows a block diagram of an ~nco~r in the ~ystem
according to the first embodiment of the invention;
FIG. 6 shows a block diagram of a ~ecoA~r in the system
according to the first embodiment of the invention;
FIG. 7 is a diagram representing the transmitted video
~ignals in a Fç~on~ embodiment of the invention;
FIGS. 7A-7C illustrate the techn~que of transmitting and
displaying a plurality of television ~lo~.am information
signal~ along with update data;
FIG. 8A ~hows a diagram .e~-e~enting the transmitted
first data stream, and FIGS. 8B and 8C show diagrams
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-12-
~,~renting the ~¢-on~ transmitted data stream in the
~cQn~ embodiment of the invention;
FIG. 9 is a block diagram of an ~nco~r in the ~-~on~
embodiment of the invention;
S FIG. 10 is a block diagr_m of _ ~coA~r in the r~c
embodiment of the invention;
FIG. 11 is a block diagr_m of a system according to a
third embodiment of the present invention;
FIG. llA-llC illustr_tes the transmission of enable
~ec_~Lion messages, enable Le~ ion and initiAli~Ation
messages, initiAli~Ation messages, and dat_ enable sequences
~- to produce the displays illustrated in FIGS. 12A - 12C
illustrating symbolic signA1 ing;
FIG. llD is a flow chart for proces~ing messages using
symbolic signaling according to one embodiment of the
present invention;
FIG. 12 is an illustration of the format for a single
page of display inform_tion in accordance with the
invention;
FIGS. 12A-12C illustrate the displays proA~re~ through
the message sequences shown in FIGS. llA-llC, _8 described
above;
FIG. 13 is ,n illustr_tion of a composite p_ge h_ving a
plurality of tiles;
FIG. 13A-13C are illustrations of tile messaging for
updating different user defined tiles having common display
information;
FIGS. 14A and 14B are illustrations of composite pages of
display information;
FIG. 15 i8 an illustr_tion of gr_phic tile mess_ging with
graphic and alphamosaic cells;
FIG. 16 is a block diagram of DV bus si~nAling for the
embodiment of FIG. 11;
FIG. 17 is a di_gr_m of a DV bus message stream over two
3S sl~ccescive video signal time periods;
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-13-
FIG. 18 i6 a diagram of a guad level (8,9) modulated
signal for a DV bue mes~age;
FIG. 19 is a diagram of a h~a~r section of a digital
~e~sage using the guad level (8,9) modulation;
FIG. 20 iF a diagram of a double buffered error detection
and cG~e_tion interleaving teçhn;que;
FIG. 21 i_ a diagram of a p_cket mes~aging sequence
including packets of varying length;
FIG. 22 i8 a diagram illustrating packet fieldR;
FIG. 23 is a diagram illustrating message fields;
FIG. 24A-24G are diagrams of CG~ Ol bus messaging
- ~ignals;
FIG. 25 is a block schemAtic diagram of the enco~r of
FIG. 11;
FIG. 26 i~ a block diagram of a desk interface unit of an
alternate embodiment of the third embodiment of the present
invention.
FIG. 27 is a block schematic di_gram of the decoder of
FIG. 11;
FIG. 28 is a block schematic di_gram of the video ouL~uL
circuit of FIG. 27;
FIG. 29 is a block diagram of a modular residual video
converter device in accordance with a preferred embodiment
of the present invention; and
FIG. 30 is a block schematic diagram of the video
digitizer circuits of FIG. 29.
Descr~Dtion Of The Preferred Embodiment
As noted above, the object of the present invention is to
distribute information. Thi~ information is transmitted
over, for example, telephone lines and converted on the
client site into video eignals ~imilar to those for
television ~eoc~Lion. The information r~hscribed to takes
the form of pages or records of market data, various
portions of which are updated from time to time to reflect
. . .
. CA 022~76~8 1999-01-12
WO93~KX PCT/US93/04361
-nge5 in the market, and t~h-e~uently ~lesented on a video
screen.
In a first embodiment of the invention, the 8;~nA1S
representing the market information are being transmitted
S asynchronously, that is, there are no set characteristic
times (e.g., television field or frame rates) to restrict
the transmission. As ~hown in FIG. 1, one or more portions
of ~ource information 10 of market data are each given
individual information identification (IID) codes, for
example, ~JSN416~ and ~MDC2000~. These portions 10 are then
---applied by an ~ncoA~r-transmitter 12 to a digital video
transmission line 14. ~eco~er-receivers 16 are ~hown
co~nected to the transmission line 14 for receiving and
displaying the enco~A portions 10. As ~hown, each ~eco~r
receiver 16 has a unigue display identification (DID) code,
for example, 'PAMU0609~, ~BOBO1205~, ~LRN0122~ and
~TBD12??~.
FIG. 2 shows ~ diagram representing the digital video
signals transmitted over the digital video trAnsmission line
14. As shown in FIG. 2, a fir~t line 20 of the transmission
includes An encoded cignal flag indicating to the ~eco~r-
receivers 16 that the following information is encoAe~ data.
The exact form of the flag i6 unimportant since the
information contained is just one bit. The line or lines 22
contain enable reception messages. The lines 24 following
the enable reception message lines 22, contain the various
data updates 1, 2 and 3.
Enable ~e~ep~ion me~sages are used to provide information
identification (IID) codes or reception keys (RK) to
decoders. The terms ~information identification codes~ and
~e~e~Lion keys~ are used interchangeably. D~co~ers use
,e~e~Lion keys to identify the portions of information that
are to be displayed on ~pecifically identified video
~creens. FIG. 3A shows a ~e~e~entative enable ~e~e~Lion
(ER) message line 22 in detail. An ER synchronizing signal
32 is sent indicating the ensuing transmission of enable
CA 022~76~8 1999-01-12
W093~23958 PCT/USg3/~361
Lecc~Lion me6sages and enabling AecoA~r6 to synchronize to
the transmis~ion. The ER 6ync ~ignal 32 i6 followed by
di6pl~y identification code (DID) - reception key (RK) sets
34, each of which includes at least one of the unique DID
codes and at least one of the IID codes as a .e~e~Lion key
(RK) for which the video screen identified by the ~roA~r-
receiver DID is authorized to di~play. In the example
shown, the ~ets are the DID/RK pairs TBD12??/MDC2000,
BOBO1205/JSN416 and LRN0122/MDC2000 and indicate that the
video ~creen co~nected to the AecoA~r-receiver having the
DID code T8D12?? i6 authorized to di~play update data for
- the 60urce information ~GL~e~1~O~ ;ng to RK MDC2000, screen
DID BOBO1205, RK JSN416; and screen DID LRN0122, RK MDC2000.
It should be noted that in the example, the video ccreen for
the decoder-receiver having DID TBD12?? is not authorized to
display update data for the 60urce information corresponding
to RK8 JSN416 and MDC2000. The enable reception mess~ge
continl~e~ for as m~ny lines (each including an ER
6ynchronizing 6ignal 32) and includes as many sets 34 as ~re
required to associate each of the authorized video screens,
by their deroAer-receiver DIDs, with one of the (many)
~ubscribed-to y~O~S or portions of source information by
their information identification codes/RKs.
The process for updating each ouL~uL display is performed
by replacing ~tiles~ in the relevant ~ display. As
6hown in FIG. 4, the cross-hatched tile 36 to be updated is
located by two row and two column (or two x-y pixel pair)
coordinates. FIGS. 3B - 3F 6how 6amples of the data enable
sequences, in which, in FIG. 3B, the 6equence for the update
of information having the IID code MDC2000 is illugtrated.
- In particular, a data synchronizing 6ign~1 42 indicates the
ensuing transmi6sion of a data enable 6equence, and i6
followed by the IID code 44 for the source of information
having IID code MDC2000 and then the coordinateg 46 of the
tile 36 to be replaced which, in this example, is 4 rows by
40 columns. The actual data for this tile 36 is presented
.
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-16-
ln a ~eries of lines, c~ pQnA~g to the number of rows in
the tile to be updated, following the data enable ~equence
line. Note that the corresponAPnce i6 not one line to one
tile row and is expl~neA below. Similar exampleg are 6hown
S for the information having IID codes JSN416 and MDC2000 in
FIGS. 3C and 3D, in which in the information having IID code
JSN416, a tile of 1 row by 11 columns ig updated, and again
in MDC2000, a reconA tile of 6 rows by 40 columns ig
updated. Alternatively, as shown in FIG. 3E, the update
-data may appear on the same line as the data enable
seguence. In particular, the sync signal 42' ig followed by
the IID code 44. ~owever, the coordinates 46' include the
pixel start number and the pixel stop number of a single row
of the update data, along with the line number of the
particular line. The update data 48 then followg on the
same line. Each tile 36 ig then com,~~e~ of the update data
48 appe_ring in, for example, a plurality of conr~ tive
lines. Further, as shown in FIG. 3F, the update data may be
presented simultAneo~ly on one line for more than one page
at a time. In particular, the sync gignal 42~ ig followed
by two IID codes 44~, and then the coordinates 46 of the
tile 36 to be replaced, which in this example, is 5 rows by
80 columns, toward the bottom of the portions of information
-having IID codes JSN416 and MDC2000. Additionally, all
authorized displays conn~cted to the video transmission may
be simultaneo~cly updated at the same coordinates by using a
special ,ece~Lion key, e.g., R~ ~ 0.
An encoder for the first embodiment of the invention is
shown ~n FIG. 5. The enco~r includea a modem 50 for
receiving data from a source of market information. Thig
data may be in the form of entire pages or ~e~G~dg of
financial information where portions are updated, or the
update data itself along with information for the
positioning of the update data on the respective digplay
screen. The ouL~uL of modem 50 is ~on.e~Led to an interface
51, which is, in turn, conn~cted to the input of a
.
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microcomputer 52. The microcomputer 52 reas~igns the data
to a~lG~iate locations in new ouL~uL displays for client~
of the information vendor. A keyboard 53 is cc, ,r Led to
the microcomputer 52 for o~--L~olling the microcomputer. A
memory 54 i~ connq Led to the microcomputer 52 and ~upplies
thereto the configuration of the new ouL~uL di~plays, the
~eoeyLion key (RK) codes for each of the new portions of
display information, and the di~play identification (DID)
codec of the client's video screen~ authorized to receive
each of the new portions of information. Based on this
information, the microcomputer 52 generates the first data
: ~tream and the sequence of recQn~ dats streams.
The ouL~uL of the microcomputer 52 is applied through an
interface 5S, to a digital video generation unit 56 which
reconfigures the ouL~uL of the microcomputer into digital
video lines. The digital video generation unit 56 also
generates the encoded signal flag and inserts the various
~ynchronizing signals at the begi nni ng of each of the
digital video lines. A clock signal generator S7 is
connected to the digital video ye,.elation unit 56 and the
microcomputer 52 for applying timing signals thereto at the
line freguency. In the event that the update information
applied to the modem 50 i~ in the form of entire pages or
records, a memory 58 is co~nected to the microcomputer 52
into which the pages or records are entered enabling the
mic~o~omputer 52 to compare one page or ~eCG~d with the
update of the page or record to extract therefrom only the
update data.
FIG. 6 i~ a block diagram of a ~DcoAPr for use with the
~ncoAer of FIG. 5. The ~eco~Pr includes a receiver 60 for
< receiving the data transmitted by the digital video
generation unit 56. The ouL~uL of the receiver 60 i6
applied to an analog ~witch 61 for ~elective application to
a video screen in the event that ~tAn~d non-coded signals
are being received. A coded signal detector 62 is coupled
to the receiver 60 for receiving the encoded signal flag and
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for switc~ng the analog switch 61 accordingly. An ER
detection gate 63 is connected to the receiver 60 for
receiving the enable reception messages cont~;n;ng the
DID/RK code ~etC. Each of the received DID codes is
compared with a unigue di6play identification code 6tored in
a ROM 64 by a comparator 65. Upon each match of the DID
code, the individual RK code for the respective portion of
information i~ stored in a memory 66.
The ouLyuL of the receiver 60 is further .-GI-~.e~Led to a
,~data detection gate 67 for receiving the data enable
-,seg~nce6. The individual RK codes in the received data
enable ~egt)~nces are compared in a comparator 68 with the
individual RK codes stored in the memory 66. Upon a match
of one of these RK codes, the accompanying di~play
coordinates of the update data are loaded into registers 69.
An analog-to-digital converter 70 proces-er the ayy~G~iate
update data at the ouLyuL of the receiver 60 and applies its
ouLy~L to a write buffer 71, which also receives the ouL~L
of the registers 69. The GuLyuL of the write buffer 71 is
applied to a picture store memory 72 in which the section
therein CG~ .~srQn~ng to the location of the update data is
updated by using the display coordinates. A synchronizing
signal detector 73 is co~nected to the ~uLyuL of the
,receiver 60 for separating the mess_ge ~ynchronizing
~ignals. The ouLy~L of the ~ynchronizing ~ign_l detector 73
is _pplied to a timing _nd oG..L~ol ~ignal generator 74 for
generating timing signals for the analog-to-digital
~GI~ve~ Ler 70, the data detection gate 67, the ER detection
gate 63 and the picture store 72. The o~Ly~L of the picture
~tore 72 i8 applied to a digital-to-analog converter 75
oo.,L~olled by the timing _nd ~G,.L.ol signal generator 74.
The ouLyuL of the digital-to-Analog ~Gl~ve~ Ler 75 is applied
through a low-pass filter 76 to another input of the Analog
switch 61.
In a re~o,~l embodiment of the invention, the video
signals representing the market information includes color
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--19--
information. In addition, stan~rd televi~ion ~Gy~m
information signals are included in the digital video
signals for ~elective viewing of realtime television
~L Gy~ ~ms on the video 8~eo~O- Thi6 transmission i6
nec~eE-rily synchronous to the chosen television stAnA~rd.
When the digital video signals are being transmitted by
ro~Y~Al cable, the usable bandwidth is in ~YcqnF of 24 MHz.
FIG. 7 shows a pictorial ~e~.e~entation of the
transmitted video signals. The encoA~A signal flag line 80,
the enable ~e_c~Lion messages lines 81 and the data enable
~equence lines 82 are transmitted during the vertical
blanking interval 83 between each field of the video signal.
During the active video portion of the field, in a first
half of each scanning line, the television R, G and B
signals 84, each originally having a bandwidth of 4 MHz and
each time compressed by a factor of six to an e~ran~e~
bandwidth of 24 MHz, are sequentially transmitted. In the
--~onA half of each ~c~nning line, the update data for
individual pages of the m~rket information are transmitted.
While the television p~Gy.am information signals 84 are in
color, the update information may be monochromatic, color or
a mixture of both. In particular, as shown, the first 8
half-lines contain the monochrome update data 85 for the
left half and right halves, respectively, corresron~ing to
RK code MDC2000. The update date 85 is followed by the
update data 86 corresponding to RK code JSN416. The update
data 86 is presented in color as the three color signals R,
G and B. The remainder of the right half of the first field
is shown as being unused in this example. The left half of
the ~?conA field contains the G, B and R comron~nts of the
- television ~.oy,am information signals 78'. The right half
of the FeconA field contains the monochromatic update data
corresponA;n~ to RK codes 208, 1234, 5, 19154 and 264.
FIGS. 7A - 7C illustrate the techn1que of transmitting
and displaying more than one television p-Gy~hm information
signal at a time along with update data for ou~ displays
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on a plurality of video 6~.~.3. ~r~c~ficAlly~ FIG. 7A
illu~trates the transmi~ion of four fields of digital video
~ignal~ ~G~ ponA;nq to two television video frames. A
vertical bl~nkinq interval 83, ~v~ .o~ ng to the vertical
bl~n~;ng interval 83 of FIG. 7, is shown. Nine different
sGu~e~ of information are 6hown as being transmitted in the
fields, namely television ~,Gy,~m information ~i~n~l~ TVl-
TV3 and ~ix tiles numbered TILE l to TILE 6 having
col,e_lo,.A;ng update data to particular portions of
financial market information. The transmis~ion of a field
stru~u~ed in this manner is done at the television r~Ann;ng
rate, as mentioned above.
The television ~lGy,am information ~ignals TVl-TV3 are
hown as being time compressed in a well known manner. The
TVl signals are shown as being tran~mitted during a portion
of every horizontal digital video line. Television ~-Gy,am
information signals TV2 and TV3 are shown as being
transmitted only during certain horizontal digital lines,
namely from line W to line X, in the case of TV2, and from
line Y to line Z, in the case of TV3. The television
program information signals TVl-TV3 are chown as pluralities
of lines having alternating odd line (TV~D) and even line
(TVrn~) fields in ~ ceFFive video fields. The television
program information signals are illustrated in FIG. 7A in
the RGB format, i.e., three primary color signals, but also
may be transmitted as one lumi~Ance and two color difference
signals, e.g., Y,U,V. Further, the television ~GyLam
information signals may be digitized and compressed, e.g.,
using the JPEG or MPEG stAn~rds or some other technique.
Also, the update data to ouL~uL display tiles TILE l -
TILE 6 are transmitted in various lines at times when the
television ~Gy,~m information signal~ are not being
transmitted. -
The update data for an ou~uL display tile may appear
anywhere in the video screen ~nd may start and stop at any
point or in any line of the digital video field, provided
.
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that the update data doe~ not occur simult~n~ ly with the
television ~GyLam information 6ignals. Thus, update data
r may occur during the vertical blAn~in~ interval 83 as shown
in the third digital video 6ignal field for update data to
TILE 3. Update data also may be a lengthy stream of data
that fills those portions of sucç~66ive lines that are not
filled by television p~Gy~am information signal6 as
illustrated in the fourth digital video ~ignal field with
respect to the update to TILE 2 and signal6 TVl and TY2.
Further, update data may be a relatively short stream of
data starting at the beginning of a line time, or in the
:middle of a line time, see, e.g., updates to TILE 6 and TILE
2 and TILE 1 in the fourth field.
In addition, there may be no update data for fin~nci~
market information as in the first digital video signal
field cont~inin~ television ~Gy.am information signal6
TV1ODD~ TV2ODD~ TV3~, although there will be some digital
data (not shown in the first field) that is transmitted, as
described below.
The re~ulting di6plays that are po~sible with this
transmission structure are illustrated in FIGS. 7B and 7C
and 13. FIG. 7B illustrates the display of the television
~Gyram information signal6 TVl and which, due to the
transmission of such signal6 during each digital video scan
line, produce full screen television display6. FIG. 7C, on
the other hand, illustrates the display of both TV2 and TV3
~ignals which, by virtue of their transmi~sion within the
stated intervals, are displayed within specific vertical
ho~ ries within the video screen. Specifically, the TV2
display must be located between horizontal lines W and X in
any horizontal location (with the proviso that it not
interfere with ou~uL display data) and TV3 must be
- displayed between horizontal lines Y and Z, in any
horizontal location (with the same proviso). The ou~
display ~G.. e,~o.linq to one of the 60urce information in
tiles TILE 1 - TILE 6 that the particular video screen is
. .
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enabled to receive can be displayed above, below or
alongside the TV2 and TV3 signals (only TILE 1 - TILE 3 are
illustrated).
Due to the complex ordering of the update data in the
first and reconA fields, the data enable se~ences in the
lines 82 must n~ce~6~rily be more complex than tho~e shown
in FIGS. 3B - 3F. In addition, the enable reception
messages also must indicate which of the video screens is
authorized to receive the televieion ~L O~L ~m information
eignals sent with the update data. In particular, ae shown
in FIG. 8A, the enable ,ece~ion messages are ~imilar to
- those shown in FIG. 3A, with the exception that in addition
to the DID/RK code sets, the meseages include a set 87
indicating which of the video screens, for example, the
screen with DID code 297, is authorized to receive which
television ~GyL~m information signals, for example, the
television ~LGy~am information ~ignal having an IID code
TV1, which also may be used as a ~e_a~ion key (RK) if
distribution is to be enabled. FIG. 8B ehows a sample data
enable seguence which includes, in addition to that
described with respect to FIGS. 3B - 3F, the coordinates of
the update data in the source field. FIG. 8C shows a sample
of the data enable sequence for identifying the television
-~.o~am information signals, and includes a data
synchronizing signal 88, a television RK code 89 and the
starting coordinates 90 of the color signals, red, green and
blue, or Y,U,V.
FIG. 9 shows a block diagram of an encoAPr for the second
embodiment. The digital video generation unit 56' has a
second set of inputs for receiving the three components of
the color television ~GyLam information signal, Y,CD1,CD2.
In particular, a source of television ~G~-am information
signal is connected to a _ynchronizing signal separation
circuit 91 for detecting the vertical and horizont~l
synchronizing signals in the video signals. The source of
the video signals is also connected to a matrix circuit 92
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for providing the three component~. Each of the~e
componentC i8 ~ubjected to compre~sion in compre~ion
circuit 93 and the three components are then applied to the
digital video generation unit 56'. The clock and sync
~ignal generator 57' applies ~ynchronizing signal~ to both
the digital video generation unit 56' and the microcomputer
52', and receives the ~ynchronizing signalg from the
separation circuit 91 for synchronization therewith.
FIG. 10 ghows a block diagram of a A~cQA~r for the fieconA
embodiment. Component~ the ~ame ae tho~e in FIG. 6 are
designated with the ~ame reference number. The APcoAPr is
substantially similar as the AecoA~r of the first embodiment
with the exception that the decoA~r is now capable of
~o~csging color ~ignal~ and the encoAeA data celectively
includes television ~G~.am information signal~. In
particular, a color AecoAer 101 is included between the
output of the receiver 60 and the input of the analog switch
61.1 - 61.3. The register 69' includes a regi~ter element
for storing the number of the picture store. The
cynchronizing signal detector 73' ~uL~u~g field
synchronizing signals in addition to line synchronizing
signals. The write buffer 71 now ~cces-e~ three picture
stores 72.1 - 72.3 corrc~l-o"li~g to the three color
components, red, blue and green. The o~uLs of these
picture stores 72.1 - 72.3 are applied to three digital-to-
analog converters 75.1 - 75.3, and then to three low pass
filters 76.1 - 76.3 for application to the other inputs of
the three analog switches 61.1 - 61.3.
Referring to FIGS. 11 to 29, a third embodiment of the
~lc_ent invention is shown, which reflects a number of
im~.ovcments to the f ir~t and 8eCG~-d embodiments described
~bove. One sygtem in Accordance with the third embodiment
includes an encoA~r 312, a digital-video (DV) bus 314, a
plurality of decoA~rg 316, a plurality of video ~creens 317,
a ~o.. L~ol bus 318, a keyboard 319, optionally a ~ouse 319',
and a gupply (or source) of display information 310 which
.
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may include realtime television pLG~Lam information signal6,
and analog and digital video ~ignals .~ e-çnting financial
market information. The DV bus 314 is preferably a rhAnnel
r~pAhle of transmitting digital and video information. This
permits the use of stAn~rd co~Yi~l cables or video cwitches
as the DV bus 314.
As illustrated in FIG. 11, each ~ecoA~r 316 has an
associated video 6creen 317, preferably constructed as an
- integral unit in a common enclosure. Alternately, as shown
in FIG. 26, each ~ecoA~r 316 may be part of a desk interface
-unit (DIU) 321, which ~u~GL~s a plurality of video 6creens
- 317, e.g., four, and a plurality of users and their
~e_~e~ive keyboards 319 and mice 319'. Each user may have
- one or more video ~creens 317 arranged in a work ~pace,
e.g., on a desk top 320. Each video ~creen may have a
unique DID. Alternately, each user or desk top 320 may have
a unique DID such that restricted di~play information may be
di~played on any video ~creen of the enabled user or
desktop.
One aspect of the ~L~-ent invention concerns improvements
in the structure of the signals (also referred to as ~DV bus
signals~ which are concatenated to form ~DV bus messages~)
and their messaging along the DV bus 314 between the encoder
312 and the plurality of decoders 316, and their di~play on
a video screen 317.
FIG. 12 illustrates the image produced on each video
screen 317, which is a composite page 200 of fi~CiAl
market information and/or television plGy~m information
signals, as described below. Each composite page is
organized as a plurality of cells 210. Each cell is
organized as a plurality of pixels 220. Every cell 210 has
an assigned location within composite page 200, by row R and
column C, relative to an origin and cannot be arbitrarily
placed. The origin may be selected to be in the upper left
3S corner or elsewhere. Similarly, every pixel 220 has an
assigned location within each cell 210, by row r and column
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c, relative to a cell origin and cannot be arbitrarily
placed. In accordance with the present invention, and as
explained below, messages transmitted along DV bus 314 are
either directly or indirectly addressed to cells.
In a preferred embodiment, each composite page 200 is
com~:-e~ of 30 rows and 100 columns of uniform and fixed-
size rectangular cells 210, ae shown in part in FIG. 12.
The coordinates of the cell 210 in the upper left corner of
the page 200 are (RO,C0). The cell 210 in the lower right
corner of the page 200 is at (R29,C99). Each fixed-size
cell 210 ha~ 128 pixels 220 organized into 8 columns by 16
rows. This represents a di6play ~creen 317 that is larger
than the size of st~nAArd pages or ~e~o~ds of financial
market information provided by commercial information
vendor~, and the size video screens provided by tho~e
vendors with their systems. Such stA~AArd pages and display
screens have 18 or 25 rows by 80 columns or 12 rows by 64
columns. Advantageously, the larger display screen permits
the user to create composite pages 200 containing more
financial market information than previously possible with
the prior systems, and further permits displaying television
~GYLam information signals and/or value added information
without ~acrificing the financial market information.
Each pixel 220 within a cell 210 may h~ve up to 256
different colors, selected from a larger palette of
16,777,216 colors. The number of colors that may be
displayed on any given video screen 317 dep~nAe on the
amount of memory of the A~ooAer 316 operatively ~o~u-e_~ed to
the video screen. For example, if a APcoA~r has been loaded
with one byte per pixel of screen store memory, or
approximately (800x480 - 384,000 pixels) 376 Kbytes of
memory, it can display 256 colorc per pixel. For another
example, if a decoAPr, which ha~ lower cost and
functionality, has been loaded with only two bits per pixel
of screen store memory, or approximately 96 Kbytes of
memory, it can only display 4 colors per pixel.
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Reducing the number of colors to be signaled al80 re~r~s
the length of the messages needed to create or "paint" a
composite page 200. For example, when four color~ are being
used, only the first two ~ignificant bits of a color byte
need be transmitted. Even when 256-color ~coA~rs are used,
clever selection of the color definitions can reduce the
amount of messages necefifiAry to transmit information
concerning a ~mall tile on the page. For example, a rirst
tile may have colors o, 1, 2, and 3 while a reconA tile may
-~-have colors 16, 17, 18, and 19. Changing the colors in the
-second tile only requires the transmission of two bits of
information per pixel.
In this third embodiment al80, DV bus messages are
transmitted as tiles. As already noted, a tile is a
rectangular region that will appear on the video screen 317
and is illustrated here by the bold black rectangle 250 on
the right side of composite p~ge 200 in FIG. 12. It may
contain any number of horizontally and vertically contiguous
cells 210. Preferably, each tile is defined by the location
of its first cell, i.e., the coordinates (row R and column
C), in its upper left corner and either its size (i.e.,
number of rows and columns of cells in the tile) or the
coordinates of the cell in it~ lower right corner.
Thi~ third embodiment of the invention preferably employs
2S two concepts of tile messaging to reduce further the amount
of overall data that is required to be transmitted. The
first ~o"ce~ is called cell wrapping. This provides for
renAing one large single continuous message to a tile for
one cell 210 after another (either horizontally or
vertically aligned) within a tile having determined
boundaries 80 that the first cell to cross the tile boundary
in the direction of continuity automatically ~wraps back~
within the tile to the begi nn~ ~g of the next row or column
80 that each cell is successively filled. The tile
ho~nAAries are preferably incG,~G~ated into the tile display
boundary coordinates provided to the decoder for the update
. -- . . .
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data. This avoids having to monitor when the next cell 210
will be out6ide of a ho~nA -ry of the tile and ,~-en~ either
a new message or next row or next column indicator. The
decision to use horizontally aligned messages or vertically
aligned ~essages may be based on the aspect ratio of the
tile ho-lnA~y 60 a~ to minimize the number of wrapping
eventC and maximize painting ~peed. When combined with run
length ~ncoA~ng of me~sage~, described below, cell wrapping
greatly im~.oves messaging efficiency.
The ~eron~ concept i8 the use of implied motion where
portions of fin~nciA~ market information contain regions
-that must be moved, either vertically (scrolled) or
horizontally (pAn~e~). For example, cG..ve..Lional financial
instrument tickers are usually panned horizontally across a
video screen, while news headlines are sometimes ~crolled
vertically. This movement can be accompli~hed by either
retransmitting all of the reguired information such that the
relative location of each column (pAn~ng) or row
(scrolling) is ad~usted for each incremental move, or in
accordance with a preferred embodiment, by transmitting only
the new information and ~implying~ the desired motion by the
prior definition of a p~nning or scrolling tile type.
Implied motion within a tile greatly im~o~es the messaging
efficiency.
Referring to FIGS. 12, and 13, the video screen 317 may
be referred to as the underlying tile 350. One top of the
underlying tile 350, one or more of the following types of
tile~, referred to as tile 250 with a letter su~fix, can be
displayea as illustrated in FIG. 13.
A graphic tile 250-G may be defined to display
information on a pixel by pixel basi~. It is used to
display graphs, charts, Fc~nr-~ images, e.g., still
- pi~u~es, value-added presentations of historical data, and
~imilar non-alph~ntlmeric character display information.
An alphamosaic tile 250-A i5 a tile entirely defined by
an extended set of ASCII characters or the eguivalent (i.e.,
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AlF~ m-eric characters). It i8 used to display normal
AlphA~t-meric character text plus any predefined extenAeA
ASCII characters. Each pixel ~ lly may have up to 256
colors. In FIG. 13, the alphamosaic tile 250-A i8
illustrated as displaying information ~G.. cr,.. ing U.S.
Government ~ecurities that are periodically updated.
Alph~nt~meric tiles 250-A are static unless they are further
defined for relative movement.
A pAnn~ng tile 250-P is an alphamosaic tile that i6
-~G,--lolled to create horizontal motion, left or right. In
~FIG. 13, pAnn~ ng tile 250-P is illustrated as the (NYSE)
- Ticker which i8 being p~nneA right to left. The character
string update ~NYSE~ has been received at the entry (partial
~5~ character) and is being automatically pAnn~ (partial
~E~ character) under the cGI.L.ol of A~coAer 316 using
implied movement. The panning effect may be a cell by a
cell advance or a pixel by pixel advance, the latter
providing a smoother image transition and presentation of
partial ch_racters.
A ccrolling tile 250-S is an alphamosaic tile that is
controlled to create vertical motion, up or down. In FIG.
13, the scrolling tile 250-S is illustrated as the
~Financial News~ and i8 being scrolled upwardly. The entire
lower row of characters has been received at the entry and
is being utomatically scrolled (partial top and bottom
rows) under the conL~ol of APcoAPr 316 using implied motion.
The scrolling may be a cell by cell advance or pixel by
pixel advance, the latter providing a smoother image
transition and ~ entation of partial characters.
A video tile 250-V is used to display a realtime
television ~.oyLam information signal. Each pixel within
the video tile may take on any color ~ G~ ~ed by the
relative television transmission stA~A~rd and the picture
store memory size of the given decoder 316. In an
embodiment wherein the A~coAPr 316 includes a picture store
memory, different TV signals may be selected for display
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within a video tile 250-V so long _s they are being
transmitted within the same vertical format. If, however, a
picture frame memory is used, which can ~tore an entire
frame of television ~Gy,am information signal~, then the
S video tile 250-V need not be limited to the same vertical
format and may be located anywhere on underlying tile 350.
The size and display location of each tile 2S0 on
underlying tile 350 is preferably initi~lly estab~ A
using a tile default ~ize and position. Each tile 250 may
be locally resized and repositioned by each user. Thus, for
example, by using a mou~e 319 or keyboard 319', e_ch user
: may redefine any tile 250 by (1) overlaying any one tile
over any other tile and overwriting the display information
of the other tile(s), (2) changing the fo~e~,o~.d/background
attributec among the di~played tiles, (3) moving a tile to
any new displ_y location on the video screen (except for
real time television video tiles 250-V, which may only be
moved horizontally in the absence of a picture frame
memory), and (4) changing its size either to display more or
less display information or to di~play the same information
in larger or smaller size.
In accord~nce with the third embodiment of the present
invention, tile messaging embodies the following five
principles:
1. Each tile 250 is uniquely named, i.e., it has a
unique IID code that is used as a ~ec~Lion key, and is
assigned ~ystem default display location and ~ize, typically
as an offset referenced to the origin cell (e.g., (RO,C0))
on the underlying tile 350 or to the origin cell of a tile
250 within the underlying tile 350. Thus, a tile 250 may be
- nested within other tiles 250 on an underlying tile 350,
such that relative offset of each tile in the chain to its
- anteceA~nt associated tile is respected and maint~in~ by
the d~roA~.
2. Tiles 250 may be locally resized and repositioned
from their system default conditions locations by individual
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user~ and may be given an offset refe~c,.~c-l to ~n origin
cell on the underlying tile, or to an origin cell of any
other tile. The remapping of the tile default location and
size to the user-defined tile location and size O~L ~ in
each user'g ~eco~Pr. DV bus messageg to update the u~er-
defined tile are transmitted with the default display
coordin_tes (unless the ~ymbolic siqnA~ng technique
de~cribed below is used) and the default tile message is
mapped onto the user-defined tile within the picture store
memory of the ~eco~Pr. If a~.v~i_te, the user's
-definition of the tile will provide display coordinates for
selecting a~L O~L iate cells selected by the user and
disregarding other cells in the DV bus message of the
default tile, so that only the display information in the
user defined tile is ~tored and displayed. Thus, the user's
redefinition of the tile has no effect on the DV bus
messages and only the user selected information is displayed
and updated.
3. It is often more efficient to retransmit the whole
tile using cell wrapping rather th_n transmitting just the
updates. This is because computational efficiency is
obtAinPA by filling in time lengths of DV bus signals with
useful data rather than blanks. This ig not usually true
-for retransmitting the whole page of financial market
information.
4. Related page or record updates often occur in burgts
and are usually received from the information vendor one row
of financial market information immediately after the other.
It is far more efficient to store all of these received
multiple contiguous-column row updates to a tile within A
portion of financial market information for a very small
time (perhaps l/20th of a recon~) before transmitting them
as a ~ingle group within a single tile on the DV Bus 314 to
all of the decoders 316. This technique avoids
retransmitting the same tile each time one row of the tile
is updated, and retransmitting each update data, but not the
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complete tile, with the a~Lv~iate b~ r ~nd off6et
di6play coordinates, e.g., 6tarting ~nd enAi~g row and
column to di6play the update in the relevant di6play
location of the video 6creen. Similarly, with reference to
FIGS. 13A-13C where two u~er6 have defined tile6 that
include ~ome common portions of the 6ame page or record of
fin~nciAl m_rket information, e.g., tile SA and tile SB, the
update data for the underlying page or .eCOLd of finAncial
market information may be tran6mitted in one of three
format6. The fir6t format is to create two ~eparate tiles
SA and SB and transmit update data for those tiles a6
necessary with a duplication of me~6age6. The recQnA and
more useful ~chnigue i6 to decompose the overlapping tiles
SA and SB into three tiles SAl which i~ unigue to user A,
SB1 which i6 unigue to user B, and SAB which i6 common to
user6 A and B. Then updates for the three tiles are
separately provided as a~LG~iate. A third technl~ue is to
cre~te a ~supertile~ S which includes all of the financial
market information. In thi6 latter embodiment, user A is
enabled to receive 6upertile S with di6play coordinate
information for retrieving only those portions of
information 6elected by user A, and u6er B is 6imilarly
enabled to receive supertile S with display coordinate
information for retrieving only those portions selected by
user B. Thus, the update message i6 only sent once,
yielding im~loved DV bus ~essaging efficiency.
5. Both contiguous-column row messaging and
contiguous-row column messaging should be ~ o~Led within
tile messaging for efficient updating of tiles.
The application of tile mes6aging greatly reAl~ceC the
~ amount of message traffic on the DV bus 314. One example is
expl A i ~e~ with reference to FIGS. 14A and 14B, which
- respectively illustrate composite page 200a having tiles Tl,
T2, T3 and T~ and composite page 200b having tiles T~, T5, T3
and T~, such that tiles T~ and T~' are different user-
-- . .
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defined tiles based on the same original portion of
f~nanc~Al market information T~*.
Firgt, it i8 noted that in prior art ~ystems, all vendors
of video f~nAnciAl market information typically use
contiguous-column row oriented messaging; all ~creen changes
are signaled by multiple individual mes6Ages, each mesgage
~on e".ing only contiguously located columng in one row of
the page or record. A gtAn~Ard page from one commercial
vendor may be ~ho~ht of as one large 6tatic alphamogaic
*ile 250-A that ig 80 columns wide and 18 rows high. When
the page i8 transmitted to the client gite for the firgt
time in recpQn~e to a page reguest by a user, it may be sent
using eighteen messages, one for each display row. Each
meggage will include a header identifying the p_ge or record
number of the gource finAnc~Al market information, the row
number, and the starting column number of the following
message, and up to 80 columns of character data. Each
message co~leD~G.,ds to a single row and ig about 100
characterg (one byte per character) in length. Thug, for an
18 row digplay, the total page requires 1800 characters to
be transmitted over the telephone line. At 180 characters
per ~econ~, it takes about ten secQndc to ~paint~ the screen
for the first time.
: When an information change O~ D~ the information vendor
updates the page by ren~ing only the new information. When
one character chAnges, for example, a gingle mess~ge is sent
having ~G..Llol information (in brackets) and the new data as
follows:
[{PAGE NO}{ROW}{STARTING CQT~ }] DATA
t{P16251}{R0}{C13}]1.
Thug, most update megsages only represent one or two new
dat~ characters to be displayed on the video ~creen to be
displayed on the video gcreen accompanied by about ten
information ~Gl.Llol ~characters~ for placing the data
characters in the proper display locations. Further, when
one fundamental data element changes it often causes a
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flurry of very ~mall individual mes~age~ to update other
row~ or columns.
With the foregoing in mind, and referring to FIGS. 14A
and 14B, if the original portion T~* is defined as an
alphamosaic tile 250-A, then, without tile me~saging and
according to the prior art, receiving a new hP~line would
require transmitting a total of nineteen messages (about
1900 characters); seven me66ages to compo~ite page 200a and
twelve mes~ages to composite page 200b. Seven of the
messages transmitted to composite page 200B would be
identical to those transmitted to composite 200a except that
- the row display location would be different to reflect the
fact that the hP~l in_ information is displayed higher on
composite page 200b than on composite page 200a.
lS Usueve~ with tile messaging, receiving a new headline
would require transmitting a total of one message (under one
thousand characters). Both composite pages 200a and 200b
would receive the ~ame tile mes~age, e.g., T~', and u~e cell
wrapping and the user-defined tile locAtion offsets and
display coordinate~ to display properly the information on
the ~e_~ective composite pages 200a and 200b.
If the original portion T~* was defined as a 6crolling
alphamosaic tile 250-S, then using tile messaging would have
resulted in both composite pages 200a and 200b being
properly led.awn by only one DV bus message of less than one
hundred characters. This ~e~.E-snt~ a nineteen times
reduction in DV bus message traffic for this simple case.
The im~ovement is even more prono!,.ee~l when more tiles and
composite pages are involved.
The third embodiment of the invention preferably employs
~ tile messaging of update data using a 8ymbolic sign~l;ng
terhn~que, which will now be described with refe~e,_e to
. FIGS. llA, llB, llC, llD, 12A, 12B, and 12C. FIG. llA
illustrates a transmission terhn;que ~imilar to that
~i-c~l~ced above with reference to FIGS. 3A - 3E. However,
for the p~ -?S of clarity, no 6ynchronization signals are
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shown, and only a single row and single column transmis~ion
are shown. The tile row and column starting and ~n~ng
locations will be transmitted in the manner described
e~ },ere.
S FIGS. llA-llC and 12A-12C illustrates message types for
alternative ~echniques of customizing and displaying
composite pages 200 of display informAtion and updating the
display information for particular user~. With specific
refe~e..~e to a FIG. llA, one techn~ue uses an enable
e-~e~Lion message 100 and data enable seq~Pnc~ 102, 103 and
104 at time tl and data enable seq~l~nces 112, 113 and 114 at
: time t2. The enable ~e~e~ion message 100 is shown as being
comprised of display identification (DID) code 120 -
reception key (RK) code 106 pairs, in this case, three code
pairs DID1/RK1, DID2/RK2 and DID3/RK3. The reception key
106 is used to authorize the decoder to retrieve update data
for a portion of financial market information having an IID
code that is the same as the lecc~Lion key. Thus, a decoder
video screen 317 having the DID 120 of IDl i8 authorized to
receive information for reception key 106a RK1, the decoder
video screen 317b with DID 120b of ID2 is authorized to
displAy financial market information for ~e_c~ion key 106b
of RK2, and 80 on. It should be understood that, altho~gh
the RK's 106 and DID's 120 are illustrated as alphanumeric
characters RKn and IDn (n being an integer) in practice it
is preferred that they be multibit, e.g., 21 or 24 bits,
code words that encrypt the actual ~ource of finAnciAl
market information. This is 60 that an unauthorized user
cannot identify and retrieve a certain financial market
information by tapping into the DV bus.
Following the enable .e_e~ion message 100, at time t
three separate data enable sequences 102-104 are
illustrated, each of which is comprised of a ~e_e~Lion key
106, row and column display location information 108,
followed by data 110. Although the data 110 i8 ~hown as
directly following the reception key 106 and row and column
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information 108, it can be tran~mitted on a ~eparate line,
immediately following the data enabling ~equence.
For the yu~ er of thi~ example, the information
displayed on the ~e~ye~Live portions of financial market
information having IID codes RK1-RK3 can be different, but
each contains at lea6t one common information field of data
110, which is represented by ~DATAl~ relating to a 30-year
U.S. Treasury bond. By transmitting the information field
data 110 with the foregoing data enable se~encefi 102, 103
and 104 for the three reception keys 106, namely RKs 106a-
106b of RK1-RK3, the three different video ~creens 317a,
317b and 317c, having correspon~ng DIDs 120a-120c of DIDl-
DID3, can display the ~ame information field 110 in
different locations as illustrated by boxes llla, lllb and
lllc in FIGS. 12A-12C respectively, using display
coordinates 108a-108c.
For example, the data enable sequence 102 places the data
110 in the upper left hand corner ~eyL~ ~nted by display
coordinates 108a (ROWl,COL1) of video ~creen 317a (box llla)
having the DID 12Oa of DID1, which was enabled with
~eceyLion key 106a of RRl. In a similar manner, seguence
103 places the information field 110 near the center of
video screen 317b (box lllb) having the DID 120b DID2,
represented by the di~play coordinates 108b (ROW10,CO~40),
which was enabled with ~e~Fy~ion key 120b of RK2. Sequence
104 places the information field data 110 toward the lower
right hand corner of video screen 317c (box lllc) having the
DID 120c of DID3, .e~,esented by the display coordinates
108c (ROW3,COL3) which was en~bled with the ~e-eyLion key
106c of RK3.
Thus, the information field data 110 is transmitted by
three geparate tile messages 102, 103 and 104 at a time t1
- ~uch that each tile has ~ different offset relative to the
upper left corner of the underlying ti~e 350. In order to
3~ customize the information displayed on various di~plays,
separate tiles must be transmitted to each video display
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317. When it is nc~ ry to update the f~nAnc~Al market
informAtion for information field data 110 during time
interval t2, again three tiles, e.g., illu~trated as data
enable ~eg~ence~ 112-114, must be tran~mitted, each having
the a~o~.iate ~e~e~ion key 106, row and column 108, and
the new financial market information for inform_tion field
data 110, e.g., DATA2, as chown in FIG. llA.
The application of symbolic ~i~n~l~ng is based on the
reAl~zAtion that the trader~ of financial instruments prefer
to select the financial market information they uce to
formulate their trades, and that 60me of that financial
m_rket information will be the Fame as that used by other
traders, and ~ome information will be different. It also is
based on the realization thAt the traders do not necesc~rily
want to view all of the information provided by a commercial
information vendor and prefer to customize their video
~creens to ~atisfy their desires.
Accordingly, the customization of the information
displayed on multiple AecoAer video screens is greatly
facilitated, and at the game time, the overhead reguired to
update information commonly used is greatly reduced,
according to the present invention, in the following
manner6. Referring to FIG. llB, one aspect of the present
~ invention provides for using enable reception and
initialization messages 116-118 and data enable seguences
128 at time t~ and 134 at time t2. Each enable reception
and initialization message 116-118 re~pectively includes a
DID code 120 for a video ~creen, an IID code which, in this
instance, is used as a seconA~ry ~e_e~-ion key (SRK) 122, in
this case ~LONGBOND~, and di~play coordinate information
108, e.g., row R and column C. ~he display coordinate
information 108 row R and column C will place the data 110
associated with the ~eConA~ry ~e_e~ion key 122 in the
designated displ~y location only for the video screen
identified in the DID/SRK set. The term ~eoonA~ry
reception key~ is a reception key that is associated with
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another ,c_eyLion key such that a AecoAPr mu~t be enabled
with the other first or primary .e_e~ion key before it can
be enabled by a reoon~ry reception key. The other
~e~e~Lion key al60 may be a ~ecQnA~ry ~e_eytion key
A~roc;ated with yet another fir6t or primAry ,eceyLion key
as expl A; neA below.
Thus, each enable .e_eyLion and init~ zation message
both enables a video screen to receive and display certain
data and init~ A li7e~ the relative display location of thAt
data on t_at video screen, even thongh no data has been
6ent. Importantly, this permits each u~er to select the
-display location on the user's video screen to display the
data cG~le~l,o.,lling to the secon~ry reception key SRK
inAep~n~ntly of the other ucers 80 that only the particul~r
seconA~ry .e_epLion key and the cG~,e_lo.. iing data need be
sent to effect the cG~le~L display. Again, the use of
~ON~O~u a~ an IID code and an SRR is for illustrative
~L~o~es and in practice an encrypted multibit bit code word
would be used as the SRK.
Thus, using enable reception and initiAli~Ation messages
116-118, video screen 317a having the DID 120a of DIDl is
enabled in this example, e.g., at the beginning of the day,
with SRK 122 LONGBOND and will display the subseguently
transmitted data 110 information starting at display
coordinates 108a (ROWl,COLl). Similarly, video screen 317b
having the DID 120b of DID2 is enabled with the SRK 122
LONGBOND and to receive and display the data 110 information
at its selected display coordinates 108b (ROW10,COL10).
~ideo screen 317c having the DID 120c of DID3 will likewise
place the data 110 information at its selected display
-. coordinates 108c (ROW20,COL60). Then, at time tl a 6ingle
tile data message 128 is transmitted compri~ing the SRK 122
-. LONGBO~D and the financial market information data 110,
shown as DATAl. Upon receiving the tile data message 128,
~ecoAer video screen 317a will reco~n~e the SRK 122
LONGBOND as match;ng its previously enabled SRK 122 and
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place the data 110 DATA1 in the designated location
according to the previously ini~;Al;7ed display coordinates
108a, i.e., the upper left h_nd corner (ROWl,COL1) box llla
as shown in FIG. 12A; video screen 317b will likewi~e
display the datA 110 DATA1 of message 128 in its center
(ROW10,COL40) box lllb, and video screen 317c will similarly
display the data 110 DATA1 of mecsage 128 in its lower right
hand corner (ROW20,COL60) box lllc. When it is .s:eF~ry to
update the financial market information at time t2, a single
tile data message 134, is transmitted, comprising the SRK
122 LONGBOND and the data 110 DATA2 to update the video
:screen. This data 110 is then displayed in the ~Lv~er
location of each video screen 317, in the same manner, to
update the display.
Referring now to FIG. llC, another aspect of the
invention conc~ns using three types of messAges to display
and update information, enable ~e~e~ion messages 100,
initialization messages 136, 137 and 138, and data enable
se~enceF 128 and 134. The enable ~eca~Lion messages 100
are used in the same manner and for the same purpose as
described above in conn~ction with FIG. llA. Then, once a
decoder is enabled with a reception key 106, the enabled
~eco~Pr is initialized with a ~?condAry reception key SRK
122 for that enabled ~_e~ion key 106, and display
coordinates 108 for displaying the subsequently transmitted
dat~ 110 in the selected display location 111 on a video
screen 317. Thus, each initialization message 136, 137 and
138 includes a first IID code correspon~ing to a previously
received reception key 106, a second IID code which is used
as a ~econ~ry reception key (SRK) 122 (in this case
LONGBOND), and display coordinate information 108, e.g., row
and column or offset f;n~nci~l m~rket inform~tion, which may
be unigue for each video screen 317. Then, at times tl and
t2, the data messages 128 and 132 described above in
3s co~.ection with FIG. llB are transmitted, having the SRK
codes 122 LONGBOND, which will be received by the enabled
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and initiali~o~ ~ecQ~~rs, and the data 110 for display at
the indic_ted display location~ llla, lllb and lllc on the
~~p~ctive video s~el.~ 317a, 317b and 317c.
The initializing messages 136, 137 and 138 are not
enabling ~e_e~ion mes6ages 100. Thus, if the ~eco~Er is
not first enabled with the reception key 106 by an enable
reception message 100, it will not retrieve the rec~n~ry
reception key 122 by an initi~lization message and will not
retrieve the data 110 from a data enable sequence of the
type 128 and 134 d~ta message.
A comparison of the information that must be transmitted
using the scheme of FIG. llA, at time t2, with that of FIGS.
llB or llC _t time tz readily demonctrates the reduction in
mes~age transmission overhe_d produced using either symbolic
signaling scheme in accordance with this form of the present
invention. Also, the techniques illustrated in FIGS. llB
and llC enh~nce the flexibility for producing user-
customized displays in accordance with part~ Ar client
requests while reducing the volume of data enable ~e~Pnce6
to display and update financial market information.
In this reg_rd, the user who is enabled with a Le_e~ion
key m_y ~elect locally a new locAtion for a tile of
finAncial market information selected from the enabled
finAnciAl m_rket information. To do so, the user would
select the tile using the keyboard 319 or a mouse 319', _nd
define an offset of the selected information by moving the
tile to its new display location on the video screen,
relative to either the origin of the underlying source
portion of the financial market informAtion or to the origin
of the def_ult tile location. T~is new tile position
information is communicated over ~G~ ol bus 318 to host CPU
425 tsee FIG. 11) which may generate a new initialization
- mess_ge with the SRK for the tile (i.e., an information
identification code) and new display coordin_tes.
There_fter, any update data for that tile will be mapped
from the position of the update d_ta relative to the default
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origin onto the user-defined tile and displayed (to the
extent the update datA o~u~ D in the u6er-defined tile).
The user may relocate the tile to a different position on
the display 6creen. This change al60 will be either
followed by an initialization mes~age so that any update
data falling within the fir6t defined tile is mApped into
the new displ_y location, which remains the s_me with
respect to the display location rel_tive to the original
page or is remembered so th_t any updAte dAta fall ~ng within
the first defined tile is mapped into the new display
location by the APcoAer, e.g., by _d~usting the display
: coordinates as the update data are stored.
The use of ~?~onA~ry ~e~c~Lion key6 provides a convenient
tech~ique to minimize message overload. Moving a tile
defined by an enabled reconA~ry reception key and initial
(or def_ult) display coordinates, has the effect of changing
the displ_y coordinates so that the data ~o~e~o"ding to
the secondary reception key will be mapped into the tile in
its new location. Thus, the user may easily customize the
provided data for commonly used data by using r- anA~ry
reception keys and ini~iAlizing the display coordinated for
the financial market information.
Referring now to FIG. llD, an embodiment of a A~coAPr 316
employing 6ymbolic signaling operates in the following
manner. The following definitions are used. DID is a
unique decoder identification code; DIDR is a DID code in a
message received by a given A~coAPr; DIDo is the unique DID
code stored in a given A~coAPr; RK is a reception key; RXR
i8 the first reception key in a message received by a
Aec:oAer; RK~, is a ecc~Lion key in a message received by a
decoAPr that was not previously stored in the AecoA~r; RXo
is a le_c~Lion key that was previously stored in the
decoder; R# is a start row number; C~ is a start column
number; and D is a 6tring of dAt_ to be displayed.
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There are at lea~t seven type~ of mes~ages, wherein the
brackets contain the identified fields of the message as
follow~:
~nable Rece~tion Messaares
[DID, RX~]
tDID, RKN, R~, C~
Tn~ t~ alization Messaae6
tRXo~ R~, C~
tRKo~ RX~
tRKo~ RK~, R~, Ct~
Data ~nable Seouence
tRKo~ D~
tRXo~ R~, C~, D~
The enable ,ece~Lion message that associates a DID and an
RK~ provides the AecoAPr having a DIDo match~ng the DIDR code
in the message with a new reception key RK~, which is ~tored
and thus becomes an RKo as to subsequent messages. The
AecoAPr may store one or more RXos at any given time.
The enable reception message that associates a DID, an RKN
and an R~ and C~ provides the APcoAer having a DIDo matching
the DIDR in the message with a new reception key RK~ and
display coordinate information (R~, C~) for that RK~. The
display coordinAtes are relative to the video screen origin
(on the underlying tile). The decoAer can store many
different RXos and their ~G~e~lo.. -l~ng display coordinates
inten~PA for dieplay on any pArticular video screen. Each
enable ~e~e~Lion message will be ignored by any APcoAPr not
having a DIDo match~g the DIDR in the received message.
The initialization message that associates an RXo and
display coordinate information R~ and C~ will provide the
. new display coordinate information for the already stored
reception key RXo for each AecoAPr that was previously
-. enabled with that ~ece~Lion key RKo. The display coordinate
information defines the offset of RKo relative to the video
screen origin (on the underlying tile).
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The init~A~ tion mes6age that A~soc-~Ates _n RX~ and an
RX~ will enable each ~PcoAPr that w_s previou~ly enabled
with RX~ with an addition_l new ~eoc~Lion key RX~ in the
received message for the same portion of display
information.
The initialization message that associates an RR~, RXN and
R~ and C~ enables each APcoAPr previously enabled with
~e~e~Lion key RK~ with an additional new ~ece~Lion key RKN
and displ_y coordinate information (R~, C~). The display
coordinate information defines _n offset for the reception
key RX~ relative to the video screen origin (on the
underlying tile).
Each initi A 1 i ~ation me~sage will be ignored by a APcoAPr
that was not previously enabled with the reception key (RX~)
that matches the reception key RX~ in the received message.
The data enable sequence that associates an RK~ and data D
is provided to each APcoAPr and the data is retrieved by
each APcoAPr that was previously enabled with the identified
RX~ and is ignored by the other AecoAPr6. If no display
coordinate information R~, C~ has been stored in the decoder
for the identified reception key RX~ in the received
message, then the decoAPr will store and display the data D
without an offset relative to the stored origin of the tile
correspon~Aing to RX~; when there i8 associated di~play
coordinate information stored it will be used.
The data enable 6equence that as60ciates an RX~, data D to
be updated and display coordinate information R~, Ct is
provided to each APcoAPr and i8 retrieved by each AecoAPr
that was previously enabled with the identified RK~ and i6
ignored by the other decoAers. The data D is ~tored and
displayed using the provided display offset information (R~,
C~). Thus, the data is displayed at a location off~et by R#
and C~ relative to either the video screen origin (if no
previous RX~ offset was stored in the AecoA~r) or the data
is displayed offset by R~ and Ct relative to the previously
stored offset of RR~.
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Referring ~till to FIG. llD, a flow chart for symbolic
sign~l~ng, from the ~e~D~e_Live of mess_ges received at the
coAPr~ will now be ~lrc~ rA. The y~ ing routine i~
entered at node 1200, and it rAr-er to step 1202, which
testC for a received message. When no message i~ received,
the APcoA~r sy6tem ~e~u~ to node 1200 and waits for a
message. When a message i6 received, the routine procee~C
to ~tep 1204 where the message i~ evalu~ted fir6t to
determine if the first ~e_e~ion key RX~ in the message i~ a
received code DIDR that matches the unigue DIDo ttypically a
code stored in a ROM device in the ~eco~r). Upon a match
-the 6ystem moves to step 1206 where the recQnA received
~e~ey~ion key RKa in that message is considered a new
reception key RK~ and i~ 6tored in the ~ecoAPr. That RX~
thus becomes a stored ~ece~ion key RKo as to any
subseguently received message.
Following storage of a .e~e~ion key at ~tep 1206, the
routine advances to ~tep 1208, which determines whether the
message contains row Rt and column Ct information associated
with the received and ~ust stored reception key. If offset
information is present, the a~sociated display coordinate
information R~, Ct is stored in step 1210, and defines the
offset for that received and stored reception key RX~. The
Offsêt is defined relative to the origin of the underlying
tile. Following storage of the information, the system
~e~ur..s to node 1200 for the next message. If there is no
display coordinate information in the message, then the
system ~e~ULIIS to node 1200 for the next message.
If at 6tep 1204 it is determined that the first reception
key RKR in the message does not match the DIDo code, then
-. the routine moves to step 1212 and the message i~ evaluated
to determine whether the first received ~ece~Lion key RKR
; matches a previously stored ~e_e~ion key ~R~ for the
~coA~. If it does not, then the routine ~e~u~ to node
1200 and waits for the next message. If it does, then the
routine proceeAs to step 1214 where the message is evaluated
.
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-44-
to determine if it al60 contains a new ~ob,.il .cc_~ion key
RK".
If a new ~ece~ion key RX~ i6 ~&~e~t, then the routine
~lo~re~C to 6tep 1216 and the new recon~ ~ece~ion key RK~
i~ stored, ~nd thus becomes a stored reception key RX~ as to
any r~h-equently received message. After 6torage of a new
~e~e~Lion key, the routine next ~Go~eflC to ~tep 1218 where
the message i~ evaluated to determine if it contains display
coordinate information R~, Ct.
- If new di~play coordinate information R~, Ct is ~ çnt
at step 1218, the off6et location information for RX~ i8
:~tored at step 1220. If the message does not contain a new
~eoc~Lion key RX~ as determined at 6tep 1214, then the
routine p~FeS to ~tep 1226 where the message is evaluated
to determine if new display coordinate information R~, Ct is
present. If it i6, it i6 6tored at step 1228 to define the
off6et for the data associated with the .e_c~Lion key RX~.
If the message does not contain digplay coordinate
information, or after any 6uch information i6 ~tored, the
routine pAcc~c to 6tep 1222 where the message i6 evaluated
to determine if any data i8 present. If no data D i6
present, then the routine ~eL~ 8 to node 1200 and wait~ for
another message. If data D i~ present, then it is 6tored
and displayed using the display coordinate information most
recently associated with the ~tored ~e_c~ion key RX~
matç~ing the received reception key RX~ in the message at
step 1212. Thereafter, the routine ~eLu~.-s to node 1200 and
waits for the next mess-jc.
It is noted that the 8ymbolic 6ignaling routine may be
combined with the nonsymbolic 6ignaling teçhni~ues described
above. It also is noted that other enabling, init~Ali7Ation
and data messages and complementary messages for disabling
reception and/or removing reception keys and di6play
coordinate information can be created, 6ent, and proce~-e~
in a simil~r manner.
CA 022~76~8 1999-01-12
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-45-
According to the ~ ent invention, the e~o~e~ stores a
composite page 200 as a number of tile definitions and
m~ 3e6. Thi~ allows the system to store, transmit, and/or
display information in an efficient manner using a ~echnique
referred to as cellular mi~.Gy,~ph~rF. Cellular
mi~ Gy-~phics is described with reference to FIG. 15, Tables
I and II, and an illustrative cellular mi~,Gy.aphics
transmission algorithm, using two (one fG,ey.v~.d/one
backy,o~.d) color~ per pixel wherein: all cells 210 in an
alphamosaic tile 2S0-A are transmitted as extenAe~ ASCII
characterc, i.e., each character is represented by one byte
-of data and there is one character per cell 210; cells of a
graphic tile 250-G are transmitted as one or more bits per
pixel and, hence, multiple bytes of data per cell 210;
graphic tiles 250-G may contain both graphic cell~ (multiple
bytes of data per cell) and alphamosaic cells (a cingle byte
of data per cell); and, for the sake of processing
efficiency, each tile 250 (except video tiles 250-V) may
run-length encode the signal~ (either horizontally or
vertically) prior to transmission.
FIG. 15 shows a graphic tile 251-G that has ten cell rows
and ten cell columns and is described in Table I, where
b=blank character per cell, a-one ASCII character per cell,
and p=pixel defined cell.
TAR~ I
Cell
Row Contents Notatlon
R0 10 blank characters lOb
R1 10 ASCII characters lOa
R2 10 blank characters lOb
-. R3 5 blank characters, 3 pixel defined Sb,3p,2b
cells, 2 blank characters
R4 3 blank character~, 3 pixel defined 3b,3p,4b
cell~, 4 blank character~
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WOg3~K8 PCT/US93/04361
R5 2 blank characters, 2 pixel defined 2b,2p,6b
cells, 6 blank character~
R6 2 blank characters, 1 pixel defined 2b,lp,7b
S cell, 7 blank characters
R7 1 blank character, 2 pixel defined lb,20,7b
cells, 7 blank charactere
R8 10 blank characters lOb
R9 10 blank character~ lOb
Because the cellular mi~lGylaphic algorithm preferably
uses run length enco~i~g and cell wrapping within the tile
251-G, the tile 251-G can be completely defined by the
messages described in TAble II. The calculations in Table
II assume that single-bit-per-pixel signaling is being used
and that each pixel-defined cell 210 is individually
specified by 16 bytes of data (uixteen rows of eight columns
of single bit vAlues).
TABLE II
Message
number Representina T~nath r in bvtesl
1 llb 1 tl]
2 8a 9 tl + 8]
3 16b 1 tl]
4 3p 49 tl + 3(16)]
Sb 1 tl]
6 3p 49 [1 + 3(16)]
7 6b 1 tl]
8 2p 33 tl + 2(16)]
9 8b 1 tl]
lp 17 tl + 1(16)]
11 8b 1 tl]
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12 2p 33 11 + 2(16)]
13 27b 2 tl ~ 1]
S TOTALS: 100 cells 198 bytes
~ Thus, by using the cellular mic~Gy~sphics technique of
the ~ qnt invention, the amount of required transmitted
data to displAy the tile 251-G is reA~ce~ by a factor of
approximately eight from 1,600 bytes to 198 bytes. The
1,600 bytes ie based on 16 bytec per cell and 100 cells.
The 198 bytes represent 13 cG..L~ol bytes, 8 ASCII
characters, 11 pixel cells (16 bytes each), and 1 blank, or:
13 + 8 + 11(16) + 1 - 198
Still greater efficiencies may be accompli~heA by using
run length encoA~ng within pixel defined cells.
Referring to FIGS. 11, 16, and 25-27, a DV bus signal
6tructure and 6ignaling method, between the en~oAPr 312 and
a plurality of AecoAPrs 316 and/or desk interface units 321,
in accordance with a preferred embodiment of the invention,
is shown. The encoAer 312 includes a receiver 510 for
receiving input messages from a host central processing unit
(CPU) 425 and a residual video ~G.Ive.Ler (RVC) 400. These
messages are then applied to an error detection and
cG..e_Lion (EDAC) circuit 520, which adds parity and
interleaving to protect against both single and bur~t
errors. The ou-~uL of the EDAC circuit 520 is p~s6e~ to
modulation circuit 530, which functions to increase the data
throughput rate and facilitate ~h-equent ~ignal ~loceOsing
and clock recovery in each ~ecoAPr. References to a AProAPr
should be understood to include desk interf_ce units 321
where the context permit~.
MoAl~lAtion circuit 530 converts the binary digital data
into a quad level (8,9) modulated ~ignal, as described
below. The o~L~L of the modulation circuit 530 is pAs~e~
to the multiplexor (MUX) circuit 540 which 6witches between,
on the one hand, the digital data from CPU 425 and video
~ CA 022~76~8 1999-01-12
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-48-
data from RVC 400 and on the other hand time-com~
television ~lGy.am information signals which are received
from television feed converter (TFC) 450. HUX circuit 540
drives the ~uL~uL of en.,o~-r 312 onto DV bus 314.
Each ~Pco~-r 316 (only one i~ A~rc~sed for the sake of
convenience) includes an analog front-end signal ~ or
(AFESP) circuit 610, which receives the DV bus -ignals,
recovers a clock signal from the modulated ~ignal and
establ~hes detection ~h~esholds for y.G~e~sing the guad
level DV bus signals. The ~L~uL of AFESP circuit 610 i5
rA~rAe~ to demultiplexor (DEMUX) circuit 620, which
demultiplexes the television ~LGy~am information signals and
the digital-video signals, such that each may be further
~lG~ F~-~ and provided to video ~creen 317. DEMUX circuit
620 p~c.--s the digital-video signal~ to demodulator circuit
630 which converts the quad level (8,9) modulated signals
into binary signals.
The ou~uL of demodulator circuit 630 i~ pA~e~ to error
detection and cG..e~Lion (EDAC) circuitry 640, which uses
and then removes the parity bits to output digital signalD
that correspond to the signal~ input to enco~-r EDAC circuit
520 as a best estimate of the intended message. The message
is then transmitted to circuit 650, which ch-c~ the syntax
of the message and stores the display information in the
designated address locations of a picture ~tore memory.
The television ~y.am information signals separated from
the DV bus message by DEMnX circuit 620 are separately
rA~ to circuit 670 which ~G.Ive~L~ the compres~ed
television ~.Gy.am information Dignal into displayable
television image signalD, and then provides those image
signals to switch 680. Switch 680 ~elects between passing
the television image signals and the digital display
information to video screen 317.
As illustrated in FIG. 17, signals transmitted on DV bus
314 are transmitted in packets t. If no television ~.Gy.am
information signals are to be transmitted on the system, the
,
CA 022~76~8 1999-01-12
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-49-
packet t m_y have a time length that ic vari_ble, according
to the amount of data in each message. If televi~ion
~luy.am information signAls are to be tr_nsmitted, then the
packet t has _ fixed and uniform time length ~G.,~srQn~ing
to time length of the television stAnAA~d video ~can line.
Thus, for NTSC televi~ion, the packet t time block ic i~bout
63.5 mi~ r:~n~.
E_ch packet t includes a digital dicplay information
packet d including a hDA~er portion H, a data portion D _nd
a parity portion P. The hei~er H contains information that
allows each ~co~r 316 to identify the beginning of a
packet t, and to detect digital signal transitions to
compens_te for the tr_nsmission loss characteristics of the
communication rhAnn~l. The parity bits P are collectively
illustrated as following the data D in FIG. 17, but in
practice may be interspersed among the data D according to
conventional parity and interleaving error detection and
.;G~.e~iLion ~o~ing techniques.
The digital packets d carry all the display information
except television jyLGy~m information signals. One or more
digital packets d constitute a DV bus ~message~ used by each
coA~r 316 to modify the displayed screen image.
Each packet t also may include a television (signal)
packet v, including one or more realtime television jyLGyLam
signals illustrated as ~TV~- Signals for different
television images are given different letters, such that
TVA, TVB, and TVC represent three different television
display images. The ~h-cript numbers 1, 2, and 3,
represent consecutive lines of a given television image
field, such that signal TVAl i~ followed by TVA2 in a
. following video packet v, thereby to provide the fir~t and
secon~ lines of the odd line (or even line) field of
-~ television image TVA. As noted above in connection with
FIG. 7A, the fields alternate odd and even video ~can lines
on the video ~creen, and two fields form a frame of video,
e.g., about one-sixtieth of a seco~ per field and one
.
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--So--
thirtieth of a ~çconA per frame. The television ~-oyLam
information signals TV are preferably time-compressed and
may be either an analog signal, for example, using
multiplexed analog component (MAC) enco~ ng, or a digital
signal, for example, using digital compression methodology
(e.g., JPEG, MPEG). In an embodiment where digital
television ~.Gy~am information signals are used, the video
packet v may be omitted so that all the digital data i8
trangmitted in the portion data D of a digital packet d, and
~ as a tile of pixel based digital display
information.
The digital packet d of each packet t may vAry from one
time length tD to the next t~l, APpPnAi~g on the amount of
data D and televi~ion video information TV that is to be
transmitted in each packet t. To reduce the amount of
memory required in each de~oAPr 316 that is equipped to
receive a realtime television ~Gy.am information signal, it
is useful to signal an amount of information n~resr-ry to
generate about one TV scan line within the time period t of
one TV line. With reference to FIG. 17, this means that the
~econd TVB line TVB2 must occur no later th~n 63.5
mi~e-ecQnAC after the first TVB line TVBl. This does not
however, require that the rQn~?c~tive TVB line signals be
uniformly or periodically ~paced.
Typically, DY bus mess_ges are not ~ent to a decoAPr 316
faster than the AecoAPr 316 can buffer and act upon them.
Bec_use the DV bus 314 ig _ simplex transmission rhAnnPl,
the encoAPr 312 must keep track of the messages being sent
to each decoAP~ 316 and the time required to execute each
message. Subsequent messages are queued until all of the
deroAPrs 316 that have to receive and act upon a given
message are able to do 80.
Referring to FIGS. 16 and 18-19, ~odulation circuit 530
and demodulation circuit 630 are complementary for the
selected modulation protocol. There are four consider~tions
for selecting a signAl modulation method: (1) clock
_
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c.y, (2) start of me~age identification, (3)
information transmi~cion rate, and (4) bit error rate. All
~coAPr~ 316 must ~ecGve~ a digit_l clock from the received
DV bus signal. Therefore, the transmitted DV bus ~ignal
must have An adequate number of digital tr_nsitions for this
~Ul~ :-?, reg_rdless of d_ta D content. Further, the decoder
316 must be able to determine the st_rt of the messAge in a
reliable manner.
In the present invention, a qu_d level digit_l signal,
lo trAnsmitting two bits of information every signAl1ng
interval SI is used a~ _ reArcnAhle engineering tr_de-off
:between data thro~ghp~t and bit error r_te. Since each
signAl~ng interval SI c_rries exactly two bits of
inform_tion, it is also referred to as A ~dibit~ interval.
An (8,9) interval modulation method i8 implemented to
transfer one word (16 bits) of demodulated data D to the
decoA~r EDAC 640 at a time. The structure of this
modulation method is illustrated in FIG. 18, wherein SI is
the signaling interval and MI is the modulation interval.
The rule for determining the signAling level of the
modulation interval MI is to maximize the transition
Gc~..ing at the leA~ing edge of the modulation interval MI.
That is, if the signal level in the signAling interval SI
just before the modulation interval MI is level 2 or 3, then
the modulation interval MI signal is set to level 0. If the
signal level in the sign_ling interval SI just before the
modulation interval MI i~ level 0 or 1, then the modulation
interval MI signal is 6et to level 3.
Referring to FIG. 19, the h~AAer field H is 50 signaling
intervals SI long and includes six subfields. These
subfields provide information to each A~roAPr for the
decoder to recover the clock signal and compensate for the
transmission characteristics of the DV bus 314 and any
interconrlections.
Subfield one has a length of 9 signaling intervals and
contains eight dibits of the maximum value signal. This is
CA 022~76~8 1999-01-12
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-52-
followed by subfield two, which also i6 9 si~nAl~n~
intervals long and which contains eight dibits of the
minimum value signal. These two subfields intentionally
violate the modulation rule and set the maximum _nd minimum
input signal range to allow the ~Pco~Pr 316 to detect the
~tart of a packet d _nd fine-tune its decision thresholds to
compensate for attenuated received-signal levels, and may be
used to ~ignal the possibility of the beg~ nn; ng of a hPA~Pr
field H. HOW-~CL~ the start of a data decision will only be
~made after all six subfields are properly received.
- Subfields ~hree, four, and five e_ch have a length of 8
signAl~ng intervals and may be used to fine-tune decision
thresholds to discriminate between gignals at levels 1 and
2, Tl2, levels 2 and 3, T23, and level~ 0 and 1, Tol,
~e_~e~Lively. Thi~ i~ analogous to double-ended clamping of
a binary digital signal.
Subfield 8iX has a length of 8 si~ ing intervals SI and
i~ used as a delay and clock run-in prior to the start of
data field D. It is al60 used to specify the interleaving
depth for Error Detection and Correction (EDAC) as explained
next.
Referring to FIGS. 16 and 19, the enco~Pr EDAC circuit
520 adds parity bits to the message. This permit~ the
decoAPr 316 to detect and ~GLLe~ the error~ that occur
during signal trAnsmission. Parity both increases the
reliability of the messaging, as evi~Pnc~ by a decreased
bit error rate, at the expense of decreasing the message
data throuyl.~u~.
Development efforts indicated that an error detection
(e.g., check~um) and replication correction method would
likely be ~nA~quate. It was diSCOVeL ed that system
performance was im~Loved by using a single error correcting
and double error detecting code (e.g., Hamming) within a
single level interleaving framework. While non-interleaved
burst error ~G~Le~Ling codes exist (e.g., Reed-solomon)~
their implementation was believed to be more difficult in an
CA 022~76~8 1999-01-12
WOg3/23 ~ PCT/US93/04~1
ASIC environment in which the ~ ent invention i6
preferably implemented.
Referring to FIG. 20, digital data D to be tr~nsmitted is
written bit by bit horizontally into a double buffer. When
the fir~t row of data is filled, data i8 written into the
next row and the parity bits P ~o~ L e~,onA jng to the data D
in the first row ~re calculated according to the EDAC
methodology rule ~elected. This ~ G~e~ cont~n~e~ until the
entire buffer is filled. The buffer i8 then locked to
prevent further input, and tr~nsmitted to the modulator
circuit 530 bit by bit vertically. The buffer may be reused
after its entire contents have been transmitted; double
buffering sustains continuous message ouL~ from the
encoA~r 312.
Each buffer row includes both data D and parity P, and
~e~.e~ents one ro~ewGLd. Assuming that a single error
correcting double error detecting code has been used,
without interleaving the following errors illustrated in
FIG. 20 have the results indicated in Table III:
TABLE III
~rror Codeword errors Action
A,J,K,L Single in data field Correctable
B Single in parity field Correctable
C,Z Double in data field Detectable, not
correctable
E,F Double Detectable, not
correctable
G,H,I Triple Not detectable,
may not give
error
-- The nature of the digital video bus 314 is that errors
occur in bursts. Apart from randomly-occurring single bit
errors, the probability of ~ second error immediately
following the first error is relatively high. For example,
CA 022~76~8 1999-01-12
.
W093t~K~ PCT/US93/04361
-54-
if the prob~bility of a first error is 10-', the probability
of the next bit being in error is not 10-' but might be 0.9,
and the probability of the following bit being in error
might be 0.8. Therefore, a single _o..e_~ing methodology is
ineffective in this type of transmis6ion c~Ann-l.
Interleaving, i.e., buffering the data to be messaged
horizontally and transmitting it vertically, cause6 burst
error6 to be spread among 6everal codewords. In this
regard, a burst error J,K, and L of length three in the
~chAnnel is mapped into three single codeword eLlGL~ and this
is correctable by the ~horen error detection and correction
, scheme.
By choosing a large interleaving depth of n codewords,
e.g., 32 codewords, it is possible to protect against
relAtively long burst errors with a relatively 6imple single
error correcting code. For example, when using an
interleAving depth n of 32, a burst error of up to 32 bits
is fully correctable, All errors of length 33 to 64 are
detectable, and all those with greater length could possibly
result in errors. The oc~.ence of single bit errors plus
burst errors will degrade the performance of the system in a
manner determined by their location.
The maximum possible interleaving depth ~pen~C on both
the maximum buffer size and the number of TV signals to be
transmitted. This is because each time-compressed TV signal
must G~ y a time slot oc~ ing once a line time, i.e., in
s~ccessive packets t. Therefore, the maximum length of
digital packet d is determined by both the television
~GyLam information signal compression factor and the number
of TV signals being transmitted simul~Aneo~sly. Preferably,
the interleaving depth n should be maximized within the time
constraints im~ee~ by the number of TV signals being
transmitted. Thus, with reference to FIG. 7A, the possible
interleaving depth n between lines U and W and between lines
X and Y are the sAme, and is greater than the interleaving
depth m between lines W and X and between lines Z and V.
CA 022~76~8 1999-01-12
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-55-
This is heca~re the latter two series of DV bus signals also
include TV lines for television ~Gy~am information signals
TV2 and TV3. Accordingly, the interleaving depth n will
change with the amount of television ~G~,am information
signals being transmitted.
Referring to FIGS. 21-23, a plurality of digital video
bus messages are now described. The messages are cG--Llolled
in two layers, a transport layer, for detecting and
receiving data sent to a specific AecoA~r 316, and a message
layer, for executing application firmware or software.
Pl G ~e~sing is done by a custom Packet Reception Application-
Specific Integrated Circuit (ASIC) including a
mi~u~G~-essQr located in the receiver module 610 of the
specific AecoAer 316. The ASIC module 610 m y have any
structural implementation so long a~ it performs the signal
processing functions described and illustrated.
Configuration of an ASIC is within the ability of a person
of ordinary skill in the art.
Regarding the transport layer, referring to FIG. 21, the
transmission of variable length packets d are concatenated
to form complete messages in the presence of time
multiplexed television ~G~m information signals (e.g.,
TVA and TVB), are shown. The message format is summarized
in Table IV below:
TABT ~ SV
Messa~e rM) Packet (t~ Tnterleavina DeDth
1 1 D0
2 D1
3 D1
4 D2
2 1 D2
- 35 2 D2
CA 022~76~8 1999-01-12
WOg3~ ~ PCT/US93/04361
3 1 Dl
2 Dl
3 D0
4 1 Dl
2 Dl
3 D2
The interleaving depth is defined in terms of the total time
of television y~Gy.&m information signals present in the
video packet v of a packet t. For example, the fourth
p_cket t in mescage 1, designAted Ml-P4 in FIG. 21, has An
interleAving depth of D2 cG~Le~ n7 to the time used by
the two TV signals.
Referring to FIG. 22, the location of the digit_l packet
d fields are illustrated. Field 0 contains a message
h~A~Pr. Field 1 cont_ins the end of message tEOM) fl~g
which indic_tes that the current packet d is the l_st one in
the current message when the EOM flAg is set. Thi~ enables
the hardware to y~oce~s the ~ecey~ion keys contAi~e~ in
fields 2 and 3 of the pAcket d, to determine whether further
y~oce~sing of this p cket d is required.
Fields 2 and 3 cont~in the le_eyLion key which i~ formed
by the address type and address. More specifically, Field 2
contains the ~address type~ which is used to specify the
meA~ing And use of the contents in the address (Field 3).
In _ preferred embodiment, the address type field contains
two bits. A value of 00 indicates that the following
address field contains a unique display identific_tion code
for a given a ~eco~r video screen, i.e., a DIDo. If the
address field value is 01, then the _ddress field contains a
new to be ~tored information identification code for a tile
250, i.e., an RX~. If the address field is 10, then the
sddress field contains a previously stored information
identification code for a tile 250, i.e., an RX~. If the
_ddress field value is 11, then the address field contains a
packet ~equence number (PSN), hAving A value of from 1 to
31, and the decoder 316 checks for sequential numbering of
....
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packete d within the me-r-g~. An out-of-sequence number
causes the entire mes~age to be re~ected.
Field 3 i~ the ~address field~ and may have up to 21
bits. Accordingly, there may be up to 22l - 2,097,152
different unique identification codes for each address type,
i.e., video ecreens and pages, records, portions and tiles
of display information.
Field 4 has sixteen bits and provides the ~message
length~ which is only transmitted in the first packet d of a
message. It indicates the total length of the message in
bytes.
Field S contains the data D used to form the display
information message. It has a variable bit length.
Regarding the message layer of the DV bus 314, there are
two clAF-~fi of messages that can be accommodated,
supervisory messages and image data messages. Supervisory
messages direct one or more A~coA~rs to perform cG..L.ol
and/or hook~eering actions, such as enabling a reception key
or defining a tile. Image data messages refresh or update
the contents of a displayed tile. Such messages always
cause the A~coAer video screen 317 to update even if the
display information is ~nch~nged.
All received packets d Are concatenated into messages At
the APcoA~r 316. The location of the received message
fields is illustrated in FIG. 23. Field 0 is the reception
key tRX) and contains 3 bytes. Bit 0 is set to 0, bits 1 &
2 contain address type and bite 3-23 contain the address
(cf. FIG. 22). Field 1 contains the ~message length~; it
uses two bytes to specify the length of the message in
byte~.
Field 2 is the ~message sequence number~ and i~ a one
byte field. It contains a message sequence number for
messages to the reception key RK specified in Field 0. The
decoA~r 316 verifies that the difference between the current
and last received message sequence number is alway~ one
modulo 2S6 to ensure that all messages to the ~.el-~
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reception key RX are received in order. When an out of
~equence number i6 detected, an error reque~t iB transmitted
by the ~coAPr 316 over the cG..L.ol bus 318 (See FIG. 11)
indicating the last ~Gr~e_~ly received message.
Field 3 i6 the ~Command~ field, and has one byte which
indicates the operation to be performed on the contents of
the data in following Field 4, the variable length part of
the mescage. A Command m~y be self acting, i.e., the data
field contente immediately following is null. The byte
length of the datA in Field 4 is limited by the time length
t of each message and the video cignals v in each message.
In A, preferred embodiment, the message Command field 3
has the following commands and data Field 4 has the
following associated data: A message Command byte O
initializes ~c~Pr hardware and cleare the video screen.
There is no associated data. A message Command byte 1 sets
the parameters to configure the video screen hardware and
software. ~c~ociated data bytes 0-7 contain the ON And OFF
period for four blink counters, and dat_ bytes 8-11 contain
the motion period for four motion counters. A message
Command byte 2 operates to clear the video ~creen, making
_11 pixels the background color. There is no associated
data. A message Command byte 3 operates enable ~e~e~ion.
It instructs the uniquely identified decoAPr 316 to enable
2S reception for the specified reception key, And associates
this reception key with the request string for the specific
tile 250 sent by the ~eco~Pr 316 to the host CPU 425 via the
cGl.~.ol bus 318. For this message Command, the associated
data is, for bytes 0-2, the tile .e_e~Lion key, and for
bytes 3-23, the tile request string. A message Command byte
4 sets the tile definition. It defines the tile 250 whose
number is specified in the address Field 3. The first
associated dat~ byte specifies the default color index for
the portion of display information. The r ~CO~ data byte
specifies the default display attribute. The third data
byte represents the number of symbolic tile definitions (the
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nu~ber of 11 byte packets following). Each of these
definitions contains a 16 bit symbol number ~tile IID or
RX), the two corner displAy coordinates (upper left and
lower right; a rectangular tile hollnA~ry i~ a~sumed), the
S default symbolic tile attributes and the value of the motion
counter if the tile i~ a r~nn~ng or scrolling tile. The
associ~ted data bytes are:
byte 0 default color index
byte 1 default display attribute
byte 2-3 default upper left row and column number
byte 4-5 default lower right row and column number
byte 6 tile motion attribute
byte 7 current motion index
byte 8 default character table
byte 9 number of text messages composing the tile
byte 10 current message sequence number(s) for tile
messages 1 to n
A message Command byte 5 cets the color table. It
contains a number (specified in data byte 0) of definitions
for the color table. Each def inition cont~ins four bytes.
The first data byte is an index (0-255) into a color table.
The three other data bytes ,e~~-ent backyLGu,-d color,
fo~ey~ou,.d color and line color respectively. Each of these
three data bytes is enco~ internally as IIRRGGBB: two
bits to define the overall INTENSITY (I), two bits to define
the RED (R) intensity, two bits for the GREEN (G) and two
bits for the BLUE (B). The associated data bytes are:
byte 0 number of color def initions
byte 1 new color index
byte 2-4 background, forey~o~u.l, line colors
byte 5-8 next color definition (same as bytes 1-4)
byte 9-12 next color def inition ( same as bytes 1-4)
A message Command byte 6 operates to send new text to the
video screen. The characters contained in the data section
are put on the screen in contiguous columns or rows,
.
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depenA ~ ng on the axi~ of ~ tivenQss, using cell
wrapping. The ar-oc;~ted d_ta bytes _re:
byte 0 message id (Tile-relative)
byte 1 mess_ge sequence number
byte 2 rel~tive row number
byte 3 relative column number
byte 4 number of data bytes following
byte 5...... data in TEXT format
A messAge Comm_nd byte 7 provides for downloAA;ng
~ mming code into the AecoA~r 316 application ~oyLam
memory. The associated data bytes are:
byte 0 ~Gy~am revision code
byte 1-4 ~ection _ddress
byte 5 l_st section flag
byte 6....... p~GyLam code
A message Command byte 8 clears a tile. It causes all
pixels in the tile to be ~et to the default bachy~ou.,d
color. There is no associated data. A message Command byte
9 is a ~Genlock~, wh$ch is functionally equivalent to _
vertical sync pulse in a video signal. There is no
associated data. A message Command byte 10 is to define a
character set. It downloads a pixel map for a character set
for converting a one character byte to a multibyte pixel
represent_tion. The associated data bytes are:
byte 0 Character table ID
byte 1 Starting character code
byte 2 Number of codes defined
byte 3...... Bit m_p def initions ( 16 bytes each)
When a tile 250 is defined in the encoder 312, a ~tatic
arr_y of messages is allocated to, and associated with, that
tile 250. All messages in the P~coAPr 312 are kept in a
queue and are sent out, in their entirety, in a message
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cycle whose period varies according to system r~h-~tll ~n~
D~,aint6.
The system i~ preferably tuned to optimize message
rch~ g for its particular mix of static alphamo~aic
tiles 250-A, graphic tiles 350-G, motion tiles 350-P, 350-
S, RVC tiles 350-V, TFC ~tiles~ 350-V, and the number of
APcoA~r~ and video screens. One suitable message
prioritizing ~h~ le is the following order: individual
AecoAPr directed messages, ~eAl~led messAges (tile motion
~GnL~ol), tile update data messages, APco~Pr re-requested
tile update messages, alphamosaic refresh messages,
administrative messages, and graphics refresh messages.
The message layer protocol ~ L8 three kinds of
attributes for cell~ 210: motion, cell and color. The
motion attribute is an eight bit word that i~ encodP~ MOV,
Cl, C0, V, NU, NU, NU, NU, where MOV, Cl, C0, V are
movement, movement cG~ ol byte 1, movement cG-.~Lol byte O,
~ideo and NU stands for ~n~re~ bits. The cell _ttribute is
an eight bit word and it combines both software and hardware
attributes. The byte is encoded REV, ULIN, NU, NU BRl, BR0
BEl, BE0 where BRl, BR0, BEl, BE0 are blink rate 1, blink
rate 0, blink effect 1, blink effect 0, REV stands for
reverse video _nd ULIN stands for underline. These l_st two
attributes are implemented in software and therefore need
not reside in the character cell. The color attribute is an
index into the color table.
The message layer protocol uses a byte oriented TEXT
format to specify ~GI~O1~ alr~nl~meric text, and graphics.
The lowest nine bytes are cG---~ol bytes and have the
following special me~nings: Byte 0 specifies that the next
byte will contain a repetition factor for run length
enco~ing to specify how many times the cell definition that
follows should be repeated along the axis of
consecutiveness. Byte 1 specifies that the next 2 bytes
will contain the relative row and column number applicable
to the following text. Byte 2 specifies that the next 16
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byte6 define a graphic cell to be put in ~.,e~-L location.
Byte 3 ~r~c~ fies that the next byte is to become the current
cell attribute, mean~ng thAt it will apply to every
subsequent cell defined in the message. Byte 4 specifies
that the next byte contains the 6ize of the cell
specifications to come. The size6 allowed are 0 for normal
6ize, 1 for double size, 2 for triple size and 3 for
quadruple ~ize. Byte 5 6pecifies that the next byte i6 to
become the current color index, me~n~ng that it will apply
to every r~heequent cell defined in the message. It i8 not
u~ed for graphic cells. Byte 6 specifies that the following
cell specifications should be put in consecutive locations
horizont_lly. In other words, to define the address of the
next cell, the current column number should be incremented.
Byte 7 specifies that the following cell specifications
should be put in cons~tive locations vertically. In other
words, to define the Address of the next cell, the current
row number should be incremented. Byte 8 specifies that the
~Lel~ cell location is not to be modified, e.g., if the
cell contains a character that i6 defined on another line.
For example, if the line 1 contains triple size characters,
it also will use line 2 and 3 to display such characters.
Therefore, all character~ on line 2 and 3 will be ~phantom
characters.~ Byte 9 specifies thAt the next byte identifies
the character table from which the following charActers will
be drAwn. The new character set remains in effect until
another change character set command, or the end of message.
Bytes OAH-OFH are not used and bytes 20H-FFH are normal cell
representations. Printable ASCII charActer codes are
preferably used wherever possible.
The following illustrates how the overall messaging
efficiency and system thro~g~ , in accordance with thi~
third embodiment of the invention, may be cAlculated.
Consider a system in which signal bandwidth is 22.5 MHz,
the packet time length t (including the header H) is
63.5 ~s, the error detection and correction code is a 24/30
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HAmming code, interleaving efficiency i~ 100%, modulation is
quad level (8,9), and packet efficiency is lOOS.
The 6i~n~l~n~ interval SI may be determined from the
6ystem bandwidth a8 follows:
a) the 6ignal edge rise time (tr) 6hould be less thAn or
equal to one-third of the si~nAling interval SI, And
b) the bandwidth of the signal (fb) is related to the
signal edge rise time by:
(fb) (tr) - 0.35
Hence, the minimum signal interval corresponAing to a
22.5 MHz bandwidth is:
SI~n ~ 3(tr) e 1.05/(fb) ~ 1.05/22.5 NHz - 46.6 ns.
The signaling interval $s therefore cho-en to be:
SI e 50 ns.
Regarding information thro~ghrvt, since quad level
modulation is chosen, two bits are transported in every
signaling interval. The capacity of the rh~n~Pl is
therefore:
ChAnnel = 2/SI = 2/50 ns ~ 40.0 Mbits/sec = 5.0
Mbytes/sec.
This capacity i~ not actu_lly attAin~~ because fir~t,
every packet starts with a 50 SI hPAAPr~ every ninth SI
after the header contains no information ((8,9) modulation
is used to Aid clock recovery), and the EDAC circuits
2S ~prenAC six parity bits to every twenty four data bits (a
(24,30) Hamming code is used).
~econ~, each packet maximally lasts 63.5 ~s. Thus, there
can be a maximum of (63,500ns/50ns) ~ 1,270 SI per packet.
The 50 SI header therefore re~ce~ the capacity by a factor
of (1270 - 50)/ 1,270 - 96.1%. The modulation efficiency is
. (8/9) - 88.8~ and the EDAC efficiency i~ (24/30)- 80%.
Therefore, the overall efficiency of the DV bus 6ignaling is
approximately ~ 0.961 x 0.888 x 0.800 ~ 68.27%. This
results in an effective DV bus capacity of:
0.6827 x 40 - 27.3 Mbits/sec c 3.4 MBytes/sec.
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In practice the DV bu~ 314 should be tr~ Ling
information at a rate of ~bout 20 Mbit6/sec or more, which
i~ more than tte..Ly (20x) times that of conventional
Ethernet systems. It should be noted that Ethernet has a 10
Mbits/~ec capacity of which perhaps only 1 Nbits/sec is
realized after protocol and/or error ~G~eL8ing.
Referring now to FIGS. 11 and 26, cGI.L~ol bus 318
018 bi-directional communication between a A~coAPr 316
(or a desk interface unit 321) and the system. Host CPU 425
may issue messages targeted to a ~pecific AecoAer or to all
decoders, or may request information from a specific
A~coA~r. A APcoA~r will send a message to the host CPU 425
when requested by the host CPU 425.
~ Typical uses of the ~GI~LO1 bus 318 from the host CPU 425
to ~coA~rs 316 are to poll a A~coA~r 316 for a message,
install a new ~PcoAPr 316 on the system, update an LED
display of a keyboard 319 at a AecoAPr 316 and maintain the
control bus protocol. Typical uses of the ~G--Llol bus 318
from the A~coA~r 316 to host CPU 425 are to transmit
keyboard and/or mouse data (i.e., user requests for display
information, or to define or move tiles), e~o.~ decoA~r
malfunctions, and request system resou~es, e.g., DV bus 314
message retransmi~sion due to a detected error in message
seq--e~cec .
The structure of ~o,.L.ol bus 318 i~ modeled after
conventional industry-stA~rd shared bus models. A
preferred protocol is one similar to an HDLC ~-nh~ 1 A~A
configuration in normal ~e~o--~e mode. A preferred ~GnL~ol
bus 318 i8 a system-wide multi-drop RS-422 or 485 network,
where the host CPU 425 serves as the primary station and up
to 63 decoA~rs 316 are connected as ~eConAAry stations to
each RS-422 or 485 strand. Bi-directional communication
between each decoAer 316 and the host CPU 425 is oG..L~olled
by a preselected polling scheme emitted by the host CPU 425.
At installation, the host CPU 425 assigns a unique
control bus address to each decoA~r. This address consicts
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of a strand ID, which identifies the RS-422 or 485 line to
which the APcoAPr i~ connected, and a 5-bit polling ID. The
polling scheme allows the host CPU 425 to poll each ~PcoAer
using a single byte, thus making the most frequently used
signal the shortest length.
In addition, the host CPU 425 sends command~ to a
-pecific ~ecoAPr 316 using its unique 21-bit APcoAPr ID.
Unless there are any errors detected, every AecoAPr 316
along a strand is polled before any APcoAPr is polled a
~econA time. This polling sequence represents a polling
cycle. The suitable nominal polling freguency of .2 second,
that ic, an outstanding message at a APCO~Pr will wait not
longer than .2 second before it is solicited by the host CPU
425. The baud rate (nominally 9600 baud) is configurable,
APp~nAing on the number of decoAPrs in the eystem. This
means that smaller systems may be able to realize a savings
by using fewer communications controllers. It also means
that ~ystems are easily upgradeable, since the system's
cG"~lol bus capacity can be increa~ed by ~A~ng
communications controllers. Where desk interface units are
used, CPU 425 assigns a polling ID for each video screen 317
and polling and command messages are sent for e~ch video
screen 317 on the system, rather than to each decoder 316.
Messages between the host CPU 425 and each decodPr 316
are in the form of a transaction. All transactions are
initiated by the host CPU 425 and take place between the
host CPU 425 and a single AecoAer. Referring to FIGS. 24A
and 24E, the host CPU 425 begins its signal by senAing a
probe message (if it has no command for the d~roA~r 316) or
a command message (if it hss a command outst~nAing for the
d~coA~r) to a specific decoAPr. Alternately, the host CPU
425 may send a ~BroAAcA~t~ message to all ~coA~r~ on that
~-ol bus strand 318. Broadcast messages serve a number
of pu.~-e~ (e.g., transmi~sion failure, ~ystem-wide
keyboard messages, changing communication parameters, etc.).
.. .. .
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80th command ~nd Bro~AcAst messages consist of a u~ADr, a
sequence element (Seq), and one or more requests (R-Frame).
Referring to FIG. 24B, each A~roAPr ~e~o..ds to _ host
CPU 425 ~ignal with either a solicitation message or, if no
solicitAtion is ready, _n idle message. Idle messages
consist of _ Seq element only (me~s_ge bit ~ O).
Solicitation messages consist of a Seq element (message bit
~ a poll element, _nd one or more reque6t fr_mes. A
request frame (R-Fr me) contains one or more request6 from
either the host CPU 425 or the AeroAer 316. No more than 64
requests can be ~ent in one R-Frame. FIG. 24C shows the
structure of _n R-Frame _nd FIG. 24D ~hows the structure of
a ~ingle request.
Of the three message classes generated by the host CPU
425, two (Probe and Comm_nd) constitute 6ignals. The
deroAer must .e~or,d within a configur_ble response interval
(nominally set _t 5 character times), otherwise the host CPU
425 regards this _~ A failed transaction. If the number of
failed transActions paCses a configurable Ai~ronn?-t
threshold (nominally set at 5), the host CPU 425 logically
Ai~ronnects the decoAer from the network and displays a
~uitable message to the system administrator.
The ignaled decoAer ~e_~onds to each host CPU signal
with a olicitation or idle message. The value of the AK
bit in the Seq element (~ee FIG. 24G and the Ai ~c~csion
below) reflects the reception stAtus of the signal. If the
~ignal was a Probe or a successfully received Command, the
AK bit is 1. If the signal was a Command, and the R-Frame
was not received ~lcce~fully, the AK bit is 0.
The decoder regards the transaction as sl~cc~ficful if the
next message ~ent by the host i~ a signal to another
A~coAPr. Otherwise, a negative acknowledgement is assumed.
If the next host message is another signal to this APcoA~r,
it retransmits the solicitation. On an error, the host CPU
425 will re-signal a APcoAPr up to a configurable number of
times (nominally 5), ind then send a broadcast message.
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Thi~ indicates a communication failure without providing a
~e_~on8e O~G~ L~.ity. The host CPU 425 then cont1nt~Ps its
polling 6equence.
As shown in FIG. 24E, bit 7 of the poll message i~ always
6et. Since a poll message can originate from either the
host CPU 425 or the ~ecoADr 316, bit 6 ic used to indicate
the source of the poll (0 ~ Host, 1 ~ APcoAPr). The
rem~ining six bits ~re the polling ID of the ~ecoAPr (1 to
63).
Referring to FIG. 24F, Command and Broadcast messages
always originate in the host CPU 425. The structure of byte
0 of these two messages is identical; however, whereas the
command message is sent to a specific decoAPr, wherein bytes
1, 2, and 3 of the command element contains the polling ID
of the decoder, the broAAcast message is sent out to all
APcoAer8 on the entire strand, wherein bytes 1, 2, and 3 of
the brQ~Ac~fit message have a polling ID - 0.
In addition to message-by-message acknowledgement~, each
command and solicitation message is assigned a sequence
number (see FIG. 24G). The sequence numbers are
cQnse~l~tive, modulo 4. These are ~c~G~ ~ed by each station
in the NR and NS bit fields of the Seq element. Comm~nds
are numbered in the NS field by the host CPU 425 and the NR
field by the decoAPr 316; solicitations are numbered in the
NR field by the host CPU 425 and in the NS field by the
APcoAPr 316. In each case, the ~equence number fields
contain the next ex~e~Led sequence number. In other words,
the NS field of the current message contains the sequence
number of the next message the F~nA1ng station expects to
send. The host CPU 425 maintains a unique NR/NS pair for
each AecoA~r. In BroAAcact messages, only the NS field is
me~ningful.
This feature provides an additional means of error
correction and detection, since a failure to match one
station's NS with the other's NR is interpreted as a request
to resend messages with prior sequence numbers. This means
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that each ~tation keeps a gueue of the last 4 mer-al eD
transmittQd. In the event of a seguence number mismatch,
all Regs (up to 64) from all outst~n~ng outho~nA mess~ges
may be concatenated into a new message with the lowest
out6t~nAi~g 6eguence number.
Referring now to FIGS. 1~, 16, and 25, a preferred
embodiment of an e~co~r 312 of FIG. 11 is 6hown. ~nGo~r
312 is constructed to interface with host CPU 425, and to
accept sign~ls from digit~l 8GUL~eS, analog source~, digital
-~video 60ul~e~ analog video 80u~ces, and realtime television
-image 6ignals, in addition to the host CPU 425. Preferably,
: the enco~Pr 312 receives video cignals from one or more
residual video converters 400 and television ~LGy-~m
information signals from one or more television feed
converters 450.
~ncoA~r 312 i6 preferably configured a6 a 6ingle printed
circuit board assembly that can be installed in a backplane
of the host CPU 425, and may be ~u~oL~ed by one of ISA,
EISA, and VME bus protocols, or an equivalent protocol.
The enco~r 312 originates messaging over the 6implex DV
bus 314 to the plurality of individual Aeco~r6 316, ~nd
al60 provides duplex communication over the ~G-.L~ol bus 318.
It includes an encoA~r CPU 505, which is preferably a high
performance 32 bit centr~l ~Locessing unit with direct
memory address (DMA) and other integrated functions (e.g.,
counter-timer). A suitable CPU 505 is model 68332 available
from Motorola. It is ~e~o..sible for cG..~Lolling all of the
e~co~r functions, including collection of incoming data,
message manipulation, determination of transmission
priority, and dissemination of outgoing data.
The CPU 505 has an associated ROM memory 506, which
contains a ~mall amount of ~L~y,am ROM code, e.g., the basic
boot code and rudimentary ~y~am functions to allow the
enGo~r 312 to perform self-test and communicate with the
host CPU 425. The bulk of the enco~r executable code is
preferably stored in a RAM 507, and may be downloaded via
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the host interface 427, thereby providing maximum
flexibility for reconfiguring the functionality of ~ncoAer
312. Alternately of course, the exec~able code could be
cont~ineA in the ROM 506.
Data received via the host interface 427 or the seriAl
interface 508 are transferred by DMA into the r.Gy~am and
DatA RAM 507 along data bus 504. The enco~Pr CPU 505 can
then ~cr~ these messages and perform any nec~ ry
manipulation or re~ e.
The Dual-Ported RAM 512 stores current messages queued by
the system, for transmission on DV bus 314. When A new
message has been prepared by the e~coA~r CPU 505, it is then
transferred via DMA bus 504 from the r.Gy.am and Data RAM
507 into the Dual-Ported RAM 512. These transfers occur
during the header period of the signals on the DV bus 314,
and are initiated by a high-level interrupt provided by a
timing generator 513. The Message Formatter And Sequence
circuit 514 acceC~?s new messages loaded into the Dual-
Ported RAM 512, and formats the message as Ai ~c~ for
transmission over the DV bus 314.
The host interface and FIFO 427 allows bi-directional
communication between the host CPU 425 and the encoder 312.
Host messages that are to be transmitted by the encoder 312
on DV bus 314 are rA~re~ from the host CPU 425 to the
~nCoApr 312 via the interface 427. Because these messages
are only composed of changes to displayed s~ ee..3 , i.e.,
update data, the average bandwidth requirements are much
lower than for ~realtime~ video switched systems.
Messages from the host CPU 425 are loaded into an input
FIFO memory device in interface 427 for retrieval by the
-. encoder CPU 505. Configuration information is also pA~~ed
from the host CPU 425 to the encoder 312. The encoAPr CPU
- 505 will periodically DMA transfer the incoming messages
from the FIFO memory in interface 427 to its local P.Gy~am
and Data RAM 507 over bus 504.
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The host interface 427 can also be u~ed for limited
informAtion flow in the other direction. Re_~& ~ nd
command Ac~n~wledgements from the ~nco~r 312 _re
communicated to the ho~t 425 via interface 427. In
S addition, d_ta received over the cG-.~Lol bus 318, e.g., data
gener_ted by the user's keyboard 319 or mouse 319', _re
trAnsferred to the host CPU 425 through this same interface
427 viA cG..L~ol bu~ mic~G~o~ oller 550. Alternately, the
cG..~Lol bus 318 may be _cce~re~ by host CPU 425 directly
through host I/F _nd FIFO device 426 _s illustrated in FIG.
25.
The RVC interface SO9a consist~ of a mono-directional
data port S09 and a bi-directional ~ Lol port SO9b that
communicate between external RVC modules 400 and _ bus
~5 microcontroller 509c. RVC modules 400 send messages to the
encoder 312 that identify pixel change data on video displ~y
adapters to which they are conn~ ~ed _s described below.
The enco~Pr data bug 504 could possibly be busy when
multiple RVC modules 400 attempt to send messages
asynchronously to the enco~Pr 312. Arbitration and flow
control is, therefore, required. Further, bus _nd priority
arbitration by the interface circuit 509a is preferably
provided by RVC bus ~G..~Loller and FIF0 SO9c in a
conventional manner. Typical techniques include: interrupt
requests generated by RVC modules 400 and subseguent polling
-of data by the encoder CPU 505; ~token passing~ between
ronnected RVC modules 400 to enable sequential access to the
interface bus 504; and time domain multiplexing (TDM) of the
interf_ce bus 504 to allow periodic _ccess by each RVC
module 400.
MeccAges delivered by the RVC modules 400 are identical
in structure to those created by the enco~r CPU 505 and are
DMA'ed directly into the Dual-Ported RAM S12. Therefore,
messages delivered by the RVC modules 400 present no
processing overhead to the encoA~r CPU SOS. However, the
encoder 312 may apply cellul~r mi~LGyLaphic tech~iques
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(optionally with run length ~ncoA~ng) to further reduce
mes6age volume on the DV bus 314.
The serial interf~ce 508 allow~ eaey communication and
downloaAing of executable code, even when the host Interface
427 is not operational. Typically, this port will not be
used during normal operation of the ~ystem.
The DV bus signaling protocol described above
in~oL~o~tes robu~t EDAC circuity 520 enhancpA by
interleaving of data. The 11~elihoo~ of e,~o,~o~-C data
being displayed on a monitor is, therefore, extremely low.
The eignal to noise performance ~hould have a bit error rate
better than 101~ in a 38 dB signal to noise ratio,
interleaving for burst error protection greater than 16 bits
and decom~ re~ TV signal to noi~e ratio better than 40 dB.
Nevertheless, a further added level of protection is
provided by replication coA i ng ~ i.e., retransmi~sion of
previously transmitted data, termed ~refrefihing.~ In other
words, undetected co~ Led data is displayed for only a
brief period of time, since the 6~me information will be
periodically retransmitted (refreshed) and corrected a short
time later, e.g., 0.5 ~econA~. Thus, the probability of
erroneo~C data being displayed for a significant period of
time is further reduced by the number of refr~-hPs, until
the message is eventually displaced from the Dual-Ported RAM
512 by more recent data. Thus, the Dual-Ported RAM serves
as a cache for each portion of display information that is
transmitted to a video screen on the system.
Yet another level of protection is i.-L,Gduced with
respect to encoAing and refre~h~ng. In this regard, an ESF
time-out period is used (see FIG. 2) such that an enable
ignal flag and enable ~e_e~ion messages must be
retransmitted before the tire ouL period expires or else the
previously enabled decoder will become intentionally
disabled. Further, retransmission of enable ~e_e~Lion
mescages permitC periodically changing the information
identification codes for each portion of restricted display
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information. This will minimize the l~el~hooA that an
unauthorized AecoAPr will be able to retrieve and display
restricted display information, and because all di~pl_y
information data will be retransmitted, removes the
li~el~hooA of cG.lu~Led data being di6played for any
~ignificant period of time.
The encoAPr 312 i~ designed to u6e as much of the DV bus
314 bandwidth as possible. Priority is given to
transmission of new data to keep latency time low. Once
this requirement has been fulfilled, the remaining DV bus
bandwidth i8 used for refre~h1ng recently transmitted data.
In one embodiment, the DV bus 314 may include up to 2000
feet of type RG-8U roaY1Al cable, and may have attached to
it up to 128 APcoAPrs 316 with a 3 dB bandwidth on the order
of from 100 Hz to 25 MHZ.
The Message Formatter and Seq~ncer 514 performs _
hardware function responsible for retrieving prepared
messages (in proper priority) from the Du~l-Ported RAM 512
and generating the proper hPA~Pr _nd message for
transmission on DV bus 314. The preferred DV bus definition
requires that one packet is transmitted every 63.5 ~6
cG~L~ollling to a television video ~can line for a VGA
format; for other televi~ion formAts, other packet time
~lengths could be used. Long messages are thus broken into
several con-ec~tive digital packets d. The Message
Formatter and Seq~encer 514 performs division of long
messages into multiple digital packets d with con~ec~tive
packet sequence numbers.
The Dual-Ported RAM 512 is preferably implemented as a
circular message store buffer, with new messages loaded by
the CPU 505 overwriting the oldest messages left in the RAM
512. Every movement of the starting data pointer by the CPU
505 causes the Message Formatter and Se~Pn~Pr 514 to begin
ren~ng the new messages before resuming the transmi~sion of
refresh messages.
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The interleave encoA~r 522 burst error protects the
outgoing packet data stream. In summary, the outgoing
packet data D ~nd parity P are stored in the interleaving
RAM buffer 524 in ~raster scan~ format. The interleave
encoA~r 522 then reads the data D and parity P with the axes
reversed. Consequently, each AecoA~r 316 i8 able to detect
and ~GLLe-t most errors caused by burst noise. As noted,
the degree of interleaving in each packet is ~epenA~nt upon
the number of television ~. Gy~ am information signals TV
being multiplexed onto the DV bus 314. The interleave level
in each packet d is cG~.L~olled by the encoAPr CPU 50S and is
communicated to the decoders 316 via the aforementioned
message field.
The timing generator 513 generates the various DV bus
dependent timing signals used by the encoder 312. An
interrupt to the encoder CPU 505 is timed to allow new
messages to be loaded into the Dual-Ported RAM 512 during
the period when the Message Formatter and Se~encer 514 is
not accessing the RAM 512. Horizontal and vertical sync
signals are provided at ouL~L 515 of timing generator 513
for A i ssemination to an optional Television Feed Converter
(TFC) 450. Multiplexor ~onL~ol signals are also generated
at output 516 for use by an ouL~uL multiplexor device 540 to
inject the converted TV ~ignals at the a~G~iate time in a
video packet v during each TV scan line time length t.
Regarding TFC 450, a number of live TV signals may be
time compressed and transmitted over the DV bus 314 for
display by remotely located d~coAer6 316. These ~tanAArd
NTSC video signals will be time compressed (e.g., by a
Multiplexed Analog Component (MAC) ter~n~que), and then
-. injected onto the DV Bus 314 in a Time Domain Multiplexed
(TDM) fashion. Further, the same television ~Gy.am
- information signal can be provided with different line
numbers so that one video screen can digplay the signal at
full size and another can display it at a different size,
e.g., 1/4 size.
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Thus, TFC ~coA~r interface 451 accepts the MAC analog
~ignal~ from several different TFCs 450. When other
televi~ion ~LGy,am information signAl compres6ion formats
are used, interface 451 is a~Gp.iately modified. In
addition, interface 451 provides horizont_l and vertical
sync sign_lc to the TFCs 450 to ~genlock~ these signals to
the master time clock in enco~Pr 312. Configuration and
~o"~ol messages are _lso pArre~ between the ho~t computer
425 and the TFC 450 vi~ a conventional low b_ndwidth ~erial
communications link (not chown).
Digital ~ignals gener_ted by the Message Formatter and
Sequence 514 _re modulated in the ~dibit~ format, i.e., with
four discrete an_log levels ~e~e_cnting two bin_ry bits of
information per si~Aling interval. Signals supplied by the
TFC Interface 451 are typically high frequency MAC analog
~ign_l~. These two sign_l types _re time multiplexed
together by multiplexor 540 to form a hybrid signal for
transmission over the DV bus 314.
The multiplexor 540 performs this selection ~ o~e3s in
.e~G.,se to cGn~.ol signal~ provided by timing generator
513. The ex_ct number of TV sign_l~, and their location
within the DV bus packet, are determined by configur_tion
information r~-sse~ from the host computer 425.
The DV bus driver 516 interfaces the analog ouL~ signal
from the multiplexor 540 onto the 75 ohm DV bus COAYi A
cable 314 in _ ~Gnvel.Lional manner.
The control bus mi~.o~G..L~oller 550 polls the cG..~.ol bus
interface 552 collects the dat_ from remotely loc_ted
decoders 316 and p~sse~ the data to host computer 425. On
large systems, this functionality m_y be performed on a
separate Digital Interf_ce Board (~ee DIB 426 FIG. 11.) The
co,.L~ol bus interface 552 cQnnects the ~ncoAer 312 to a
multi-point twisted pair ~G..L~ol bus 318. Drivers are used
to send and receive differential signAls on this ~G---.ol bus
318.
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In one ver~ion of the third embodiment of the ~ nt
invention, the encoA~r 312 was designed using Application-
Specific Integrated Circuits (ASICs). Three Field
mmable Gate Array (FPGA) ASICe were defined using
commercially available devices. Increases in FPGA densities
will allow partitioning the design into fewer FPGAs. The
functions of the three FPGAs are distributed a8 follows.
a~I~ FUNCTIONS
1. Host Interface Ho~t Interface & FIFO 427 (except the
FIFO itself) (ISA bus)
2. Video Dual-Ported RAM 512
3. Message Message Formatter ~ Se~lencer 514
Timing Generator 513
Interleave Encoder 522
Referring now to FIG. 29, a mo~ Ar residual video
converter (RVC) 400 in accord~nce with a preferred
embodiment of the present invention is shown. In this
embodiment, RVC 400 includes a video front end and sync
separator circuit 710, three video digitizer circuits 720, a
video data switch 730, a system image RAM bank 740, a last
frame RAM bank 750, a pixel comparator 760, and a pixel
change circuit 770 for identifying which cells 210 of a
composite page 200 of display information have changed pixel
information and the pixel change information.
Preferably, each RVC 400 operates under the co~ ol of a
micrG~Lo~e~-or (CPU) 780. CPU 780 has associated memory RAM
781 and memory ROM 782 and a direct memory Address
capability, and a DMA control and data bus 785. CPU 780
also has an encoder interface 783, for interfacing with an
~nco~r data bus interface 509a and ~o.-~.ol bus interface
509b (FIG. 25) And a host CPU interface 784, for interfacing
with a host CPU 425.
The RVC 400 may be configured to accept one of three
different types of input video ~ignals, namely monochrome,
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EGA/CGA, or VGA. For monochrome video s~nAl~, three BNC
connector~ 711 are provided to accept video feeds from three
~nA~penA~nt monochrome video ~ignal feeds. For EGA/CGA
video signal-, one type DB-9 connector 712 is provided to
accept one EGA or one CGA input video ~ignal feed. For VGA
video signal~, one type DB-15 oG~ e Lor 713 is provided to
accept a ~ingle VGA input video signal feed, such that the
signal may be analog or digital RGB signals. The~e
cQnnectorD and their pin cornectionD, are conventional and
known in the art. Preferably, RVC 400 includes A jumper or
6witch ~election (not Fhown) to select which ror nQctor
ou~yuL, c~s,.eD~o.,ling to the type of video signal feed, will
be input to the RVC 400. ThiD may be in.iol~orated into
front end circuit 710 or into a cable converter having a
6tAnAArd c~- .e--Lor on one end.
Referring to FIG. 29, the front end circuit 710 includes
circuits to separate the horizontal ~nd vertical Dync
DignalD from the input video signals. In the case of non
composite video inputD, the a~~G~Liate video connector pins
must be selected for provision of these same signals. When
RVC 400 is to be used to digitize a three color signal,
e.g., CGA, EGA, or VGA, the sync signals respectively fed to
the three video digitizers 720 are synchronous. Further,
front end circuit 710 may include an analog color matrixing
circuit to cG.-veL L color R,G,B signals into Y,U,V signals
for more efficient digital encoAing of the signals. When
the RVC 400 is used to digitize three monochrome video
signals, all three sets of sync signals may be asynchronous.
Alternately, each RVC could be configured with one type
of cQnn~ctor, e.g., cQrnector 711, 712 or 713, in a
dedicated manner for processing only the co~e~~onAin~ type
of video signal. This configuration would simplify the
manufacture of moAl~lAr circuits, so that different RVC 400~8
would be used for processing the different format video
signals. Thus, the user of the RVC 400 may select the
appropriately configured module and insert it into the
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printed circuit board for cGI.~e~Ling the received video
signal.
Referring to FIGS. 29 and 30, the three video digitizer
circuits 720 have the same construction and operate in the
came manner, and therefore only one 6uch circuit is
described. Each video digitizer circuit 720 receives from
front end circuit 710 one video ~ignal video input feed at
input 721, a vertical sync signal VSYNC for that video
signal at input 721v, and a horizontal ~ync signal HSYNC for
that video ~ignal at input 72lh. The vertical sync signals
are r~reA directly through circuit 720 to Gu~ 722v.
: A double-throw switch 723 i~ provided to configure
circuit 720 to ~Locrss digital video signals and analog
video ~ignals. Switch 723 may be manually configured or,
more preferably, configured by RVC CPU 780 by a~ iate
commands over the control and data bu~ 783. Switch 723 is
illustrated in FIG. 30 in the pocition for accepting and
digitizing analog video cignals. In this configuration, the
signal VIDEO at input 721 is pAsrr~ to a flash analog to
digital converter tflash ADC) 724 ~nd a digital threshold
comparator 725.
Flash ADC 724 accepts differential analog video signals,
for minimization of common-mode yL oul~d noise, where it is
locally OG~el Led to a single ended signal. The flash ADC
724 is preferably capable of operating at the 32 MHz VGA
video rate, and its ou~- may be asynchronous, and not
AerenAent on any timing clock. Thus, flash ADC 724 converts
the sampled analog signal VIDEO into, e.g., an eight bit
digitized ouL~u~.
In the preferred embodiment, the digital threshold
comparator 725 performs a combinatorial logic function that
maps the m-bit ou~u~ value of flaeh ADC 724 into an n-bit
pixel value, e.g., a two bit value. Thi~ renders the analog
signal VIDEO compatible with conventional video signAls that
are digitally tr~nsmitted. Digital threshold comparator 725
uses three ~GYL ammable binary thresholds that define four
.
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video signal amplitude regions. The binary tl~E~old valuec
are ~lGyL~mmed by CPU 780 at input 725. Thus, the two bit
digital signal assigns the analog input signal amplitude to
four levels. More particularly, the 8-bit digital value is
mapped into a quad level (8,9) modulated signal which has
two bits of data per Qignaling interval.
This is usually adequate when ylo~essing monochrome
signal6. u~wevar~ when ~o~ ing color 6ignalQ, this
results in four pos~ible values for each of the R,G,B, (or
Y,U,V) eignals. Hence, only cixty-four different colors may
be represented by the RVC 400. Further, assigning two bits
:to each of the R,G,B (or Y,U,V) 6ignals does not necess~rily
~eyLe~ent the best use of digital bandwidth.
In an alternate embodiment more than two bit~ could be
uQed. For example, R'3, G-3, and B=2 bits (and 6imil~rly
Y=3,U=3, and V=2 bits) m~y be used when a~v~,iate for the
video signals being ~L GC~ I -6~ . Al~o, when other
transmission system formats are used, flash ADC 724 digital
threshold comparator 725 should be ad~usted to provide and
an a~v~iate m-bit digital conversion rate and the desired
mapping of the m-bit digital value of the ~ampled analog
video data to an n-bit pixel data signal compatible with the
sy6tem.
- When the video signal~ VIDEO at input 721 are diqital,
typically a two bit ~ignal, switch 723 is placed in the
digital position (not shown), the video ~ignals VIDEO are
simply r~ through for further ~Lo~e_sing. Thus, in the
present embodiment, the two bit digital pixel data
representing the input video signals VIDE0 are available at
node 726. The ouLyuL of circuit 720 provides the pixel data
at ouL~ 726 to video data switch 730, along with the
vertical sync r--l r~~ VSYNC at o~ L 722v, the horizontal
sync p~ er HSYNC at ouL~uL 722h, and the phase locked
horizontal sync pul~es PHASE ~ n at GuL~uL 722pl.
It has been realized that simply sampling the video
signal6 at the pixel frequency is not likely to be
, _
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~ufficient to digitize the incoming video data at the proper
sampling rate and phase. Sampling the analog video ~ignals
at a frequency different from the pixel rate of the video
~ignal would result in aliasing the frame of pixel data and
its sync pulse resulting from the difference between the two
frequencies.
Sampling near the middle of each pixel minimizes any
threshold ambiguity. HOWeVeL~ simply match~ng the sampling
frequency and the pixel rate frequency does not guarantee
this will occur. Conseguently, in accordance with the
current invention, each video digitizer circuit 720 al~o
contains two phase locked loop (PPL) circuits to meet the
two criteria of frequency matc~;~g and mid-point sampling
(collectively referred to as 'pixel phase lock~).
The video signal at input 721 can be arbitrary.
Therefore, it is impossible to determine the pixel clock
freguency from the video data alone. However, the nominal
horizontal scan rate and exAct number of pixels n per
horizontal line are known from configurAtion information
supplied to RVC CPU 780. As noted, each display has a
defined number of cells per row and a defined number of
pixels per line in a cell and the video ~can line used to
display a line of pixels across the video screen is known,
e.g., 63.5 ~s. This information may be used to generate a
divisor value for a ~divide by n~ counter 727, which value n
is provided by CPU 780 at input 728. The ~divide by n~
counter 728 is thus loaded with a ~byL~mmed divisor n such
that n is egual to the number of pixels per horizontal video
scan line of the video screen 317 (tot_l pixels, not just
visible pixels). The buL~uL from counter 727 may be a
pulse, since only the rising edge of the signal is used for
phase lock ~u~G~es.
The 1~A~ ing edge of the horizontal sync pulse HSYNC input
at 721h is PA~ through an adjustable delay circuit 728,
and then is PA~ to one input of a first phase comp_rator
731. The other input to phase comparator 731 is the output
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of divide by n counter 727. Phase comparator 731 pro~l~res
an error ~ignal that ~e~.Lsents the phase difference between
the delayed pulse HSYNC and the ouL~uL of counter 727. This
error signal is then used to adjust the frequency of a
S voltage ~o,.~.olled oscillator (VC0) 732 ~o that sampling
frequency matching ph~se lock is maint~neA. The error
signal is amplified a~L~iately such that VC0 732 GuL~L
frequency i8 driven in the direction to minimize the
~ampling frequency ph~se error.
This phase comparator 731 is preferably a state-machine
~variety, ~ince only the rising edges of the incoming ~ignals
are used for phase comparison. The phase comparator 731
al80 may in~o-~ol~te sample-~nd-hold circuitry to minimize
VC0 732 ouL~uL frequency ripple, while maintaining an
acceptably fast loop response. The Motorola MC145159
Frequency Synthesizer IC in~o~o-ates a sample-and-hold
phase detector plus ~. Gy~ ammable counters, and may be used
to implement much of the PLL circuitry of video digitizer
720.
The G~L~U~ of the VCo 732 may not ne~e~s~rily be a
precise 50/50 duty factor. Therefore, the oscillator is
designed to run at twice the pixel frequency, and its ouL~uL
is fed into a ~divide by 2~ flip-flop 733. The ou~L from
flip-flop 733 is a uniform square wave that is the sample
clock rate at output 729 and, as noted, is input to divide
by n counter 727.
The phase ~Gl.L.ol circuitry described above thus assures
that the pixel ~ample clock at ~u~uL 729, which i~
generated by the RVC 400, matches the incoming video pixel
data frequency at o~u~ 726.
A ~?~onA phase comparator 734 is used to compare the
pixel phase with the sample clock at ~uL~u~ 729. Thus, one
input is the digital pixel data at node 726, and the other
input is the sampling rate ou~uL from divider 733. The
GuL~ from the pixel phase comparator 734 is used to
control delay circuit 728, which is preferably line~rly
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adjustable. The delay may be implemented as a ~imple
variable RC circuit, ~ince only ~1/2 pixel delay must be
proA~c~A. When the delay is ad~u~ted by the pixel pha6e
comparator 734, the pha~e reference for the pixel frequency
is changed. This, in turn, proA~ceC a comparable ~hift in
the phase of the pixel ~ample clock at ouL~uL 729.
~referably, phase comparator 734 al~o i6 a state-machine
variety to compare only ri~ing edges of the input 6ignal~.
However, ~pecial consideration must be made in pha6e
comparator 734 to account for the arbitrary nature of the
incoming video ~ignal data. In this regard, phase
: comparator 734 mu~t inco~polate a Fample-and-hold type
circuit, because pha~e error information may be produced by
only a dozen or 60 pixelc (one character), while the ou~
~ignal must be held stable for an entire video frame. The
response of the pha~e control loop must take into accou.,L
the fact that phase error ~ampling may occur only once per
video frame (e.g., every 16.7 ms).
Referring to FIG. 29, the ouLy~Ls from the three video
digitizer circuits 720 connect to a 2-bit video data 6witch
730. Switch 730 is preferably operated in rotary fashion,
60 that each video input (illustrated as number~ 1, 2, and
3) is connected in turn for one video frame of pixel data.
As a result, each video ~ignal input is ~ampled for changes
once every three frames, for a ~ignal transmission latency
of about 50 ms. In the case of asynchronous monochrome
inputs, the average latency may be slightly longer, and is
pPnA~nt upon the frame phase relationships between the non
gen-locked video cignal~.
The high sampling rate of each video 6ignal input assures
that minor 6creen changes (e.g., blinking characters) are
rapidly detected and broadcast quickly enough to maintain
the desired visual effect on the video screens 317 of the
deco~Prs 316.
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Switch ?30 also may be co..Llolled by CPU 780 to conn~ L
selectively to one particular video input more or less
frequently than the other inputS.
The ~u~uL of switch 730 is a ~tream of pixel data
correspon~ng to one current frame of display information.
This pixel data is pAsr~~ to a ~ystem image~ RAM bank 740,
a ~last fr_me~ RAM bank 750, and a pixel comparator 760.
The pixel comparator 760 has as inputs the ~tream of pixel
dat~ from the ou~u~ of video data switch 730 coL.e~lo~ ing
to the one ~u.. e.. ~ frame of display information for a given
video signal, the pixel data ~G..~-l,o~ ng to the last frame
-of display information for the given video eignal, which was
previously stored in last frame RAM bank 750, and the pixei
data CO~LC ~OI~A;ng to the frame of display information that
is currently displayed for the given video signal, which was
previously stored in sygtem image RAM bank 740. The pixel
comparator 760 uses these three inputs to test for changes
in ~cce~6ive frames.
The system image RAM bank 740 i~ a memory device (or an
area of memory in a large memory device) contAining a cache
of pixel data corresron~ing to the images displayed on a
system video screen 317 for each particular portion of
display information that i6 transmitted by the three video
signals inputs. The cached pixel dat_ match the ~net pixel
change data~ previously transmitted to the encoA~r 312,
-i.e., the pixel data for displaying the ou~L display
information ~G~ or.ling to the video ~ignal~ VIDEO and any
6ubsequent messageg providing update data (pixel change
d_ta) for updating the ou~- display based on differences
between F~cces6ive frames of the ~ource VIDEO. The net
pixel change data also is stored in a picture memory of each
remotely located decoA~r 316 and is used to generate the
G~ - images displayed on a video ~creen 317. As expl A; neA
in more detail below, the pixel data cont~in~~ in RAM 740
for any given frame is only updated when update dat~
messages are broadca~t, e.g., to or by an encoder 312,
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thereby to update the pixel data di6play information held in
the LLOye_Live memories of the remotely located ~coAPr~ 316
and system image bank 740.
The last frame RAM Bank 750 i~ a memory device (or an
area of memory in a large memory device) contA~n~n~ pixel
data for the last frame of display information for each
input video signal- The ~G~eOponA~ng pixel data for each
~last~ frame of di6play information in RAM 750 iô completely
updated with the ~current~ pixel data for that frame (from
video data switch 730) a~ the ~uLLe.. L~ frame pixel data is
compared with the COLLeSPOn~in~ prior last frame and the
- sy~tem image frame.
The sy~tem image and last fr~me RAM banks 740 and 750 are
organized with byte-wide (8-bit) data paths. Thio allows
the dAta to be read and written with a 120 ns cycle time at
the VGA data rate. Buffering and wider memory organizat$on
may be used, if necer--ry, to further increase cycle time.
Once the video data switch 730 has selected a new video
6ignAl input c~nnrl, the last frame RAM Bank 750 is
operated in a ~Read-Modify-Write~ mode. This allows the
contents of the RAM 750 to be read into pixel comparator
760, while new data from the ou~u~ of video switch 730 is
written into RAM 750 later in the same cycle.
The pixel comparator 730 procesF~ the three input frames
of pixel data to determine if a valid pixel change has
G~1Led. If the current frame pixel data (2-bit value)
matches the last frame pixel data, and these data are
different than the corre~pon~n~ pixel data retrieved from
the 6ystem image RAM bank 740, then a change over two
~uccessive frames has been detected and it is considered
that a valid pixel change has been detected. If, instead,
the current pixel data does not match the last frame data,
- then it is considered that either the last frame or the
current frame cont~ne~ an error (noise) or it does not
~G~e~Gl~d to a valid change. In other words, the system
waits for cGLLe~lo~ n~ pixels in two successive frames to
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be different than the C~1L~ O~ ng pixel in the sy~tem
image frame before AeclAring that a valid pixel change has
G~ d .
Even ~ho-~gh the RANs 740 and 750 may be delivering byte-
wide data, each set of corre~ponA~ng 2-bit pixelc is
preferably compared ~nAepenAPntly. The two bit~ e~ Qnt
four possible different inten~ity levels. The o~-~uL from
the pixel comparator 760 is a two bit value representing the
absolute value of the pixel intensity chAnge. The ouL~L is
pAcreA to pixel datA ch~nqe circuit 770 for ~oce~sing and
identifying pixel change data that i8 to be provided to an
encoA~r 312.
The foregoing comparison algorithm i~ highly immune to
noise, eince only stable (but changed) pixel data is flagged
as changed. If greater noise immunity is desired,
additional ~next to last~ frame RAM device~ could be used
and the algorithm modified to wait for more than two
con~e~tive frames to have the same changed pixel data
different from the system image.
Referring to FIG. 29, pixel data change circuit 770, in
the preferred embodiment of the present invention includes a
cell change RAN device 771, a change thre~hold comparator
772, a cGl.L.ol logic device 773, a cell addre~s change
first-in-fir~t-out (FIFO) device 774, and a binary adder
775.
The cell change RAM 771 is a small RAN memory bank (or an
area of memory in a large memory device) partitioned into
cells 776 such that each cell 776 ~G~ ronA~ to one cell
210 of a video screen image of display information and each
cell 210 (FIG. 12) can display a di~play character, e.g., an
AlFh~m-meriC or a~cii character. Each cell 776 contains an
8-bit binary ~alue representing the sum of the absolute
value of the inten~ity level change of the pixels in the
cell. Thi~ ~um is referred to as a ~weighted cum~ because
it reflects the magnitude of the intensity level difference
of the pixels, and not just the number of pixels that have
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changed. In other words, a larger intensity change is more
6ignificant than a ~maller intensity change and the
magnitude of the change is weighted accordingly.
In the present invention, there are eno~gh cells 776 in
cell change RAM 771 to compare each cell 210 of a video
frame of di6play information transmitted by the input video
signals, and thus RAM 771 need only be 1/16th the size of
either system image or last frame RAM bank 740 and 750.
Preferably, RAMs 740, 750 and 771 are discrete memory
devices with DMA access 80 to minimize the time required to
read and write data.
: The cell change RAM 771 is operated in Read-Modify-Write
mode. The contents of one cell 776 are read and numerically
added, at binary adder 775, to the pixel change value that
is supplied by the pixel comparator 760 for the
co~e~lo,.ling cell 210 of digplay information. The weighted
sum is then rewritten into the same cell 776 in the same
cycle. Thus, each cell 776 acts as a cumulative counter
that is incremented by the pixel change value from
comparator 760 co~.e~l~G~ g to the absolute value of the
intensity change. The data in a given cell 776 of cell
change RAM 720 is reset to zero when the RVC CPU 780 or the
encoA~r 312 broadcasts the pixel change data co~es~,~nl;ng
to the given cell 776 to the encoder 312 or decoAer 316
respectively.
In a preferred embodiment, the corresponAing cells 210 of
the current video frame, last video frame and pixel map for
a complete page 200 of display information are compared, one
cell at a time, and the corrc~o..ling cells 776 are updated
with pixel change values. At the end of each complete frame
. 200, each cell 776 for that frame 200 contains a binary
value that represents the weighted sum of the absolute
values of the number of pixel data changes in the
corresponding cell 210, since the cell 210 was last updated
3S and the cell 776 count was last reset. Each cell 776 thus
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holds the weighted sum of 128 pixel change values, since
each cell 210 contains 128 pixels.
For example, referring to FIG. 29, no pixel changes have
been detected for the cells labeled 776a and 776b. Howe~e.,
7 weighted pixel counts have been detected for the cell
labeled 776c in row 1 column 3. The cell labeled 776d in
row 2 column 2 holds the value FF, indicating that at least
255 weighted pixel changes have been detected. Since each
cell 776 only holds an 8-bit value, the binary ~dder 776
must ~clamp~ the total at FF, and not allow the weighted
count data to rollover. Note, the maximum possible weighted
sum for a cell having 128 pixels and four intensity levels
(two bits per pixel) is 512.
The change threshold comparator 772 i8 a binary
comparator whose threshold is ~-Gy~mmed by the CPU 780.
Whenever a cell change value, i.e., the weighted ~um ou-~u-
from adder 776, reaches that preset count t~reshold~ the
cGn~ol logic device 773 is actuated to load the address of
the cell 210 ~ol~c~,o~ g to cell 776 into the cell change
address FIFO device 774. The comparator 772 is enabled only
during the comparison of the last pixel 220 of each cell 210
(i.e., the lower right-hand pixel) to minimize multiple
detection of cells 210 with substantial changes.
During periods of minimal change activity, the CPU 780
may ~1 G~ am the count threshold ~s low a 1, thereby enabling
it to detect single-level single-pixel change~ in a given
cell 210. However, during periods of high system activity,
or during rapidly changing video frames, the count threshold
may be selectively ~og.ammed at a level high enough to
reduce mess~ge traffic to an acceptable level and still
detect significant changes in the video information that
will provide an accurate display to the user.
The cell address data that i8 contained in cell change
address FIFO 774 is later used by the converter CPU 780 to
identify those cells 210 with cumulative weighted pixel
changes at or above the predetermined count threshold. In
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this regard, the CPU 780 may simply AccqF~ the FIF0 774 to
determine the cell 210 addresse~ correrponAing to cells 776
with above threshold changes, rather than ~equentially
reA~i~g every cell 776 in the cell change RAM 771.
Further, by loaA~ng the cell change values into the FIF0
774 along with the cell 210 addresses, the converter CPU 780
can make further priority decisions regarding the order in
which cell 210 pixel change data is broA~ca~t.
The cG,.L.ol logic device 773 i~ ~e_~G..sible for
coordinating and ~ynchronizing the actions of the RAM banks
740 and 750, pixel comparator 760, threshold comparator 772,
and cell change address FIF0 774. It also interrupts the
CPU 780 at the a~G~iate time to initiate retrieval and
manip~lAtion of pixel data.
RVC CPU 780 is responsible for configuring all the
various ~G~ ol register~ within the RVC 400 and for
retrieving and manipulating the pixel data in the indicAted
or identified cells 210 with changes. After a complete
video frame has been digitized and compared, the CPU 780 is
interrupted by the cG,.~ol logic 773. The CPU 780 then
performs the following functions: (1) Addresses of cells
210 with corresponAing cells 776 having counts at or above
the predetermined count threshold are read from the FIF0
774; (2) Pixel data for changed cells 210 corresponAing to
cells 726 in RAM 775 are transferred to the CPU RAM 781 from
the system image and last frame RAM banks 740 and 750 (this
dual transfer o~ because the 'current' frame pixel data
has by this time already been written into the last frame
data via DMA bus 785); (3) new pixel change data are written
from the last frame RAM bank 750 into the system image RAM
- bank 740 (via DMA bus 785); (4) Updated cells 776 in the
cell change RAM 771 are zeroed for detection of new change
- data and non updated cells 776 are left as incremented, if
at all, ~uch that pixel changes in subseguent frames may
cause such cells to excee~ the estAblished count threshold;
and (5) Message(s) cont~ining update data, i.e., the pixel
,
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change dat_ from the ch_nged cells, are prep_red for
broaAca~t to the system encoA~r 312, for distribution to
remotely connected A~coAPrs 316 during sampling of the next
frAme of display inform_tion.
The CPU 780 should be f_st eno~gh to handle modest
amounts of video changes during the vertical blanking
interval (1.4 ms). ~ho~lA the CPU 780 become overloaded
with ~,~Lo~re~ ch_nges, the cG,.LLol logic 773 m_y be
configured to insert blank video frames between actu~l frame
comparisons, thereby allowing the CPU 780 to access the RAMs
740, 750 and 771 for extenAeA periods of time. The only
side-effect of inserting blank frames is a temporary
increased latency for broaAs~st of pixel change information.
The CPU 780 software should be capable of detecting
certain special case video changes. For example, a screen
going completely blank ~ho~lA be detected and ~n~o
without reguiring direct messaging of each pixel.
The CPU RAM 781 preferably cont_ins executable code,
p~Gy~ m data, and pixel data. Pixel data are temporarily
moved from the system image and last frame RAM banks 740 and
750 via bus 775 to the CPU RAM 781 for generation of pixel
change data messages as expl A i n~A below.
In a preferred embodiment, RVC 400 is configured with an
interface 783 that co-r-~Ls to an encoder 312 ViA two buses:
a mono-directional data bus 783d and a bi-directional
~GIl~ ol bus 783c. This allows the RVC 400 to format
complete messages, and transmit each message to the encoADr
312 when instructed to do so by the encoAer 312 or host CPU
425. By completely formatting the messages, and notifying
the encoA~r 312, the processing burden on the encoA~r CPU
(not shown in FIG. 30) is ~ubstantially reduced. This
results in increasing the mess~ge handling capacity and
thlo~-Jl.l ~L of the encoA~r 312 and its ability to distribute
more display information and update data more quickly to the
plur~lity of decoders 316.
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The ~n~oAPr interface 783 typically receives polling
signals from an PncoA~r 312 to determine whether an RVC 400
has any pending m.~ a~. At the poll, the RVC 400 empties
itC ohL~L message gueue into an input message gueue for the
encQA~r 312. The polling i~ preferably performed at a
configurable rate (nominally .25 sec).
Further, the RVC 400 is preferably ~G.-Llolled by host CPU
425 and includes a host computer interface 484. The host
CPU 425 provides the RVC 400 with conL ol information, over
a bus 784b. From the pe,D~_Live of the ~ncoAer 312,
messages originating from RVC 400 appear to be updates to a
: pixel-based video or graphic tile rather than a character
cell-based alphamosaic tile.
The host CPU 425 can, for example, tell the RVC 400 to:
(1) generate a test image, (2) enable/disable sampling of a
specific video signal input, (3) set the input sampling
interval (nominally .25 seconds), (4) assign a tile
identification code to messages derived from a specified
portion of a video image, (5) assemble a ~ e-.L complete
image derived from a video input (rather than ~ust the
changes), and (6) empty its ouLyuL queue.
There are two types of user requests for an ouL~
display to which the RVC 400 is adapted to .e_~OI.d~ a new
page delivered by the information vendor, and an old page
requested by a new viewer.
For a new page, RVC 400 creates and sends a blank ~creen
message and thus resets the 'System Image~ and ~Last Frame~
RAM banks 740 and 750 for that video signal to all blank~.
As the new portion of display information is received from
the information vendor, it may be sent to the enco~Pr 312
for transmission to the decoder 316 and video screen 317.
There i~ a 3-frame latency delay that is insignificant when
- compared to the time required for transmitting the new
display information from the information vendor site over a
i5 telephone line to the client (i.e., subscriber) ite.
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When a new viewer reguest~ a portion of di~play
information that ic ~LeuLly stored in the ~y~tem imAge RAM
bank 740, the RVC 400 immediately transmit~ the entire
portion ~s an update me~eage to the enoo~r 312 for
transmission to the ueer reguesting the display. This
latency is le~s than one frame time. Thereafter, the new
user will receive only update data messages for that page in
the same manner as the existing users.
It should be understood that more or less th~n three
10 - video digitizer circuit~ 720, with a~G~Liate change~ in
the correspon~ing switch 730 and dat~ ~G~e6sing circuits,
- could be used in other embodiments for ~rc_e-Fing more or
less than three discrete video 8 i gnA l ~ and composite, non
composite or both composite and non composite video signals
using the s me residual video converter unit 400.
Advantageously, the present invention provides for a
reduced time to ~e~o,.d to a user's reguest to view a page
or record of di~play information that is already being
viewed by another user by caching the ouL~uL display at the
client's site, and providing the complete ou~uL display as
change information to the new user and continlling to provide
only relative changes in each of the plurality of c~rhe~
portions to other existing users of that display
information. Further, the invention ~G~7~e~ video
information in a manner thAt is essentially transparent to
the user and does not add significantly to the time required
to display a new page of information and re~l~c~C the burden
on an enco~r type device at the subscribers site. Further,
because each converter can be made a8 a module, ru~Gl Ling
additional video signal sou ~e_ can e~sily be ob~ine~ by
~ing more modules, without significantly bur~ning the
PncoA~r device.
Referring to FIGS. 11, 16 and 26 to 28, a A~coA~r 316 in
accordance with a preferred embodiment of the present
invention i8 ~hown.
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In the y~ .nt invention, and with reference to FIG. 26,
the AecoAer 316 of the present invention may be resident
inside a desk interface unit (DIU) 321, which i6 adapted to
handle ~coA~r functionality, including mouse 319' h~n~ljng,
keyboard 319 and message retransmission/flow redirection,
and to drive 6everal video screens 317, and which may be
po6itioned for the use of one or more than one user on one
or more trading disks 320. Preferably, a single DIU 321 is
designed to ~uy~OlL up to four individual users and thus
includes coT~lQctor~ for four keyboard~ 319, four mice 319~,
and four color video screens 317. Alternately, the four
color monitor ports may be configured to drive a total of
twelve monochrome video screens 317.
As ~irC~ e~ above in connection with FIG. 11, the
~eco~r 316 may be installed as a ~eparate printed circuit
board assembly inside an enclosure also housing the video
screen 317. Thi~ provides for a mo~vlar 6y6tem whereby each
video ~creen has a unique di6play identification code stored
in memory of the ~eco~r 316, and thereby e~h~nces
restriction of secure display information to authorized and
permitted video screens.
Regardless of its location, each ~ecoA~r 316 (or DIU 321,
and herein collectively referred to as ~decoder 316~) is
provided to connect each user's input devices 319, 319' and
video screens 317 to both the DV bus 314 and the cGr.L~ol bus
318.
Referring to FIGS. 16 and 27, a preferred emhoAiment of a
decoder 316 is shown. The Analog Front-End circuit 610
co~nects to the DV bus 314 and (1) receives the DV bus
signals and maintains proper impedance match~ng; (2) post-
- egualizes the DV bus analog signal; (3) double-end clamps
the signal for threshold setting; and (4) converts the guad-
- level signal into a 2-bit binary signal.
The Analog Front-End circuit 610 provides a high
impe~ce input to maintain ~L~e~ transmission line
impefiAnce matrhing; Overvoltage protection also is provided
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to make ~-coA~r 316 tolerant of electrical disturhA--es.
The DV bus ro~YiAl cable 314 will eYhihit freguency
A~p~nA~nt loss and group delay (~isper6ion) characteristics.
The magnitude of these effects ~epP~A~ upon the length and
type of cable selected. For example, RG-59U will exhibit
much higher loss per unit length at high frequencies than
will RG-8U foam core cable. The Analog Front-End circuit
610 is thus preferably designed to accept widely varying
signal levels and high frequency rolloff, ~epenAing upon its
lo - location along the DV bus 314.
- Some form of additional adaptive equalization may be used
: to CG~e~ for loss and dispersion effects. This ~ignal
egualization improves the error performance and noise
toler_nce of the system.
To ~on~e~ the quad-level analog signal received from the
DV bus 314 into a 2-bit binary signal, detection thresholds
are established by the analog circuitry. By double-end
clamping the DV bus packet d he~Pr H signal, the Analog
Front-End circuit 610 can determine the upper and lower
- signal level~ and the three signal thresholds as described.
The Front-End circuitry 610 then CGI~Ve~ L8 the quad-level
signal into 2-bit binary input signal for processing by the
Packet Reception ASIC 622.
- The Analog Front-End circuit 610 al80 may be adapted to
-receive, r~cQn~ition, and repeat the DV bus messaging data
if the received signal level falls below a predetermined
threshold. This repeater function could be bypa~ by a
mech~nical rel~y 6hould signal levels be adequate, or if the
d~coAPr 316 is inoperative. The ~eco~r 316 also may
reconAition and repeat the television ~G~,am information
~ignals on the DV bus 316 by using information contained
within the message he~Pr H.
The Packet Reception ASIC 622 receives signals from the
Analog Front-End circuit 610, and (1) ~eco~es the heA~er H
to identify the beginn~ng of each packet d, ~Gy,ams the
dibit threshold levels, and determines the interleaving
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depth; (2) creates horizontal and vertical sync p~ es for
use by the Video O~L~uL Circuits 660 and TV n~CoAPr 670; (3)
performs error detection and ~G~ .e_Lion (EDAC) on each data
packet d received; (4) compares each data packet against the
stored ~reception key~ information (a display identification
code or an information identification code) to determine if
the dat~ requires further ~,Gce~sing by the AecoAPr CPU 690;
(5) inte,~u~ the AP~oAPr CPU 690 at the beginn;ng of
vertical bl~nking ~o that updates may be made to the Video
RAM 662 and Attribute RAM 664 of the Video O~L~L Circuit
660 (see FIG. 28); and (6) loads accepted data packets d
- into the Message Buffer 625, and inte,,uyLs the A~co~r CPU
690 for further ~,o~e~sing.
The incoming datA is first ~tored in the Interleave RAM
642. The Packet Reception ASIC 622 then reads the data with
the axes rever~ed, and performs the EDAC function. The
Packet Re-e~Lion ASIC 622 AecoAes the header bits to
determine the interleave factor to reconfigure the
interleave structure on a packet-by-packet basis. As with
the encoAPr circuit, the AecoAPr ASIC may be implemented by
any number of circuits and stru~L~Les, so long as the
described functions are performed, which is within the
abilities of a person of ordinary skill in the art.
The Message Buffer 625 is a dual-ported ~tatic RAM device
that can be accos-~d by both the Packet Reception ASIC 622
and the AecoAPr CPU 690. Arbitration is provided by the
conventional RAM c~..LLol circuitry within the Message Buffer
625 to prevent simultaneo~ accees. Messages that have been
decoded and error cGLLe~Led are compared against hardwired
or previously enabled e~e~ion key~, which also are stored
-- in the RAM of Message Buffer 625. Those messages that match
.eceyLion keys are then loaded into the RhM of Mes~~~e
- Buffer 625 from the Packet Recc~Lion ASIC 622. Once a
complete message (that matches a reception key) has been
loaded into the MessAge Buffer 625, the CPU 690 is notified
via an interrupt from ASIC 622 over bus 623. The CPU 690
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may then int~Lu~ its normal ~Loylam operation and retrieve
the complete message from the Message Buffer 625.
In the preferred embodiment, Aeco~r CPU 690 i6 a 32-Bit
P~d~ceA Instruction Set Computer (RISC) CPU having a
S suitable ~Gy.am for cG.. ~olling ~e~oA~r 316 operations.
One such device is the LSI Logic Model No. ~R33000 CPU,
which is capable of exe_~Ling an average of ~lightly less
than one instruction per clock cycle, providing an execution
~peed of approximately 20 million instructions per FecQn~
- (NIPS). The CPU 690 is preferably capable of both high
speed ~Gy-am execution, and high speed data transfers via
its two ~ Gy~ &mmable direct memory access r~nn~1~ DMAo and
DNAl. It is responsible for (1) collection and processing
messages that match le_c~Lion keys; (2) responAing to
procesFe~ messages by specific actions and modification of
displayed information; (3) DMA transfer of video and
attribute information to/from the various video display
memories; (4) delivery and collection of data to/from the
C6l.L~ol Bus Interface 626; and (5) collection of input
information from ~eyboards 319 and mice 319'.
In an alternate embodiment, the functionality previously
described may be accomplished by a lower performance 16-bit
CISC CPU such that a ~ingle A~COA~r 317 may contain a CPU
690 which is a type 80188 CPU, thereby reducing the cost of
~ the d~cQA~r 317.
The CPU 690 has an associated ROM device 692 and an
associated ~.~y,am and Data RAN device 694. RON 692
preferably contains a small amount of ~oy~am ROM including,
for example, the basic boot code, and rudimentary ~Gy.am
functions to allow the ~co~r to perform self-test and
communicate with the host computer 425 via the DV and
~G-,--ol buses 314 and 318. Only basic operating functions
are executed from ROM 692, thereby allowing systcm
flexibility with executable code downloaded via the DV bus
314. Thus, upon power up, the CPU 690 will begin execution
of the ~Gy~&m stored in ROM 692 first performing self-test
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of all circuitry, then Acknowledging the 6tatus to the host
425 via the ~G-.L ol bus 318.
RAM 694 contains both executable code (ingtructions) and
~oy~am data. In this embodiment, the bulk of the
executable code for A~coA~r 316 i~ ~tored in the RAM 694,
thereby providing maximum flexibility for reconfiguring the
~ecoA~r operation. Alternately, of cour~e, the entire
~-~m code could be contained in ROM 692. Upon interrupt
by the Packet Reception ASIC 622, the CPU 690 operates to
DMA transfer the incoming message from the Message Buffer
625 to the ~.oy~m and Data RAM. The CPU 690 may then
resume normal ~Gy.am execution, and perform interpretation
of the newly received message at a later time.
In one embodiment, a Ae~o~r 316 using a 20 MIPS
~4~ ' 7-Qr 690 can ~ed~aw a complete bit-mapped graphics
image (2 bits/pixel) in approximately 165 ms. The DV bus
314 can deliver a full screen graphics image in
approximately 32 ms. Because the encoA~r 312 will not
repeat a DV bus message until its refresh period (nominally
200 ms) has elapsed, no dec~Aer 316 will lose a message due
to overflow even under worst-case cond;tions.
Referring to FIGS. 27 and 28, the decoder 316 preferably
contains a number of identical video ouL~u~ circuits 660.
Four are illustrated in FIG. 28. All video signals are
preferably delivered to a single 60-pin connector 668 and
conventional ouL~L cables may be attached to connector 668
to drive four or twelve video screens.
Each video ~uL~uL circuit 660 (only one is described)
accepts bit-mapped pixel data from the CPU 690 and displays
the pixels on associated video screens 317 (not shown in
-- FIGS. 27 and 28). Functions guch as par.ning, scrolling,
bl;nking and insertion of live TV are ~ ' performed by the
- video o~L~uL circuit 660. A single vic -~ ouL~L circuit 660
can provide signals to one VGA color video screens, or to
three VGA scan rate monochrome video screens. When
configured for three monochrome video ~creens, all three
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video ~creens may contain different information, with
separate tile~ and sync ~ignals. How v6~, limitations
within the illustrated architecture of video uu~uL circuit
660 ~.e~nL use of the pAnn~ ng and scrolling features when
configured for non genlocked monochrome video screens.
Referring to FIG. 28, the video RAM 662 is preferably
configured as 512R words of 32 bits each. During the active
video time (non-blA~ng), the video ~uL~ circuit 660
reads pixel data from the video RAM 662 on a realtime ba~i~.
-:At VGA scan rates, the video RAM 662 must supply a 32-bit
~word to the video data register 663 every 120n~.
: The address bus 661 driving the video RAN 662 is
multiplexed between the video ASIC 665 and the CPU 690.
During active di~play time, the video ASIC 665 ~G~,~rol8 the
address bus 661. During vertical blA~;ng the CPU 690 ~as
cG,.L.ol over the addres~ bus 661. The Packet Reception ASIC
622 provides an interrupt to the CPU 690 to notify it that
vertical b~ g has begun, and commence any required data
transfers by the CPU 690.
The CPU 690 utilizes the time during vertical b~Anking to
load new pixel data into the video RAM 662 via DMA transfer.
When the video ou~ circuit 660 i~ configured to drive a
single color video screen, all the video data co~e_~ond~ to
~the s me video screen, and the CPU 690 may simply overwrite
-~old pixel data with new data. Howeve~, when configured to
-drive three monochrome video screen~, the pixel data
cont~ine~ in a single 32-bit word may relate to three
indep~n~Pnt screens. Therefore, the CPU 690 must first read
the pixel data from the video RAM 662, modify the bit~
relating to the updated tile, and rewrite the pixel data
into the video RAM 662.
Assuming a 120ns cycle time on both the video RAM 662 and
rLo~am and Data RAM 694, the CPU 690 can transfer
approximately 6000 words during a single vertical retrace
3s period (assuming negligible interrupt latency and DMA ~etup
time). This is sufficient data to update approximately 188
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cells on a single color video screen. Read and write
transfers may be pipel~ned, so that the read ~nd write data
may not relate to the same cells on the screen. This
reAl~ce the number of cell~ that c~n be updated on a single
monochrome ~creen during the retrace period to a~oximately
94. Even so, the dat_ transfer bandwidth between the CPU's
~LGy~m _nd Data RAM 694 and the video RAM 662 far ~Yc~eA~
the ability of CPU 690 to ~ecoAe messages and format pixel
data.
The video data register 663 receives a 32-bit word from
the video RAM 662 approximately every 120ns during active
video time. The ou~u~s from register 663 directly drive
the pixel multiplexor 666. Alternatively, multiplexor 666
mAy be an integral part of register 663 with selection
performed by tri-ctate ~nL.ol.
pAnning and scrolling of display information is
cG..~olled by the video ASIC 665, and may be implemented by
a combination of video RAM 662 _ddress manipul_tion and
multiplexor 666. Implied movement may be performed by
reAAing the ctored data and rewriting it in the memory in
the new addresses (one pixel at a time) or by adjusting the
address when rPAAing stored data for display.
The video palette DAC 667 is ct~AArdly available and
provides RGB o~L~uL signals based on a ~G~.ammable color
lookup table. It contains a 256 element lookup table, where
each entry contains an 8-bit value for each of the three
color ouL~- signals. The table is ~G~L~mmed directly by
the CPU 690 using data bus 661 and address bus 661A.
The video palette DAC 667 is capable of o~L~u~Ling the
three analog video signals (RGB) at VGA pixel rates
-~ (approximately 32 MHz). The values for each Oh~U~ are
determined by indexing the internal RAM array of pallet DDC
667, based upon the address supplied by the video data
multiplexor 666. The three ouL~u~s can represent RGB
signals for a single VGA color video screen, or can be used
independently for three monochrome video screens. The video
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palette DAC 667 al60 can also be used to combine sync
~ignals with the video G~ LS, thereby providing composite
video, if desired.
The video 6witch~n~ circuit 680 ~lll~ws the ADcoAPr 316 to
feed alternative video input signals through to the video
ouL~Ls from the ~Poo~Pr 316. This swi~chi~ is under
realtime ~Gy~am ~o.,L~ol. In ~ddition, the Video Switch;ng
680 provide~ ~ high speed video 6witch to select either the
palette DAC 66? ouL~u~s or ouL~uL8 from an optional TV
~AecoA~r 670. Sign~ls provided by the video ASIC 665 cG.. ~,ol
.the actuation of these video ~witches, based upon the TV
- signals ~elected, ~nd the beam position on the video screen
317.
T~AepenA~nt ~ttributes may be assigned for each cell on
the video screen(~). Therefore an Attribute RAM 664 is
included for storage of these attribute values. Typic~l
attributes include blink, highlight, cur60r, p~n~ing~
~crolling, etc. As with the video RAM 662, the CPU 690 may
update the Attribute RAM 664 during the vertical b~A~ki ng
interval by enabling its address A ~nd data D drivers.
The video ASIC 665 reads the Attribute RAM 664 during
active video time once for every horizontal cell location
(approximately every 240ns). The video ASIC 665 also
coordinates the display of video information from the video
' RAM 662 and Attribute RAM 664. Once the CPU 690 has loaded
--the nece~cAry data into RAMs 662 and 664, the video ASIC 665
will continuously display the stored information without the
intervention of the CPU 690.
The video ASIC 665 ~ 016 (1) re~ing dat~ from the
video RAM 662, and clor~;~g it into the v$deo data register
663; (2) r~ing dat~ from the Attribute RAM 664, ~nd
clocking it into its internal register6; (3) co,lLlolling the
video multiplexor 666 Felection of data input to the video
DAC 667 (ne~es6~ry for pa~n~ng); (4) generating ~G~e~
horizontal sync, vertical ~ync, and bl~n~1~g signal6 for use
by the video palette DAC 667 and video ~witc~i~g circuits
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680; and (5) generating cv..L~ol signAl~ for actuation of the
video switching circuit 680 to display realtime television
y~Gy am information s;~nAl~ and ~tored financial market
information. Video ASIC 665 also may be implemented by any
number of circuits and structure so long as the described
functions are performed, which is within the abilities of a
person of ordinary ~kill in the art.
Referring to FIG. 27, the cG,.Llol bus interface 626
connects A~coA~ 316 to a multi-point twifited-pair cG~ ol
bus 318. RS-422 or 485 drivers (or similar interface
devices) are used to ~end and receive differential ~ignals
: on ~o..L.ol bus 318. The ~G.-L~ol bus interface 626 is
interrupt-driven using industry-st~nAArd techn~ques.
The keyboard interface 682 provides a serial interface to
a number of, for example, four, yW~h~-~ type keyboards 319.
Keyboard data is retrieved from the keybo~rd interface 682
via the data bus 661D once an interrupt has been received.
Keyboard 319 is preferably operated in a block transfer,
multid~ G~ed, polled mode. Keystrokes are not made
available to the system until a block terminator is entered.
At least two types of keyboards may be used: One with an
internal LCD display and one without. The LCD display
preferably ~ypuLLs two lines of data with forty characters
each. The keyboard may be similar to a stAnA~rd IBM
keyboard with twelve function keys across the top.
Keyboards 319 are connected to the host CPU 425 through
the control bus 318. The cG~.L,ol bus 318 allows a maximum
of 63 desk interface unit 321 per cable, or a theoretical
maximum of 252 keyboards (assuming 4 keyboards are attached
to each DIU 21). System response time is a function of the
information content, the number of DIUs 321 per cable, and
the transmission rate. A polling period of approximately .2
6 conA~ can be achieved with 63 DIUs 321 at a 38.4 Kbaud
rate. ThiC means that an outst~nAing request on cGI.L~ol bus
318 will be presented to the sy~tem in at most .2 ~econds,
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even if all DIUs 321 on the s_me cable have outstAnA~ng
requests.
Typed characters are displayed on a video screen without
any ~e~e~Lible delay. The polling cycle of .2 FeConAc is
inadequ_te for this ~ e. Therefore, the decoAer 316
y~GC'F-e~ the ke~sL.okes, buffers them and al60 immediately
creates a display ouL~uL in the 6elected location on the
- selected video screen 317. When the next poll o~r , the
A~coAer 316 will not responA with the buffered characters
~unless a block terminator has been entered prior to the
~poll.
: If there is an individual AecoA~r 316 for each display
monitor 317 rather than a DIU 321, keyboard and mouse
commands are still communicated to all decoA~rs by
inte~G~u.ecting them. This configuration is functionally
identical to a DIU configuration, except that the ability to
gen-lock must be externally messaged.
The mouse interface 684 provides a ~erial interface to,
for example, four mice 319'. Mouse d~ta is retrieved from
the mouse interface 684 via the data bus 661D, once an
interrupt has been received. Simply providing mouse 319'
functionality to A trading desk cAn significantly raise the
cost of a trading room. Without the present invention, the
workstation must either be located at the trading desk or
~pensive cabling and 6ignal amplifiers must be used to
transport the mouse ~ignal between the eguipment room and
the trading desk. Advantageously, according to the present
invention, the encoAer and A~coA~r information di~tribution
system performs most mouse 6ignal processing locally at the
desk and when appropriate communicates the result to the
eguipment room via the multid G~ed cc--L-ol bus 318. This
design also reduces the ~ocessing load on the host CPU 425.
Mouse 319' functions are broadly classifiable as (1)
cur60r motion and/or field highlighting, (2) clicking, and
(3) dragging. All mouse 319' actions ex~ep~ clicking are
handled locally at the trader's desk. Mouse clicks are
~ .
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transmitted through the polled keyboard 319 to the host CPU
425, which then act~ upon them.
Referring to FIG. 12, eAch video screen 317 has page-
~p~nAPnt default settings for cursor style and/or field
highlighting for each tile 250. The mouse position on the
~creen is communicated instAntly through the keyboard 319 to
the ~PcoAPr 316 which then temporarily overwrites the
selected cells in the required manner. The cursor (not
~hown) is smoothly moved on a pixel-by-pixel basis.
Overwritten cells 210 are buffered within the AecoA~r 316
and are replaced when the cursor pocition i~ moved away.
: When required by the application generAting the displayed
page, the cursor may be replaced by Automatic field
highlighting without any required click input.
Clicking, the ~l G~e~S of pressing and releasing a mouse
button, or double clicking, the process of clicking a mouse
button twice in rapid s~r~e~cion, indicates that the
application generating the ouL~L display mu~t take some
computation_l action in response to a user request. Mouce
clicks (and/or double clicks) are transmitted through the
polled keyboard 319 to the host CPU 425. The host CPU 425
then executes the indicated action and the results (e.g.,
new tiles 250) are then transmitted through the ~ncoA~r 312
to the appropriate video screen 317. The polling rate is
sufficiently high that no perceptible delay is generated by
this signaling methodology.
Dragging is the ~ocess of holding down a mouse button
while moving the mouse. Most mouse applications do not drag
the ~contents~ of the window. That is, the window and its
contents remains stationary while a new temporary substitute
marquee border is drawn and moved across the video screen.
When the button is released the temporary substitute marguee
border i8 removed and the contents of the window are redrawn
at the new location on the screen. The contents of the
window are not conti~ lly redrawn as it is dragged across
the page to reduce the amount of CPU processing that would
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be reguired to constantly rewrite the video memory.
Applications that ledLaw the contents while being dragged
significantly load the CPU as eviAenc~ by the inability of
all but the fastest mach~ner to keep up with rapid dragging.
It is not practical to have a ~ingle hoct CPU machine
~G~e~S multiple composite pages of windc~ d~agging
simultaneously unlesc thi~ border 6ubstitution methodology
is employed.
The smallest part of the compogite page 200 that may be
- dragged is a tile 250. The tile eubstitute marquee border
- may be moved to any location on the display screen; the tile
- 250 will be ~snapped~ to the nearest cell 210 boundary when
L edL awn.
When a mouse button is pressed, the ~button down~ command
is sent to the host CPU 425; when it is released, the
~button up~ location of the mouse and 6elected tile 250
identifier are transmitted through the polled keyboArd 319
to the host CPU 425 which acts upon them by (1) transmitting
a Define Tile Location command byte to the a~p~G~iate
A~coAPr redefining the new location for only that video
screen, and (2) refrech~ng the entire tile 250 to all
A~coA~rs 316 presently di6playing the tile 250. Symbolic
signaling is preferably employed 80 that all gubsequent
updates to that composite page 200 will be transmitted only
once, regardless of how many ~ecoA~rs 316 have had their
--- tile locations moved.
Mouse ~.o~_sing is effectively decomposed into two parts
(1) local ~lo~essing of all high bandwidth video .el~awing
operAtions and (2) remote application processing followed by
a one-time redrawing of the video screen. Local (i.e.,
distributed) h~n~l~ng of high bandwidth page drawing
associated with mouse motion red~cec the CPU load on the
remote application generating the ou~ display. This can
be significant when the remote application i_ generating
many interActive mouse tile changes.
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Provision is al80 made for the host CPU 425 to respond to
OL D and other reque~ts. Each message that goe~ out to a
co~er 316 i8 sequentially numbered. When a given APco~Pr
316 F~n~es an out-of-sequence message number, it re-requests
the missing messages by ren~n~ the number of the last
message received to the host CPU 425 via the ~G..L~ol bus
318. To save ~Gce~sing time, all keyboArd 319 requests Are
concAtenated and action is only taken after all keyboards
319 on the CG-~L~ ol bus have been polled at least once. In
effect, this means that the host computer 425 will make one
polling loop around all ~ecoA~rs 316 on the cGl.L~ol bus
before responAing to an error reque~t. If the Bit Error
Rate is 10-9 at a thro~ghp~t of 25 Mbit/sec, then on average
there will be 0.025 error requests per ~con~ or 1 error
retransmission request every 40 ~Qc-on~C.
In a preferred embodiment, the encoder 312 is capable of
caching at least 500 composite pages 200 (100 x 30
characters per page) including cell attributes, and storing
at least 4,000 tile names and have a memory base address ~et
to any one of four locations using a Berg clip. The Host
CPU 425 input/ou~u~ should include a base address set to
any one of four locations using a Berg clip and an interrupt
(if required) may be set to any one of four locations using
a Berg clip. The data throughput is at about 2.5 MB/sec (20
Mbit/sec) after protocol processing in the absence of any
co-transmitted TV signals, and each co-transmitted full
Ccreen TV cignal may not degrade the data throughput by more
than 0.5 MB/sec (4 Mbits/sec). Codeword lengths for the
video screen display ID code may be 21 bits (2,097,152
possibilities) and the tile information ID code may be 24
.~ bits (16,777,216 possibilities). A preferred display screen
317 includes ~creen attributes of 100 horizontal cells and
30 vertical cells, each cell having 8 horizontal pixels and
16 vertical pixels, with each cell blinking at 4 rates of
on/off; scrolling for 2 ~eparate alphamosaic tiles of any
size, up or down, with soft or hard scrolling, with 4 soft
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rates; rann~ng for 4 separate alphamosaic tiles of any size,
left or right, with 4 soft p~a,nn~ng rates. Also, the
character size may be 6ingle, double, triple, or quadruple
height and width. Up to 8 different ~imulta~ realtime
TV signals, having a total display area of not more than
four video screens, each displayable at full, 1/4 or 1/8
screen size may be ~ G~ Led. Each TV signal may be shifted
horizontally to within 1 cell, but may not be vertically
shifted (unless a frame store RAM is used in place of a
picture store RAM 662 in the decoAers).
Numerous alterations of the structure herein disclosed
will suggest themselves to those skilled in the art.
However it is to be understood that the embodiments herein
disclosed are for ~L~r~s of illustrAtion only and not to
be construed as a limitation of the invention.
