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Patent 2285627 Summary

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(12) Patent Application: (11) CA 2285627
(54) English Title: METHOD FOR PRODUCING PLANAR TRENCHES
(54) French Title: PROCEDE DE PRODUCTION DES SILLONS PLATS
Status: Dead
Bibliographic Data
(51) International Patent Classification (IPC):
  • H01L 21/763 (2006.01)
  • H01L 21/762 (2006.01)
(72) Inventors :
  • SODERBARG, ANDERS KARL SIVERT (Sweden)
  • OGREN, NILS OLA (Sweden)
  • SJODIN, ERNST HAKAN (Sweden)
  • ZACKRISSON, OLOF MIKAEL (Sweden)
(73) Owners :
  • TELEFONAKTIEBOLAGET LM ERICSSON (Not Available)
(71) Applicants :
  • TELEFONAKTIEBOLAGET LM ERICSSON (Sweden)
(74) Agent: MARKS & CLERK
(74) Associate agent:
(45) Issued:
(86) PCT Filing Date: 1998-03-23
(87) Open to Public Inspection: 1998-10-01
Availability of licence: N/A
(25) Language of filing: English

Patent Cooperation Treaty (PCT): Yes
(86) PCT Filing Number: PCT/SE1998/000528
(87) International Publication Number: WO1998/043293
(85) National Entry: 1999-09-24

(30) Application Priority Data:
Application No. Country/Territory Date
9701154-8 Sweden 1997-03-26

Abstracts

English Abstract




Method for improving the topography over trench structures
in which the provision of extra poly-semiconductor material e.g.
polysilicon 20 or nitrate or oxide in the regions of the trench edges
and, if necessary, the subsequent oxidation of the extra material
prevents the occurrence of regions of high mechanical stress.


French Abstract

La présente invention concerne un procédé d'amélioration de la topographie sur des structures de sillon dans lesquelles l'apport d'un matériau polysemiconducteur supplémentaire, par exemple du polysilicium 20, du nitrate ou un oxyde, dans les régions des bords de sillon, et si nécessaire, l'oxydation ultérieure du matériau supplémentaire, empêchent l'apparition de régions de tension mécanique élevée.

Claims

Note: Claims are shown in the official language in which they were submitted.



10

Claims
1. Method for producing trenches in a substrate (2) of semiconductor material
(2)
having a planar surface (3) comprising the steps of:
masking the desired position of a trench (1) in a planar surface (3) of a
substrate (2)
by means of a mask (4),
etching a trench (1) of a desired depth in said planar surface (3),
processing some or all of the exposed surfaces of the substrate (2) to form a
first
insulating layer (9),
depositing a second layer of insulating material (6) on the first insulating
layer (9)
wherein said second layer of insulating material (6) has a thickness which is
equal
to, or greater than, the width of the trench (1),
etching back the second layer of insulating material (6) until the first
insulating layer
(9) on the planar surface (3) is exposed but said trench (1) still contains
said second
layer of said insulating material (6),
whereby a substantially vertical downward step (8) of height h is formed over
the
trench (1),
characterised by the steps of:
depositing an insulating film (21) of the same type of material as said
insulating
material (6) over the exposed surfaces of said wafer (2) and said second layer
(6) in
trench (1);
anisotropically etching back the insulating film (21) so that the depth d of
the
insulating film (21) remaining on said second layer of insulating material (6)
in said
trench (1) in the region of the edges of the trench (1) is less than or
substantially
equal to the height h of the step (8).
2. Method according to claim 1 characterised in that it comprised the step of
oxidising said second layer in trench (1) before depositing an insulating film
(21) of
the same type of material as said insulating material (6) over the exposed
surfaces of
said wafer (2) and said second layer (6) in trench (1).


11

3. Method according to claims 1 or 2 characterised in that the semiconductor
material (2) is from groups 3 or 5 of the periodic table.
4. Method according to any of the previous claims characterised in that the
semiconductor material (2) comprises silicon.
5. Method according to any of the previous claims characterised in that the
insulating film (21) and second layer of insulating material (6) comprises
poly-semiconductor material, amorphous semiconductor material, micro-
crystalline
semiconductor material or one or more crystalline semiconductor material
compounds.
6. Method according to any of the previous claims characterised in that the
first
insulating layer (9) is an oxide of semiconductor material.
7. Method according to any of the previous claims characterised in that the
mask (4)
is an oxide of semiconductor material which protects underlying surfaces from
being etched and oxidised.
8. Method according to any of the previous claims characterised by the further
step
of oxidising the etched-back insulating film (21).
9. Method according to claim 8 characterised in that the thickness of the
insulating
film (21) before being oxidised is adapted so that after being completely
oxidised
the resulting oxide layer (22) is substantially coplanar with the exposed
planar
surface (3).
10. Method according to any of the previous claims characterised in that said
insulating film (21) is deposited with a structure which is more rapidly
oxidised than
the structure of said second layer of insulating material (6).


12

11. Trench in a semiconducting substrate characterised in that it has been
produced
by a method according to any of claims 1-10.

Description

Note: Descriptions are shown in the official language in which they were submitted.



CA 02285627 1999-09-24
WO 98/43293 1 PCT/SE98/00528
METHOD FOR PRODUCING PLANAR TRENCHES
Technical Field of the Invention
The present invention relates to trenches in semiconductor products having a
substantially planar surface. .
Description of Related Art
In order to isolate components in integrated circuits from each other refilled
trench
structures have been developed. There are many different methods of forming
such
trenches. The most common methods for making filled trenches are described in
Wolf, S., "Silicon Processing for the VLSI Era Volume II", pages 45-~6, ISBN-0-

961672-4-5, 1990. Lattice Press USA. The main steps are that a trench is
etched into
the silicon substrate surrounding each component to be isolated on a wafer. An
isolating oxide layer is then deposited in the trench and on the silicon
substrate to
isolate the component from the surroundings. The trench is then filled by
depositing
polysilicon over the whole wafer to a thickness which is sufficient to fill
all the
trench structures. Thus the polysilicon is also deposited on the oxide layer
on the
planar surfaces of the silicon substrate between the trenches. This
polysilicon is then
etched away in order to expose the oxide layer on the planar surface. Some of
the
polysilicon over the trench is also removed by this etching. This leaves
components
in the form of an island of silicon surrounded by a trench of isolating
polysilicon. In
order to build up successive layers of components it is desirable that each
successive
layer of the integrated circuit is built upon a substantially planar surface.
However,
m practice, the removal of some of the polysilicon over the trench leaves a
downward vertical step. The oxide walls of the trenches usually have sloping
tops
which incline downwardly towards the inside of the trench. Owing to this, the
thickness of the polysiiicon in the substantially planar polysilicon filling
in the
trench decreases as it approaches the trench walls. The polysilicon is then
oxidised
to form an isolating oxide cover over the trench. During this oxidisation it
is


CA 02285627 1999-09-24
WO 98/43293 2 PGT/SE98/00528
possible that the silicon substrate in the regions near the trench edges which
have
only a thin covering of polysilicon is also oxidised. This produces high
mechanical
stresses in these regions. Subsequent processing often uses wet etching to
remove
thermally produced oxides. The etching speed for wet etching for oxides is
greatly
dependent on the mechanical stress in the oxides. This means that the oxides
in
regions of high mechanical stress are etched deeper than the rest of the
surface
leading to grooves along the edges of the trench. During further processing it
is
possible that these grooves become filled with conducting material to such a
depth
that later processing to remove undesirable conducting material is ineffective
and
strings of surplus conducting material remain in the grooves. These strings
can
cause problems such as short circuits particularly if the strings are so high
that they
contact conductors laid over the trench.
Summary
An object of the present invention is to produce trenches surfaces which are
more
planar than previous trench surfaces. Another object of the invention is to
provide a
method for eliminating the problem of strings of surplus conducting material
remaining in grooves along trench edges.
In accordance with the invention this object is accomplished by providing
extra
amounts of trench material along the edges of the trenches in order to prevent
the
occurrence of grooves along the trench edges. In the case of silicon-based
processing this is done by depositing on to the trench filling material a
layer of
2~ polysilicon, oxide, nitride or the like which is then etched back by an
anisotropic
etch i.e. an etching process which attacks the layer to be etched
significantly faster
in the vertical direction than in the horizontal. This leaves extra material
along the
trench edges. This process can take place before or after the oxide layer is
grown on
the polysilicon in the trench. In the case of non-oxidisable material such as
oxide or
nitride the thickness of the extra material after etching should be
approximately the
same as the height of the downward vertical step. In the case of polysilicon,
the


CA 02285627 1999-09-24
WO 98/43293 3 PCT/SE98/00528
thickness of the polysilicon deposited is preferably chosen such that when all
of the
extra polysilicon is oxidised during the subsequent oxidation the resulting
oxide
layer has approximately the same height as the step height. The extra material
in the
form of oxide, nitride or polysilicon strings along the trench edges protect
from
oxidation the underlying silicon which otherwise would be oxidised and produce
regions of high mechanical stress. In the absence of regions of high
mechanical
stress the subsequent wet etching proceeds more evenly and the production of
unwanted grooves at the trench edges is avoided. By using the same type of
material
that is used to fill the trench as the extra material less mechanical stress
is produced
in the trench after oxidation.
The oxidation of the extra thickness of the polysilicon material near to the
trench
edges also provides a thicker oxide layer near to the trench walls.. By
choosing the
correct dimensions for the extra polysilicon strings it is possible to produce
oxides
layers at the trench edges which are substantially the same thickness as the
surrounding oxide layers and in this way achieve a more planar surface. By a
suitable choice of deposition temperature it is possible to adjust the grain
size of
deposited silicon i.e. deposition at 580°C produces amorphous silicon
while
deposition at 600°C produces micro-crystalline silicon and deposition
at 620°C
gives polycrystalline silicon. Amorphous silicon oxidises more quickly than
micro-
crystalline silicon which oxidises more quickly than polycrystalline silicon.
It is
therefore possible to adjust the relative oxidation rates of the trench
material and the
extra material to form a desired trench cross-sectional profile by adjusting
the
deposition temperature of the extra material.
A trench formation formed in accordance with the invention has a number of
advantages. An obvious advantage is that the surface over the trench no longer
has
a vertical step which reduces the risk of undesirable material being trapped
in the
trench and later causing problems. An other advantage is that a more even
planar
surface is achieved after the oxide or nitride has been deposited or after the
polysilicon has been deposited and etched back in a method according to the


CA 02285627 1999-09-24
WO 9_8/43293 ~. PCT1SE98/00528
invention. A further advantage is that the mechanical stresses in the trench
are
reduced.
Brief description of the drawings
The invention will be described in more detail below by means of examples~of
embodiments of trench structures formed according to the invention and with
referenced to the appended drawings in which:
Figures la-lh shows in cross-section stages in the formation of a trench
according
to a prior art method; and,
figures 2a-2i shows in cross-section stages in the formation of a trench
according to
one embodiment of the present invention.
i ~ Detailed Description of the Embodiments
Figure la shows the first stage in a known method of producing a trench. A
trench 1 has been etched into a silicon substrate 2 of a wafer which has a
planar
surface 3. An isolation layer 4 of, for example silicon dioxide or silicon
nitride or a
combination of these, on top of the planar surface acts as a mask during
etching of
the trench 1.
In figure lb a second isolating layer 9 of, for example silicon dioxide or
silicon
nitride or a combination of these, has been grow or deposited in the trench 1
and on
the first isolating oxide layer 4. It is also possible to deposit the
isolation layer 9
after the first isolation 4 has been removed from the planar surface 3.
In figure 1 c a polysilicon layer 6 has been deposited over substantially the
whole of
the silicon substrate 2 and in the trench 1 to a thickness which is sufficient
to
overfill the trench 1. A dip or vertically downward step 8' is present over
the trench
1.


CA 02285627 1999-09-24
WO 98/43293 S PCT/SE98/00528
In figure 1 d the polysilicon layer 6 has been etched away in order to expose
the
second insulating layer 9 on the substantially planar surface of the silicon
substrate
2. This second insulating layer 6 is resistant to the etching. This leaves
islands of
silicon substrate 2 separated by a trench 1 with walls 9 of isolating oxide
and a core
of polysilicon 6. When the polysilicon 6 is etched away from the wafer surface
to
expose the second insulating layer 6 a downward vertical step 8 remains over
the
trench 1. This is caused by over-etching of the polysilicon layer 6. This over-
etching
is required to ensure that all the polysilicon on top of the planar surface 3
is
removed.
The surface of the polysilicon 6 remaining in the trench 1 is then oxidised to
form
an isolating oxide cover 10 over the trench as shown in figure 1 e. The
silicon
substrate 2 in the regions 12 where the oxide walls of the trenches 1 have
sloping
tops which incline downwardly towards the inside of the trench has only a thin
1 ~ covering of polysilicon 6. During the oxidation process it is possible
that the silicon
substrate 2 is also oxidised, especially in the region where the cover oxide
is thin
prior to the oxidation step. This produces high mechanical stresses in regions
12 and
in the oxide 9, 10 near these regions.
Subsequent processing often uses wet etching to remove thermally produced
oxides
such that the isolation layer 9 on the planar surface 3 is thinned or even
removed
entirely. In the event that isolation layer 4 is still present it is also
conceivable that it
is also, at least, partially thinned. The etching speed for wet etching for
oxides is
greatly dependent on the mechanical stress in the oxides. This means that the
oxides
2~ in regions 12 of high mechanical stress are etched deeper than the rest of
the
surface. As shown in figure 1 f this can leads to irregular grooves 14 along
the edges
of the trench 1.
During subsequent processing including the deposition of conducting material
16
these grooves 14 become filled with conducting material 16 as shown in figure
1 g.


CA 02285627 1999-09-24
WO 98/43293 6 PCT/SE98/00528
The duration of later processing to remove unwanted conducting material 16 may
be
insufficient to remove all the conducting material 16 at the bottom of the
grooves 14
and strings 18 of surplus conducting material lb may be left in the grooves as
shown in figure lh. These strings 18 can cause problems such as short circuits
particularly if the strings are so high that they contact conductors laid over
the
trench during subsequent processing.
In an embodiment of the method according to the present invention for forming
planar trenches, as illustrated in Figures 2a-2d, a trench is etched in the
substrate in
a conventional manner, for example, as described above with respect to Figures
1 a-
I d. For the sake of example the invention is illustrated by embodiments using
a
silicon substrate, silicon oxides as insulating material and polysilicon as a
filling
material. It is also conceivable to use other semiconductors e.g. silicon
carbide or
other group 3 or group ~ materials, or other suitable materials for the
substrate and
1 ~ the insulating materials can be any suitable compounds such as oxides,
nitrides or
the like, and combinations thereof. Furthermore the trench filling material is
not
limited to polysilicon but could be, for example, amorphous silicon, micro-
crystalline silicon or crystalline silicon compounds. In the event that the
trench
structure is formed in a substrate based on a material other than silicon is
used then
it is naturally possible to use other filling materials with the appropriate
properties
In figure 2e it can be seen that extra seams 20 of the same type of material
that has
been used to fill the trench, in this case polysilicon, have been laid along
the edges
of the trenches by any suitable method. One example of such a method is to
first
deposit a polysilicon film 21 of a thickness t of, for example, 0.3-0.8 Tm
over the
entire wafer. This film 21 is deposited also directly onto the polysilicon 6
in the
trench I and on the sides of the downward vertical steps 8 so that the
vertical steps 8
are 2t closer to each other after the film 21 has been deposited. The
thickness t of
this film 21 is dependent on the height h of the downward vertical step of the
trench.
This film 2I is shown by a dashed line in figures 2e. Film 2I is then etched
back a
distance t with an anisotropic etch which etches primarily in the vertical
direction.


CA 02285627 1999-09-24
WO 98/43293 '7 PCT/SE98/00528
This exposes the oxide layer 4 and/or 9 on the planar surface and the
polysilicon in
the centre of the trench but leaves extra seams of polysilicon 20 along the
trench
edges where the vertical thickness of film 2 i is greatest.
In a preferred embodiment of the invention the thickness t of film 21 and the
duration of the anisotropic etch is calculated to give a thickness d for the
extra
seams 20 such that after oxidation of the polysilicon in the seams 20, the
resulting
oxide layer has a thickness substantially equal to that of insulating oxide
covering
the silicon surface 3. The topography of the polysilicon 6, 20 is now such
that there
are no regions having only a thin covering of polysilicon. The wafer is then
oxidised
in the conventional manner in order to form an isolating oxide cover 22 over
the
trench 1 from the exposed polysilicon 6. 20, as shown in Figure 2f. As there
is more
polysiiicon material available for oxidation in region 12 the silicon
substrate in
region 12 is not oxidised and regions of high mechanical stress do not occur.
The
more uniform thickness of the polysilicon layer before oxidising leads to a
more
uniform oxide layer. By varying the shape and dimensions of the extra seams of
polysilicon 20 it is possible to produce an oxide layer which is substantially
flat and
coplanar with the exposed surface of the surrounding substrate. Furthermore,
by a
suitable choice of deposition temperature, it is possible to adjust the grain
size of
deposited silicon i.e. deposition at 580°C produces amorphous silicon
while
deposition at 600°C produces micro-crystalline silicon and deposition
at 620°C
gives polycrystalline silicon. Amorphous silicon oxidises more quickly than
micro-
crystalline silicon which oxidises more quickly than polycrystalline silicon.
It is
therefore possible to adjust the relative oxidation rates of the trench
material and the
2~ extra material to form a desired trench cross-sectional profile by
adjusting the
deposition temperature of the extra material.
As shown in figure 2g, due to the absence of regions of high mechanical stress
no
grooves are formed during wet etching back of the thermal oxides.


CA 02285627 1999-09-24
WO 98/43293 $ PCT/SE98/00528
As shown in figures 2h and 2i, any subsequent filling of conducting material
16 has
a more even depth and removal of conducting material 16 can be performed
without
leaving strings of unwanted conducting material.
In a second embodiment of a method according to the present trenches are
formed
using the processes described above with reference to Figures 2a-2d. The
polysilicon 6 in the trench is then oxidised to form a layer of silicon oxide
before the
extra seams 20 of material are laid along the edges of the trenches. This
layer of
silicon oxide acts as a stop layer with respect to further processing and
prevents the
underlying polysilicon 6 in the trench from being etched or oxidised in the
following
processing stages. The polysilicon is preferably oxidised at a comparatively
low
temperature in the region of 800 °C to 900 °C.
In a third embodiment of the invention instead of polysilicon a further layer
of oxide
1 ~ is deposited over the entire wafer, including the trench walls, after the
steps of
filling the trench with polysilicon and subsequent etching back of the
polysilicon
have been performed. The depth of this further layer is dependent on the
height of
the vertical step of the trench and the required height of the seams as
described later.
This oxide layer is then etched back to the earlier oxide layer with an
anisotropic
etch which etches primarily in the vertical direction thus leaving, as in the
embodiment above, extra seams of material along the trench edges. The
thickness of
the extra seams (and thus the thickness of the deposited oxide layer) is
chosen such
that the remaining oxide layer along the trench edges has a thickness (height)
substantially equal to that of the original insulating oxide layer and that
the trench
walls are displaced towards each other an amount sufficient to cover any
regions of
the trench edges which have a thin covering of polysilicon. If the thickness
of each
of the extra seams is greater than half the maximum trench width then the
trench
will be completely filled by these seams. After anisotropic etching-back a
trench
surface substantially coplanar with the surrounding exposed planar surface
will be
produced. These extra seams of oxide will not be oxidised during subsequent


CA 02285627 1999-09-24
WO 98/43293 9 PCT/SE98/00528
processing of the wafer and therefore will prevent high mechanical stresses
arising
near the trench edges.
In a fourth embodiment of the invention, a further layer of nitride is
substituted for
the further layer of oxide mentioned in the third embodiment of the invention.
In a
similar manner as described for the third embodiment, this nitride layer is
deposited
over the wafer and subsequently etched back.
In all the embodiments of the invention the isolating layers can be made from
any
suitable insulating material including such materials such as oxides, nitrides
or the
like of the substrate material.
The methods according to the invention are preferably performed after active
components have been created on the substrate and after they have been
protected
1 ~ from etching and oxidation by coverings of etch-resistant and oxidation-
resistant
material.

Representative Drawing
A single figure which represents the drawing illustrating the invention.
Administrative Status

For a clearer understanding of the status of the application/patent presented on this page, the site Disclaimer , as well as the definitions for Patent , Administrative Status , Maintenance Fee  and Payment History  should be consulted.

Administrative Status

Title Date
Forecasted Issue Date Unavailable
(86) PCT Filing Date 1998-03-23
(87) PCT Publication Date 1998-10-01
(85) National Entry 1999-09-24
Dead Application 2004-03-23

Abandonment History

Abandonment Date Reason Reinstatement Date
2003-03-24 FAILURE TO REQUEST EXAMINATION
2003-03-24 FAILURE TO PAY APPLICATION MAINTENANCE FEE

Payment History

Fee Type Anniversary Year Due Date Amount Paid Paid Date
Application Fee $300.00 1999-09-24
Maintenance Fee - Application - New Act 2 2000-03-23 $100.00 2000-03-08
Registration of a document - section 124 $100.00 2000-09-21
Maintenance Fee - Application - New Act 3 2001-03-23 $100.00 2001-03-08
Maintenance Fee - Application - New Act 4 2002-03-25 $100.00 2002-03-21
Owners on Record

Note: Records showing the ownership history in alphabetical order.

Current Owners on Record
TELEFONAKTIEBOLAGET LM ERICSSON
Past Owners on Record
OGREN, NILS OLA
SJODIN, ERNST HAKAN
SODERBARG, ANDERS KARL SIVERT
ZACKRISSON, OLOF MIKAEL
Past Owners that do not appear in the "Owners on Record" listing will appear in other documentation within the application.
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Document
Description 
Date
(yyyy-mm-dd) 
Number of pages   Size of Image (KB) 
Drawings 1999-09-24 9 73
Representative Drawing 1999-11-29 1 4
Cover Page 1999-11-29 1 33
Description 1999-09-24 9 441
Abstract 1999-09-24 1 49
Claims 1999-09-24 3 91
Correspondence 1999-11-04 1 2
Assignment 1999-09-24 2 103
PCT 1999-09-24 10 367
Assignment 2000-09-21 2 77