Note: Descriptions are shown in the official language in which they were submitted.
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Description
ATM switching device for high data rates
Due to the increasing demand for the
transmission of visual information in modern
communications technology, such as, for example, still
and moving images in video telephone applications or
the representation of high-resolution graphics on
modern personal computers, the significance of
transmission and switching technologies for high data
transmission rates (greater than 100 Mbit/s) is
increasing. The asynchronous transfer mode (ATM) is a
familiar data transmission method for high data rates.
At present, data transmission based on the asynchronous
transfer mode provides for a variable transmission bit
rate of up to 622 Mbit/s.
Known switching devices including those based
on the asynchronous transfer mode are usually of
modular construction. As a rule, a multiplicity of
modules which, for example, implement an interface
connecting subscriber lines or a central controller can
be plugged in on a central connector assembly common to
all modules, a so-called "backplane" and are connected
to one another via this backplane. The resultant
modularity of the switching devices provides for, among
other things, easy adaptability of a switching device
to different configurations and simplified fault
analysis in a case of servicing.
In this arrangement, the circuit switching
devices (e. g. switching networks) of switching systems,
in particular, are arranged on one or more separate
circuit switching assemblies which can also be plugged
in on the backplane.
From the data sheet "MOS INTEGRATED CIRCUIT
~PD98410", NEC Corporation, 1997, Document No.
512624EJ1VODS00 (1st edition),
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Int. File Reference: PCT/DE98/03425
a large-scale integrated circuit switching chip is
known which allows addressing of a number of
subscriber-related interfaces via a high-frequency
ATM-specific bus interface (UTOPIA: Universal Test &
Operations PHY Interface for ATM).
In EP 0 506 134 A1, an ATM switching device is
described which exhibits a circuit switching unit
comprising a databus and a multiplexer device. The
multiplexer device connects the databus to subscriber
- lines for input signals via serial/parallel converters.
The databus in connected to subscriber lines for output
signals via address-controller-controlled storage
devices and via parallel/serial converters.
The present invention is based on the object of
developing an ATM switching device of modular
construction, in which a multiplicity of subscriber
line devices can be connected, in such a way that a
large-scale integrated circuit switching chip designed
for ATM applications can be used.
According to the invention, this object is
achieved by means of the features of claim 1.
To provide for better understanding of the
functions and operation of an ATM switching device, it
appears to be necessary to discuss known principles in
greater detail once more.
In the transmission method known as
asynchronous transfer mode (ATM), fixed-length data
packets, so-called cells, are used for transporting the
data. An ATM cell is composed of the so-called cell
"header", which contains the switching data relevant to
the transport of an ATM cell and has a length of five
bytes, and the so-called "payload" field which has a
length of 48 bytes.
AMENDED SHEET
IPEA/EP
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Int. File Reference: PCT/DE98/03425
When a connection is being set up in the
switching technology designed in accordance with the
asynchronous transfer mode, interconnection tables
containing the switching and routing information
consisting of a virtual channel identifier - called VCI
in the text which follows - and a virtual path
identifier - called VPI in the text which follows - are
set up in the respective ATM switching device by
exchanging signaling information before the beginning
of the transmission of useful data in an ATM
communication network. In the interconnection
AMENDED SHEET
IPEA/EP
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tables, a VCI value is allocated to the virtual channel
identifier and a VPI value is allocated to the virtual
path identifier. The switching data or routing
information, respectively, entered in the
interconnection tables specify how the virtual paths
or, respectively, virtual transmission channels
contained in the virtual paths of the incoming and
outgoing connections at the ATM switching device are
coordinated with one another by the signaling, i.e.
which input is linked to which output by switching
operations. ATM cells transferred via these virtual
connections have switching data, consisting essentially
of a VPI value and a VCI value, in the header . The ATM
header data are processed, i.e. the switching data
arranged therein are detected and weighted, at the
input of an ATM switching device. The ATM cells are
then switched by a circuit switching device, arranged
in the ATM switching device, to an output representing
a particular destination by using the routing
information stored in the interconnection table.
When the circuit switching device is arranged
on a separate circuit switching assembly, a
high-frequency databus (clock rate > 50 MHz) of the
large-scale integrated circuit switching chip, which
connects a large-scale integrated circuit switching
chip to subscriber line devices, would have, for
structural reasons, a length of approximately 30 to
40 cm, even in relatively small switching devices,
which length is too great for the required clock rate
for reasons of line theory. An additional aggravating
factor is that when a number of subscriber line devices
are in contact with the high-frequency databus, an
additional reduction in bus length is required in order
to maintain the conditions required by line theory.
The arrangement according to the invention then
provides the advantage that, when the large-scale
integrated circuit switching chip is arranged
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on a base assembly and multiplexer devices are
interposed between the large-scale integrated circuit
switching chip and the subscriber line devices, the
length of the high-frequency databus - which connects
the large-scale integrated circuit switching chip to
the multiplexer devices, can be kept very short.
In addition, the high-frequency databus is
decoupled in time from the subscriber-line-
device-individual databuses by interposing the
multiplexer devices, so that each individual
subscriber, line-device-individual databus can be
operated at a lower clock rate which, if necessary, can
be predetermined individually by the subscriber line
device. In addition, a pure point-to-point connection,
i.e. only two connections per connecting line, is
produced between a multiplexer device and a subscriber
line device. The resultant, more advantageous line
characteristics provide for a length of the
subscriber-line-device-individual databus which is more
generous compared with the high-frequency databus.
Advantageous further developments of the
invention are specified in the subclaims.
In the text which follows, an illustrative
embodiment of the invention is explained in greater
detail with reference to the drawing, in which:
Figure 1 shows a structural diagram for the
diagrammatic representation of the essential
functional units of a circuit switching chip
designed in accordance with the asynchronous
transfer mode;
Figure 2 shows a structural diagram for the
diagrammatic representation of the essential
functional units arranged on a base assembly
of a
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switching device according to the invention.
Figure 1 shows a diagrammatic representation of
the essential functional units of a large-scale
integrated circuit switching chip X15. The circuit
switching chip X15 is connected to a high-frequency
databus DB via an input interface ESS and an output
interface ASS. In addition, the circuit switching chip
X15 is connected to a first memory - not shown in the
drawing - via a first interface DSS and to a second
memory - not shown in the drawing - containing
switching data or, respectively, routing information,
via a second interface HSS.
ATM cells arriving are forwarded via the input
interface ESS to an input separator IS which separates
the header and the payload of the incoming ATM cell
from one another. The data of the payload are forwarded
via the first interface DSS to the first memory where
they are temporarily stored. The switching data located
in the header of the ATM cell are partly forwarded to a
control unit QQ, and the VCI value contained in the
switching data and the VPI value are forwarded to the
second memory via the second interface HSS. Using the
routing information stored in the form of
interconnection tables in the second memory, the VCI
value and the VPI value are reweighted for forwarding
to the ATM cell.
If an arbitration unit A of the circuit
switching chip X15 signals to the control unit QQ that
a subscriber line device - not shown in the
drawing - which is connected via the databus DB is
requesting data, the control unit QQ checks whether ATM
cells allocated to this subscriber line device have
been temporarily stored. If this is so, the header
previously separated, containing the reweighted
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VCI value and the reweighted VPI value, and the
associated payload are combined in an output selector
OS, and written onto the databus DB via the output
interface ASS.
Figure 2 shows a diagrammatic representation of
the essential functional units arranged on a base
assembly BBG of a switching device according to the
invention. The base assembly BBG exhibits a large-scale
integrated circuit switching chip X15 which is
connected to a first memory MEM1 and a second memory
MEM2 via in case one memory databus. The first memory
MEM1 is used for temporarily storing useful information
stored in an ATM cell. In the second memory MEM2,
routing information for the ATM cells to be switched is
stored in the form of switching tables. For a
connection to subscriber line devices, not shown in the
drawing, the circuit switching chip X15 has a first and
a second high-frequency (50 MHz clock rate) databus
DBO, DB1 having a width of 16 bits.
The base assembly BBG has eight connection
slots SLOTO,...,SLOT7 to provide contact with subscriber
line units, and four multiplexes devices MUXO,...,MUX3
arranged in close vicinity to the circuit switching
chip X15. A first and a second multiplexes device MUXO,
MUX1 are connected via the first high-frequency databus
DBO, and a third and a fourth multiplexes device MUX2,
MUX3 are connected via the second high-frequency
databuses DB1, to the circuit switching chip X15. The
length of the first and the second high-frequency
databuses DBO, DB1 is minimized by arranging the
multiplexes devices MUXO,..., MUX3 in close vicinity to
the circuit switching chip X15.
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To connect subscriber line devices to the
circuit switching chip X15, a first connection slot
SLOTO is connected via a first subscriber-line-
device-individual databus TBO, and a second connection
slot SLOT1 is connected via a second subscriber-line-
device-individual databus TB1, to the first multiplexes
device MUXO. Analogously, the third to eighth
connection slots SLOT2,...,SLOT7 are connected to the
second to fourth multiplexes devices MUX1,...,MUX3. Since
hitherto only eight-bit-wide chips have been known for
ATM-specific chips, a subscriber-line-device-individual
databus TBO,...,TB7 is composed of two separate
eight-bit-wide databuses.
Connecting a subscriber line device to a
multiplexes device MUXO,...,MUX3 via a separate
subscriber-line-device-individual databus TBO,...,TB7
produces a defined point-to-point connection between
this subscriber line device and the associated
multiplexes device MUXO,...,MUX3. The associated
advantageous line characteristics make it possible to
transmit data via a longer transmission link.
Due to the fact that the subscriber-line-
device-individual databuses TBO,...,TB7 are decoupled in
time from the first and second high-frequency databuses
DBO, DBl, which is achieved by the multiplexes devices
MUXO,...,MUX3, each subscriber-line-device-individual
databus TBO, ..., TB7 can be operated at a separate, lower
clock rate predetermined by the respective subscriber
line device.
