Note: Descriptions are shown in the official language in which they were submitted.
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.1ITTER FRE(,~UENCY SHIFTING 0-E MODULATED
SIGNAL SYNCHRONIZATION MAPPER
Technical Field
This invention pertains to minimization of low frequency
fitter during bit stuff mapping of plesiosynchronous data signals into
synchronized data signals.
Background
"Bit stuffing" is a well known technique used in synchro-
nizing data signals by "mapping" such signals from one data rate to a
different data rate. For example, as shown in Figure 1, plesiosynchron-
ous signals such as DS-l, DS-2 or DS-3 signals respectively character-
ized by 1.544 Mb/s, 6.312 Mb/s or 44.736 Mb/s clock rates are com-
monly mapped from a plesiosynchronous link to a SONET/SDH link
having a different characteristic clock rate such as the 1.728 Mb/s rate
of the SONET VT1.5 signal. An electronic device known as a "map-
per" performs the mapping operation. After transmission over the
SONET/SDN link, the signal is desynchronized (demapped) by a
demapper which reconverts the SONET/SDH signal to a
plesiosynchronous signal for transmission over another plesiosynchron-
ous link.
The bit stuffing technique involves insertion ("stuffing") of
positive or negative bits into the data stream during the mapping opera-
tion. If these bit "stuffs" are performed in a regular and efficient
manner they impose unacceptable low frequency fitter on the mapped
data stream. It is very difficult to remove such low frequency fitter
when the data stream is desynchronized ("demapped"), particularly in
older "legacy" systems utilizing 40 Hz fitter filters. Consequently, the
prior art has evolved various bit stuffing techniques for minimizing low
frequency fitter by translating fitter energy to higher frequencies at
which it is more easily removed.
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One prior art technique utilizes phase lock loops (PLLs)
incorporating voltage controlled oscillators (VCOs) having frequency
characteristics governed by the level of the FIFO buffer (sometimes
called an "elastic store") through which the data stream is processed.
However, VCO-based PLL techniques involve comparatively expensive
analog circuitry. In another prior art technique known as "threshold
modulation", the sawtooth-like characteristic of the FIFO buffer fill
level is monitored and used to perform dithering of the bit stuffing
operation. However, this requires monitoring of the FIFO buffer depth,
and access to the FIFO buffer pointers. Moreover, the frequency of the
aforementioned sawtooth characteristic affects the higher frequency
band into which the fitter energy is translated, constraining circuit
design if the sawtooth frequency is fixed.
The present invention addresses the foregoing problems.
Summary of Invention
The invention utilizes a phase lock control loop containing
a "delta-sigma" (0-E) modulator which functions as a VCO to
synchronize the data rate of an output data stream to that of an input
data stream such that fitter energy is shifted up in frequency, simplifying
attenuation of the fitter energy when the data stream is desynchronized
(demapped). The modulator generates an accurate pulse train which a
mapper incorporating the modulator interprets as stuff/null/de-stuff
commands in such a manner that the mapping operation is lossless over
time (i.e. the number of bits in equals the number of bits out over time)
thus allowing utilization of a FIFO buffer without the need to monitor
the buffer's depth or its pointers.
Brief Description of Drawings
Figure 1 schematically depicts mapping of signals from a
plesiosynchronous link for transmission on a SONET/SDH link and
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subsequent depapping of the SONET/SDH link for transmission on
another plesiosynchronous link.
Figure 2 is a block diagram representation of a first order
phase lock loop incorporating a ~-E modulator in accordance with the
invention.
Figure 3 graphically depicts the system transfer function of
the Figure 2 apparatus, with the upper plot depicting the gain vs. fre
quency characteristic and the lower plot depicting the phase vs. fre
quency characteristic.
Figure 4 is a block diagram representation of a signal
synchronization mapper incorporating the Figure 2 apparatus.
Figures SA-SC graphically illustrate the 10:1 fitter attenua-
tion achievable by the invention. Figure SA depicts a 25Hz 10 unit
interval (UI) peak-to-peak fitter signal representative of signals input to
the Figure 2 apparatus; Figure SB depicts a 25Hz 2 UI peak-to-peak
fitter signal representative of signals output by the Figure 2 apparatus;
and, Figure SC graphically depicts a 25Hz 1 UI (approx.) peak-to-peak
fitter signal obtained after 40Hz filtration of the Figure SB signal.
Description
Figure 2 depicts a phase lock loop (PLL) incorporating a
0-E modulator 10 which produces an output signal characterizing the
phase (and hence frequency) of the desired output data stream. This
output signal is fed back through a first divider 12, which divides the
feedback signal by a factor Nl . The input signal characterizing the
phase (and hence frequency) of the input data stream is applied to a
second divider 14, which divides the input signal by a factor N2. to
facilitate phase comparison of the aforementioned input and output
signals. The signals output by first and second dividers 12, 14 are input
to phase detector 16 which outputs a "rate" error signal representative
of the phase difference between the input and output data streams. 0-E
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modulator 10 and its above-described external feedback loop thus forms
a first order PLL, with the rate signal output by phase detector 16
driving D-E modulator 10 as a notional voltage controlled oscillator
(VCO) which is implied in the Figure 2 circuit without requiring an
actual (expensive) analog VCO. (The external feedback characteristic
constitutes the dominant pole of the Figure 2 circuit's first order re-
sponse, although the circuit has higher orders.)
0-E modulator 10 consists of subtracter 18, adders 20, 22,
24; delay elements 26, 28, 30; quantizer 32 and multiplier 34. Multi-
plier 34 multiplies the aforementioned output signal produced by D-E
modulator 10 by a factor M. This M-multiplied signal is applied to the
"-" input of subtracter 18 to establish the interval over which subtracter
18 integrates the rate signal output by phase detector 16, resulting in
output of a signal val by subtracter 18. Adder 20 adds the val signal
output by subtracter 18 to the AO signal output by delay element 26,
resulting in output of a signal AO+val by adder 20. Adder 22 adds the
AO+val signal output by adder 20 to the A l signal output by delay
element 28, resulting in output of a signal AO+A1 +val by adder 22.
Adder 24 adds the AO +A 1 + val signal output by adder 22 to the AO + val
signal output by adder 20, resulting in output of a signal 2A0+AI +2val
by adder 24. Quantizer 32 outputs -1, 0, or + 1 depending on whether
the signal 2A0+Al +2val output by adder 24 is respectively less than,
between, or greater than the quantizer's threshold values ~[(Ml2)+KS],
where M, KS are constants as hereinafter explained. In the preferred
embodiment KS=36 and M=4,094. Therefore, ~[(Ml2)+KS] _
~2,083. If the value output by adder 24 (i.e. 2A0+AI +2val) exceeds
2,083 then quantizer 32 outputs the value + 1. If (2A0+AI +2val) <
-2,083 then quantizer 32 outputs the value -1. If -2,083 <_
(2A0+AI +2val) <_ 2,083 then quantizer 32 outputs the value 0. See
Riley et al "Delta-Sigma Modulation in Fractional-N Frequency Synthe-
sis", IEEE Journal of Solid-State Circuits Vol. 28, No. 5, May 1993,
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pp. 553-559 for further details of 0-E modulators, particularly factors
affecting stability and overflow characteristics thereof.
The -1, 0, or + 1 signals output by quantizer 32 are pro-
cessed by delay element 30 which in turn outputs either a phase incre-
S ment (pll inc) command signal to insert a stuff bit into the mapped VC-
11 or VC-12 in the output SONET/SDH data stream; or, a phase
decrement (pll dec) command signal to remove a stuff bit from the
output data stream. Only one or the other of pll-inc or pll dec can be
asserted at one time to either speed up or slow down the output data
stream. If neither pll inc nor pll dec are asserted then a null operation
is performed, such that the output data stream's rate remains unaffected.
It can thus be seen that the "rate" signal output by phase detector 16
(i. e. the difference between the actual and desired frequencies of the
signal output by 0-E modulator 10) is used to proportionately steer the
duty cycle of 0-E modulator 10 toward the desired average value by
making the modulator's average output value equal to the input value.
The time required to accomplish such steering results in a low pass fitter
attenuation effect which is apparent by comparison of Figures SA, SB
and SC. As seen in Figure SC, some high frequency noise is an inevita-
ble side effect of the modulator's operation, but such noise can be
readily dealt with and is therefore tolerable.
Figure 3 graphically depicts the transfer function of the
Figure 2 apparatus, which is characterized by the following parameters:
Input Gain: K, - N2
k; x (;(.s)
Transfer Function: T(.s) _
1 + G(.s) x H(.s)
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1
Forward Gain: C~(.s~) = K~,~ x .S'ig(.s) x Kv~o x -
.5
.S + 1
where .S'i~(.s~) _ (,s,2 + .sM + M)
Reverse Gain: 11(.s
N2
2x ~x F"
VCO Gain: K~~~, _
N1
Phase Detector Gain: K~,~ = N2 x K.S
2x ~
In a preferred embodiment of the invention suitable for
mapping T1 and E1 tributaries to SONET/SDH streams, the following
T1 mode constants were used: F~, = 1.544e6, Nl = 772, N2 = 772, M
= 4094, and Ks = 36. The control loop depicted in Figure 2 has an
effective 2KHz operating frequency, with outputs (i.e. the aforemen-
tioned pll_inc, pll dec, or an absence of either) produced every SOO~s,
corresponding to the bit stuff/destuff opportunities presented during
synchronization of SONET/SDH data streams.
As shown in Figure 4, a mapper incorporating a D-E
modulator-based signal synchronizer (DSS) 36 as shown in Figure 2
requires no communication between FIFO buffer 38 and DSS 36 (i.e.
buffering of the input stream to the output stream is independent of the
above-described duty-cycle dithered modulation of the input stream's
jittery. FIFO buffer 38 accommodates the instantaneous frequency
difference between the input and output data streams. The mapper has a
low pass response and will not track high frequency fitter. DSS 36
measures the phase of the input data stream as data enters FIFO buffer
38 and regulates the phase of the output data stream by generating phase
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inerement/phase decrement commands as previously explained.
Protocol generator 44 combines the phase increment/phase decrement
commands with data read from buffer 38, thereby allowing data
throughput to be matched in an inherently lossless (albeit discrete)
S manner. Data is written blindly into FIFO buffer 38, such that DSS 36
does not need to keep track of the buffer's write pointer 40. Only the
buffer's read pointer 42, which is separate from DSS 36, keeps track of
write pointer 40. If no data is available, read pointer 42 is not adjusted.
If FIFO buffer 38 is full, data is read out of the buffer. In either case,
for a brief time during initialization, overflow and underflow of buffer
38 serves to effectively center write pointer 40 and read pointer 42 with
respect to buffer 38. Such initialazation-centering of the buffer pointers
corrupts the data stream, but this is inconsequential due to its very
temporary nature. Once the pointers are centered, further data corrup-
tion is avoided since the above-described control loop incorporated in
DSS 36 compensates for changes in relative frequency within the loop's
bandwidth (i.e. data is transferred from buffer 38 to protocol generator
44 and thence to the mapped output data stream on a first-in first-out
basis and at a rate which prevents post-initialzation overflow and under-
flow of buffer 38). Given the aforementioned lossless phase measure-
ment, this centering mechanism can be separated from DSS 36, thus
avoiding complicating the design of DSS 36.
As will be apparent to those skilled in the art in the light of
the foregoing disclosure, many alterations and modifications are possi-
ble in the practice of this invention without departing from the spirit or
scope thereof. For example, the foregoing description assumes a
protocol which allows only one bit to be "stuffed" during each bit
stuff/destuff opportunity. The invention is readily adapted to use with
protocols allowing a plurality of bits to be stuffed during each bit
stuff/destuff opportunity. This can be accomplished by replacing tri-
level quantizer 32 with a mufti-level quantizer, since stability and
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accuracy issues affecting the operation of multi-level quantizers in 0-E
modulators affect only analog implementations. Accordingly, the scope
of the invention is to be construed in accordance with the substance
defined by the following claims.
