Note: Descriptions are shown in the official language in which they were submitted.
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1 PICTURE-IN-GUIDE GENERATOR WITH DIGITAL TUNER
BACKGROUND OF THE INVENTION
The present invention relates generally to electronic program guide systems
and methods,
and more particularly, to a system and method of providing a picture-in-guide
display using a
picture-in-guide generator with a digital tuner.
The disclosures of the following patent applications are incorporated fully
herein by
reference: Application No. 08/475,395 filed June 7, 1995; International
Application
W096/07270; Application No. 60/053.330 filed July 21, 1997; Application No.
60/061,119 filed
October 6, 1997; and Application No. 60/05.237 filed August 12, 1997. Also
incorporated by
reference is the publication entitled "The CTC 140 Picture in Picture System
(CPIP) Technical
Training Manual" available from Thomson Consumer Electronics, Inc.,
Indianapolis, IN.
An electronic program guide (EPG) provides a television viewer with updatable
television
schedule information in the form of an on-screen graphical display. The EPG
may provide
scheduling information for current and future broadcast programs as well as
summaries of
television program content for a particular program.
One particularly convenient format for an EPG is a picture-in-guide (PIG)
display. A PIG
display includes a real-time video image of a tuned television program
displayed in a small
window inset in a larger graphic guide. The PIG display provides many options
to the viewer.
The viewer may continue to view the television program s/he was watching
before entering the
guide while browsing through the television scheduling information in the
guide. Alternatively,
the program displayed in the PIG window may change to correspond to a selected
channel in the
guide as the viewer cursors through program listings in the guide. The viewer
may also pull up
the PIG display to find out more information about the program s/he is
currently watching, such
as startlstop time or a program synopsis, while continuing to view the program
in the inset PIG
window.
Typically, a PIG display is produced using an EPG generator, which includes a
microprocessor, a vertical blanking interval (VBI) decoder/slicer, an on-
screen display generator,
a digital-to-analog converter (DAC), synchronization (synch) circuitry, and a
memory on one
chip, and a separate chip including a picture-in-picture (PIP) generator, a
DAC, synch circuitry,
and microprocessor interface circuitry.
The PIP generator uses a video signal and memory to create a big background
picture and
a small inset picture. The small picture is generated by storing entire frames
from the video
signal into memory. Complex filtering is performed on these frames stored in
memory to achieve
high quality but reduced in size images. As a result, a composite display
having a big picture in
the background and a small picture as an inset, the PIP window area on the
screen of the
television monitor, is generated.
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1 However, the use of a PIP generator is often costly. For instance, the
memory in the PIP
generator is relatively expensive compared to the rest of the components in
the PIP generator.
Also, high speed computational processing is required to perform the complex
filtering. Also.
using separate chips for the EPG generator and PIP generator requires more
components and is
more difficult to integrate into consumer electronics components such as
televisions, VCR's,
satellite receivers, or the like.
For a PIG display, however, it is unnecessary to provide two real-time video
images since
the main display comprises textual and graphical information, e.g., a program
guide, and not a
real-time. moving video image. Thus, through the use of a PIG generator,
significant cost saving
is achievable. Also, the addition of a dedicated tuner to a PIG generator
provides additional
advantages.
SUMMARY OF THE INVENTION
A display generator feeds drive signals to the output synchronized to the
television
monitor. EPG information is extracted from the television signal and stored in
memory. The
number of pixels used to represent the television signal is reduced. The
reduced number of pixels
television signal is stored in memory. The EPG data and the television signal
are retrieved from
memory and stored in the display generator. The EPG data and the television
signal are fed from
the display generator to the output in a continuous data stream ordered to
produce a picture-in-
guide display on the monitor. The picture-in-guide generator is implemented on
a single
integrated circuit chip along with the circuitry generating the graphics.
The addition of a dedicated tuner to the PIG generator chip allows the PIG
generator to
capture VBI data at any time whether the viewer is watching the television or
not. This greatly
improves the ability of the PIG generator to provide real-time data services.
The additional tuner
also improves the PIG display by allowing a main tuner, such as the television
tuner, to stay on
one channel. This eliminates on-screen display (OSD) "bounce" as the main
tuner provides
horizontal and vertical synchronization (HSYNC and VSYNC) signals that become
unstable
during channel changes. An alternative solution to the OSD bounce problem is
for the PIG
generator to include a function that will generate stable HSYNC and VSYNC at
all times such
as a pseudo-sync generator. However, the drawback is that an addition of a
pseudo-sync
generator would require additional work by a television manufacturer, for
example, to incorporate
pseudo-sync generator capabilities into an existing television chassis.
In one aspect of the invention, a picture-in-guide generator apparatus
includes a digital
tuner provided on a single chip. The digital tuner is configured to receive a
television signal and
to tune the television signal received to a specific channel. The picture-in-
guide generator
apparatus also includes a video interface configured to receive a television
signal tuned to a
specific channel and a tuner selector coupled to the digital tuner and the
video interface and
configured to determine status of the video interface and the digital tuner.
The tuner selector
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outputs one of the television signals received by the digital tuner and the
video interface based
on the determined status. The display controller is also included and is
configured to reduce pixel
size of the television signal outputted by the tuner selector and to extract
electronic program
guide information from the outputted television signal. Furthermore, the
picture-in-guide
generator includes a memory storing the extracted program guide information
and the reduced
pixel size television signal and a display generator retrieving the electronic
program guide
information and the television signal and supplying signals to a television
monitor in an ordered
continuous data stream to produce a picture-in-guide display on the television
monitor.
Many of the attendant features of this invention will be more readily
appreciated as this
picture-in-guide generator apparatus becomes better understood by references
to the following
detailed description considered in connection with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
The features of specific embodiments of the best mode contemplated of carrying
out the
1 ~ invention are illustrated in the drawings, in which:
FIG. 1 illustrates a program guide display in a picture-in-guide (PIG) format;
FIG. 2 is a schematic of a PIG generator according to one embodiment of the
invention;
FIG. 3 is a schematic of the organization of data in RAM according to one
embodiment
of the invention;
FIG. 4 is a block diagram of one embodiment of the invention combined with a
full-screen
video display system;
FIG. 5 is a flow diagram of a process of the host tuner operating with a PIG
generator; and
FIG. 6 is a flow diagram of a process of an auxiliary tuner with a host tuner
in a television
operating with a PIG generator.
DETAILED DESCRIPTION
According to the invention, a picture-in-graphics (PIG) generator is provided
for
producing a PIG display on a television screen or computer monitor. There are
generally three
display types available in a television system using a PIG generator. The
first type is a full-screen
video display comprising a real-time image of a broadcast television program.
The second type,
a PIG display, includes background graphics and a real-time video image in a
small inset
window. The third type of display is a full-screen graphics display.
FIG. 1 illustrates a PIG display 10 of an electronic program guide (EPG)
comprising a
graphics portion 12 and a picture window 14. The picture window 14, hereafter
referred to as
the PIG window, contains a video image of the television program displayed in
the full-screen
video display, but in reduced size, generally reduced by a factor of three in
both width and height,
i.e., 1 /9 the size of the screen.
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The graphics portion 12 of the PIG display 10 takes up a majority of the
screen. The
graphics portion generally includes text, icons, and background graphics of
several different
colors. The graphics may include highlighting of text or sections of the
screen. In an EPG
system. the viewer can generally navigate through different guides without
changing the
television program displayed in the PIG window 14. In some EPG systems, when
the viewer
places a cursor 16 on a different channel designation 18 or program title 20
in the graphics
portion, the system automatically tunes the associated digital tuner 50, if
available. or the host's
tuner to the selected channel and displays the program broadcast on that
channel in the PIG
window 14.
The components necessary in the present invention to generate a PIG display 10
are
provided on a single chip to be incorporated into televisions, VCR's, stand-
alone units. satellite
receivers or the like. By providing all the components on a single chip, the
overall package size
can be reduced as well as the overall gate count and bus interface size of
that chip.
FIG. 2 is a schematic of the components of the present invention provided on a
single chip
21. These include a microprocessor 22, a memory controller or direct memory
access (DMA)
device 24. synchronization regenerating (synch) circuitry 28, analog-to-
digital conversion (ADC)
30c, automatic gain control circuitry (AGC) 30b, DC clamp circuitry 30a, a PIG
window
generator 32, a display generator 34, a color space converter 60 digital-to-
analog conversion
(DAC) circuitry 36, pixel clock 38, NTSC decoder 52, and VBI dicer ZZ.
The microprocessor 22 is relatively slow compared to the video processing
hardware, e.g.,
the PIG window generator 32 and the display generator 34. The microprocessor
22 organizes
data storage in the RAM 26 and can assign addresses for both text data and
video data.
Preferably, there is only one RAM 26. The RAM 26 is accessed by four different
components:
the microprocessor 22, the PIG window generator 32, the display generator 34
and the VBI slicer
ZZ. This places a high access load on the RAM as all four components may vie
for access to the
RAM simultaneously. However, only one sample of so many bits may be accessed
per cycle.
A multiplexing device is used to resolve the arbitration between the
components. Accordingly,
the microprocessor 22, PIG window generator 32, the display generator 34, and
the VBI dicer
ZZ each access the RAM 26 through the DMA 24. The DMA 24 is a multiplexing and
arbitrating
circuit that facilitates sharing of the RAM 26 by switching access between the
four components
in turn. The DMA 24 includes buffer memories to temporarily store data input
from out-of turn
components between access cycles. The DMA 24 stores text and video data in the
correct
address in the RAM 26 and then retrieves the appropriate data from a selected
address from the
RAM 26 when needed.
The system also receives a video signal from the digital tuner 50. Otherwise.
it receives
a video signal from the host YY. The digital tuner is a National Television
Standards Committee
(NTSC) tuner implemented in digital circuitry as opposed to analog circuitry.
One such example
of a digital tuner is a NTSC tuner created as an integrated single chip and is
disclosed by US
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1 Patent No. 5,737,035 issued to Rotzoll, the disclosure of which is
incorporated herein by
reference. The digital tuner 50 provides a separate data source for an EPG
System for data such
as VBI data or video signals.
Conventional EPG systems rely upon the NTSC tuner available in the host
system, the
host system being either a TV or a VCR. In a dual-tuner host, a host system
having two NTSC
tuners, the EPG system can collect EPG and related data while the viewer is
watching the
television. In a single-tuner host, a host system having only one NTSC tuner,
the EPG system
can only collect information when the host system is off. The dependence on
the NTSC tuner
of the host system restricts the timeliness and hence the quality of the
information provided by
the EPG.
In a single-tuner host, the NTSC tuner which is pan ofthe television or VCR
provides the
video signals to display the television program in a conventionally full-
screen format. The digital
tuner 50 independently supplies the video signals to the PIG generator 32 to
present the PIG
display. As a result, the PIG generator always has an available data source,
whether the host
system is on or off or if the NTSC tuner of the host system is otherwise
occupied. Therefore, the
availability of an independent NTSC tuner, i.e. the digital tuner 50,
completely under the control
of the EPG ensures that timely data is provided to the EPG. This further
enables real-time
services containing real-time or constantly updated data. such as weather or
stock reports, to be
provided and used by the PIG generator without disruption of the services
being provided by the
host system.
Furthermore, the digital tuner 50 is of a lower quality and cost than a
typical NTSC tuner
of a host system. Hence, the digital tuner 50 in the PIG generator provides a
low-cost and
effective picture-in-picture (PIP) tuner for a TV or a VCR not otherwise
equipped. This can
prove to be advantageous to manufacturers of TVs and VCRs that want to provide
PIP
functionality or a secondary tuner but are prohibited by cost concerns.
FIG. 4 is a simplified block diagram of one such implementation. Tuner 301 is
part of the
host system and digital tuner 303 is the tuner coupled with the PIG generator
of the present
invention. Both tuners 301 and 303 provide independent video signal to a tuner
selector 305.
The tuner selector 30~ selects the video source for the PIP/PIG display that
will be created by the
PIG Generator system 350. Since the digital tuner 303 is less expensive and
generally lower
quality than the tuner 301, the digital tuner 303 would not usually be used as
a main picture
source. The PIG generation system 350 extracts EPG data from the video signal
and reduces the
picture size and stores the resultant text and video data in the EPG memory
309. If a digital tuner
is available to the system, then the EPG system tunes the digital tuner 303;
extracts EPG data;
and stores the data in EPG memory 309 anytime that the EPG is not on-screen.
FIG. 5 illustrates an overview of the host tuner operating with the PIG
system. In step
411, the process determines the state of host system. In one embodiment, the
state of the host
system is determined by examining a series of electrical control lines such
that when one or more
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1 control lines have a ''logical 1 ", the host system is powered on.
Alternatively, a signal detector
determines the state of the host by examining the television signals supplied
by a tuner of the host
system to the PIG system. When no television signals supplied by the host
system is detected,
the host system is powered off. In another embodiment, the state of the host
system is
determined by a monitor program (implemented in software, hardware, or both)
that transmits
commands to a similarly enabled host system and receives responses from the
host system.
Based on the commands sent and the responses received, the state of the host
system is
determined by the monitor program. For example, if the monitor program sends a
power on
status command to the host system and no response is received within a
predetermined amount
of time, the host system is determined to be powered off. However, if the
monitor program sends
a power on status command to the host system and a successful response is sent
from the host
system, then the host system is determined to be powered on.
If the host system is powered on, as determined in step 413, then the EPG does
not extract
data. If the host system is not powered on, as determined in step 413, then in
step 419 the host
tuner is tuned to a data channel to receive the television signal containing
data. In step 417, the
data is extracted and, in step 421, the data is sent to the EPG memory.
Referring back to FIG. 4, it is preferable that the tuner 301 provides the
video source for
the full-screen video display that is feed from the tuner selector 305 to a
display-type selector 307
which supplies full-screen video images to a display 310. Similarly, the PIG
generator system 350
provides the PIG display to the display-type selector 307 which provides the
images to the
display 310.
FIG. 6 illustrates an overview process of the host tuner in a television
operating in
conj unction with the digital tuner acting as an auxiliary tuner. In step 451,
the process determines
the state of television, similar to step 411 illustrated in FIG. 5, by
examining control lines or
using a monitor program. If the television is powered on, as determined in
step 453, then the
process determines in step 455, if the television is in full screen mode. Full
screen mode means
that the television handles full screen television images, i.e. a real-time
video image of a tuned
television program displayed on the entire television display. If the
television is in full screen
mode, then the host tuner in the television continues to handle the full
screen television images
for the television display in step 461. Also, the auxiliary tuner is tuned to
a data channel to
receive the television signal and extracted data is routed to the EPG memory
(step 463).
If the television is not in full screen mode, then the host tuner in the
television is tuned to
a data channel to receive the television signal and extracted data is routed
to the EPG memory
(step 457). In step 459, the auxiliary tuner handles the television images for
the television
display, in one embodiment, for a PIG display to include a real-time video
image of a tuned
television program displayed in a small window inset in the larger graphic
guide. However, if
the host system is not powered on, as determined in step 453, then the process
connects a pre-
assigned tuner, the auxiliary or host tuner, to handle the EPG data and the
other tuner to handle
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1 the television images for the television display. In one embodiment, the pre-
assigned tuner is the
auxiliary tuner, the digital tuner, to handle the EPG data. In this
embodiment, the digital tuner
being of lower quality then the host tuner is pre-assigned to handle the EPG
data with the
television off to ensure that the host tuner is immediately available to
handle the full screen
television images for the television display when the television is powered
on.
Referring back to FIG. 2. horizontal and vertical (h- and v-) synchronization
signals are
split from the video signal provided by the host tuner and routed to the synch
circuitry 28. The
hsync and vsync signals extracted from the conventional video baseband signal
(CVBS) is used
in video decimation by the PIG window generator. The synch circuitry 28 is
coupled to a pixel
clock 38. The pixel clock determines the x- and y-coordinates of each pixel to
be displayed on
the screen. The y-coordinate corresponds to the scan line number of the
screen, and the x-
coordinate corresponds to the pixel number in each scan line.
The video portion of the input video from the digital tuner ~ 0 is processed
from a 45MHz
intermediate frequency (I/F) signal to a CVBS by a demodulator XX. The CVBS
signal is
1 ~ converted into a stream of digital samples by the analog to digital
converter (ADC) 30c. The
CVBS signal is first processed by the DC clamp 30a and automatic gain control
30b to reduce
distortion in the signal due to, for example, low frequency noise and do
bounce when switching
the signal.
The NTSC decoder 52 converts the digital sample stream to digital YUV video
signals
corresponding to a full screen video image. The PIG window generator 32
receives the digital
YUV video signals and reduces the overall picture size by decimating the video
data before
sending it to the DMA 24 for storage in the video data section 33 of the RAM
26. To decimate
the video data, the PIG window generator 32, in cooperation with the synch
circuitry 28, selects,
for example, one out of every three pixels and one out of every three scan
lines. i.e., a 1:3 ratio,
and then sends this data to the DMA 24 for storage in RAM 26. Other decimation
ratios are
possible., e.g., 1:4, in order to generate different sized PIG windows.
The correct address for storing the video data from PIG window generator 32 in
the RAM
26 is determined by address mapping circuitry 40 which is preferably
incorporated into the DMA
24. Using the synch signal from the synch circuitry 28 and the pixel clock 38,
the address
mapping circuitry 40 stores video data corresponding to each pixel on the CRT
in an appropriate
address site in the RAM for later access for display. This process is
generally referred to as "bit
mapping."
The display generator 34 includes a graphics generator which formats fonts for
the text
to be displayed, icons, color and highlighting, and background graphics for
the graphics portion
12 of the PIG display 10. The graphics data is routed to the address mapping
circuitry 40 which.
in cooperation with the DMA 24, stores the video data in address sites in the
RAM 26
corresponding to pixel coordinates on the screen.
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1 Generation of the PIG display 10 (FIG. 1 ) according to an embodiment of the
present
invention in FIG. 2 will now be explained.
In response to a viewer command device. e.g., an IR remote, for a given PIG
display, the
microprocessor 22 accesses the appropriate text data for that display from the
raw text data 31
in the RAM 26 in FIG. 3. The microprocessor 2? configures the text data for
display and routes
the text data, with appropriate addresses for display of the text, to the DMA
24 for storage as
video data 33 in the RAM 26.
All video data for generating the PIG display 10, including the text and
graphics of the
graphics portion 12, and the video image of the PIG window 14, is stored as
video data 33 in the
RAM 26 as described above. The display generator 34, in cooperation with the
address mapping
circuitry 40 and synch circuitry 28, accesses the pre-organized contents of
the video data 33 in
the RAM 26 to create an image for display on the screen of the CRT 62. The
data for each pixel
to be displayed on the screen is stored as video data 33 in the RAM 26 with an
address
corresponding to the x- and y-coordinate of that pixel on the screen. The
display generator 34
1 ~ accesses the appropriate data from the RAM 26 for each pixel in sequence
as determined by the
pixel clock 3 8 and synchronization for pixel output uses the h- and v-synch
signals from the host
tuner.
Although it is preferable to store the entire screen field or frame in RAM 26
at one time
in a bit mapped fashion; less than the entire screen, i.e., only part of the
screen, could be stored
at one time and the display processing could in effect be executed in pixel
groups that are smaller
than the entire screen.
The display generator 34 outputs digital YLJV signals. The color space
converter 60
digitally converts the YLJV signals to digital RGB signals. The DAC circuitry
converts the
digital RGB to analog RGB signals for display on the screen of the CRT 62.
In an alternative embodiment of the invention, RAM 26 is located "off chip"
where it is
connected by a data bus to DMA 24. RGB converter 60, CRT 62, and viewer
commands 70 are
part of the television apparatus. In other words. these components serve the
dual function of
helping to display the television signal in conventionally in a full screen
format and to display
the picture-in-guide format. The other components are unique to the picture-in-
guide format.
The design of the PIG circuitry according to the present invention on a single
chip 21
provides a more economical package with a reduced size and gate count. The
invention reduces
overall gate count by requiring only a single gate array for each of the
microprocessor 22, synch
circuitry 28, DAC circuitry 36, digital tuner 50 and DMA 24, instead of two
gate arrays for each
of these components on separate PIP and EPG chips as used in known television
systems to
generate a PIG display. It should also be noted that display generator 34
feeds both picture
information and EPG information to CRT 62 under the control of pixel clock 38
and synch
circuitry 28 in a continuous stream of data. Thus. a video (i.e., moving
picture) image is created
in an EPG display without a high speed switch.
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The described embodiment of the invention is only considered to be preferred
and
illustrative of the inventive concept; the scope of the invention is not to be
restricted to such
embodiment. Various and numerous other arrangements may be devised by one
skilled in the
art without departing from the spirit and scope of this invention. For
example, separate RAM's
could be used to store the EPG data and the reduced size television signal.
Further, the invention
could be used in a digital television transmission system as well, in which
case the ADC, DAC,
and VBI slicer could be eliminated.
15
25
35
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