Note: Descriptions are shown in the official language in which they were submitted.
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SYSTEM FOR CONTROLLING MODE CHANGES IN A VOLTAGE DOWN-CONVERTER
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to voltage converters. More particularly, the invention
relates
to the management and control of an on-chip voltage down-converter that steps
down an
external power supply to a lower, internal power supply for memory devices.
2. The State of the Art
Semiconductor systems involve circuitry requiring a broad range of power.
Microprocessors typically operate at higher voltage levels than memories, for
example. In
order to make an external power source compatible with both a microprocessor
and its
memory, for example, the voltage from the external power supply must be down-
converted.
FIG. 1 illustrates one example of a prior art voltage down-converter.
Amplifier 2
drives the gate of p-channel metal-oxide semiconductor (MOS) transistor 4. The
source of
transistor 4 connects to external power source 6 and the drain of transistor 4
connects to load
circuit 8. The voltage across load circuit 8 drops as current consumption in
circuit 8
increases, and when the voltage drops below that of reference generator
circuit 10 then
amplifier 2 lowers the voltage across the gate of transistor 4. Transistor 4
increases in
conductivity as its gate voltage decreases and consequently supplies load
circuit 8 with
current.
FIG. 2 illustrates another example of a prior art voltage down-converter. N-
channel
MOS transistor 20 has a low threshold voltage and is configured as a source
follower. In
one example driver transistor 20 is a natural MOS built on a substrate without
a special
implant and with a very large aspect ratio (W/L). Replica transistor 22 is
coupled to driver
transistor 20 and has a smaller aspect ratio than transistor 20. Amplifier 24
and resistors 26
complete a control loop with transistor 22. Amplifier 24 controls the gate of
transistor 22
and keeps the voltage at node 28 in a desired range. Consequently transistor
20 provides
current through node 30 when voltage at node 28 drops below a predetermined
level.
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FIG. 3 illustrates a more detailed version of the voltage converter in FIG. 2.
Replica
circuit 40 has a similar function to that of transistor 22 in FIG. 2. Stand-by
circuit 42 and
active circuit 44 perform the function of driver transistor 20 in FIG. 2. The
prior art voltage
converter in FIG. 3 has two operation modes: stand-by and active. In stand-by
mode,
current leakage to the load is very low. In active mode the transistors are on
and provide up
to the maximum level of current.
One problem with the aforementioned designs is the need for perfect matching
among the driver and reference parts. Another problem is that temperature and
process
variations must be compensated by the replica circuit. Also, a reference
circuit is always on
since the follower needs a bias to operate. Finally, problems arise in the
prior voltage down-
converters while switching between active and stand-by mode. The prior voltage
down-
converters may fail to achieve a good response to the current step. The prior
voltage down-
converters may also have dangerous voltage spikes while switching modes.
BRIEF DESCRIPTION OF THE INVENTION
The invention provides a system to manage the switching between active to
stand-by
transition and stand-by to active transition. The system to manage switching
between active
and stand-by and stand-by to active modes has two transitions. The first
transition is the
stand-by to active transition. In one embodiment, the load current for the
internal, stepped-
down power is initially furnished by a load capacitor, acting as a charge
tank, on the internal
power node. Prior to entering active mode, a replica transistor for the active
mode is biased
to charge a capacitor. When the voltage at the internal power supply node
drops to a
determined level, a switch biases the driver transistor to the node with the
capacitor that was
charged by the replica transistor, thus activating the driver transistor and
increasing the
current to the load circuit.
The second transition of the system is the active to stand-by transition. The
transition is indicated by the fall of an enable signal. In one embodiment, a
delay signal is
interjected between the fall of the enable signal and the time at which stand-
by mode is
entered. The delay signal provides time for a driver transistor gate to be
discharged and a
node to be charged towards stand-by values. Comparators charge and discharge
the gate and
node as long as the delay signal is high. A switch disconnects the driver
transistor from the
power supply node when the enable signal falls so that current stops flowing
from the driver
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transistor while the comparator discharges the gate of the driver transistor.
The system
enters stand-by mode at the end of the delay signal.
BRIEF DESCRIPTION OF THE FIGURES
FIG. 1 is a schematic diagram of a prior art voltage down-converter.
FIG. 2 is a schematic diagram of a prior art voltage down-converter.
FIG. 3 is a more detailed schematic diagram of the prior art voltage down-
converter
in FIG. 2
FIG. 4 is a schematic diagram of one part of a voltage down-converter system
for
transition from stand-by to active modes.
FIG. 5 is a diagram of timing signals used for transition from active to stand-
by
modes.
FIG. 6 is a detailed schematic diagram of the system in FIG. 4 including
circuitry for
transition from active to stand-by modes.
FIG. 7 is a flow diagram illustrating a method of transitioning from active to
stand-
by modes according to one embodiment of the invention.
DETAILED DESCRIPTION OF THE INVENTION
Persons of ordinary 'skill in the art will realize that the following
description of the
present invention is only illustrative and not in any way limiting. Other
embodiments of this
invention will be readily apparent to those skilled in the art having benefit
of this disclosure.
FIG. 4 is a schematic diagram illustrating one embodiment of the invention.
Circuit
50 replaces active circuit 44 of FIG. 3 and is provided to illustrate the
transition from stand-
by to active mode. Transistor 52 serves as a replica transistor while
transistor 54 serves as a
driver. External power supply 56 couples to both transistors 52 and 54. In
stand-by mode,
switches 58, 60 and 62 are off, while switch 64 is on. One of ordinary skill
in the art will
appreciate that a switch conducts electricity when on and does not conduct
electricity when
off.. Transistor 52 is biased by current fiom transistor 66 and charges node
68, which in one
embodiment includes capacitor 70, to approximately 2V. In one embodiment
capacitor 70 is
400pF. Node 72 is kept one threshold lower, or approximately 800 mV. The gate
of
transistor 54 is therefore 800mV lower than its source, which is coupled to
internal voltage
source VCC 74, and therefore off. Additionally, switch 62 prevents current
from flowing
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through transistor 54 to the load circuit (not shown). In one embodiment,
transistors in the
invention are p-channel MOS transistors.
Switches 58, 60 and 62 are turned on and switch 64 turns off in order to
transition to
active mode. Transistor 54 is decoupled from node 72 and is coupled to node
68, which is at
approximately 2V. Transistor 54 activates and may conduct current through the
now
coupled transistor 76 to the load circuit (not shown). With switches 58, 60
and 62 on, and
switch 64 off, circuit 50 is in active mode.
FIG. 5 illustrates a timing diagram with enable, delay and enable-delayed
signals.
Enable signal 78 is low during stand-by mode 80. Enable signal 78 rises to
communicate the
transition from stand-by mode 80 to active mode 82. In the prior art, a
falling enable signal
would communicate the transition from active to stand-by mode. The invention
provides a
delay before transitioning from active to stand-by modes. In one embodiment,
the delay is
approximately 300ns. Delay signal 84 is high during to-stand-by mode 86 and
off in stand-
by mode 88. Enable-delayed signal 90 rises at the beginning of active mode 82
and remains
high until the end of to-stand-by mode 86.
FIG. 6 is a schematic diagram illustrating one embodiment of the invention.
FIG. 6 is
a more detailed illustration of the circuit illustrated in FIG. 4. Circuit 100
replaces active
circuit 44 of FIG. 3 and is provided to illustrate the transition from active
to stand-by mode.
Transistor 102 serves as a replica transistor while transistor 104 serves as a
driver. External
power 106 couples to both transistors 102 and 104. In' active mode, switches
108, 110 and
112 are on, while switch 114 is off. When the circuitry (not shown) associated
with system
100 receives a low input from enable signal 78 (shown in FIG. 5), switches
108, 110, and
112 turn off. Switch 114 is off during active mode 82 and remains off until
the fall of
enable-delayed signal 90 (i.e., switch 114 remains off until stand-by mode
88), at which time
switch 114 turns on. Current from transistor 116 biases transistor 102. Node
118 is
disconnected from the gate of transistor 104.
Comparators 120 and 122 are activated during to-stand-by mode 86 (shown in
FIG.
5) with delay signal 84. With switches 110 and 114 off during to-stand-by mode
86,
comparator 120 compares the voltage at node 124 with node 126 and discharges
node 124
toward ground as long as the potential at node 124 is greater than that at
node 126.
Comparator 122 charges node 118 toward a predetermined value, which in one
embodiment
is approximately 2V. When enable-delayed signal 90 falls at the end of to-
stand-by mode 86
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(see FIG. 5), switch 114 turns on and couples the gate of transistor 104 to
node 126 and
shuts off transistor 104.
FIG. 7 is a flow diagram illustrating the method of transitioning from active
to stand-
by modes. In block 150, receiving a to-stand-by signal during the transition
from active to
stand-by modes. In block 155, decoupling a driver transistor from a load
circuit. In block
160, comparing a drive transistor gate voltage to a first predetermined node
voltage and
discharging the gate toward ground as long as the gate voltage is greater than
the
predetermined node voltage. In block 165, comparing the voltage at a second
predetermined
node to a predetermined voltage and charging the second predetermined node
towards the
predetermined voltage. In block 170, switching off the driver transistor.
While embodiments and applications of this invention have been shown and
described, it would be apparent to those skilled in the art that many more
modifications than
mentioned above are possible without departing from the inventive concepts
herein. The
invention, therefore, is not to be restricted except in the spirit of the
appended claims:
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