Note: Descriptions are shown in the official language in which they were submitted.
CA 02529132 2005-12-12
WO 2004/111596 PCT/EP2004/050633
1
D E S C R I P T I O N
Serial Bus Interface and Method for Serially Interconnecting
Time-Critical Digital Devices
BACKGROUND OF THE INVENTION
Technical Field of the Invention
The invention generally concerns digital serial buses and more
specifically relates to a serial bus interface for time-
critical serial interconnection of peripheral devices and a
method for operating same.
Description and Disadvantages of the Prior Art
In the arenas of entertainment electronics, fabric automation,
and also computer systems (e. g. servers, mainframes, etc.),
embedded control of peripheral devices having remote
actor/sensor interfaces, serial bus standards like IzC axe
used to access the peripheral devices for read and write their
registers as well as getting or setting environmental
information. Such a serial bus standard (specification) is
defined by an interconnecting wire and interface structure and
all the formats and procedures for communication, i.e.
communication protocols, within the (embedded) system. The
communication protocol, in particular, avoids all
possibilities of confusion, data loss and blockage of
information.
The I'C (IIC = Intra Tntegrated Circuit) bus, more
particularly, is a universal 2-wire bus, i.e. it consists of a
clock and a data line each of which are wired 'OR' (Figure 1).
This means that in rest or when transmitting a logical '1',
the clock and the data line are pulled up by a resistor with a
large value and thus can be driven down with one or more of
CA 02529132 2005-12-12
WO 2004/111596 PCT/EP2004/050633
2
open collector outputs of the controller chips implemented on
the bus. Due to the pull-up resistors, when the bus is free,
both lines are in a 'HTGH' state. A master usually determines
the clock speed, but a particular chip on the bus can slow the
transmission down, by prolonging the cycles. Peripheral
devices connected to the bus are addressed completely by
software. In addition, new devices or functions can easily be
clipped on to an existing TZC bus. Data are transmitted
between the master and slave at speeds of 100 kHz, 400 kHz or
3,4 MHz. Generation of clock signals on the IZC bus is always
the responsibility of master devices i.e. each master
generates and sends .its own clock signals when transferring
data on the bus. In addition, the I2C bus protocol allows fast
devices to communicate with slow devices and to define a bus
clock source if different devices with different clock speeds
are connected to the bus.
Referring to Figure 1 again, as mentioned above, an I'C bus
implementation comprises two wires, a serial data (SDA) and a
serial clock (SCL) wire that carry information between the
devices connected to the bus. Each device is recognized by a
unique address and can operate as either a transmitter or
receiver of information, depending on the function of the
device. For instance, an LCD driver is only a receiver whereas
a memory can both receive and transmit data. In addition,
devices can also be considered as masters or slaves when
performing data transfers. As an illustrative example, a
master is a device which initiates a data transfer on the bus
and generates the clock signals to permit that transfer. At
that time, any device addressed is considered a slave.
The IZC bus is a typical solution for so-called "embedded
applications", i.e. it is used in a variety of
microcontroller-based consumer and telecommunication
applications as a control, diagnostic and power management
bus. The typical application field for the I'C bus is inside
(i.e. embedded in) devices like television sets and telephone
CA 02529132 2005-12-12
WO 2004/111596 PCT/EP2004/050633
3
devices like phone base-stations of digital (DECT) cordless
phones, where buses are not much more than a meter.
Other known serial interface specifications to be mentioned in
the present context are the known "FireWire(TM)" interface for
high-speed data transfer between peripheral devices and a
computer, and the known "Universal Serial Bus (USB)"
interface, a plug-and-play interface between a computer and
add-on devices (such as audio players, joysticks, keyboards,
telephones, scanners, and printers).
Although serial buses, in general, don't have the throughput
capability of parallel buses, they advantageously do require
less wiring and fewer IC connecting pins. But within the above
mentioned limited electronic compartment, those serial buses
only run at low speed (100 Kbit/s - 3Mbit/s) compared to the
controller in charge using those buses to access the remote
functions. Thus the controller has to wait, wasting a lot of
processing power until a remote access has completed.
Furthermore those buses are laid out to attach several
peripherals as mufti-drop participants on the same wires.
While such implementation saves some wiring effort it also
introduces specific weakness in regards to reliability and
availability since the whole setup is exposed to complete
failure in case just one element on the bus fails.
Thus, for high availability and fault tolerant implementation
as well as covering concurrent maintenance aspects, a
different setup must be chosen. Each peripheral requires its
own interconnection to the controller in charge for driving
these peripheral units. But with standard buses like the USB
mentioned above there is still the small bandwidth issue while
migrating to more advanced standards like USB drives, a higher
pin count and more effort in front end synchronization
circuitry are required.
It is therefore desirable to provide a serial bus interface
CA 02529132 2005-12-12
WO 2004/111596 PCT/EP2004/050633
4
and method for operating same that can be used in the above
discussed application fields and that, in particular, are
tolerant against variations and differences between different
peripheral devices in clock speeds, circuit (line) lengths or
the like. It is emphasized that 'time-critical' in the present
context means that the clock cycle time is considerably lower
than the run time between the master and the peripheral
devices connected to it.
SUMMARY OF THE INVENTION
The underlying idea of the invention is to keep a driver
buffer of the bus master most time active, except of a defined
time interval where a response from the slave is expected.
This approach guarantees that a signal echo caused by a
request packet sent from the master reflected on a far non-
terminated end of the slave gets terminated. The traveling
time for such signal echo is defined by the distance in wire
length between the master and the slave and/or the electrical
characteristics of the transmission line.
According to a preferred embodiment of the invention, a serial
peer-to-peer interface for a digital serial bus and an
according method for operating same are proposed, wherein the
serial bus comprises a bus master and at least one bus slave
and wherein the serial peer-to-peer interface consists of at
least one bi-directional data line and one unidirectional
clock line that allow for operation at any clock frequency, in
particular for operation in a range where the clock period is
shorter than the traveling time of data on the data line, and
wherein the bus master comprises at least one driver buffer
for sending and/or receiving data. The proposed interface and
method, in particular, keep the driver buffer active, except
of a defined time interval where a response from the at least
one bus slave is expected. Thus a request echo of a request
packet sent from the master reflected on a far non-terminated
end of the slave gets terminated automatically.
CA 02529132 2005-12-12
WO 2004/111596 PCT/EP2004/050633
In other words, the slave receives the request packet, adds
some processing time and sends a response delayed by a certain
time delay. The response packet arrives at the master after a
further traveling delay. At that time, the request echo is
already terminated and does no more disturb the data
transmission.
The proposed bus interface comprises an adjustable delay
element at the master as well as at the slave that move the
above mentioned interval exactly to that point where a
response packet arrives at the master. After such response was
received, the driver buffer gets activated again while an
according driver buffer on the slave side gets deactivated.
Due to an active termination, a response echo gets canceled
after a further round trip. During that time, any input on a
receiver buffer on the slave side is ignored.
The approach proposed herein allows for driving a high fan-out
of peripheral devices (100 ... 1000) by a controller on
interfaces with just two wires while at the same time high
data transmission rate can be achieved and point-to point
interconnection allows for fault tolerance and concurrent
maintenance. Furthermore the data transfer rate can be
controlled by a master instance in the controller and no
additional components like oscillators or phase-locked-loops
(PLLs) are required on the peripheral slave. Also by having
always only one driver active at the respective end of the
transmission line the implementation allows for usage of
driver and receiver buffers for standard voltage levels while
keeping the advantages of a low resistance terminated bus but
avoiding high driving currents in average.
It is noteworthy that the method described herein for bi-
directional data exchange at high frequency is not limited to
just one data line but can be applied to any arbitrary number
of bi-directional data lines running in parallel with same
CA 02529132 2005-12-12
WO 2004/111596 PCT/EP2004/050633
6
delays and synchronous to the clock applied to increase the
throughput of such interface.
The proposed serial interface/bus protocol and apparatus, in
addition, allow to interconnect at least two time-critical
digital end devices including but not limited to any consumer
electronics (TV sets, Set-Top boxes, DVD players, digital
video cameras, digital phones etc.) in a broad frequency area
and to allow a precise timing of these interconnected devices
independent of the absolute and relative cable lengths between
the devices.
Furthermore, the proposed serial interface and method for
operating same enable full-automated self-calibration of an
underlying serial bus also in the above mentioned environment
including devices with distinguishing clock speeds and/or
distinguishing serial bus line lengths.
BRIEF DESCRIPTION OF THE DRAWINGS
In the following and referring to the accompanied drawing, the
invention will be described in more detail by way of preferred
embodiments from which further features and advantages of the
invention become evident. In more detail,
Figure 1 is a schematic view of the bus structure and
wiring of the known I2C serial bus standard;
Figure 2 is a more simplified view of a serial bus
structure as in Figure 1 in order to
illustrate the disadvantages of prior art
serial bus systems;
Figure 3 is a schematic block view of an embedded
controller function according to the
invention that connects to several
CA 02529132 2005-12-12
WO 2004/111596 PCT/EP2004/050633
7
peripheral devices via a serial bus
interface;
Figure 4 shows the details of the signal path between
an embedded controller and a slave function
of a peripheral device shown in Figure 3;
Figures 5A - C illustrates the relationship of data
patterns on a transmission line depicted in
Figure 4 in respect to two processing units
on a master and on a slave side; and
Figures 6A, B are flow diagrams in order to illustrate a
method for time delay adjustment according
to the invention.
DETAILED DESCRIPTION OF THE PREFERRED EMEODIMENTS
Figure 1 depicts a typical structure of the known I'C serial
bus standard. It consists of a serial clock line (SCL) 10 and
a serial data line (SDA) 15. In the present example, there are
connected two IZC masters 20, 25 and two IzC slaves 30, 35 to
the clock line 10 and to the data line 15 of the T'C bus.
Both, the clock line 10 and the data line 15, are driven by a
supply voltage 50 (+U) and are terminated via the respective
two supply lines 52, 54 by means of two high-impedance
(typically in the range of '2,2 kOhm' each in the present
example) resistors 40, 45. The shown IZC bus is a "multi-drop"
bus which means that there can be attached a number of master
and slave devices to the bus.
The shown IzC bus structure further comprises said high-
impedance pull-up resistors 40, 45 in order to achieve a high
level signal since all attached device are open collector
drivers. Therefore the bus is not terminated with line
impedance which means the signal and clock period must be much
CA 02529132 2005-12-12
WO 2004/111596 PCT/EP2004/050633
8
longer than the travelling time of an electrical pulse along
the data line 15. In addition, the multi-drop network of the
bus would generate lots of electrical reflections at a high
speed operation.
In Figure 2 it is illustrated how reflection-free transmission
is achieved on a low impedance line 60 in a bus structure
depicted in Figure 1. The line 60, at both terminal ends,
comprises resistors 65, 65' (R1) and resistors 70, 70' (R2)
that have to meet the line impedance to avoid any reflection.
Therefore the drivers 75, 75' (for sending data on the bus)
and 80, 80' (for receiving data from the bus) for such a line
must drive a high current to get the appropriate voltage swing
on the other end of the line. This causes high power
consumption to support standard voltage levels or requires
special receivers with low thresholds and potential
differential transmission for noise immunity. To drive a 50
Ohm line at a voltage swing of 2 V would require 40 mA drive
current which would add-up several watts for multiple line
support.
Figure 3 shows a preferred embodiment of the serial bus
interface according to the invention where a master (embedded
controller function) 100 is connected to exemplarily three
slaves (peripheral devices 1 - n) 125 via separate peer-to-
peer (point-to-point) line connections 110 - 120. The embedded
controller function 100 contains a serial master function 105
that connects to an internal bus interface of the embedded
controller function 100. The serial master function 105
contains several registers that allow by read or write access
from the controller core to program the master and transmit or
receive data by use of the serial interfaces 110, 115 and 120
to/from the peripheral devices 125.
The peripheral interfaces (devices) 125 contain a serial slave
function 130 and additional local registers and actor/sensor
interfaces 135. The data sent by the master function 105 act
CA 02529132 2005-12-12
WO 2004/111596 PCT/EP2004/050633
9
on those interfaces in the peripheral devices 125 and status
information from those interfaces are sent to the master
function by use of a read from the master. Each serial
interface 1l0 - 120 consists of two wires, one carrying data
in a half duplex operational modus, and the other being an
adjacent clock. All data are transmitted in both directions
synchronous to this clock which is fed from the master
function 105.
With a proper physical layout of the shown wiring 110 - 120 in
a serial bus system while taking data signal integrity into
account, the clock frequency to be used is adjustable in a
wide range from DC up to highest frequencies. The upper
frequency limit is given by the distance between controller
and remote device due to attenuation as well as chip silicon
and board layout characteristics where data and clock edges go
out of synchronization due to skew and runtime delay effects
between clock and data. Such upper limit may be'in the range
of 500 MHz while distances up to several meters can be covered
at lower frequencies. In case those interfaces are driven off-
card, the signal quality can be kept by using impedance
matching coaxial cabling. Due to the synchronous design, a
wide variety of implementations and requirements can be
covered.
Figure 4 shows the details of the signal path between the
master function 105 in the embedded controller 100 and the
slave function 130 in the peripheral device 125.
The clock signal is driven by an output buffer 205 inside the
controller which matches, together with a resistor 240 located
close to the output pin on device 100, the impedance of the
transmission line 245. The clock signal is received by an
input buffer 250 which feeds at least the slave function 130
and may provide further device functions internal and external
to the peripheral device 125. The bi-directional data signal
is interconnected to the master function 105 by an output
CA 02529132 2005-12-12
WO 2004/111596 PCT/EP2004/050633
buffer 255 and an input buffer 265. Both buffers are connected
by a same pin 220 arranged on the module 100 to a line
impedance matching resistor 215. The output buffer 255 gets
enabled by the control signal 225 for data transmission to the
peripheral device 125 and while the data line 210 requires a
termination for any reflected signal pattern.
The peripheral device 125 provides a same bi-directional data
input 270 and output 260 that connect to the pin 230 which is
followed by the series termination resistor 250. The output
buffer 260 also gets enabled by the control line 235 from the
slave function 130.
To exchange data between the master function 105 and the slave
function 130, a defined data protocol may be used. Such a
protocol, in a preferred embodiment, consists of a tag
information what type of data are send or requested, an
address information for selecting specific registers in the
slave as well as a data portion. Also a special pattern may
exist to issue a reset operation at the peripheral device 125.
A further special pattern may exist just to request an
unspecified or status information from the slave. The master
always has full control of the sequence of a transaction.
Accordingly it sends a tag to the slave 130 to start the
transaction. The arrangement allows for the data and clock
signals to arrive synchronously on the processing unit 290
which contains a de-serialize function and a state machine.
The details of this function and this state machine are
described in more detail hereinafter with reference to Figure
5A.
According to the protocol implemented the processing unit 290
assembles a response packet and sends it back to the
processing unit 280 which also contains a state machine and a
de-serialize function. While receiving the processing unit 280
disables the driver 255 by the control line 225 for a certain
timeframe after a request was sent to allow for the receive
CA 02529132 2005-12-12
WO 2004/111596 PCT/EP2004/050633
11
buffer 265 to get the response at full voltage swing and not
reduced by line termination. This allows for the receive
buffer 265 to operate with well-known Transistor-Transistor
Logic (TTL) or Low-Voltage Transistor Logic (LVTL) standard
voltage levels.
In case the clock period (reciprocal frequency) comes in the
range of the round trip delay of the signal or is below such
time, a further function of the delay element 275 comes to
play. The delay element 275 allows for a continuous
termination of the line except for that time window when the
response from the slave arrives. The termination during all
other time is required since signal reflections occur more and
more separated from the signal generating driver itself and
travel as echoes separately on the line and can cause
distortions at a receiver depending on line length and clock
frequency used on the interface. The simple method to overcome
these effects is an active termination at least on one end of
the line. It is worthwhile to notify that the slave can always
receive and decode a message from the master without
dependency on delay compensation or line length since clock
and data are always synchronous at the slave input.
Figures 5A - 5C show the relationship of the data patterns on
the transmission line 210 in respect to the two processing
units on master 280 and on slave side 290.
In Figure 5A it is now illustrated by way of a timing diagram
how data packets are transmitted on a transmission line
depicted in Figure 9. Tn the upper part of the diagram data
packets sent and received by the master are shown together
with the corresponding driver states of drivers 225 and 235
depicted in Figure 9. Tn the lower part there are shown
corresponding bus interface states for one of the slaves
(peripheral devices) 125 shown in Figure 3.
CA 02529132 2005-12-12
WO 2004/111596 PCT/EP2004/050633
12
A parameter 'TMdelay' depicted in the upper part of the
diagram is a programmable delay (included in processing unit
275 depicted in Figure 4) at the master for the response
receive window. In other words, this parameter according to
the invention is used to adjust an active response state of
the master where it can receive at all response packets
arriving at the master. In correspondence to that, another
parameter 'TSdelay' is the programmable delay (included in
processing unit 295 depicted in Figure 4) of the slave for
sending the response which is used to adjust the time window
on side of the slaves) for sending data packets in response
to an arrived data packet from the master.
As can be seen more particularly from Figure 5A, the above
mentioned state machine included in processing unit 280 keeps
most of the time the driver buffer 255 active ('HIGH' state)
by use of the control signal 225, independently of sending a
data pattern or not, except of a defined interval T rec 515
where a response from the slave is expected. This mechanism
guarantees that a request echo 505 of a request packet 500
sent from master function 105 reflected on the far non-
terminated end at pin 230 gets terminated at the near end by
the combination of series resistor 215 and activated buffer
255. The traveling time for the request echo 505 rates T21 and
is defined by the distance in wire length 1 between master
function 105 and slave function 130 as well as the electrical
characteristics of the transmission medium.
The slave function 130 receives 525 the request packet 500
after time T1, adds some processing time 'T_proc' of unit 290
and sends a response packet 530 delayed by the programmable
delay element 295. The response packet 530 arrives 510 at the
master after a further traveling delay of T1. At that time,
the request echo 505 is already terminated and does no more
disturb the data transmission.
CA 02529132 2005-12-12
WO 2004/111596 PCT/EP2004/050633
13
During receipt 510 of the response packet 530, the buffer 255
on master is tri-state and the processing unit 280 operates in
input mode. Since the exact point in time, where the master
has to prepare for such input and disable the driver buffer
255, is dependent on the signal traveling time T1, a
measurement method is required to adjust the driver enable
signal 225 driven by the processing unit 280. The processing
unit 280 implements a programmable delay element 275 that
moves the tri-state window T_rec exactly to that point where
the response packet 530 arrives 510 at the master. After the
response packet 530 is received 510, the driver buffer 255
gets activated again while the driver buffer 260 on the slave
side gets deactivated. Due to the active termination on pin
220, a response echo 535 of the response packet 530 that
arrives520 the master after further time T1 gets canceled
after a further round trip. During that time any input on the
receiver buffer 270 on the slave 125 is ignored.
Method for Delav Ad-iustment
Figure 5B illustrates in more detail the electrical conditions
during a pre-mentioned delay adjustment. During the adjustment
steps, the parameter 'TMdelay' is first set to a maximum value
to guarantee any echo of a request packet is terminated.
Accordingly, the parameter 'TSdelay' is also set to a maximum
value in order to enable data packets being sent by the master
to receive at the slave at all. The maximum value for
'TSdelay' may be equal or exceed 'TMdelay' while both maximum
values must allow for a delay beyond the round-travel time of
a signal.
During adjustment phase the receive window of the master is
approached successively by the response packet 530 by step-
wise decrementing the parameter 'TSdelay' in the slave by
sending appropriate information from the master.
It is emphasized that this method applied for setting the
correct delays in the master function 105 and the slave
CA 02529132 2005-12-12
WO 2004/111596 PCT/EP2004/050633
14
function 130 is part of the present invention. The method is
required in cases where the clock period of the serial
interface is in the range or shorter than the traveling time
of the signal T1 and significant echoes caused by signal
reflection occur on the pins 220 and 230. Since the delays of
these echoes are dependent on the line length 1 of line 210
and 245 as well as the dielectric characteristics of the
transmission line an empirical method is used to adjust the
receive window on the master 105 rather than giving a
calculation recommendation.
To start a scan for setting the receive window to the correct
delay the delay unit 275 in the master function and delay 295
in the slave are both set to the mentioned maximum delay which
has to be in range beyond the roundtrip time for an echo T21.
Thereby the delay 295 must be equal or larger than the delay
275. Typically both delays are given as multiples of clock
cycles of the clock transmitted to the slave. The master
starts then to request a short response from the slave and
monitors during its receive window T-rec for an answer from
the slave. After each response the delay 295 in the slave
function 130 gets decremented by appropriate commands sent
from the master. When the position in time set for the receive
window T-rec equals the traveling time for the response T1
plus the actual delay set in delay element 295 a correct
adjustment of the two delay units 275 and 295 is found and the
master gets a valid response. This setting can be optimized
for a minimum delay in response by subtracting the same delay
in number of clock cycles from both delay units.
The delay unit 295, in a further embodiment, may also contain
the capability for adding a programmable number of sub-cycle
delays of one clock cycle. These sub-cycles can be generated
out of a delay chain built into the delay unit 295. Such
feature helps to adjust the data transitions on the master
side to the local clock reference. Another solution for this
adjustment is an over-sampling of the data stream received at
CA 02529132 2005-12-12
WO 2004/111596 PCT/EP2004/050633
the master and resynchronization to the clock domain. In this
case no sub-cycle delay function is required on the slave
side.
It is noteworthy that the method described to find the delay
adjustment has to start with large delays that get decreased
rather than short delays to increase. The latter procedure
will cause problems since echoes get detected first in the
T-rec window and deliver wrong settings for the delays.
Figure 6A depicts a flow diagram for ,illustrating in more
detail the necessary procedural steps for the pre-described
delay adjustment in case of a single slave (i.e. only one
peripheral device) environment. The shown routine starts with
step 600 where the delay parameter of the master 'TMdelay' is
set to an empirically pre-determined maximum value
TMdelay-max. In the next step 605, the delay parameter of the
slave 'TSdelay' is set accordingly to an likewise empirically
pre-determined maximum value TSdelay_max. After having
initialized the two delay parameters in the above manner, in
t_he following step 67.0, the master sends a certain message
(data packet) to the slave. After this, within the above
described empirically pre-determined response window Trec, in
step 615 the master changes over to a wait state where it can
receive at all a response packet from the slave. In other
words, a response packet sent by the slave to the master will
only be received by the master if the packet arrives at the
master within the time window Trec. It is noteworthy that the
two steps 610 and 615 can be regarded as the known 'polling'
algorithm.
After having sent 610 the data packet to the slave, the master
checks 620 if it has received any valid response packet form
the slave. Validity means that the received packet is not
damaged or incomplete since not being received completely
within the time window Trec. If the master didn't receive a
valid response packet, the parameter 'TSdelay' is decremented
CA 02529132 2005-12-12
WO 2004/111596 PCT/EP2004/050633
16
625 by a certain empirically pre-determined amount and the
procedure then jumps back to step 610 and sends another data
packet again to the slave. The shown loop 610 - 620 is
repeated as long as no valid response packet is received by
the master.
If the check 620 reveals that the master received a valid
response packet from the slave, i.e. the current value of the
parameter 'TSdelay' is the right one to enable the master to
receive response packets from the slave, it is continued with
step 630 where the delay parameter of the master 'TMdelay' is
decreased by the current value of parameter 'TSdelay', in
other words is set to the difference (TMdelay - TSdelay). 2n
order to satisfy also the timing requirements on side of the
slave, the parameter 'TSdelay' is set zero in step 635 in
order to keep a valid relative delay between the master and
the slave. Steps 630 and 635, in other words, are only
defining an offset-removal or -subtraction since, as mentioned
beforehand, only the relative delay between the master and the
slave are of concern.
Multiplexing of Multiple Lines
Referring now to Figure 5C, the electrical conditions for a
multiplex application where two different slaves with
different line lengths are served by the master are
illustrated in more detail. The master always receives the
response from ,slave 1' or 'slave 2' at the same time delay
'TMdelay', namely after sending a request. 'Slave 1' gets a
higher delay value 'TSdelayl' programmed compared to 'slave 2'
as its line length L1 is shorter than L2 of the second slave.
'Slave2' gets a shorter delay value ,TSdelay2' programmed. The
slave with the longest line length may be set to TSdelay = 0
while in each other slave a certain delay > 0 gets programmed
to artificially lengthen the shorter interconnection Lx to the
master and provide the response at the same delay compared to
the slave at the longest line interconnection. Since this
CA 02529132 2005-12-12
WO 2004/111596 PCT/EP2004/050633
17
implementation just exploits the delay element 295 in each
slave and has no further resource requirement for the master
this method allows for implementing an arbitrary number of
slaves multiplexed by just one master.
The adjustment mechanism described beforehand allows for
correct adjustments of delays to drive the serial protocol
between one master function 105 and one slave function 130 in
a peripheral device 125. As shown in Figure 3 a second part of
the invention is the capability of the master to drive
multiple serial links 110 - 120 in a multiplexed manner where
each of the links may have a different length and therefore
the travel time of the signal Tl between master and the
different peripheral devices varies. The delay adjustment
method described above allows to find an adjustment for each
individual line 110 - 120 by programming the delay in each
slave specifically. Tt was also shown that the data exchange
operates for any set of delays in the units 275 and 295 that
positions the response packet and the receive window T_rec at
the same point in time. Therefore selecting a higher delay
than a minimal one required in the units 275 and 295 for a
specific line is equivalent to a longer line 210. Applying
this to the adjustment for the multiple links one has just to
find this link with the largest distance and to settle with
the delay for such link the receive window T-rec. Now all
other delays in the other peripheral devices can be
recalculated and adjusted to the new position of the receive
window T~rec. This results in a very same setting in the
master for the delay controlling the driver buffer 225 to
communicate with any slave and allows for a very simple
implementation of a multiplexor function in the master by just
switching to a different data line.
Furthermore certain broadcast functions can be applied to all
peripheral devices at the same time which also will deliver a
synchronous response from all peripheral devices at the same
time and simplify the exploitation of the responses. For
CA 02529132 2005-12-12
WO 2004/111596 PCT/EP2004/050633
18
example a plug detection or alive information can be requested
by the master with simultaneous responses from all slaves. The
response for such polling of information can be done in a
cyclic manner and can be combined with further status
information from the slave e.g. interrupt information of the
slaves.
Similar to Figure 6A, in Figure 6B the necessary procedural
steps for the pre-described delay adjustment in case of a
multiple slave (i.e. at least two peripheral devices)
environment are illustrated in more detail by way of a flow
diagram. The shown routine starts with step 700. In step 702
an integer variable n is initialized with the value zero. This
integer variable is used in the following procedure to assign
a slave number to each slave of the multiple slave
environment. In step 703 the integer variable n is incremented
by '1' and in the following step 705 all the procedural steps
600 - 635 performed in a single slave environment are
accomplished for a given slave n. As described above, the
outcome of the pre-described steps 600 - 635 is an adjusted
value of the delay parameter of the master 'TMdelay'. Thus in
step 710 a table is generated where for each slave n the
corresponding value of 'TMdelay' is inserted. By way of check
step 715, the steps 600 - 635 are performed for all slaves in
the underlying multi-slave environment.
After having generated 710 the table for all slaves with slave
numbers 1 -n (n > 1), in step 720 the delay parameter of the
master 'TMdelay' is set to the maximum of all TMdelay values
contained in the right column of the generated 710 table. In
addition, in step 725 the values of the delay parameters of
all slaves 'TSdelay' are adjusted by the difference (~) value
of the following two values, the maximum value of the
parameter 'TMdelay' set in step 720 and the value of 'TMdelay'
contained in the table 710 for the underlying slave with slave
number #. By the combination of the last two steps 720 and 725
it is thereby guaranteed that the final values of the delay
CA 02529132 2005-12-12
WO 2004/111596 PCT/EP2004/050633
19
parameters 'TMdelay' and 'TSdelay' are compatible with the
potentially differing line and clock requirements of all
slaves (including their different clock speeds, cable lengths
etc.).
