Language selection

Search

Patent 2739188 Summary

Third-party information liability

Some of the information on this Web page has been provided by external sources. The Government of Canada is not responsible for the accuracy, reliability or currency of the information supplied by external sources. Users wishing to rely upon this information should consult directly with the source of the information. Content provided by external sources is not subject to official languages, privacy and accessibility requirements.

Claims and Abstract availability

Any discrepancies in the text and image of the Claims and Abstract are due to differing posting times. Text of the Claims and Abstract are posted:

  • At the time the application is open to public inspection;
  • At the time of issue of the patent (grant).
(12) Patent: (11) CA 2739188
(54) English Title: METHOD AND SYSTEM FOR AUTOMATED TEST OF MULTI-MEDIA USER DEVICES
(54) French Title: METHODE ET SYSTEME POUR ASSURER L'ESSAI AUTOMATISE DES DISPOSITIFS DE L'UTILISATEUR FINAL
Status: Granted and Issued
Bibliographic Data
(51) International Patent Classification (IPC):
  • G1R 31/28 (2006.01)
  • H4N 17/00 (2006.01)
(72) Inventors :
  • VALAKH, VLADZIMIR (United States of America)
  • MIRANDA, VICENTE (United States of America)
  • VILLANUEVA, RAFAEL (United States of America)
  • RACEY, DARBY (United States of America)
(73) Owners :
  • CONTEC LLC
(71) Applicants :
  • CONTEC LLC (United States of America)
(74) Agent: MOFFAT & CO.
(74) Associate agent:
(45) Issued: 2020-04-14
(22) Filed Date: 2011-05-05
(41) Open to Public Inspection: 2012-11-05
Examination requested: 2016-04-20
Availability of licence: N/A
Dedicated to the Public: N/A
(25) Language of filing: English

Patent Cooperation Treaty (PCT): No

(30) Application Priority Data: None

Abstracts

English Abstract


A test system, for example for set top boxes or game consoles, includes logic
to
reformat media signals output by a device under test, logic to receive the
reformatted
media signals and to analyze them for errors, and a pluggable interface
coupling and
device under test to the logic to reformat the media signals.


French Abstract

Un système dessai, par exemple pour décodeurs ou consoles de jeux, comprend la logique pour reformater la sortie des signaux médiatiques à laide dun périphérique soumis à lessai, la logique pour recevoir les signaux médiatiques reformatés et les analyser pour détecter les erreurs, et un couplage dinterface branchable et un périphérique soumis à lessai pour la logique afin de reformater les signaux médiatiques.

Claims

Note: Claims are shown in the official language in which they were submitted.


-10-
CLAIMS
What is claimed is:
1. A test system, comprising:
a first programmable multimedia test module configured to send and receive
signals to and
from a unit under test via signal cables;
a retainer comprising a first signal interface and a second signal interface,
the first signal
interface configured to interface with the signal cables and the second signal
interface configured
to interface with the unit under test;
a plurality of interface modules, each configured to swappably interface to
the retainer and
to the unit under test, each interface module of the plurality of interface
modules configured to
align signal terminals of the second signal interface with signal terminals of
an I/O signal interface
corresponds to the particular type of unit under test and comprises a
different alignment of signal
terminals; and
the each interface module of the plurality of interface modules comprising a
memory-
encoded identification of the particular type of unit under test with which it
is adapted to interface.
2. The test system of claim 1, further comprising:
a slide rack configured to engage the unit under test with one of the
plurality of interface
modules that is plugably interfaced to the retainer.
3. "I he test system of claims 1 or 2, further comprising:
an analysis module coupled to the first programmable multimedia test module
and to a
second programmable multimedia test module; and
each of the first programmable multimedia test module and the second
programmable
multimedia test module configured to read from a corresponding retainer the
memory encoded
identification of the particular type of unit under test, and to communicate
with the analysis module

-11-
to download decode logic from the analysis module to decode media formats
specific to the
particular type of unit under test.
4. The test system of claim 3, further comprising:
the analysis module configured to receive the memory encoded identification of
the
particular type of unit under test from each of the first programmable
multimedia test module and
the second programmable multimedia test module; and
the analysis module configured to select test and analysis logic specific to
the particular
type of unit under test, and to associate each of the test and analysis logic
specific to the particular
type of unit under test with signals received from a programmable interface
module corresponding
to the particular type of unit under test.
5. The test system of claims 3 or 4, further comprising:
each of the first programmable multimedia test module and the second
programmable
multimedia test module configured to convert the media formats specific to the
particular type of
unit under test into binary signals communicated to a first analyzer of the
analysis module and a
second analyzer of the analysis module, respectively.
6. The test system of any one of claims 1 to 5, further comprising:
the each interface module of the plurality of interface modules comprising an
interface to
a source signal selector that provides a plurality of audio/video source
signals from a network
video service provider.
7. The test system of claim 6, further comprising:
the each interface module of the plurality of interface modules configured to
make the
memory encoded identification of the particular type of unit under test
readable from the retainer.

-12-
8. The test system of claims 6 or 7, further comprising:
the each interface module of the plurality of interface modules configured to
communicate
the memory encoded identification of the particular type of unit under test to
the source signal
selector.
9. The test system of any one of claims 1 to 8, further comprising:
the retainer comprising a third signal interface to a source signal selector
that provides a
plurality of audio/video source signals from a network video service provider.
10. The test system of any one of claims 1 to 9, further comprising:
a high definition multimedia interface (HDMI) daughter board coupled to the
interchangeable cable interface module, the HDMI daughter board configured to
decode and test
HDMI signals for compliance with a high bandwidth digital content protection
(HDCP)
specification.

Description

Note: Descriptions are shown in the official language in which they were submitted.


-1-
Method and System for Automated Test of Multi-Media User Devices
[1] FIELD
[2] This application relates to automated test equipment.
[3] BRIEF DESCRIPTION OF THE DRAWINGS
[4] In the drawings, the same reference numbers and acronyms identify
elements or
acts with the same or similar functionality for ease of understanding and
convenience.
To easily identify the discussion of any particular element or act, the most
significant
digit or digits in a reference number refer to the figure number in which that
element is
first introduced.
[5] FIG 1 illustrates a prior-art test system for end-user devices such as
set
top boxes and game consoles.
[6] FIG 2 illustrates an embodiment of a novel automated test system for
end-user devices.
[7] FIG 3 illustrates an embodiment of a novel programmable multiformat
board.
[8] DETAILED DESCRIPTION
[9] References to "one embodiment" or "an embodiment" do not
necessarily refer to the same embodiment, although they may.
[10] Unless the context clearly requires otherwise, throughout the description
and
the claims, the words "comprise," "comprising," and the like are to be
construed in an
CA 2739188 2019-06-14

-2-
inclusive sense as opposed to an exclusive or exhaustive sense; that is to
say, in the
sense of "including, but not limited to." Words using the singular or plural
number also
include the plural or singular number respectively. Additionally, the words
"herein,"
"above," "below" and words of similar import, when used in this application,
refer to
this application as a whole and not to any particular portions of this
application. When
the claims use the word "or" in reference to a list of two or more items, that
word covers
all of the following interpretations of the word: any of the items in the
list, all of the
items in the list and any combination of the items in the list.
[11] FIG 1 illustrates a test system for user devices such as set top boxes
and game
consoles. Multiple units under test (UUT1, UUT2, ...UUTN) are coupled to
multiple
multi- media-format boards: MFBI, MFB2, MFBN. The multi-media-format boards
may each offer a set of media format conversion functionality. The
connectivity
employed between a particular UUT and its associated MFB may vary according to
the make and model of the UUT and or MFB. Some UUTs may receive signals which
are not directed from or through the MFB with which they are associated, for
example
signals from a service provider head-end. The inputs to a MFB, UUT, and the
connections between an MFB and UUT, may vary according to the make and model
of UUT. complicating the testing process.
[12] Polling, control, initialization, and configuration signals provided
by the
service provider (e.g., a cable television network operator, an Internet
Service
Provider, etc.) to the UUT are supplied via a direct connection between the
UUT and
the service provider network.
[13] In order to swap a UUT with another for testing purposes, it may be
necessary
to manually reconfigure the connections between the UUT and the MFB, and the
UUT and the service provider.
[14] Each MFB may be coupled to test logic (e.g. a laptop computer), for
example
via a Universal Serial Bus (USB). Each MFB may drive an infrared (IR) signal
source (IRI, IR2...IRN) to control the UUT. A USB hub may be employed to
expand
the number of ports available on a laptop, personal computer, or other test
device.
[15] FIG 2 illustrates an embodiment of a novel automated test system for end-
user
devices. Inputs to a unit under test (UUT) are received at a pluggable
interface
module 202, which adapts and positions the signals to be received by the UUT
204.
The interface module 202 comprises inputs to and outputs from the UUT 204.
CA 2739188 2019-06-14

-3-
[16] A multi-media format board 206 (MFB) may be configured with logic that is
downloaded and installed on the board 206, making it a programmable multi-
media
format board (PMFB). This may enable use of a single PMFB with multiple makes
and models of UUT. The PMFB 206 may be configured to provide all of the inputs
that the UUT 204 receives, and to receive all outputs of interest for testing
from the
UUT 204. In this manner, it may be possible to simple disengage a particular
UUT
from the interface module 202, and plug in a new UUT, without manually
removing
or installing any cabling or connections to the UUT 204 or PMFB 206.
[17] The interface module 202 may comprise an identification (e.g. an assembly
part number) that corresponds to the supported model. This identification may
be
coded into a non-volatile memory of the interface module 202. The PMFB 206 may
be adapted to automatically detect the make and model of a UUT 204 coupled
thereto
by interacting with the UUT 204 and/or with the interface module 202, and may
download and/or activate appropriate logic (e.g. from the test/analysis logic
208) to
interact with and facilitate the testing of the UUT 204. Upon detecting the
make and
model of a UUT 204, the PMFB 206 may inform the test/analysis logic 208 of
this
information, so that the test/analysis logic 208 may select appropriate test
and analysis
logic for the UUT 204. Logic of the test system may provide for parallel
processing,
such that each UUT 204 may be tested independently and concurrently. Multi-
threading may be employed to accomplish this.
[18] The PMFB 206 may convert outputs of the UUT 204 to a binary format
suitable for processing and analysis by the test/analysis logic 208. Each PMFB
206
may have associated test logic, or multiple PMFBs may output data in parallel
to
shared test/analysis logic. Outputs of the PMFB 206 to test/analysis logic 208
may be
provided in some embodiments via universal serial bus (USB). The pluggable
interface module 202 may be adapted to fit, e.g. slot into, a retainer 210.
The interface
module 202 is interchangeable and may be specific to a make and model of UUT
204,
whereas the retainer 210 may comprise a universal configuration (inputs and
outputs)
common among all makes and models of UUT 204. A slide rack 212 driven by a
lever
214, crank, or other mechanism may be provided for loading the UUT 204 and for
mechanically engaging it with the interface module 202 via operation of the
lever 214
or other control. The lever 214 or other control may likewise be employed to
disengage the UUT 204 from the interface module 202, at which point the UUT
204
and/or the
CA 2739188 2019-06-14

-4-
modular interface 202 may be removed and replaced with another UUT 204 and/or
interface module 202.
[19] The PMFB 206 may comprise logic for the decoding and reformatting of
various media formats, such as Component, Composite, S-video, HDMI, and analog
video. The format logic may also support S/PDIF and/or coaxial/optical audio
formats, to name just some examples. Logic to decode different media formats
may
be downloaded by the PMFB 206 in some embodiments. Thus, a single PMFB 206
may be employed with various UUTs that operate upon or output various media
formats.
[20] Polling, control. Initialization, and configuration signals provided
by the
service provider (e.g., a cable television network operator, an Internet
Service
Provider, etc.) to the UUT are provided via a source signal selector 216. The
source
signal selector 216 may choose from among multiple available service provider
sources and direct signals from the chosen source to the interface module 202
(note
that the signals from the chosen source may in some implementations be
directed to
the retainer 210, which may comprise inputs and outputs common to all makes
and
models of UUT 204. For example, the source signal selector 216 may choose
signals
from a particular headend of a cable television provider, depending upon the
make/model of the UUT 204. The source signal selector 216 may choose signals
from
ditlerent service providers depending on the type of U UT (e.g. set top box,
game
console, etc.). The source signal selector 216 may comprise a configurable RF
attenuation control to stress the RF input of the unit under test. This may be
employed
to detect anomalies on units failing when the RF level is below certain
threshold
levels.
[2 1 ] A carousel server (OLL, e.g. a Motorola Offline Loader, not shown in
drawings) may be employed to load code objects on various set-top boxes.
Deploying
an OLL may increase the throughput of loading desired code objects independent
from a service provider source. The signal selector 216 may be used in
conjunction
with the OLL to help prepare the set-top boxes with specific code objects.
[22] Either or both of the PMFB 206 or source signal select or 216 may
determine
the make and/or model of the UUT 204. If the PMFB 206 makes this
determination, it
CA 2739188 2019-06-14

-5-
may in some embodiments communicate the make/model information to the source
signal selector 216 and/or direct the PMFB 206 to select a particular source.
If the
source signal selector 216 makes this determination, it may, in some
embodiments,
communicate the information the PMFB 206 and/or direct the PMFB 206 to select
a
particular source. Media signals may be provided via a tunable RF channel from
a
local source 218, instead of from the provider network. The local source need
not be
"local" to the test system, but may be any source other than the service
provider
network. The local media test signals may be substituted for signals from the
provider
network (e.g. the provider signals may be filtered out and replaced), or the
local
signals may supplement the polling, control, initialization, and configuration
signals
normally provided by the service provider.
[23] The source 218 of the local media test signals may be a separate server
for this
purpose, and/or the test/analysis logic 208 or devices may provide the local
media test
signals. In some embodiments, the media test signals may be selected according
to the
make and/or model of the UUT 204. The system may include logic to apply the
media
test signals to the UUT via a same physical medium as service provider
configuration
signals are applied to the UUT. This logic may be comprised by the source
signal
selector 216, the pluggable interface module 202, the media format board 206,
or
some other device (e.g. an RF coupler in the signal path).
[24] Control signals that drive features of the UUT 204 may be provided,
for
example by an IR port and/or USB from the PMFB 206. PCT or SPI control and
data
exchange may also be employed to interact with the UUT 204. The PMFB 206 may
operate as a frame grabber which captures one or more frames output by the UUT
204, buffers the captured frame(s), converts them to a data stream, and
transfers them
to the test/analysis logic 208, for example via a USB interface.
[25] Logic to capture and process new/updated or different media formats,
or
to interact with new/different makes and models of UUT 204, may be dynamically
loaded to the PMFB 206 by the test/analysis logic 208 or another device.
Dynamic
loading of logic to the PMFB 206 may be based upon a determination of the make
and/or model number of the UUT204.
[26] A test platform employing features of the described test system
embodiment(s) maybe arranged in horizontal, vertical, and/or grid
configurations,
with one, two, four, eight, or up to 24 UUT test stations, to name some of the
possibilities.
CA 2739188 2019-06-14

-6-
[27] FIG 3 illustrates an embodiment of a novel programmable multi-media
format board. Various components readily apparent to those skilled in the art
are
omitted from the illustration for purposes of keeping the description concise.
The
board may be programmed with new/changed media processing logic via parallel
port, USB, or other digital interfaces, which may communicate and store
upgrades to
SDRAM, FLASH memory (not shown), or other volatile or nonvolatile program
memory (e.g. memory of audio and video decoder blocks). Various board
functions
are coordinated using logic comprised by an FPGA, EPROM, EEPROM, ASIC, or
other program memory storage. An IR port is available for communicating
commands
wirelessly to a UUT.
[28] The board has a capability to receive and decode various media
formats, such as CVBS, Component, S-Video, HDMI (high definition multimedia
interface), S/PDIF, Digital audio, PCM, Dolby, and DTS. A secure daughter
board
222 may be used to decode and test HDMI signals, with the decoded result then
passed to the MFB. The HDMI daughter board tests the signal to comply with
HDCP
(high bandwidth digital content protection), because the decoded HDMI signal
cannot
be passed to a PC, laptop, or other unsecure digital platform without
violation of the
HDCP specification. The board may also have a capability to receive and decode
analog, SPDIF, optical signals, as well as RF signals (e.g. via coaxial
cable).
[29] The board may comprise logic (e.g. in FPGA) to determine the make
and model of a coupled UUT, and to adapt the applied media decoding logic
accordingly, and to communicate the make and model information to a signal
source
for the UUT (or cause the signal source to select a signal suitable to the
make and/or
model of the UUT). This make and model information may be obtained from the
UUT, or from the pluggable interface module, or from another source, depending
on
the implementation.
[30] The board may comprise logic (e.g. in FPGA) to adapt the applied
media decoding logic based upon instructions from a signal source or other
external
device.
[31] "Logic" refers to signals and/or information embodied in circuits
(e.g.
memory circuits) that may be applied to influence the operation of a device.
Software,
hardware, and firmware are examples of logic. In general, logic may comprise
combinations of software, hardware, and/or firmware.
[32] Those skilled in the art will appreciate that logic may be distributed
CA 2739188 2019-06-14

-7-
throughout one or more devices, and/or may be comprised of combinations of
instructions in memory, processing capability, circuits, and so on. Therefore,
in the
interest of clarity and correctness logic may not always be distinctly
illustrated in
drawings of devices and systems, although it is inherently present therein.
[33] The techniques and procedures described herein may be implemented via
logic
distributed in one or more computing devices. The particular distribution and
choice
of logic is a design decision that will vary according to implementation.
[34] Those having skill in the art will appreciate that there are various
logic
implementations by which processes and/or systems described herein can be
effected
(e.g., hardware, software, and/or firmware), and that the preferred vehicle
will vary
with the context in which the processes are deployed. For example, if an
implementer
determines that speed and accuracy are paramount, the implementer may opt for
a
hardware and/or firmware vehicle; alternatively, if flexibility is paramount,
the
implementer may opt for a solely software implementation; or, yet again
alternatively,
the implementer may opt for some combination of hardware, software, and/or
firmware. Hence, there are several possible vehicles by which the processes
described
herein may be effected, none of which is inherently superior to the other in
that any
vehicle to be utilized is a choice dependent upon the context in which the
vehicle will
be deployed and the specific concerns (e.g., speed, flexibility, or
predictability) of the
implementer, any of which may vary. Those skilled in the art will recognize
that
optical aspects of implementations may involve optically-oriented hardware,
software,
and or firmware.
[35] The foregoing detailed description has set forth various embodiments
of the
devices and/or processes via the use of block diagrams, flowcharts, and/or
examples.
Insofar as such block diagrams, flowcharts, and/or examples contain one or
more
functions and/or operations, it will be understood as notorious by those
within the art
that each function and/or operation within such block diagrams, flowcharts, or
examples can be implemented, individually and/or collectively, by a wide range
of
hardware, software, firmware, or virtually any combination thereof Several
portions
of the subject matter described herein may be implemented via Application
Specific
Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs), digital
signal
processors (DSPs), or other integrated formats. However, those skilled in the
art will
recognize that some aspects of the embodiments disclosed herein, in whole or
in part,
can be equivalently implemented in standard integrated circuits, as one or
more
CA 2739188 2019-06-14

-8-
computer programs running on one or more computers (e.g., as one or more
programs
running on one or more computer systems), as one or more programs running on
one or more processors (e.g., as one or more programs running on one or more
microprocessors), as firmware, or as virtually any combination thereof, and
that
designing the circuitry and/or writing the code for the software and/or
firmware
would be well within the skill of one of skill in the art in light of this
disclosure. In
addition, those skilled in the art will appreciate that the mechanisms of the
subject
matter described herein are capable of being distributed as a program product
in a
variety of forms, and that an illustrative embodiment of the subject matter
described
herein applies equally regardless of the particular type of signal bearing
media used
to actually carry out the distribution. Examples of a signal bearing media
include,
but are not limited to, the following: recordable type media such as floppy
disks,
hard disk drives, CD ROMs, digital tape, and computer memory; and transmission
type media such as digital and analog communication links using TDM or IF
based
communication links (e.g., packet links).
[36] In a general sense, those skilled in the art will recognize that the
various
aspects described herein which can be implemented, individually and/or
collectively,
by a wide range of hardware, software, firmware, or any combination thereof
can be
viewed as being composed of various types of "electrical circuitry."
Consequently, as
used herein "electrical circuitry" includes, but is not limited to, electrical
circuitry
having at least one discrete electrical circuit, electrical circuitry having
at least one
integrated circuit, electrical circuitry having at least one application
specific
integrated circuit, electrical circuitry forming a general purpose computing
device
configured by a computer program (e.g., a general purpose computer configured
by a
computer program which at least partially carries out processes and/or devices
described herein, or a microprocessor configured by a computer program which
at
least partially carries out processes and/or devices described herein),
electrical
circuitry forming a memory device (e.g., forms of random access memory),
and/or
electrical circuitry forming a communications device (e.g., a modem,
communications
switch, or optical-electrical equipment).
[37] Those skilled in the art will recognize that it is common within the art
to
describe devices and/or processes in the fashion set forth herein, and
thereafter use
CA 2739188 2019-06-14

-9-
standard engineering practices to integrate such described devices and/or
processes
into larger systems. That is, at least a portion of the devices and/or
processes
described herein can be integrated into a network processing system via a
reasonable
amount of experimentation.
[38] The foregoing described aspects depict different components contained
within,
or connected with, different other components. It is to be understood that
such
depicted architectures are merely exemplary, and that in fact many other
architectures
can be implemented which achieve the same functionality. In the conceptual
sense,
an arrangement of components to achieve the same functionality is effectively
"associated" such that the desired functionality is achieved. Hence, any two
components herein combined to achieve a particular functionality can be seen
as
"associated with" each other such that the desired functionality is achieved,
irrespective of architectures or intermedial components. Likewise, any two
components so associated can also be viewed as being "operably connected", or
"operably coupled", to each other to achieve the desired functionality.
CA 2739188 2019-06-14

Representative Drawing
A single figure which represents the drawing illustrating the invention.
Administrative Status

2024-08-01:As part of the Next Generation Patents (NGP) transition, the Canadian Patents Database (CPD) now contains a more detailed Event History, which replicates the Event Log of our new back-office solution.

Please note that "Inactive:" events refers to events no longer in use in our new back-office solution.

For a clearer understanding of the status of the application/patent presented on this page, the site Disclaimer , as well as the definitions for Patent , Event History , Maintenance Fee  and Payment History  should be consulted.

Event History

Description Date
Letter Sent 2024-05-06
Common Representative Appointed 2020-11-07
Grant by Issuance 2020-04-14
Inactive: Cover page published 2020-04-13
Pre-grant 2020-03-05
Inactive: Final fee received 2020-03-05
Amendment After Allowance (AAA) Received 2020-02-13
Notice of Allowance is Issued 2020-01-31
Letter Sent 2020-01-31
4 2020-01-31
Notice of Allowance is Issued 2020-01-31
Inactive: Approved for allowance (AFA) 2020-01-09
Inactive: Q2 passed 2020-01-09
Common Representative Appointed 2019-10-30
Common Representative Appointed 2019-10-30
Amendment Received - Voluntary Amendment 2019-06-14
Maintenance Request Received 2019-04-08
Inactive: S.30(2) Rules - Examiner requisition 2018-12-20
Inactive: Report - No QC 2018-12-17
Amendment Received - Voluntary Amendment 2018-07-27
Maintenance Request Received 2018-02-12
Amendment Received - Voluntary Amendment 2018-02-06
Inactive: S.30(2) Rules - Examiner requisition 2018-01-30
Inactive: Report - No QC 2018-01-16
Amendment Received - Voluntary Amendment 2017-07-27
Maintenance Request Received 2017-04-21
Inactive: S.30(2) Rules - Examiner requisition 2017-02-24
Inactive: Report - No QC 2017-02-23
Maintenance Request Received 2016-05-05
Letter Sent 2016-04-28
All Requirements for Examination Determined Compliant 2016-04-20
Request for Examination Requirements Determined Compliant 2016-04-20
Request for Examination Received 2016-04-20
Maintenance Request Received 2015-05-05
Letter Sent 2014-07-31
Maintenance Request Received 2014-07-22
Reinstatement Requirements Deemed Compliant for All Abandonment Reasons 2014-07-22
Reinstatement Request Received 2014-07-22
Deemed Abandoned - Failure to Respond to Maintenance Fee Notice 2014-05-05
Maintenance Request Received 2013-04-11
Application Published (Open to Public Inspection) 2012-11-05
Inactive: Cover page published 2012-11-04
Inactive: IPC assigned 2011-05-26
Inactive: First IPC assigned 2011-05-26
Inactive: IPC assigned 2011-05-26
Inactive: Filing certificate - No RFE (English) 2011-05-19
Application Received - Regular National 2011-05-19

Abandonment History

Abandonment Date Reason Reinstatement Date
2014-07-22
2014-05-05

Maintenance Fee

The last payment was received on 2020-04-02

Note : If the full payment has not been received on or before the date indicated, a further fee may be required which may be one of the following

  • the reinstatement fee;
  • the late payment fee; or
  • additional fee to reverse deemed expiry.

Patent fees are adjusted on the 1st of January every year. The amounts above are the current amounts if received by December 31 of the current year.
Please refer to the CIPO Patent Fees web page to see all current fee amounts.

Fee History

Fee Type Anniversary Year Due Date Paid Date
Application fee - standard 2011-05-05
MF (application, 2nd anniv.) - standard 02 2013-05-06 2013-04-11
Reinstatement 2014-07-22
MF (application, 3rd anniv.) - standard 03 2014-05-05 2014-07-22
MF (application, 4th anniv.) - standard 04 2015-05-05 2015-05-05
Request for examination - standard 2016-04-20
MF (application, 5th anniv.) - standard 05 2016-05-05 2016-05-05
MF (application, 6th anniv.) - standard 06 2017-05-05 2017-04-21
MF (application, 7th anniv.) - standard 07 2018-05-07 2018-02-12
MF (application, 8th anniv.) - standard 08 2019-05-06 2019-04-08
Final fee - standard 2020-06-01 2020-03-05
MF (application, 9th anniv.) - standard 09 2020-05-05 2020-04-02
MF (patent, 10th anniv.) - standard 2021-05-05 2021-04-20
MF (patent, 11th anniv.) - standard 2022-05-05 2022-04-06
MF (patent, 12th anniv.) - standard 2023-05-05 2023-04-05
Owners on Record

Note: Records showing the ownership history in alphabetical order.

Current Owners on Record
CONTEC LLC
Past Owners on Record
DARBY RACEY
RAFAEL VILLANUEVA
VICENTE MIRANDA
VLADZIMIR VALAKH
Past Owners that do not appear in the "Owners on Record" listing will appear in other documentation within the application.
Documents

To view selected files, please enter reCAPTCHA code :



To view images, click a link in the Document Description column (Temporarily unavailable). To download the documents, select one or more checkboxes in the first column and then click the "Download Selected in PDF format (Zip Archive)" or the "Download Selected as Single PDF" button.

List of published and non-published patent-specific documents on the CPD .

If you have any difficulty accessing content, you can call the Client Service Centre at 1-866-997-1936 or send them an e-mail at CIPO Client Service Centre.


Document
Description 
Date
(yyyy-mm-dd) 
Number of pages   Size of Image (KB) 
Description 2011-05-04 9 447
Drawings 2011-05-04 3 52
Claims 2011-05-04 2 52
Abstract 2011-05-04 1 10
Representative drawing 2011-12-11 1 5
Cover Page 2012-10-22 1 30
Description 2017-07-26 9 426
Claims 2017-07-26 5 159
Claims 2018-07-26 3 97
Description 2019-06-13 9 439
Abstract 2019-06-13 1 8
Claims 2019-06-13 3 96
Cover Page 2020-03-19 1 28
Representative drawing 2020-03-19 1 5
Commissioner's Notice - Maintenance Fee for a Patent Not Paid 2024-06-16 1 533
Filing Certificate (English) 2011-05-18 1 156
Reminder of maintenance fee due 2013-01-07 1 111
Courtesy - Abandonment Letter (Maintenance Fee) 2014-06-29 1 171
Notice of Reinstatement 2014-07-30 1 165
Reminder - Request for Examination 2016-01-05 1 117
Acknowledgement of Request for Examination 2016-04-27 1 188
Commissioner's Notice - Application Found Allowable 2020-01-30 1 511
Amendment / response to report 2018-07-26 5 145
Fees 2013-04-10 1 45
Fees 2014-07-21 1 53
Fees 2015-05-04 1 61
Request for examination 2016-04-19 1 42
Maintenance fee payment 2016-05-04 1 55
Examiner Requisition 2017-02-23 3 187
Maintenance fee payment 2017-04-20 1 60
Amendment / response to report 2017-07-26 18 920
Examiner Requisition 2018-01-29 4 227
Amendment / response to report 2018-02-05 1 48
Maintenance fee payment 2018-02-11 1 61
Examiner Requisition 2018-12-19 3 176
Maintenance fee payment 2019-04-07 1 56
Amendment / response to report 2019-06-13 15 598
Amendment / response to report 2020-02-12 1 33
Final fee 2020-03-04 2 49
Maintenance fee payment 2020-04-01 1 25
Maintenance fee payment 2021-04-19 1 25
Maintenance fee payment 2022-04-05 1 25
Maintenance fee payment 2023-04-04 1 25