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Sommaire du brevet 2739188 

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Disponibilité de l'Abrégé et des Revendications

L'apparition de différences dans le texte et l'image des Revendications et de l'Abrégé dépend du moment auquel le document est publié. Les textes des Revendications et de l'Abrégé sont affichés :

  • lorsque la demande peut être examinée par le public;
  • lorsque le brevet est émis (délivrance).
(12) Brevet: (11) CA 2739188
(54) Titre français: METHODE ET SYSTEME POUR ASSURER L'ESSAI AUTOMATISE DES DISPOSITIFS DE L'UTILISATEUR FINAL
(54) Titre anglais: METHOD AND SYSTEM FOR AUTOMATED TEST OF MULTI-MEDIA USER DEVICES
Statut: Accordé et délivré
Données bibliographiques
(51) Classification internationale des brevets (CIB):
  • G1R 31/28 (2006.01)
  • H4N 17/00 (2006.01)
(72) Inventeurs :
  • VALAKH, VLADZIMIR (Etats-Unis d'Amérique)
  • MIRANDA, VICENTE (Etats-Unis d'Amérique)
  • VILLANUEVA, RAFAEL (Etats-Unis d'Amérique)
  • RACEY, DARBY (Etats-Unis d'Amérique)
(73) Titulaires :
  • CONTEC LLC
(71) Demandeurs :
  • CONTEC LLC (Etats-Unis d'Amérique)
(74) Agent: MOFFAT & CO.
(74) Co-agent:
(45) Délivré: 2020-04-14
(22) Date de dépôt: 2011-05-05
(41) Mise à la disponibilité du public: 2012-11-05
Requête d'examen: 2016-04-20
Licence disponible: S.O.
Cédé au domaine public: S.O.
(25) Langue des documents déposés: Anglais

Traité de coopération en matière de brevets (PCT): Non

(30) Données de priorité de la demande: S.O.

Abrégés

Abrégé français

Un système dessai, par exemple pour décodeurs ou consoles de jeux, comprend la logique pour reformater la sortie des signaux médiatiques à laide dun périphérique soumis à lessai, la logique pour recevoir les signaux médiatiques reformatés et les analyser pour détecter les erreurs, et un couplage dinterface branchable et un périphérique soumis à lessai pour la logique afin de reformater les signaux médiatiques.


Abrégé anglais


A test system, for example for set top boxes or game consoles, includes logic
to
reformat media signals output by a device under test, logic to receive the
reformatted
media signals and to analyze them for errors, and a pluggable interface
coupling and
device under test to the logic to reformat the media signals.

Revendications

Note : Les revendications sont présentées dans la langue officielle dans laquelle elles ont été soumises.


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CLAIMS
What is claimed is:
1. A test system, comprising:
a first programmable multimedia test module configured to send and receive
signals to and
from a unit under test via signal cables;
a retainer comprising a first signal interface and a second signal interface,
the first signal
interface configured to interface with the signal cables and the second signal
interface configured
to interface with the unit under test;
a plurality of interface modules, each configured to swappably interface to
the retainer and
to the unit under test, each interface module of the plurality of interface
modules configured to
align signal terminals of the second signal interface with signal terminals of
an I/O signal interface
corresponds to the particular type of unit under test and comprises a
different alignment of signal
terminals; and
the each interface module of the plurality of interface modules comprising a
memory-
encoded identification of the particular type of unit under test with which it
is adapted to interface.
2. The test system of claim 1, further comprising:
a slide rack configured to engage the unit under test with one of the
plurality of interface
modules that is plugably interfaced to the retainer.
3. "I he test system of claims 1 or 2, further comprising:
an analysis module coupled to the first programmable multimedia test module
and to a
second programmable multimedia test module; and
each of the first programmable multimedia test module and the second
programmable
multimedia test module configured to read from a corresponding retainer the
memory encoded
identification of the particular type of unit under test, and to communicate
with the analysis module

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to download decode logic from the analysis module to decode media formats
specific to the
particular type of unit under test.
4. The test system of claim 3, further comprising:
the analysis module configured to receive the memory encoded identification of
the
particular type of unit under test from each of the first programmable
multimedia test module and
the second programmable multimedia test module; and
the analysis module configured to select test and analysis logic specific to
the particular
type of unit under test, and to associate each of the test and analysis logic
specific to the particular
type of unit under test with signals received from a programmable interface
module corresponding
to the particular type of unit under test.
5. The test system of claims 3 or 4, further comprising:
each of the first programmable multimedia test module and the second
programmable
multimedia test module configured to convert the media formats specific to the
particular type of
unit under test into binary signals communicated to a first analyzer of the
analysis module and a
second analyzer of the analysis module, respectively.
6. The test system of any one of claims 1 to 5, further comprising:
the each interface module of the plurality of interface modules comprising an
interface to
a source signal selector that provides a plurality of audio/video source
signals from a network
video service provider.
7. The test system of claim 6, further comprising:
the each interface module of the plurality of interface modules configured to
make the
memory encoded identification of the particular type of unit under test
readable from the retainer.

-12-
8. The test system of claims 6 or 7, further comprising:
the each interface module of the plurality of interface modules configured to
communicate
the memory encoded identification of the particular type of unit under test to
the source signal
selector.
9. The test system of any one of claims 1 to 8, further comprising:
the retainer comprising a third signal interface to a source signal selector
that provides a
plurality of audio/video source signals from a network video service provider.
10. The test system of any one of claims 1 to 9, further comprising:
a high definition multimedia interface (HDMI) daughter board coupled to the
interchangeable cable interface module, the HDMI daughter board configured to
decode and test
HDMI signals for compliance with a high bandwidth digital content protection
(HDCP)
specification.

Description

Note : Les descriptions sont présentées dans la langue officielle dans laquelle elles ont été soumises.


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Method and System for Automated Test of Multi-Media User Devices
[1] FIELD
[2] This application relates to automated test equipment.
[3] BRIEF DESCRIPTION OF THE DRAWINGS
[4] In the drawings, the same reference numbers and acronyms identify
elements or
acts with the same or similar functionality for ease of understanding and
convenience.
To easily identify the discussion of any particular element or act, the most
significant
digit or digits in a reference number refer to the figure number in which that
element is
first introduced.
[5] FIG 1 illustrates a prior-art test system for end-user devices such as
set
top boxes and game consoles.
[6] FIG 2 illustrates an embodiment of a novel automated test system for
end-user devices.
[7] FIG 3 illustrates an embodiment of a novel programmable multiformat
board.
[8] DETAILED DESCRIPTION
[9] References to "one embodiment" or "an embodiment" do not
necessarily refer to the same embodiment, although they may.
[10] Unless the context clearly requires otherwise, throughout the description
and
the claims, the words "comprise," "comprising," and the like are to be
construed in an
CA 2739188 2019-06-14

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inclusive sense as opposed to an exclusive or exhaustive sense; that is to
say, in the
sense of "including, but not limited to." Words using the singular or plural
number also
include the plural or singular number respectively. Additionally, the words
"herein,"
"above," "below" and words of similar import, when used in this application,
refer to
this application as a whole and not to any particular portions of this
application. When
the claims use the word "or" in reference to a list of two or more items, that
word covers
all of the following interpretations of the word: any of the items in the
list, all of the
items in the list and any combination of the items in the list.
[11] FIG 1 illustrates a test system for user devices such as set top boxes
and game
consoles. Multiple units under test (UUT1, UUT2, ...UUTN) are coupled to
multiple
multi- media-format boards: MFBI, MFB2, MFBN. The multi-media-format boards
may each offer a set of media format conversion functionality. The
connectivity
employed between a particular UUT and its associated MFB may vary according to
the make and model of the UUT and or MFB. Some UUTs may receive signals which
are not directed from or through the MFB with which they are associated, for
example
signals from a service provider head-end. The inputs to a MFB, UUT, and the
connections between an MFB and UUT, may vary according to the make and model
of UUT. complicating the testing process.
[12] Polling, control, initialization, and configuration signals provided
by the
service provider (e.g., a cable television network operator, an Internet
Service
Provider, etc.) to the UUT are supplied via a direct connection between the
UUT and
the service provider network.
[13] In order to swap a UUT with another for testing purposes, it may be
necessary
to manually reconfigure the connections between the UUT and the MFB, and the
UUT and the service provider.
[14] Each MFB may be coupled to test logic (e.g. a laptop computer), for
example
via a Universal Serial Bus (USB). Each MFB may drive an infrared (IR) signal
source (IRI, IR2...IRN) to control the UUT. A USB hub may be employed to
expand
the number of ports available on a laptop, personal computer, or other test
device.
[15] FIG 2 illustrates an embodiment of a novel automated test system for end-
user
devices. Inputs to a unit under test (UUT) are received at a pluggable
interface
module 202, which adapts and positions the signals to be received by the UUT
204.
The interface module 202 comprises inputs to and outputs from the UUT 204.
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[16] A multi-media format board 206 (MFB) may be configured with logic that is
downloaded and installed on the board 206, making it a programmable multi-
media
format board (PMFB). This may enable use of a single PMFB with multiple makes
and models of UUT. The PMFB 206 may be configured to provide all of the inputs
that the UUT 204 receives, and to receive all outputs of interest for testing
from the
UUT 204. In this manner, it may be possible to simple disengage a particular
UUT
from the interface module 202, and plug in a new UUT, without manually
removing
or installing any cabling or connections to the UUT 204 or PMFB 206.
[17] The interface module 202 may comprise an identification (e.g. an assembly
part number) that corresponds to the supported model. This identification may
be
coded into a non-volatile memory of the interface module 202. The PMFB 206 may
be adapted to automatically detect the make and model of a UUT 204 coupled
thereto
by interacting with the UUT 204 and/or with the interface module 202, and may
download and/or activate appropriate logic (e.g. from the test/analysis logic
208) to
interact with and facilitate the testing of the UUT 204. Upon detecting the
make and
model of a UUT 204, the PMFB 206 may inform the test/analysis logic 208 of
this
information, so that the test/analysis logic 208 may select appropriate test
and analysis
logic for the UUT 204. Logic of the test system may provide for parallel
processing,
such that each UUT 204 may be tested independently and concurrently. Multi-
threading may be employed to accomplish this.
[18] The PMFB 206 may convert outputs of the UUT 204 to a binary format
suitable for processing and analysis by the test/analysis logic 208. Each PMFB
206
may have associated test logic, or multiple PMFBs may output data in parallel
to
shared test/analysis logic. Outputs of the PMFB 206 to test/analysis logic 208
may be
provided in some embodiments via universal serial bus (USB). The pluggable
interface module 202 may be adapted to fit, e.g. slot into, a retainer 210.
The interface
module 202 is interchangeable and may be specific to a make and model of UUT
204,
whereas the retainer 210 may comprise a universal configuration (inputs and
outputs)
common among all makes and models of UUT 204. A slide rack 212 driven by a
lever
214, crank, or other mechanism may be provided for loading the UUT 204 and for
mechanically engaging it with the interface module 202 via operation of the
lever 214
or other control. The lever 214 or other control may likewise be employed to
disengage the UUT 204 from the interface module 202, at which point the UUT
204
and/or the
CA 2739188 2019-06-14

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modular interface 202 may be removed and replaced with another UUT 204 and/or
interface module 202.
[19] The PMFB 206 may comprise logic for the decoding and reformatting of
various media formats, such as Component, Composite, S-video, HDMI, and analog
video. The format logic may also support S/PDIF and/or coaxial/optical audio
formats, to name just some examples. Logic to decode different media formats
may
be downloaded by the PMFB 206 in some embodiments. Thus, a single PMFB 206
may be employed with various UUTs that operate upon or output various media
formats.
[20] Polling, control. Initialization, and configuration signals provided
by the
service provider (e.g., a cable television network operator, an Internet
Service
Provider, etc.) to the UUT are provided via a source signal selector 216. The
source
signal selector 216 may choose from among multiple available service provider
sources and direct signals from the chosen source to the interface module 202
(note
that the signals from the chosen source may in some implementations be
directed to
the retainer 210, which may comprise inputs and outputs common to all makes
and
models of UUT 204. For example, the source signal selector 216 may choose
signals
from a particular headend of a cable television provider, depending upon the
make/model of the UUT 204. The source signal selector 216 may choose signals
from
ditlerent service providers depending on the type of U UT (e.g. set top box,
game
console, etc.). The source signal selector 216 may comprise a configurable RF
attenuation control to stress the RF input of the unit under test. This may be
employed
to detect anomalies on units failing when the RF level is below certain
threshold
levels.
[2 1 ] A carousel server (OLL, e.g. a Motorola Offline Loader, not shown in
drawings) may be employed to load code objects on various set-top boxes.
Deploying
an OLL may increase the throughput of loading desired code objects independent
from a service provider source. The signal selector 216 may be used in
conjunction
with the OLL to help prepare the set-top boxes with specific code objects.
[22] Either or both of the PMFB 206 or source signal select or 216 may
determine
the make and/or model of the UUT 204. If the PMFB 206 makes this
determination, it
CA 2739188 2019-06-14

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may in some embodiments communicate the make/model information to the source
signal selector 216 and/or direct the PMFB 206 to select a particular source.
If the
source signal selector 216 makes this determination, it may, in some
embodiments,
communicate the information the PMFB 206 and/or direct the PMFB 206 to select
a
particular source. Media signals may be provided via a tunable RF channel from
a
local source 218, instead of from the provider network. The local source need
not be
"local" to the test system, but may be any source other than the service
provider
network. The local media test signals may be substituted for signals from the
provider
network (e.g. the provider signals may be filtered out and replaced), or the
local
signals may supplement the polling, control, initialization, and configuration
signals
normally provided by the service provider.
[23] The source 218 of the local media test signals may be a separate server
for this
purpose, and/or the test/analysis logic 208 or devices may provide the local
media test
signals. In some embodiments, the media test signals may be selected according
to the
make and/or model of the UUT 204. The system may include logic to apply the
media
test signals to the UUT via a same physical medium as service provider
configuration
signals are applied to the UUT. This logic may be comprised by the source
signal
selector 216, the pluggable interface module 202, the media format board 206,
or
some other device (e.g. an RF coupler in the signal path).
[24] Control signals that drive features of the UUT 204 may be provided,
for
example by an IR port and/or USB from the PMFB 206. PCT or SPI control and
data
exchange may also be employed to interact with the UUT 204. The PMFB 206 may
operate as a frame grabber which captures one or more frames output by the UUT
204, buffers the captured frame(s), converts them to a data stream, and
transfers them
to the test/analysis logic 208, for example via a USB interface.
[25] Logic to capture and process new/updated or different media formats,
or
to interact with new/different makes and models of UUT 204, may be dynamically
loaded to the PMFB 206 by the test/analysis logic 208 or another device.
Dynamic
loading of logic to the PMFB 206 may be based upon a determination of the make
and/or model number of the UUT204.
[26] A test platform employing features of the described test system
embodiment(s) maybe arranged in horizontal, vertical, and/or grid
configurations,
with one, two, four, eight, or up to 24 UUT test stations, to name some of the
possibilities.
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[27] FIG 3 illustrates an embodiment of a novel programmable multi-media
format board. Various components readily apparent to those skilled in the art
are
omitted from the illustration for purposes of keeping the description concise.
The
board may be programmed with new/changed media processing logic via parallel
port, USB, or other digital interfaces, which may communicate and store
upgrades to
SDRAM, FLASH memory (not shown), or other volatile or nonvolatile program
memory (e.g. memory of audio and video decoder blocks). Various board
functions
are coordinated using logic comprised by an FPGA, EPROM, EEPROM, ASIC, or
other program memory storage. An IR port is available for communicating
commands
wirelessly to a UUT.
[28] The board has a capability to receive and decode various media
formats, such as CVBS, Component, S-Video, HDMI (high definition multimedia
interface), S/PDIF, Digital audio, PCM, Dolby, and DTS. A secure daughter
board
222 may be used to decode and test HDMI signals, with the decoded result then
passed to the MFB. The HDMI daughter board tests the signal to comply with
HDCP
(high bandwidth digital content protection), because the decoded HDMI signal
cannot
be passed to a PC, laptop, or other unsecure digital platform without
violation of the
HDCP specification. The board may also have a capability to receive and decode
analog, SPDIF, optical signals, as well as RF signals (e.g. via coaxial
cable).
[29] The board may comprise logic (e.g. in FPGA) to determine the make
and model of a coupled UUT, and to adapt the applied media decoding logic
accordingly, and to communicate the make and model information to a signal
source
for the UUT (or cause the signal source to select a signal suitable to the
make and/or
model of the UUT). This make and model information may be obtained from the
UUT, or from the pluggable interface module, or from another source, depending
on
the implementation.
[30] The board may comprise logic (e.g. in FPGA) to adapt the applied
media decoding logic based upon instructions from a signal source or other
external
device.
[31] "Logic" refers to signals and/or information embodied in circuits
(e.g.
memory circuits) that may be applied to influence the operation of a device.
Software,
hardware, and firmware are examples of logic. In general, logic may comprise
combinations of software, hardware, and/or firmware.
[32] Those skilled in the art will appreciate that logic may be distributed
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throughout one or more devices, and/or may be comprised of combinations of
instructions in memory, processing capability, circuits, and so on. Therefore,
in the
interest of clarity and correctness logic may not always be distinctly
illustrated in
drawings of devices and systems, although it is inherently present therein.
[33] The techniques and procedures described herein may be implemented via
logic
distributed in one or more computing devices. The particular distribution and
choice
of logic is a design decision that will vary according to implementation.
[34] Those having skill in the art will appreciate that there are various
logic
implementations by which processes and/or systems described herein can be
effected
(e.g., hardware, software, and/or firmware), and that the preferred vehicle
will vary
with the context in which the processes are deployed. For example, if an
implementer
determines that speed and accuracy are paramount, the implementer may opt for
a
hardware and/or firmware vehicle; alternatively, if flexibility is paramount,
the
implementer may opt for a solely software implementation; or, yet again
alternatively,
the implementer may opt for some combination of hardware, software, and/or
firmware. Hence, there are several possible vehicles by which the processes
described
herein may be effected, none of which is inherently superior to the other in
that any
vehicle to be utilized is a choice dependent upon the context in which the
vehicle will
be deployed and the specific concerns (e.g., speed, flexibility, or
predictability) of the
implementer, any of which may vary. Those skilled in the art will recognize
that
optical aspects of implementations may involve optically-oriented hardware,
software,
and or firmware.
[35] The foregoing detailed description has set forth various embodiments
of the
devices and/or processes via the use of block diagrams, flowcharts, and/or
examples.
Insofar as such block diagrams, flowcharts, and/or examples contain one or
more
functions and/or operations, it will be understood as notorious by those
within the art
that each function and/or operation within such block diagrams, flowcharts, or
examples can be implemented, individually and/or collectively, by a wide range
of
hardware, software, firmware, or virtually any combination thereof Several
portions
of the subject matter described herein may be implemented via Application
Specific
Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs), digital
signal
processors (DSPs), or other integrated formats. However, those skilled in the
art will
recognize that some aspects of the embodiments disclosed herein, in whole or
in part,
can be equivalently implemented in standard integrated circuits, as one or
more
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computer programs running on one or more computers (e.g., as one or more
programs
running on one or more computer systems), as one or more programs running on
one or more processors (e.g., as one or more programs running on one or more
microprocessors), as firmware, or as virtually any combination thereof, and
that
designing the circuitry and/or writing the code for the software and/or
firmware
would be well within the skill of one of skill in the art in light of this
disclosure. In
addition, those skilled in the art will appreciate that the mechanisms of the
subject
matter described herein are capable of being distributed as a program product
in a
variety of forms, and that an illustrative embodiment of the subject matter
described
herein applies equally regardless of the particular type of signal bearing
media used
to actually carry out the distribution. Examples of a signal bearing media
include,
but are not limited to, the following: recordable type media such as floppy
disks,
hard disk drives, CD ROMs, digital tape, and computer memory; and transmission
type media such as digital and analog communication links using TDM or IF
based
communication links (e.g., packet links).
[36] In a general sense, those skilled in the art will recognize that the
various
aspects described herein which can be implemented, individually and/or
collectively,
by a wide range of hardware, software, firmware, or any combination thereof
can be
viewed as being composed of various types of "electrical circuitry."
Consequently, as
used herein "electrical circuitry" includes, but is not limited to, electrical
circuitry
having at least one discrete electrical circuit, electrical circuitry having
at least one
integrated circuit, electrical circuitry having at least one application
specific
integrated circuit, electrical circuitry forming a general purpose computing
device
configured by a computer program (e.g., a general purpose computer configured
by a
computer program which at least partially carries out processes and/or devices
described herein, or a microprocessor configured by a computer program which
at
least partially carries out processes and/or devices described herein),
electrical
circuitry forming a memory device (e.g., forms of random access memory),
and/or
electrical circuitry forming a communications device (e.g., a modem,
communications
switch, or optical-electrical equipment).
[37] Those skilled in the art will recognize that it is common within the art
to
describe devices and/or processes in the fashion set forth herein, and
thereafter use
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standard engineering practices to integrate such described devices and/or
processes
into larger systems. That is, at least a portion of the devices and/or
processes
described herein can be integrated into a network processing system via a
reasonable
amount of experimentation.
[38] The foregoing described aspects depict different components contained
within,
or connected with, different other components. It is to be understood that
such
depicted architectures are merely exemplary, and that in fact many other
architectures
can be implemented which achieve the same functionality. In the conceptual
sense,
an arrangement of components to achieve the same functionality is effectively
"associated" such that the desired functionality is achieved. Hence, any two
components herein combined to achieve a particular functionality can be seen
as
"associated with" each other such that the desired functionality is achieved,
irrespective of architectures or intermedial components. Likewise, any two
components so associated can also be viewed as being "operably connected", or
"operably coupled", to each other to achieve the desired functionality.
CA 2739188 2019-06-14

Dessin représentatif
Une figure unique qui représente un dessin illustrant l'invention.
États administratifs

2024-08-01 : Dans le cadre de la transition vers les Brevets de nouvelle génération (BNG), la base de données sur les brevets canadiens (BDBC) contient désormais un Historique d'événement plus détaillé, qui reproduit le Journal des événements de notre nouvelle solution interne.

Veuillez noter que les événements débutant par « Inactive : » se réfèrent à des événements qui ne sont plus utilisés dans notre nouvelle solution interne.

Pour une meilleure compréhension de l'état de la demande ou brevet qui figure sur cette page, la rubrique Mise en garde , et les descriptions de Brevet , Historique d'événement , Taxes périodiques et Historique des paiements devraient être consultées.

Historique d'événement

Description Date
Lettre envoyée 2024-05-06
Représentant commun nommé 2020-11-07
Accordé par délivrance 2020-04-14
Inactive : Page couverture publiée 2020-04-13
Préoctroi 2020-03-05
Inactive : Taxe finale reçue 2020-03-05
Modification après acceptation reçue 2020-02-13
Un avis d'acceptation est envoyé 2020-01-31
Lettre envoyée 2020-01-31
month 2020-01-31
Un avis d'acceptation est envoyé 2020-01-31
Inactive : Approuvée aux fins d'acceptation (AFA) 2020-01-09
Inactive : Q2 réussi 2020-01-09
Représentant commun nommé 2019-10-30
Représentant commun nommé 2019-10-30
Modification reçue - modification volontaire 2019-06-14
Requête visant le maintien en état reçue 2019-04-08
Inactive : Dem. de l'examinateur par.30(2) Règles 2018-12-20
Inactive : Rapport - Aucun CQ 2018-12-17
Modification reçue - modification volontaire 2018-07-27
Requête visant le maintien en état reçue 2018-02-12
Modification reçue - modification volontaire 2018-02-06
Inactive : Dem. de l'examinateur par.30(2) Règles 2018-01-30
Inactive : Rapport - Aucun CQ 2018-01-16
Modification reçue - modification volontaire 2017-07-27
Requête visant le maintien en état reçue 2017-04-21
Inactive : Dem. de l'examinateur par.30(2) Règles 2017-02-24
Inactive : Rapport - Aucun CQ 2017-02-23
Requête visant le maintien en état reçue 2016-05-05
Lettre envoyée 2016-04-28
Toutes les exigences pour l'examen - jugée conforme 2016-04-20
Exigences pour une requête d'examen - jugée conforme 2016-04-20
Requête d'examen reçue 2016-04-20
Requête visant le maintien en état reçue 2015-05-05
Lettre envoyée 2014-07-31
Requête visant le maintien en état reçue 2014-07-22
Exigences de rétablissement - réputé conforme pour tous les motifs d'abandon 2014-07-22
Requête en rétablissement reçue 2014-07-22
Réputée abandonnée - omission de répondre à un avis sur les taxes pour le maintien en état 2014-05-05
Requête visant le maintien en état reçue 2013-04-11
Demande publiée (accessible au public) 2012-11-05
Inactive : Page couverture publiée 2012-11-04
Inactive : CIB attribuée 2011-05-26
Inactive : CIB en 1re position 2011-05-26
Inactive : CIB attribuée 2011-05-26
Inactive : Certificat de dépôt - Sans RE (Anglais) 2011-05-19
Demande reçue - nationale ordinaire 2011-05-19

Historique d'abandonnement

Date d'abandonnement Raison Date de rétablissement
2014-07-22
2014-05-05

Taxes périodiques

Le dernier paiement a été reçu le 2020-04-02

Avis : Si le paiement en totalité n'a pas été reçu au plus tard à la date indiquée, une taxe supplémentaire peut être imposée, soit une des taxes suivantes :

  • taxe de rétablissement ;
  • taxe pour paiement en souffrance ; ou
  • taxe additionnelle pour le renversement d'une péremption réputée.

Les taxes sur les brevets sont ajustées au 1er janvier de chaque année. Les montants ci-dessus sont les montants actuels s'ils sont reçus au plus tard le 31 décembre de l'année en cours.
Veuillez vous référer à la page web des taxes sur les brevets de l'OPIC pour voir tous les montants actuels des taxes.

Historique des taxes

Type de taxes Anniversaire Échéance Date payée
Taxe pour le dépôt - générale 2011-05-05
TM (demande, 2e anniv.) - générale 02 2013-05-06 2013-04-11
Rétablissement 2014-07-22
TM (demande, 3e anniv.) - générale 03 2014-05-05 2014-07-22
TM (demande, 4e anniv.) - générale 04 2015-05-05 2015-05-05
Requête d'examen - générale 2016-04-20
TM (demande, 5e anniv.) - générale 05 2016-05-05 2016-05-05
TM (demande, 6e anniv.) - générale 06 2017-05-05 2017-04-21
TM (demande, 7e anniv.) - générale 07 2018-05-07 2018-02-12
TM (demande, 8e anniv.) - générale 08 2019-05-06 2019-04-08
Taxe finale - générale 2020-06-01 2020-03-05
TM (demande, 9e anniv.) - générale 09 2020-05-05 2020-04-02
TM (brevet, 10e anniv.) - générale 2021-05-05 2021-04-20
TM (brevet, 11e anniv.) - générale 2022-05-05 2022-04-06
TM (brevet, 12e anniv.) - générale 2023-05-05 2023-04-05
Titulaires au dossier

Les titulaires actuels et antérieures au dossier sont affichés en ordre alphabétique.

Titulaires actuels au dossier
CONTEC LLC
Titulaires antérieures au dossier
DARBY RACEY
RAFAEL VILLANUEVA
VICENTE MIRANDA
VLADZIMIR VALAKH
Les propriétaires antérieurs qui ne figurent pas dans la liste des « Propriétaires au dossier » apparaîtront dans d'autres documents au dossier.
Documents

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Liste des documents de brevet publiés et non publiés sur la BDBC .

Si vous avez des difficultés à accéder au contenu, veuillez communiquer avec le Centre de services à la clientèle au 1-866-997-1936, ou envoyer un courriel au Centre de service à la clientèle de l'OPIC.


Description du
Document 
Date
(yyyy-mm-dd) 
Nombre de pages   Taille de l'image (Ko) 
Description 2011-05-04 9 447
Dessins 2011-05-04 3 52
Revendications 2011-05-04 2 52
Abrégé 2011-05-04 1 10
Dessin représentatif 2011-12-11 1 5
Page couverture 2012-10-22 1 30
Description 2017-07-26 9 426
Revendications 2017-07-26 5 159
Revendications 2018-07-26 3 97
Description 2019-06-13 9 439
Abrégé 2019-06-13 1 8
Revendications 2019-06-13 3 96
Page couverture 2020-03-19 1 28
Dessin représentatif 2020-03-19 1 5
Avis du commissaire - Non-paiement de la taxe pour le maintien en état des droits conférés par un brevet 2024-06-16 1 533
Certificat de dépôt (anglais) 2011-05-18 1 156
Rappel de taxe de maintien due 2013-01-07 1 111
Courtoisie - Lettre d'abandon (taxe de maintien en état) 2014-06-29 1 171
Avis de retablissement 2014-07-30 1 165
Rappel - requête d'examen 2016-01-05 1 117
Accusé de réception de la requête d'examen 2016-04-27 1 188
Avis du commissaire - Demande jugée acceptable 2020-01-30 1 511
Modification / réponse à un rapport 2018-07-26 5 145
Taxes 2013-04-10 1 45
Taxes 2014-07-21 1 53
Taxes 2015-05-04 1 61
Requête d'examen 2016-04-19 1 42
Paiement de taxe périodique 2016-05-04 1 55
Demande de l'examinateur 2017-02-23 3 187
Paiement de taxe périodique 2017-04-20 1 60
Modification / réponse à un rapport 2017-07-26 18 920
Demande de l'examinateur 2018-01-29 4 227
Modification / réponse à un rapport 2018-02-05 1 48
Paiement de taxe périodique 2018-02-11 1 61
Demande de l'examinateur 2018-12-19 3 176
Paiement de taxe périodique 2019-04-07 1 56
Modification / réponse à un rapport 2019-06-13 15 598
Modification / réponse à un rapport 2020-02-12 1 33
Taxe finale 2020-03-04 2 49
Paiement de taxe périodique 2020-04-01 1 25
Paiement de taxe périodique 2021-04-19 1 25
Paiement de taxe périodique 2022-04-05 1 25
Paiement de taxe périodique 2023-04-04 1 25