Note: Descriptions are shown in the official language in which they were submitted.
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METHODS FOR TESTING UNPROGRAMMED OTP MEMORY
FIELD OF THE INVENTION
[001] The present invention relates generally to non-volatile memory. More
specifically, the
invention is directed a sensing scheme for one-time programmable (OTP)
memories.
BACKGROUND OF THE INVENTION
[002] Over the past 30 years, anti-fuse technology has attracted significant
attention of
many inventors, IC designers and manufacturers. An anti-fuse is a structure
alterable to a
conductive state, or in other words, an electronic device that changes state
from not
conducting to conducting. Equivalently, the binary states can be either one of
high resistance
and low resistance in response to electric stress, such as a programming
voltage or current.
There have been many attempts to develop and apply anti-fuses in
microelectronic industry,
but the most successful anti-fuse applications to date can be seen in FGPA
devices
manufactured by Actel and Quicklogic, and redundancy or option programming
used in
DRAM devices by Micron.
[003] A summary of the progression of anti-fuse development follows as
evidenced by
issued United States patents.
[004] Anti-fuse technology development started with U.S. Patent No. 3,423,646
(Cubert et
al.), which disclosed a thin film formable diode PROM built as an array of
horizontal and
vertical conductors with a thin dielectric (aluminium oxide) between the
conductors, at their
crossings. Such NVM memory was programmed through perforation of the
dielectric in some
of the crossings. A formable diode would act as an open circuit until a
voltage of sufficient
magnitude and duration is applied to the crossing to cause forming of the
aluminum oxide
intermediate layer at which time device would act as a tunnelling diode.
[005] U.S. Patent No. 3,634,929 (Yoshida et al.) disclosed an inter-metal
semiconductor
anti-fuse array, the structure of the anti-fuse consisting of a thin
dielectric capacitor (A102,
Si02 or Si3N4) utilizing two (Al) conductors located above and connected to
the
semiconductor diode.
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[006] A programmable dielectric ROM memory structure using a MOS capacitor and
a
MOS switching element was shown in U.S. Patent No. 4,322,822 (McPherson). This
cell was
formed as a standard gate-oxide-over-substrate capacitor having a gate
connected to a MOS
transistor using a buried contact. In order to lower the oxide breakdown
voltage, which
needed to be smaller for the anti-fuse capacitor then for the MOS switch, a V-
shaped grove
in the capacitor area was proposed. Since the capacitor was formed between the
poly gate
and the grounded p-type substrate, the rupture voltage had to be applied to
the capacitor
through an access transistor. The Gate/Drain and Gate/Source edges of the
access
transistors were located at the second field oxide, much thicker then the gate
oxide in the
channel area, which greatly improved Gate/S-D breakdown voltage.
[007] U.S. Patent No. 4,507,757 (McElroy) proposed a method for lowering gate
oxide
breakdown voltage through avalanche junction breakdown. Although the original
McElroy
ideas evolved around using gated diodes to locally induce avalanche breakdown,
which in
turn lowered dielectric rupture voltage by enhanced electron tunnelling, he
actually
introduced or embodied other and perhaps more important elements to anti-fuse
technology:
(a) Dual gate oxide anti-fuse: access transistor gate oxide thicker then anti-
fuse dielectric.
McElroy's dual gate oxide process steps are: initial gate oxidation, etching
areas for thinner
gate oxide and subsequent gate oxidation. This procedure is now used in
standard CMOS
technologies for "I/0" and "1T" devices. (b) A "common-gate" (planar DRAM
like) anti-fuse
connection where access transistor connects to anti-fuse diffusion (Drain)
node and all the
anti-fuse gates are connected together. This is opposite to McPherson
arrangement and
results in much denser cell since the buried contact is eliminated. (c)
Limiting resistor
between common anti-fuse gate and external ground. (d) Two-terminal anti-fuse
MOS device
(a half transistor): McElroy concluded that only two terminals are needed in
anti-fuse
capacitor: D and G. The Source is not really needed for anti-fuse programming
or operation
and can be fully isolated from the active area. The bulk connection does not
play any role
either except for the avalanche breakdown. So the source role is limited to
collecting carriers
from the avalanche breakdown should the local substrate potential increase to
forward bias
the emitter of a parasitic n-p-n device formed by D, B and S.
[008] It wasn't until 1985 when U.S. Patent No. 4,543,594 (Mohsen) proposed an
anti-fuse
design suitable for redundancy repair. As such application requires much lower
density than
PROM, it was easier to supply external high voltage necessary to rupture the
oxide without
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actually passing this voltage through the access transistors. Mohsen's anti-
fuse structure
consisted of a thin oxide (50-150A Si02) polysilicon capacitor over a doped
region. He
believed that silicon from the substrate or silicon from the electrode where a
polysilicon
electrode is used melts into pin holes in the insulative layer to provide the
conductor, and his
test data showed that where the oxide layer is approximately 100A thick and
has an area
between 10 to 500 um2, fusion occurred at a voltage of 12 to 16 volts. The
current required to
cause this fusion is less than 0.1 uA/um2 of capacitor area, and the resulting
fused link has a
resistance of approximately 0.5 to 2K ohms. A link, once fused, can handle
currents of up to
100 milliamps at room temperature for approximately one second before it heals
to an open
fuse. Taking into account electron migration wear-out, the predicted wear-out
lifetime of a
link, once fused, is substantially greater than 3E8 hours.
[009] The possibility of anti-fuse self-healing under current stress appeared
to be the main
roadblock for application of this technology in such areas like PROMs, PLDs
and FPGAs,
where constant fuse stress was required. The anti-fuse healing problem was
resolved later
by Mohsen and others at Actel in U.S. Patent No. 4,823,181. Actel teaches the
way to
implement a reliable programmable low impedance anti-fuse element by using an
ONO
structure instead of silicon dioxide. Actel's method required an ohmic contact
after dielectric
rupture. This was achieved either by using heavily doped diffusion, or by
putting an ONO
dielectric between two metal electrodes (or silicide layers). The necessity of
an Arsenic
doped bottom diffusion electrode was revised later in U.S. Patent No.
4,899,205 (Hamdy et
al.), where it was allowed for either top-poly or bottom-diffusion to be
highly doped.
[0010] U.S. Patent No. 5,019,878 (Yang et al.) taught that if the drain is
silicided, the
application of a programming voltage in the range of ten to fifteen volts from
the drain to the
source reliably forms a melt filament across the channel region. A gate
voltage may be
applied to control the specific transistors to melt. IBM discovered similar
effect by proposing
a channel anti-fuse in U.S. Patent No. 5,672,994 (Au et al.). They discovered
that with
0.5um technology, the BVDSS for the nmos transistor is not only in the order
of 6.5V, but
once the S-D punch through occurs it creates permanent damage resulting in few
kilo ohms
leakage between the source and the drain.
[0011] U.S. Patent Nos. 5,241,496 and 5,110,754 to Micron, disclosed a DRAM
cell based
anti-fuse (trench and stack). In 1996, Micron introduced a well-to-gate
capacitor as an anti-
fuse in U.S. Patent No. 5,742,555 (Marr et al.). U.S. Patent No. 6,087,707
(Lee et al.)
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proposed an N-Well coupled anti-fuse as a way to eliminate undercut defects
associated with
polysilicon etching. U.S. Patent No. 6,421,293 (Chandelier et al.) proposed a
similar anti-fuse
structure, but with n+ regions removed to create an asymmetrical
("unbalanced") high voltage
access transistor using the N-well as a drain electrode.
[0012] U.S. Patent No. 6,515,344 (Wollesen) proposed a range of P+/N+ anti-
fuse
configurations, implemented using a minimum size gate between two opposite
type diffusion
regions.
[0013] NMOS anti-fuses have been built in an isolated P-well using a standard
Deep N-Well
process. An example of Deep N-Well based anti-fuses is disclosed in U.S.
Patent No.
6,611,040 (Geisomini et al.).
[0014] U.S. Patent Nos. 6,960,819 (Chen et al.) and 6,700,176 (Ito et al.)
disclose other
Deep N-Well anti-fuses. These anti-fuses consisted of a capacitor featuring
direct tunnelling
current rather then Fowler Nordheim current. These applications confirm that
anti-fuse
performance is generally improved for thinner gate oxide capacitors (approx
20A, which is
typical for transistors in 0.13um process).
[0015] U.S. Patent No. 6,580,145 (Wu et al.) disclosed a new version of a
traditional anti-
fuse structure utilizing dual gate oxides, with the thicker gate oxide being
used for nmos (or
pmos) access transistors and the thinner gate oxide for the capacitor. The N-
Well (or P-Well)
is used as a bottom plate of the anti-fuse capacitor.
[0016] The idea of creating a source drain short through the gate by
separately breaking the
S-G and D-G dielectric regions of the transistor is disclosed in U.S. Patent
No. 6,597,234
(Reber et al.).
[0017] U.S. Patent No. 6,753,590 (Fifield et al.) disclosed an anti-fuse built
from a MOS
transistor having gate connected to the gate of a capacitor, degenerated by a
thinner gate
oxide and heavy doping under the channel through additional implantation (a
diode). The
rupture voltage is applied to a bottom plate of the capacitor.
[0018] In U.S. Patent No. 6,667,902 (Peng), Peng attempts to improve a classic
planar
DRAM-like anti-fuse array by introducing "row program lines" which connect to
the capacitors
and run parallel to the word lines. If decoded, the row program lines can
minimize exposure
of access transistors to a high programming voltage, which would otherwise
occur through
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already programmed cells. Peng and Fong further improve their array in U.S.
Patent No.
6,671,040 (Fong et al.) by adding a variable voltage controlling programming
current, which
allegedly controls the degree of gate oxide breakdown, allowing for multilevel
or analog
storage applications.
[0019] Most recently, U.S. Patent No. 6,777,757 (Peng) shows a memory array
using a
single transistor structure. In the proposed memory cell, Peng eliminates the
LDD diffusion
from a regular NMOS transistor. A cross-point array structure is formed of
horizontal active
area (SID) stripes crossing vertical poly gate stripes. Drain contacts are
shared between
neighbouring cells and connected to horizontal wordlines. Source regions are
also shared
and left floating. Peng assumes that if the LDD diffusion is omitted, the gate
oxide breakdown
location will be far enough from the drain area and a local N+ region will be
created rather
than D-G (drain-gate) short. If such a region was created, the programmed
cells could be
detected by positively biasing the gate and sensing the gate to drain current.
In order to
reduce the G-D or S-D (source-drain) short probability, Peng proposes
increasing gate oxide
thickness at the G-D and S_D edges through modification of a gate sidewall
oxidation
process. Peng's array requires that both source and drain regions be present
in the memory
cells, row wordlines coupled to transistor drain regions, and the column
bitlines formed from
transistor gates. Such an unusual connection must be very specific to Peng's
programming
and reading method, requiring a decoded high voltage (8V in 1.8V process)
applied to all
drain lines except for the one to be programmed. The decoded high voltage (8V)
is applied to
the gates of the column to be programmed, while the other gates are kept at
3.3V.
[0020] Although Peng achieves a cross-point memory architecture, his array
requires CMOS
process modifications (LDD elimination, thicker gate oxide at the edge) and
has the following
disadvantages: (a) All row decoders, column decoders and sense amplifiers must
switch a
wide range of voltages: 8V/3.3V/OV or 8V/1.8V/OV. (b) During a program
operation, the 3.3V
column drivers are effectively shorted to 8V row drivers or OV drivers through
programmed
cells. This puts many limits on the array size, affects driver size and
impacts reliability and
effectiveness of programming. (c) Every program operation requires that all
the array active
areas (except for the programmed row) are biased at 8V. This leads to large
N++ junction
leakage current, and again limits array size. (d) The gate oxide breaking spot
is assumed to
be located far enough from the drain area so the punch through is not
happening at 8V bias.
At the same time, the transistor must operate correctly at 1.8V biasing ¨
connecting to the
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channel area. This is not achievable without significant process modification.
(e) Peng
assumes that the gate oxide will not break on the source or drain edge if the
LDD is not
present. It is however known in the art that the S/D edges are the most likely
locations for the
oxide breakdown because of defects and electric field concentration around
sharp edges.
[0021] Peng attempts to solve some of the high voltage switching problems in
U.S. Patent
No. 6,856,540 (Peng). The high blocking voltage on wordlines and bitlines is
now replaced
with "floating" wordlines and bitlines, and restrictions on the distance from
the channel to the
source and drain regions has been changed. Although floating wordlines and
bitlines may
ease problems with high voltage switching, they do not solve any of the above
mentioned
fundamental problems. Additionally they introduce severe coupling problems
between the
switched and the floating lines.
[0022] Today, anti-fuse developments concentrate around 3-dimensional thin
film structures
and special inter-metal materials. All these anti-fuse technologies require
additional
processing steps not available in standard CMOS process, prohibiting anti-fuse
applications
in typical VLSI and ASIC designs, where programmability could help overcome
problems
with ever shrinking device life cycles and constantly rising chip development
costs. Therefore
there is an apparent need in the industry for a reliable anti-fuse structures
utilizing standard
CMOS process.
[0023] Prior art anti-fuse cells and arrays either require special processing
steps or suffer
from high voltage exposure of MOS switching elements, leading to
manufacturability and
reliability problems. They are also limited to low density memory
applications, with the
exception of Peng's single transistor cell, which in turn has very doubtful
manufacturability.
[0024] A significant issue with current non-volatile memories, such as Flash
and OTP
memories, is the speed at which data states of the memory cells can be sensed,
which
directly impacts overall performance of the memory. Performance of a memory,
either
embedded in a system or as a discrete memory device, can be the performance
bottleneck
for the system it is part of, relative to other processes executed by the
system.
[0025] Non-volatile memories, such as Flash memories and OTP memories, use
current
sensing schemes as is well known in the art. These schemes are typically
single ended,
meaning that a sense amplifier circuit compares the current driven through one
bitline which
carries data of a memory cell connected to it, with a reference current. The
reference current
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can be generated in a variety of ways, including synthesis by a reference
voltage generator,
or through a reference memory cell. The single bit digital output from a
current sense
amplifier represents the state of the bitline current relative to the
reference current. In Flash
memory, the current of a bitline will depend on the programmed threshold value
of the
memory cell. In an anti-fuse OTP memory, the current of a bitline will depend
on the
conductivity of the formed anti-fuse link.
[0026] Unfortunately, current sensing schemes are relatively slow. DRAM
sensing on the
other hand is much faster than current sensing schemes, since a voltage or
charge is sensed
on the bitlines. DRAM memories are organized in a folded bitline architecture,
where pairs of
bitlines are connected to their own bitline sense amplifier. Both bitlines
(complementary) are
precharged to some mid-point voltage level prior to a read operation, then a
memory cell will
either add to or remove charge from, one of the bitlines. Even a small voltage
differential
between the folded bitlines can be quickly detected by the bitline sense
amplifier.
[0027] DRAM provides an optimal balance between high density and performance,
which is
why it is exclusively used for computer systems with ever-increasing demands
for capacity
and performance. In contrast, current anti-fuse OTP memories are relatively
slow, but have
useful non-volatile applications where DRAM is unsuitable or impractical to
manufacture.
Applications include onboard FLASH replacement, boot and processor code
storage, PROM,
EEPROM and EPROM replacement, MASK ROM replacement, and other applications
where
data must be securely retained in the absence of power. Unfortunately, even
for such
applications, the relatively slow performance of anti-fuse OTP memories can
negatively
impact the performance of the system that relies on the anti-fuse OTP memory,
whether it is
a set-top box, PDA, or cell phone.
[0028] It is, therefore, desirable to provide a simple and reliable, high
density, anti-fuse array
architecture suitable for implementation in standard CMOS technology, with
high speed
sensing performance.
SUMMARY OF THE INVENTION
[0029] It is an object of the present invention to obviate or mitigate at
least one disadvantage
of the previous OTP sensing schemes.
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[0030] In a first aspect, there is provided a method for testing an
unprogrammed one-time-
programmable (OTP) memory cell. The method includes precharging a first
bitline and a
second bitline to a first voltage; activating a normal memory cell connected
to the first bitline;
coupling a second voltage to the first bitline and the second bitline;
comparing a voltage
characteristic of the first bitline to a predetermined voltage characteristic
of the second bitline
after the second voltage is coupled to the first bitline and the second
bitline; and, determining
if the normal memory cell is defective in response to the comparing of the
voltage
characteristic of the first bitline to the predetermined voltage
characteristic of the second
bitline. According to one embodiment of the first aspect, the first voltage is
VSS and the
second voltage is a positive voltage greater than VSS. According to another
embodiment of
the first aspect, coupling includes driving the first bitline and the second
bitline with a sense
amplifier circuit.
[0031] According to yet another embodiment, comparing includes sensing a
voltage level of
the first bitline relative to the second bitline with the sense amplifier
circuit, and coupling
includes coupling a reference capacitance to the second bitline, where the
reference
capacitance is less than the capacitance of the normal memory cell. In this
embodiment,
determining includes determining that the normal memory cell is defective when
the first
bitline voltage is sensed to be greater than the second bitline voltage.
[0032] In yet another embodiment, activating further includes activating a
test memory cell
connected to the second bitline, where the test memory cell being identical to
the normal
memory cell and omitting an anti-fuse device. In this particular embodiment,
the normal
memory cell and the test memory cell are activated at the same time, and
determining
includes determining that the normal memory cell is defective when the first
bitline voltage is
sensed to be greater than the second bitline voltage. This determination can
be made
because the normal memory cell adds a smaller capacitive load to the first
bitline than the
test memory cell adds to the second bitline when they are defective.
[0033] Alternately, determining includes determining that the normal memory
cell is defective
when the second bitline voltage is sensed to be greater than the first bitline
voltage. This
determination can be made because the test memory cell has higher capacitive
coupling of
the second voltage to the second bitline than the normal memory cell
capacitive coupling of
the second voltage to the first bitline, when the normal memory cell is
defective.
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[0034] In the embodiment where the both the normal memory cell and the test
memory cell
are activated at the same time, the normal memory cell includes an access
transistor and an
anti-fuse device connected to the access transistor, and activating includes
driving a cell
plate voltage connected to the anti-fuse device to the first voltage and
driving a wordline
connected to the access transistor to a test voltage. Alternately, the normal
memory cell
includes a single transistor anti-fuse device having a variable thickness gate
oxide, and
activating includes driving a wordline connected to the single transistor anti-
fuse device to a
test voltage.
[0035] Other aspects and features of the present invention will become
apparent to those
ordinarily skilled in the art upon review of the following description of
specific embodiments of
the invention in conjunction with the accompanying figures.
BRIEF DESCRIPTION OF THE DRAWINGS
[0036] Embodiments of the present invention will now be described, by way of
example only,
with reference to the attached Figures, wherein:
Fig. 1 is a circuit diagram of a DRAM-type anti-fuse cell;
Fig. 2 is a planar layout of the DRAM-type anti-fuse cell of Figure 1;
Fig. 3 is a cross-sectional view of the DRAM-type anti-fuse cell of Figure 2
along line x-x;
Fig. 4 is a cross-sectional view of an anti-fuse transistor according to an
embodiment of the present invention;
Fig. 5 is a planar layout of the anti-fuse transistor of Figure 4;
Fig. 6a and 6b are planar layouts of an alternate anti-fuse transistor
according
to an embodiment of the present invention;
Fig. 7a and 7b are planar layouts of an alternate anti-fuse transistor
according
to an embodiment of the present invention;
Fig. 8 is a planar layout of an alternate anti-fuse transistor according to an
embodiment of the present invention;
Fig. 9 is a flow chart of a method for forming a variable thickness gate oxide
for the anti-fuse transistor of the present invention;
Fig. 10a-10c illustrate the formation of the variable thickness gate oxide in
accordance with steps of the flow chart of Figure 9;
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Fig. 11a is a cross-point configured anti-fuse transistor memory array
configured for single-ended sensing according to an embodiment of the present
invention;
Fig. llb is a cross-point configured anti-fuse transistor memory array
configured for differential sensing according to an embodiment of the present
invention;
Fig. 12 is a layout of the anti-fuse transistors of the memory array shown in
Figure 11;
Fig. 13 is a folded bitline configured anti-fuse transistor memory array
according to an embodiment of the present invention;
Fig. 14 is a layout of anti-fuse transistors employing wordline segments
according to an embodiment of the present invention;
Fig. 15 is a circuit diagram of a combined sense and programming circuit
according to an embodiment of the present invention;
Fig. 16 is a circuit schematic of a folded bitline anti-fuse memory array,
according to an embodiment of the present invention;
Fig. 17a is a flow chart showing a method for sensing data using the folded
bitline anti-fuse memory array of Figure 16, according to an embodiment of the
present invention;
Fig. 17b is a timing diagram showing signal transitions in accordance with the
method described in Figure 17a;
Fig. 18 is a circuit schematic of a folded bitline anti-fuse memory array
having
an alternate reference charge circuit, according to embodiment of the present
invention;
Fig. 19a is a flow chart showing an alternate method for sensing data using
the folded bitline anti-fuse memory array of Figure 16 or 18, according to an
embodiment of the present invention;
Fig. 19b is a timing diagram showing signal transitions in accordance with the
method described in Figure 19a;
Fig. 20 is a circuit schematic of a folded bitline anti-fuse memory array
having
a selectable reference charge circuit, according to embodiment of the present
invention;
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Fig. 21 is a circuit schematic of a folded bitline anti-fuse memory array
having
a capacitive loading reference charge circuit, according to embodiment of the
present
invention;
Fig. 22a is a flow chart showing an alternate method for sensing data using
the folded bitline anti-fuse memory array of Figure 21, according to an
embodiment of
the present invention;
Fig. 22b is a timing diagram showing signal transitions in accordance with the
method described in Figure 22a;
Fig. 23 is a timing diagram showing signal transitions in accordance with an
alternate sensing method, according to an embodiment of the present invention;
Fig. 24 is a timing diagram showing signal transitions in accordance with an
alternate sensing method, according to an embodiment of the present invention;
Fig. 25 is a circuit illustration of four metal bitlines connected to
respective
memory cells;
Fig. 26 is a circuit schematic of a folded bitline anti-fuse memory array
having
a column precharge circuit, according to an embodiment of the present
invention;
Fig. 27 is a flow chart showing a method of precharging the bitlines of the
folded bitline anti-fuse memory array of Figure 26, according to an embodiment
of the
present invention;
Fig. 28 is a circuit schematic of a folded bitline anti-fuse memory array
having
an alternate column precharge circuit, according to an embodiment of the
present
invention;
Fig. 29 is a circuit schematic of a folded bitline two-transistor anti-fuse
memory
array having test cells and dummy cells, according to embodiment of the
present
invention;
Fig, 30 is a circuit schematic of a folded bitline single-transistor anti-fuse
memory array having test cells and dummy cells, according to an alternate
embodiment of the present invention;
Fig. 31 is a flow chart of a capacitive loading test for unprogrammed OTP
cells, according to a present embodiment;
Fig. 32 is a flow chart showing an alternate capacitive loading test
embodiment;
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Fig. 33 is a flow chart of a capacitive coupling testing method for
unprogrammed OTP memory cells, according to a present embodiment; and
Fig. 34 is a flow chart of a general unprogrammed OTP testing method,
according to a present embodiment.
DETAILED DESCRIPTION
[0037] Generally, the present invention provides an array of non-volatile
memory cells
arranged in a complementary bitline configuration following a folded or an
open bitline
architecture. The following description specifically refers to the preferred
folded bitline
arrangement, but it equally applies to the alternative open bitline
arrangement or to
combinations of the two. The memory array further includes precharge circuits
for
precharging the bitline pairs to a voltage reference, a reference circuit for
injecting a
reference charge on one bitline of each bitline pair, and bitline sense
amplifiers for sensing a
voltage differential between said bitline pairs. The voltage differential will
depend on the
programming state of the non-volatile memory cells coupled to the bitlines
through an
activated wordline.
[0038] Prior to a discussion of the folded bitline anti-fuse memory array
embodiments,
following is a description of the preferred anti-fuse memory cell to be used
in the
embodiments of the present invention. The preferred anti-fuse memory cell is
used here as
an example only, as many other non-volatile memory (NVM) cells can be utilized
with the
embodiments of the present invention. Other NVM cells can include two-
transistor or 1.5-
transistor anti-fuse memory cells. In the following description the term MOS
is used to denote
any FET or MIS transistor, half-transistor or capacitor structure.
[0039] As previously discussed, a DRAM-type memory array using a planar
capacitors as an
anti-fuse instead of as a storage capacitor is already known, as demonstrated
in U.S. Patent
No. 6,667,902. Figure 1 is a circuit diagram of such a memory cell, while
Figures 2 and 3
show the planar and cross-sectional views respectively, of the known anti-fuse
memory cell
of Figure 1. The memory cell of Figure 1 includes a pass, or access transistor
10 for coupling
a bitline BL to a bottom plate of anti-fuse device 12. A wordline WL is
coupled to the gate of
access transistor 10 to turn it on, and a cell plate voltage Vcp is coupled to
the top plate of
anti-fuse device 12 for programming anti-fuse device 12.
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[0040] It can be seen from Figures 2 and 3 that the layout of access
transistor 10 and anti-
fuse device 12 is very straight-forward and simple. The gate 14 of access
transistor 10 and
the top plate 16 of anti-fuse device 12 are constructed with the same layer of
polysilicon,
which extend across active area 18. In the active area 18 underneath each
polysilicon layer,
is formed a thin gate oxide 20, also known as a gate dielectric, for
electrically isolating the
polysilicon from the active area underneath. On either side of gate 14 are
diffusion regions
22 and 24, where diffusion region 24 is coupled to a bitline. Although not
shown, those of skill
in the art will understand that standard CMOS processing, such as sidewall
spacer formation,
lightly doped diffusions (LDD) and diffusion and gate silicidation, can be
applied. While the
classical single transistor and capacitor cell configuration is widely used, a
transistor-only
anti-fuse cell is further desirable due to the semiconductor array area
savings that can be
obtained for high-density applications. Such transistor-only anti-fuses must
be reliable while
simple to manufacture with a low cost CMOS process.
[0041] According to an embodiment of the present invention, Figure 4 shows a
cross-
sectional view of an anti-fuse transistor that can be manufactured with any
standard CMOS
process. In the presently shown example, the anti-fuse transistor is almost
identical to a
simple thick gate oxide, or input/output MOS transistor with one floating
diffusion terminal.
The disclosed anti-fuse transistor, also termed a split-channel capacitor or a
half-transistor,
can be reliably programmed such that the fuse link between the polysilicon
gate and the
substrate can be predictably localized to a particular region of the device.
The cross-section
view of Figure 4 is taken along the channel length of the device, which in the
presently
described embodiment is a p-channel device. Those of skill in the art will
understand that the
present invention can be implemented as an n-channel device.
[0042] Anti-fuse transistor 100 includes a variable thickness gate oxide 102
formed on the
substrate channel region 104, a polysilicon gate 106, sidewall spacers 108,
first and second
diffusion regions 110 and 112 respectively, and LDD regions 114 in each of the
diffusion
regions 110 and 112. The variable thickness gate oxide 102 consists of a thick
oxide and a
thin gate oxide such that a portion of the channel length is covered by the
thick gate oxide
and the remaining portion of the channel length is covered by the thin gate
oxide. Generally,
the thin gate oxide edge meeting diffusion region 112 defines a fusible edge
where oxide
breakdown can occur. The thick gate oxide edge meeting diffusion region 110 on
the other
hand, defines an access edge where gate oxide breakdown is prevented and
current
- 13 -
CA 02807739 2013-03-01
between the gate 106 and diffusion region 110 is to flow for a programmed anti-
fuse
transistor. While the distance that the thick oxide portion extends into the
channel region
depends on the mask grade, the thick oxide portion is preferably formed to be
at least as
long as the minimum length of a high voltage transistor formed on the same
chip.
[0043] In a preferred embodiment, the diffusion region 110 is connected to a
bitline through
a bitline contact (not shown), or other line for sensing a current from the
polysilicon gate 106,
and can be doped to accommodate programming voltages or currents. This
diffusion region
110 is formed proximate to the thick oxide portion of the variable thickness
gate oxide 102,
while optional diffusion region 112 can be left floating. To further protect
the edge of anti-fuse
transistor 100 from high voltage damage, or current leakage, a resistor
protection oxide
(RPO), also known as a salicide protect oxide, can be introduced during the
fabrication
process to further space metal particles from the edge of sidewall spacer 108.
This RPO is
preferably used during the salicidiation process for preventing only a portion
of diffusion
region 110 and a portion of polysilicon gate 106 from being salicided.
[0044] It is well known that salicided transistors are known to have higher
leakage and
therefore lower breakdown voltage. Thus having the optional diffusion region
112 salicided
will enhance oxide breakdown during programming, yet having a non-salicided
diffusion
region 110 will reduce leakage. Diffusion region 110 and optional diffusion
region 112 can be
doped for low voltage transistors or high voltage transistors or a combination
of the two
resulting in same or different diffusion profiles.
[0045] A simplified plan view of the anti-fuse transistor 100 is shown in
Figure 5. Bitline
contact 116 can be used as a visual reference point to orient the plan view
with the
corresponding cross-sectional view of Figure 4. The active area 118 is the
region of the
device where the channel region 104 and diffusion regions 110 arid 112 are
formed, which is
defined by an OD mask during the manufacturing process. The dashed outline 120
defines
the areas in which the thick gate oxide is to be grown via an 002 mask during
the
manufacturing process. OD simply refers to an oxide definition mask that is
used during the
CMOS process for defining the regions on the substrate where the oxide is to
be formed, and
0D2 refers to a second oxide definition mask different than the first. Details
of the CMOS
process steps for fabricating anti-fuse transistor 100 will be discussed
later. It should be
noted that floating diffusion region 112 is an optional structure for anti-
fuse transistor 100 that
- 14 -
CA 02807739 2013-03-01
can be used to enhance the probability of thin gate oxide breakdown, as will
be discussed
later.
[0046] Programming of anti-fuse transistor 100 is based on gate oxide
breakdown to form a
permanent link between the gate and the channel underneath. Gate oxide
breakdown
conditions (voltage or current and time) depend primarily on i) gate
dielectric thickness and
composition, ii) defect density, and iii) gate area, gate/diffusion perimeter.
The combined
thick and thin gate oxide of anti-fuse transistor 100 results in a locally
lowered gate
breakdown voltage, in particular an oxide breakdown zone, in the thin gate
oxide portion of
the device. In other words, the disclosed structure assures that the oxide
breakdown is
limited to the thinner gate oxide portion.
[0047] Additionally, the anti-fuse transistor embodiments of the present
invention take
advantage of a typically prohibited CMOS manufacturing design rule for gate
oxide design
layout and formation to enhance gate oxide breakdown performance. All gate
oxide
processing steps in today's CMOS processes assume and are optimized for
uniform gate
oxide thickness within the active gate area. By introducing the variable
thickness gate oxide
devices into the standard CMOS flow, additional defects and electrical field
disturbances are
created at the boundary between the thick and thin gate oxides. Those defects
may include,
but are not limited to: oxide thinning, plasma etching of silicon at the
boundary, residues from
cleaning process and silicon recess due to different thermal oxidation rates
between
unmasked and partially masked regions. All these effects increase trap and
defect density at
the thin oxide boundary, leading to increased leakage and locally lowered
breakdown
voltage. Therefore, a low voltage, compact anti-fuse structure can be created
without any
process modification.
[0048] While the anti-fuse transistor described above is suitable for OTP
memory array
applications due to its compact size, additional modifications can be made to
anti-fuse
transistor 100 to further increase thin oxide breakdown probability. As
mentioned above, gate
area, gate/diffusion perimeter is a factor that can increase the probability
of thin gate oxide
breakdown. To incorporate this breakdown mechanism, the previously shown
floating
diffusion region 112 can be added to the anti-fuse transistor structure, and
the floating
diffusion/gate perimeter is preferably increased by incorporating multiple
line segments and
angles to the diffusion/gate boundary. Further breakdown enhancement can be
achieved by
- 15 -
CA 02807739 2013-03-01
heavily doping floating diffusion region 112 to a concentration similar to
diffusion regions of
the high voltage transistors.
[0049] In a typical CMOS process, the diffusion regions, LDD and channel
implantation are
different for thin gate oxide transistors and thick gate oxide transistors.
According to an
embodiment of the present invention, the diffusion regions, LDD and the thin
gate oxide
channel implantation of the anti-fuse transistors can be either type; the low
voltage type
corresponding to the thin gate oxide, or the high voltage type corresponding
to the thick gate
oxide (I/0 oxide), or both, provided that the resulting thin gate oxide
threshold voltage is not
greater in magnitude than the thick gate oxide threshold voltage.
[0050] Embodiments of the anti-fuse transistor employing increased floating
diffusion region
perimeter are shown in Figures 6-8.
[0051] Figure 6a shows an anti-fuse transistor 200 having an "L" shaped
gate/diffusion
perimeter, also referred to as the fusible edge, at the floating diffusion end
of the device.
Anti-fuse transistor 200 is essentially the same as anti-fuse transistor 100
shown in Figures 4
and 5. An active region 202 has a diffusion region with bitline contact 204,
and a polysilicon
gate 206 formed over a variable thickness gate oxide layer (not shown). The
0D2 mask 208
defines where the thick gate oxide is formed underneath polysilicon gate 206.
In the present
embodiment, the floating diffusion region, channel region, and polysilicon
gate share a
common "L" shaped edge. The edge consists of two edge segments oriented at an
angle
with respect to each other. While the presently shown embodiment shows the
angle to be
about 90 degrees, the angle can be set to 135 degrees if desired.
[0052] Figure 6b shows an anti-fuse transistor 210 having a straight "S"
shaped
gate/diffusion perimeter, also referred to as the fusible edge, at the
floating diffusion end of
the device. Anti-fuse transistor 210 is essentially the same as anti-fuse
transistor 200 shown
in Figure 6a. An active region 202 has a diffusion region with bitline contact
204, and a
polysilicon gate 206 formed over a variable thickness gate oxide layer (not
shown). The 0D2
mask 208 defines where the thick gate oxide is formed underneath polysilicon
gate 206. In
the present embodiment, the floating diffusion region, channel region, and
polysilicon gate
share a common straight "S" shaped edge. The edge consists of three edge
segments
oriented at 90 degree angles with respect to each other.
- 16 -
CA 02807739 2013-03-01
[0053] Figures 6a and 6b illustrate examples where the polysilicon gate can be
shaped to
increase the floating diffusion region perimeter. Figures 7a and 7b illustrate
examples where
the diffusion region and/or the polysilicon gate can be shaped to increase the
floating
diffusion region perimeter.
[0054] In Figure 7a, anti-fuse transistor 300 has a straight gate/diffusion
perimeter at the
floating diffusion end of the device. A shaped active region 302 has a
diffusion region with
bitline contact 304, and a polysilicon gate 306 formed in a "U" shape over the
shaped active
region 302. The 0D2 mask 308 defines where the thick gate oxide is formed
underneath
polysilicon gate 306. Due to the narrowed active region 302, a portion of
polysilicon gate 306
will form an access edge 310 that is substantially smaller in perimeter than
fusible edge 312
defined by another portion of polysilicon gate 306. In this particular
example, the polysilicon
gate is effectively divided into two portions that are coupled to each other.
The first portion
forms a channel in the active area between the diffusion region with bitline
contact 304, while
the second portion is positioned adjacent to the floating diffusion region.
The first portion is
formed over thick gate oxide and the second portion is formed over thin gate
oxide.
[0055] In Figure 7b, anti-fuse transistor 314 has a straight gate/diffusion
perimeter at the
floating diffusion end of the device. A shaped active region 302 has a
diffusion region with
bitline contact 304, and a straight polysilicon gate 306 formed over the
shaped active region
302. The 002 mask 308 defines where the thick gate oxide is formed underneath
polysilicon
gate 306. Due to the narrowed active region 302, a portion of polysilicon gate
306 will form
an access edge 310 that is substantially smaller in perimeter than fusible
edge 312 defined
by another portion of polysilicon gate 306.
[0056] Therefore, as shown in Figures 6a, 6b, 7a and 7b, the perimeter fusible
edge can be
increased with a combination of polysilicon gate and active area shaping to
enhance thin
oxide breakdown during programming operations.
[0057] Figure 8 shows a pair of anti-fuse transistors, of which only one will
be described as
both are substantially symmetrical to each other. Anti-fuse transistor 400 has
an active
region 402 with a diffusion region with bitline contact 404. A polysilicon
gate 406 formed over
a variable thickness gate oxide layer (not shown). The 002 mask 408 defines
where the
thick gate oxide is formed underneath polysilicon gate 406. In the present
embodiment, the
floating diffusion region, channel region, and polysilicon gate share a common
straight "U"
- 17 -
CA 02807739 2013-03-01
=
shaped edge. A polysilicon contact 410 is used to make electrical contact with
a metal
wordline. The diffusion region containing the bitline contacts 404 are
oriented as shown to
allow for sufficient spacing of RPO 412 from the respective contacts 404. The
applicability of
the paired anti-fuse transistors shown in Figure 8 will be described later
with regards to
folded bitline sensing architectures.
[0058] While not shown in Figures 6a, 6b, 7a and 7b, an RPO can be used to
ensure that
the diffusion regions with the bitline contact and a portion of the
polysilicon gate is free from
salicidation.
[0059] A method of creating a variable thick gate oxide from a standard CMOS
process
according to an embodiment of the present invention, is to utilize a well
known two-step
oxidation process. A flow chart outlining this process is shown in Figure 9,
while Figures 10a-
10c show the various stages of the variable thickness gate oxide formation
corresponding to
specific steps in the process.
[0060] First, an intermediate gate oxide is grown in all active areas
determined by the OD
mask in step 500. In Figure 10a, this is shown as the formation of
intermediate gate oxide
600 on the substrate, over the channel region 602. In following step 502, the
intermediate
gate oxide 600 is removed from all the designated thin gate oxide areas using
an 0D2 mask.
Figure 10b shows the remaining portion of intermediate gate oxide 600 and the
future thin
oxide area 604. In the last gate oxide formation step 504, a thin oxide is
grown again in all
active areas as originally defined by the OD mask. In Figure 10c, the thin
gate oxide 606 is
grown over the intermediate gate oxide 600 and the thin oxide area 604.
[0061] As a result, the area covered by the 0D2 mask during step 502 will have
a gate oxide
thickness being a combination of the intermediate gate oxide 600 and the final
thin gate
oxide 606. The same procedure can be extended for more than two oxidation
steps, or other
equivalent procedures can be used to produce two or more gate oxide
thicknesses on the
same die, which is determined by at least one thick gate oxide mask 0D2.
[0062] Typically, the 0D2 mask is considered a non-critical masking step, a
low resolution
mask is used and the design rules require a large margin of the 0D2 mask over
active gate
areas and particularly, do not have provisions for the 0D2 mask ending within
the active gate
area. According to the present invention, the 0D2 mask ends within the active
gate area
creating a split-channel anti-fuse structure that features thicker gate oxide
on the drain (i.e.
- 18 -
CA 02807739 2013-03-01
diffusion contact) side and thinner gate oxide on the opposite side (either
channel or non-
connected source side). In principle, this technology requires that the gate
length (polysilicon
line width) should be larger then the process minimum and depends on actual
0D2 mask
tolerances, but otherwise does not require any process or mask grade change.
The minimum
gate length for the split channel anti-fuse structure can be approximated as a
sum of
minimum gate length for the thick and thin gate oxide. Those skilled in the
art will appreciate
that accurate calculations can be made based on mask tolerances, and the gate
length can
be minimized by tightening 0D2 mask tolerances.
[0063] Once the variable thickness gate oxide has been formed, additional
standard CMOS
processing steps can be employed at step 506 to complete the anti-fuse
transistor structure
as shown in Figure 4. This can include formation of the polysilicon gate, LDD
regions,
sidewall spacers, RPO, and diffusion regions, and salicidation, for example.
According to a
preferred embodiment of the presently discussed process, a salicidiation step
is included to
salicide the polysilicon gate and the floating diffusion region of the anti-
fuse transistor. An
RPO is formed over the diffusion region before hand to protect it from the
salicidation
process. As previously mentioned, the salicided floating diffusion region will
enhance oxide
breakdown in the region.
[0064] Now an application of the above-described anti-fuse transistor
embodiments will be
discussed. As mentioned earlier, the compactness of the proposed anti-fuse
transistor
makes it suitable for memory array applications, and more specifically, OTP
memory array
applications.
[0065] Figure 11a illustrates a plurality of anti-fuse transistor memory cells
arranged in a
basic cross-point array, according to an embodiment of the present invention.
Sensing is
single ended in the present embodiment. The anti-fuse transistor memory array
700 includes
anti-fuse transistors 702 coupled to wordlines WLO-WL3 and bitlines BLO, BL1,
BL2 and BL3.
Anti-fuse transistors 702 can be implemented with any of the previously
described anti-fuse
transistors. Each bitline is connected to a p-channel isolation transistor
704, which in turn is
connected to p-channel pass gates 706, 708, 710 and 712. It is noted that
isolation
transistors 704 are thick gate oxide transistors, where this thick gate oxide
can be the same
combination of the intermediate oxide and the thin gate oxide used for the
anti-fuse transistor
embodiments of the present invention. The gate terminal of all isolation
transistors 704
receive isolation voltage VB, while the gate terminals of pass gates 706, 708,
710 and 712
-19-
CA 02807739 2013-03-01
receive column select signals YO, Y1, Y2 and Y3 respectively. The column
select signals
perform a one of four bitline selection to couple one of the bitlines to cross-
point sense
amplifier 714. Cross-point sense amplifier 714 can be a current sense
amplifier that
compares the current of the bitline to a reference current !REF, and generally
denotes single-
ended sensing schemes in the present description, where a bitline voltage or
current is
compared to a reference signal carried on another line.
[0066] Figure 12 illustrates a layout configuration of four anti-fuse
transistors 702 shown in
Figure 11a. Each anti-fuse transistor of Figure 12 have a layout similar to
anti-fuse transistor
100 shown in Figure 5, except that there is no floating source diffusion
region to reduce the
overall area of each cell. Accordingly, the same reference numerals are used
to denote the
same elements in Figure 12. For the memory array configuration shown in Figure
12, each
bitline contact 116 and active area 118 is shared by two anti-fuse
transistors, and the 0D2
mask 120 is extended along the wordline direction for all the anti-fuse
transistors aligned
along the same row.
[0067] The anti-fuse transistors are programmed by rupturing the gate oxide,
preferably at
one of the thin/thick gate oxide boundary and the thin gate oxide/source
diffusion edge. This
is accomplished by applying a high enough voltage differential between the
gate and the
channel of the cells to be programmed and a substantially lower voltage
differential, if any,
on all other cells. Therefore, once a permanent conductive link is formed, a
current applied
to the polysilicon gate will flow through the link and the channel to the
diffusion region, which
can be sensed by conventional sense amplifier circuits.
[0068] With reference to Figure 11a, the cell coupled to WLO and BLO is
programmed by
applying a negative voltage ¨VPP to WLO and a positive voltage VPOS (or VDD)
to BLO,
while keeping the other wordlines at VDD and the other bitlines at OV or
another voltage
significantly smaller then VPOS. This will expose the cell to be programmed to
a voltage
differential of V=VPOS + VPP, while all the other cells will be exposed to
significantly lower
voltage. Note that a positive programming voltage VPOS has to be applied to
the cell to be
programmed, but once programmed this cell would read as a low state. Either
individual cell
or multiple cells sharing the same word line can be programmed simultaneously.
Although
programming circuitry is not shown, those of skill in the art will understand
that such circuits
can be coupled to the bitlines, and incorporated into the wordline driver
circuits.
- 20 -
CA 02807739 2013-03-01
[0069] Once a cell in a row has been programmed, every time the negative
voltage is
applied to this row for programming another cell, a short between this word
line and the bit
line of the programmed cell will occur pulling this the bit line towards the
negative voltage.
According to the present invention, the thick gate oxide isolation transistors
704 are used to
isolate the bit lines from the rest of the chip, including the sense
amplifiers. These devices
can be un-decoded or Y-decoded. Keeping the isolation devices at ground or at
the VB level
allows the bit lines to float towards a negative voltage, thus having no
effect on the
programming operation. The voltages used for program (PGM) and read operations
are
summarized in Table 1 below.
[0070] Table 1
WL
-VPP VDD OV or -Vtp
VDD or VPOS PGM No Access SOAK
BL Floating or -VPP PGM Blocked No Access No Access
Precharge to VDD Soft PGM No Access READ
[0071] The un-programmed cells behave like switched capacitors, featuring very
low leakage
current. In the idle (non-accessed) state, all the word lines WL are kept at
VDD, at the same
level as the back-bias for the array. All the bit lines BL are also precharged
to VDD and
therefore, there is no leakage and no current flowing anywhere in the array
even if some of
the cells were programmed. To execute a read operation with memory array 700,
one of the
word lines is activated, by driving WLO to OV for example, or to another
appropriate voltage
sufficient for inducing a channel underneath the polysilicon gate. If the cell
was not
programmed, the bit line will see an increased capacitance and minimally
increased leakage.
On the other hand, if the cell was programmed, a relatively low resistance
(5000hm ¨
500kOhm) within the cell will start discharging the bit line towards ground
via the grounded
WLO. This difference of behavior can be sensed using a variety of sense
amplifier designs
known in the art. A simple solution is to use a current sense amplifier, such
as well known
sense amplifier 714 that is widely used in Flash memories, where the BL
current is compared
to a reference current. As the anti-fuse ON-resistance can vary significantly
from cell to cell,
- 21 -
CA 02807739 2013-03-01
the above-mentioned current sensing scheme requires a very precise current
source of
about luA. Unfortunately, such small current sensing is slow and susceptible
to noise.
[0072] One technique to improve the cell current through a programmed anti-
fuse is by
multiple programming or "soaking" the programmed cell. Cell soaking is widely
known and
used in non-volatile memory design, either using external programming
equipment or an on-
chip state machine.
[0073] All these complications can however be avoided by using a differential,
or twin cell
arrangement, where two memory cells are accessed at the same time with only
one cell
programmed. Accordingly, data mapping would be required to ensure that each
memory cell
is paired with a memory cell representing the complementary data. A typical
DRAM or SRAM
sense amplifier system can be used for such an arrangement. Figure llb
illustrates another
configuration of anti-fuse transistors 702 shown in Figure llb arranged in the
twin cell
configuration. The elements of Figure llb are essentially the same as those in
Figure 11a,
with the exception of differential sense amplifier 716 which replaces cross-
point sense
amplifier 714, and the connection of pass gates 706, 708, 710 and 712. Pass
gates 706 and
708 now have their gate terminals connected to YO, while pass gates 710 and
712 have their
gate terminals connected to Y1. Therefore, activation of YO will turn on both
pass gates 706
and 708. The bitlines are now labeled as complementary pairs, BLO/BLO* and
BL1/BL1*,
where one pair of complementary bitlines is coupled to the differential sense
amplifier 716
during a read operation. Those of skill in the art will understand that such a
sense amplifier is
a type of dual-ended sensing scheme, since either one of the bitlines
connected to the
differential sense amplifier 716 will typically carry a reference voltage
while the other will
carry data of the accessed memory cell. In the present example, the reference
voltage will be
the complement of the data of the memory cell being accessed.
[0074] Prior to a read operation, all the bitlines are precharged to VDD.
Since the bitlines
are all precharged to VDD, one of the bitlines will be pulled toward ground
through a
programmed cell during a read operation when one wordline is activated.
Sensing data from
a pair of bitlines carrying VDD and ground becomes straightforward.
[0075] Although the simple differential sensing scheme seems well suited for
read
operations of the programmed array, it poses tremendous test problems because
the un-
programmed memory array yields random and unstable data. In addition, such
differential
- 22 -
CA 02807739 2013-03-01
cell arrangement does not provide means for margin adjustment necessary for
program
verify operation. These and other drawbacks of the above described sensing
architectures
can be mitigated by employing a folded bitline architecture with a dual ended
sensing
scheme, as shown in a preferred embodiment in Figure 13.
[0076] Figure 13 shows a folded bitline architecture employing the previously
described anti-
fuse transistors 702. Memory array 800 is similar to memory array 700 of
Figure 11b, except
that memory cells 702 are arranged in the folded bitline architecture.
[0077] The following is an example of a read operation of programmed data in
memory array
800. It is assumed that the two anti-fuse transistors 702 located between BLO
and BLO* are
used to store one bit of data, where the cell connected to WLO is not
programmed, while the
cell connected to WL2 is programmed. To read these two transistor cells, WLO
and WL2 are
driven to ground. Since the top cell is not programmed, BLO will remain at the
precharge
level of VDD. However, since the bottom cell is programmed, BLO* will
discharge towards
ground through the cell. Note that the top and bottom anti-fuse transistor
cells between BL1
and BL1* are also accessed. However, these bitlines are isolated from the
sense amplifier
since only YO would be driven to ground to activate pass transistors 706 and
708 and couple
BLO/BLO* to folded bitline sense amplifier 716. Those of skill in the art will
understand that
the column select signals YO and Y1 can be activated at a predetermined time
after the
wordlines are driven, to give the bitlines time to discharge to a sufficiently
low voltage level,
preferably to ground to provide the largest sensing margin.
[0078] Figure 14 illustrates an alternate differential cell arrangement
according to another
embodiment of the present invention. The anti-fuse transistor cells shown are
identical to
those shown in Figure 12, but are now arranged such that the polysilicon
wordlines are
broken into segments 820, where each segment 820 is coupled to two different
anti-fuse
transistor cells. Alternatively, the anti-fuse transistor pair shown in Figure
8 can be used here
as well. The segments can be connected to metal wordlines through wordline
contact 822 via
intermediate metal lines as required. It is well known in the art that the
combination of metal
wordlines connected to polysilicon wordline segments improves overall
performance of the
memory array. The particular arrangement shown in Figure 14 enables single-
ended sensing
or dual-ended sensing of the bitlines by configuring the wordline decoders. In
other words,
the wordline drivers can be controlled dynamically to drive only one wordline
or two wordlines
simultaneously in similar fashion to the DRAM decoder shown in issued U.S.
Patent No.
- 23 -
CA 02807739 2013-03-01
6,549,483. In the current application however, the single ended mode is used
for a non-
volatile memory cell test, and program and verify operations, whereas the dual
ended mode
is used for normal read operations only. Such a combination allows for
independent sensing
optimization for read, test and verify, resulting in greatly improved read
margins. The details
of the single ended sensing mode will be described later.
[0079] According to an embodiment of the present invention, programming
circuits can be
incorporated with the sensing circuit of the differential sense amplifier
circuit. Figure 15 is a
circuit diagram of an embodiment of such a circuit for n-type antifuse.
Sense/program circuit
900 includes a high voltage cross-coupled p-type latch circuit 902 and a low
voltage sense
circuit 904 separated by thick gate oxide isolation transistors 906 controlled
by Viso. Viso is
preferably a variable voltage signal, such that Viso can be less than VDD for
data verification
after programming to limit current draw. The cross-coupled latch circuit 902
receives VPP or
another program blocking voltage, and each branch of the latch circuit 902 is
connected to a
complementary pair of bitlines BLi/BLi*, while the sense circuit 904 receives
a 1.2V supply
voltage. Viso is preferably set to a maximum voltage level of about
VDD+Vt=1.8V to isolate
the more sensitive sense circuit transistors from the VPP voltage.
[0080] In a programming operation, sense circuit 904 receives write data,
which is coupled
to latch circuit 902 via activated isolation transistors 906. Latch circuit
902 effectively
performs a level shift of the 1.2V data to VPP, which is then driven onto the
appropriate
bitline. Furthermore, during read operation the back bias connection is
preferably maintained
at a high voltage, while the supply voltage is kept at or below VDD to turn
off the high voltage
PMOS transistors at all times.
[0081] As previously described, the folded bitline architecture shown in
Figure 13 uses a
bitline sense amplifier 716 for sensing a voltage differential on the
complementary bitlines
BLO/BLO* or BL1/BL1*. According to an embodiment of the present invention,
bitline sense
amplifier 716 can be implemented with a standard DRAM CMOS cross-coupled
inverter
circuit, which is well known in the DRAM field. With the appropriate timing
control and
associated bitline sensing circuits, high speed sensing of the described anti-
fuse memory
cells arranged in a complementary bitline scheme, such as the folded bitline
architecture, can
be achieved.
- 24 -
CA 02807739 2013-03-01
[0082] Figure 16 is a schematic of a portion of a folded bitline anti-fuse
memory array, similar
to that shown in Figure 13. In order to simplify the schematic, only one
folded bitline pair
BL/BL*, its associated bitline sensing circuitry, and two wordlines are shown.
Folded bitline
anti-fuse memory array 1000 includes wordlines WLO and WL1 connected to the
gate
terminals of n-channel anti-fuse transistors 1002 and 1004, n-channel
isolation transistors
1006 and 1008 for coupling the upper portion of the bitlines to the lower
portion of the bitlines
in response to signal ISO, and bitline sensing circuitry. The bitline sensing
circuitry includes a
precharge circuit 1010, a reference charge circuit 1012, and a bitline sense
amplifier 1014.
[0083] The precharge circuit 1010 includes two n-channel precharge transistors
1016 and
1018 connected in series between BL and BL* and having their gate terminals
connected to
precharge signal BLPCH. The shared source/drain terminal of precharge
transistors 1016
and 1018 receives a precharge voltage VPCH. In operation, both precharge
transistors 1016
and 1018 will turn on to precharge bitlines BL and BL* to VPCH in response to
an active high
logic level of BLPCH, in preparation for a read operation.
[0084] The reference charge circuit 1012 includes n-channel steering
transistors 1020 and
1022 connected in series between BL and BL*, a capacitance circuit implemented
as an n-
channel transistor 1024, and a p-channel precharge transistor 1026. Steering
transistor 1020
has its gate terminal connected to even selection signal E_REF, while steering
transistor
1022 has its gate terminal connected to odd selection signal O_REF.
Capacitance circuit
1024 has its gate terminal connected to voltage supply VCC, and is connected
in series with
precharge transistor 1026 between the shared source/drain terminal of steering
transistors
1020 and 1022 and voltage supply VCC. Precharge transistor 1026 has its gate
terminal
connected to precharge signal PCH*. Generally, capacitance circuit 1024 will
be precharged
when a low logic level PCH* pulse is received. The duration of the PCH* pulse
can be
predetermined based on the size of transistor 1024 and the desired reference
charge to be
provided. Once precharged, either steering transistor 1020 or 1022 is turned
on to couple the
reference charge of capacitance circuit 1024 to the corresponding bitline. By
example, the
charge being added to a bitline can be approximately 50 millivolts. It is
noted that signals
E_REF and O_REF can be controlled by the same even/odd addressing bit used for
selecting WLO or WL1. In one embodiment, activation of WLO will cause E_REF to
be
activated, thereby coupling the reference charge to the complementary bitline.
- 25 -
CA 02807739 2013-03-01
[0085] The bitline sense amplifier 1014 consists of a standard cross-coupled
inverter circuit
that is well known in the art. The circuit includes p-channel transistors 1028
and 1030, both
connected in series to respective n-channel transistors 1032 and 1034. The
common drain
terminal of p-channel transistors 1028 and 1030 receives a high logic level
enable signal
H_EN, while the common source terminal of n-channel transistors 1032 and 1034
receives a
low logic level enable signal L_EN. H_EN can be a lowered internal VCC level,
while L_EN
can be a VSS level. The operation of bitline sense amplifier 1014 in the DRAM
art is well
known. When enable signals H_EN and L_EN are activated, either at the same
time or at
different times, bitline sense amplifier 1014 will sense a small voltage
differential between BL
and BL*, and quickly drive both BL and BL* to the full logic level states of
H_EN and L_EN.
[0086] It is noted that the memory array of Figure 16 is inverted relative to
the embodiment
shown in Figure 13. More specifically, the memory array of Figure 13 uses p-
channel anti-
fuse memory cells while the memory array of Figure 16 uses n-channel anti-fuse
memory
cells. Accordingly, the values shown in Table 1 for operating the memory array
of Figure 13
should be inverted for the memory of Figure 16.
[0087] The memory array shown in Figure 16 can be operated in one of two
different modes.
The first mode is a standard single cell/bit mode, while a second mode is a
two cell/bit mode.
In the two cell/bit mode, one memory cell connected to one bitline of the
folded bitline pair
and a second memory cell connected to the other bitline of the folded bitline
pair are both
accessed at the same time by driving their respective wordlines at the same
time. In each of
the two different operating modes, a redundancy mode can be used. In the
single cell/bit
redundancy mode, two wordlines corresponding to two memory cells connected to
the same
bitline are activated during a read operation. In the two cell/bit redundancy
mode, two
wordlines corresponding to two memory cells connected to the same bitline and
two
wordlines corresponding to two memory cells connected to the other bitline are
activated
during a read operation. The redundancy mode increases the reliability of the
memory array
by activating two memory cells connected to the same wordline for reading one
bit of data.
Those skilled in the art will understand that wordline decoding logic can be
implemented to
enable activation of the necessary wordlines. Further details of the single
cell/bit and two
cell/bit operation will follow.
[0088] The high speed sensing scheme of the present embodiment is possible due
to the
nature of the previously described anti-fuse structure. The programmed anti-
fuse memory
- 26 -
CA 02807739 2013-03-01
cell of the present embodiments will behave like a resistive element, and in
the presently
shown configuration, will add charge to a bitline through its corresponding
wordline.
[0089] The general high speed sensing scheme for a single cell/bit mode of
operation
according to an embodiment of the present invention is as follows. It is
assumed that ISO is
at the high logic level to turn on isolation transistors 1006 and 1008, and
that capacitance
circuit 1024 has been precharged. First, both BUBL* are precharged to a first
voltage supply
level provided by VPCH, such as VSS, by activating BLPCH and turning on
transistors 1016
and 1018. Then one wordline, such as WLO, is driven to a second supply voltage
level
preferably opposite to the first voltage supply level, such as VCC for
example. WLO is
connected to anti-fuse memory cell 1004, which has its drain terminal
connected to BL*.
Occurring substantially at the same time as WLO is driven, E_REF is driven to
the high logic
level to turn on steering transistor 1020 and couple the capacitance circuit
1024 to bitline BL.
Now a reference charge will be present on bitline BL, which will raise the
voltage of BL by
about 50 millivolts for example. Enable signals H_EN and L_EN can then be
driven to high
and low voltage levels respectively for enabling bitline sense amplifier 1014.
[0090] If memory cell 1004 has been programmed and conducts (a blown state of
anti-fuse),
then wordline WLO will raise the voltage level of BL* from the precharge
voltage of VSS
towards VCC through the conduction path of the memory cell. Preferably, the
voltage of BL*
will be 100 millivolts, which is higher than the reference voltage of BL, when
the bitline sense
amplifier 1014 is activated. This voltage differential is quickly detected,
amplified and latched
by bitline sense amplifier 1014. On the other hand, if memory cell 1004 has
not been
programmed, then BL* will remain at the precharge voltage of VSS, which is
less than the
reference voltage of BL. In this case, the bitline sense amplifier 1014 will
latch the opposite
state.
[0091] The high speed sensing scheme for a two cell/bit mode of operation
according to an
embodiment of the present invention is as follows. It is assumed that ISO is
at the high logic
level to turn on isolation transistors 1006 and 1008. Reference charge circuit
1012 can be
disabled for the two cell/bit mode of operation as a reference charge is not
required. First,
both BUBL* are precharged to a first voltage supply level provided by VPCH,
such as VSS,
by activating BLPCH and turning on transistors 1016 and 1018. Then a pair of
wordlines,
such as WLO and WL1, are driven to a second supply voltage level preferably
opposite to the
first voltage supply level, such as VCC for example. WLO is connected to anti-
fuse memory
- 27 -
CA 02807739 2013-03-01
cell 1004, which has its drain terminal connected to BL* and WL1 is connected
to anti-fuse
memory cell 1002, which has its drain terminal connected to BL. In the two
cell/bit mode, one
of memory cells 1002 and 1004 will always be programmed and the other will not
be
programmed. Therefore, one bitline will always remain at VSS while the other
rises to about
100 millivolts. Enable signals H_EN and L_EN can be driven to high and low
voltage levels
respectively for enabling bitline sense amplifier 1014.
[0092] A detailed high speed sensing operation of the folded bitline anti-fuse
memory array
of Figure 16 according to an embodiment of the present invention will now be
described with
reference to the flow chart of Figure 17a and the timing diagram of Figure
17b. Figure 17b
shows signal traces for the control signals used in the bitline sensing
circuitry of Figure 16,
and of the wordline and bitline voltages. The presently described method is
directed to a
single cell/bit bit mode of operation.
[0093] It is presumed that signal ISO remains at the high voltage level for
the read operation,
and that memory cell 1004 connected to WLO is a programmed memory cell. The
method
starts at step 1100, where the capacitance circuit 1024 is precharged when
PCH* is pulsed
for a predetermined duration of time. Following at step 1102, the bitlines are
precharged to
the first voltage supply level, such as VSS in the present example, by pulsing
BLPCH to the
high logic level for a predetermined duration of time. In the present example,
the BLPCH and
PCH* pulses are concurrent, but can occur at any time relative to each other
but before a
wordline is activated. Based on the decoded row address, the desired wordline
is driven to
the second voltage supply level at step 1104. WLO will be driven to VCC in the
present
example. Occurring at substantially the same time, but noted as step 1106,
E_REF is driven
to VCC to turn on steering transistor 1020. Although not shown in Figure 17b,
O_REF
remains at VSS.
[0094] Because memory cell 1004 is programmed, the VCC biased wordline will
charge up
BL* through its conductive channel. E_REF turns on steering transistor 1020 to
add the
reference charge to BL. Steering transistor 1020 is kept on for a
predetermined period of
time, and then shut off by driving E_REF to VSS at step 1108. Shortly
afterwards at step
1110, H_EN is driven to the high logic level and L_EN is driven to the low
logic level to
activate bitline sense amplifier 1014. The differential between BL and BL* is
sensed and fully
latched by the bitline sense amplifier 1014. The ISO signal is driven to the
low logic state to
turn off isolation transistors 1006 and 1008 during sensing, to decrease the
load on the
- 28 -
CA 02807739 2013-03-01
bitline sense amplifier 1014. This also allows the wordline to be turned off
in order to
accelerate bitline precharge for the next read cycle.
[0095] In Figure 16, a memory cell is connected to one bitline while either
steering transistor
1020 or 1022 is connected to the other bitline, acting as a reference bitline.
The bitline from
which data is to be sensed from a connected memory cell can be called a data
bitline.
Unfortunately, there can be a capacitance imbalance seen by one bitline versus
the other,
since the electrical characteristics of a memory cell will be different than
that of steering
transistors 1020 and 1022. Therefore, to ensure that the bitlines are better
balanced during a
sensing operation, dummy memory cells can be used instead of the steering
transistors 1020
and 1022, according to an embodiment of the present invention. More
specifically, dummy
memory cells are identical to "normal" memory cells in the memory array. By
using dummy
memory cells for delivering the reference voltage, the bitline to wordline
coupling becomes
virtually identical on both the reference bitline and the data bitline.
[0096] Figure 18 is a schematic of an alternate folded bitline anti-fuse
memory array
according to another embodiment of the present invention. The alternate folded
bitline anti-
fuse memory array shown in Figure 18 is similar to that shown in Figure 16,
but employs an
alternate reference charge circuit that uses dummy memory cells. Folded
bitline anti-fuse
memory array 1200 includes the same numbered elements as previously shown and
described in Figure 16, and hence no further description of these elements is
required.
Reference charge circuit 1202 includes dummy memory cells 1204 and 1206, each
having a
gate terminal connected to dummy wordline DWLO and DWL1 respectively.
[0097] It is noted that while normal anti-fuse memory cells have only one
source diffusion
region, dummy memory cells 1204 and 1206 have an additional drain diffusion
region for
receiving the reference voltage. Dummy memory cells 1204 and 1206 are not
programmed,
but a dummy cell will form a conductive channel between its source and drain
terminals
when a positive gate voltage is applied. The common terminal of dummy memory
cells 1204
and 1206 is connected to a capacitance means 1208 and a precharge transistor
1210. N-
channel precharge transistor 1210 has a gate terminal connected to precharge
signal PCH. It
is noted that the configuration of capacitance means 1208 and n-channel
precharge
transistor 1210 functions equivalently to capacitance circuit 1024 and p-
channel precharge
transistor 1026, except that capacitance means 1208 is precharged when PCH
pulses to the
high logic level to turn on precharge transistor 1210.
- 29 -
CA 02807739 2013-03-01
[0098] In the presently shown embodiment, reference charge circuit 1202 is
connected to
the upper bitlines, whereas the reference charge circuit 1012 of Figure 16 was
connected to
the lower bitlines. In a further embodiment, the reference charge circuit 1012
of Figure 16
can be modified to replace the n-channel steering transistors 1020 and 1022
with dummy
memory cells. As previously discussed, the n-channel isolation transistors
1006 and 1008
effectively divide the bitlines into an upper portion and a lower portion,
where the upper
portion is a high voltage domain and the lower portion is a low voltage
domain. Because
signal ISO is limited to a predetermined low supply voltage, any high voltages
appearing on
the upper portion of the bitlines during programming operations will be
blocked from the more
sensitive low voltage bitline sense amplifier circuitry connected to the lower
portion.
Accordingly, those skilled in the art will understand that the transistors of
the high voltage
domain can have gate oxide thicknesses that are greater than those transistors
in the low
voltage domain.
[0099] In the previously described embodiments, PCH* is first pulsed for a
predetermined
duration of time, and the steering transistors 1020 and 1022 are turned on
then off before the
bitline sense amplifier 1014 is activated. According to an embodiment of the
present
invention, the timing of the precharge signal PCH* and the signals E_REF and
O_REF, can
be controlled to adjust the amount of charge being added to the bitline acting
as a reference
bitline. Hence the reference level of the reference bitline can be adjusted.
[00100] Figure 19a is a flow chart illustrating an alternate sensing
method using the
folded bitline anti-fuse memory array of Figure 16, while Figure 19b is a
corresponding timing
diagram showing the traces of the control signals used in the folded bitline
anti-fuse memory
array 1000. The method starts at step 1300, where precharging of the
capacitance circuit
1024 begins. This corresponds to PCH* falling to a low logic level. Then at
step 1302, the
bitlines are precharged to a first voltage supply, such as VSS for example. A
selected
wordline, such as WLO, is driven to a second voltage supply, such as VCC for
example, at
step 1304. Memory cell 1004 will then couple the WLO voltage to BL* if it is
programmed. At
step 1306, the reference charge provided by capacitive circuit 1024 is coupled
to BL. More
specifically, signal E_REF is driven to the high logic level to turn on
steering transistor 1020.
It is noted that PCH* is still at the low logic level, therefore more charge
than the method of
Figure 17a can be added to BL. At step 1308, PCH* is raised to the high logic
level to turn off
precharge transistor 1026. Following at step 1310, E_REF is driven to the low
logic level to
- 30 -
CA 02807739 2013-03-01
turn off steering transistor 1020. At step 1312, the bitline sense amplifier
1014 is activated
and the differential between BL and BL* is sensed.
[00101] The sensing method shown in Figure 19a is similar to the sensing
method
shown in Figure 17a, except that PCH* remains active to keep precharge
transistor 1026
turned on while steering transistor 1020 is turned on. Figure 19 is one
example of the timing
control over E_REF and PCH* for adjusting the reference charge to be provided.
Those
skilled in the art will understand that the PCH* pulse duration and the E_REF
signal
deactivation time can be tailored to achieve the desired reference charge on
the un-
accessed bitline. The timing can be controlled externally in a test mode, or
internally with well
known logic circuitry. This adjustability allows for several advantageous
applications.
[00102] By adjusting the reference charge level on the reference bitline,
the relative
conductive capability of a programmed anti-fuse memory cell can be tested.
Hence
convenient cell margining operations can be executed since the timing of PCH*
and E_REF
(or O_REF) can be calibrated to expected or experimental reference charges
applied to the
reference bitline. The method of Figure 19a can be used for program verify
operations, to
ensure that the programmed cells have a sufficient conducting current. In a
two-cell per bit
mode of operation, reference voltages, and hence the reference charge
circuits, are not
used. However, in a test mode, a reference charge can be progressively
increased on one
bitline while a programmed memory cell connected to the complementary bitline
conducts.
Eventually, the bitline sense amplifier will flip its state, which reveals the
voltage applied to
the bitline by the programmed memory cell.
[00103] The embodiment of the invention shown in Figures 16 and 18 can
sense the
difference in voltage between a pair of folded bitlines, in order to sense the
programmed or
unprogrammed state of an anti-fuse memory cell. Furthermore, timing of the
reference
charge circuit 1012 can be adjusted to change the reference charge being added
to the
reference bitline. This can be done for testing operations, as previously
described, or to
ensure that the optimal reference voltage level is provided to improve sensing
margins of
programmed anti-fuse memory cells. Those skilled in the art will understand
that process
variations can change the current conducting level of programmed anti-fuse
memory cells,
therefore, having the ability to adjust the reference voltage after the memory
array is
programmed will ensure reliable operation.
- 31 -
CA 02807739 2013-03-01
[00104] Another technique for adjusting the charge being added to an
reference bitline
without having to adjust timing of control signals is to selectively add more
capacitance to the
reference bitline. Figure 20 is a schematic of an alternate folded bitline
anti-fuse memory
array according to another embodiment of the present invention. The alternate
folded bitline
anti-fuse memory array shown in Figure 20 is similar to that shown in Figure
16, but employs
an alternate reference charge circuit that can increase the amount of charge
to be added to
an reference bitline.
[00105] Folded bitline anti-fuse memory array 1400 includes the same
numbered
elements as previously shown and described in Figure 16, and hence no further
description
of these elements is required. Reference charge circuit 1402 includes
supplemental
capacitance circuits 1404 and 1406, each having a gate terminal connected to a
selection
signal C1 and C2, respectively. The supplemental capacitance circuits are
shown in the
present embodiments as n-channel transistors connected in parallel to primary
capacitance
circuit 1024, but p-channel transistors can be used with equal effectiveness.
To supplement
the charge provided by primary capacitance circuit 1024, one or both of
capacitance circuits
1404 and 1406 can be activated by driving C1 and C2 to the high logic level.
Transistors
1404 and 1406 can be identically sized as transistor 1024, or each can be
sized differently.
Furthermore, any number of additional capacitance circuits can be included,
and any
combination of supplemental capacitance circuits can be activated, to provide
more flexibility
and finer control over the reference charge to be added to the reference
bitline. The sensing
operation can be the same as previously described for Figure 17a.
[00106] While the embodiments for adjusting the reference charge by signal
timing
control and supplemental capacitance addition have been described exclusively
of each
other, the two techniques can be used in combination to obtain the highest
amount of
flexibility. For example, any number of supplemental capacitance circuits can
be activated
and precharged while the steering signal E_REF or O_REF are activated, as per
the sensing
method previously described for Figure 19a.
[00107] In the previously described embodiments of the high-speed sensing
scheme,
a reference charge was added to one bitline acting as a reference bitline of
the folded bitline
pair. Controlled timing of the reference charge circuit and/or selective
addition of
supplemental capacitance can be used for providing a reference charge. At high
clock
speeds however, it may not be practical or possible to generate the necessary
timing for
- 32 -
CA 02807739 2013-03-01
proper operation. Therefore, a high speed self-sensing scheme for the
differential bitline anti-
fuse memory array, according to an embodiment of the present invention, is
proposed.
[00108] In the high-speed self-sensing scheme according to the present
embodiment,
an additional capacitance can be added to the data bitline of the
complementary bitline pair
from which data of a connected memory cell is to be sensed. In other words,
the additional
capacitance is not added to the reference bitline. The additional capacitance
added to the
bitline changes the rate at which its voltage rises relative to the other
bitline (such as the
reference bitline) that does not have the additional capacitance added to it.
[00109] Figure 21 is a schematic of the alternate folded bitline anti-fuse
memory array
according to the present embodiment of the invention. The alternate folded
bitline anti-fuse
memory array shown in Figure 21 is similar to that shown in Figure 16, but
employs an
alternate reference charge circuit that adds capacitance to the data bitline.
Folded bitline
anti-fuse memory array 1500 includes the same numbered elements as previously
shown
and described in Figure 16, and hence no further description of these elements
is required.
Reference charge circuit 1502 includes previously described steering
transistors 1020 and
1022, and a capacitance means 1504 connected to the shared source/drain
terminal of
transistors 1020 and 1022. The sensing operation of folded bitline anti-fuse
memory array
1500 will now be described with reference to the flow chart of Figure 22a and
the timing
diagram of Figure 22b.
[00110] It is assumed that transistor 1004 is to be accessed (Case 1 shown
in Figure
22b), and is an unprogrammed anti-fuse memory cell which does not have a gate
to drain
conduction channel. In Figure 22a, the sense operation starts at step 1600
where the bitlines
are precharged to the first voltage supply, such as VSS for example. This
corresponds to
BLPCH pulsing high in Figure 22b. Following at step 1602, a selected wordline
is driven to a
second voltage supply, such as VCC for example. Occurring concurrently with
the selected
wordline activation, but noted as step 1604, signal O_REF is raised to VCC to
turn on
steering transistor 1022. Hence the capacitance means 1504 is coupled to the
same bitline
that memory cell 1004 is connected to. At step 1606, the sense amplifiers are
turned on by
driving H_EN and L_EN to the high and low logic levels respectively. With both
bitlines BL
and BL* precharged to VSS, the p-channel transistors 1028 and 1030 of bitline
sense
amplifier will turn on and pull both BL and BL* towards H_EN. Since memory
cell 1004 is
non-conductive, both bitlines BL and BL* should rise at approximately the same
rate.
- 33 -
CA 02807739 2013-03-01
[00111] However, since BL* has the additional capacitance means 1304
connected to
it, it will rise at a slower rate relative to BL. Therefore, once BL rises to
the threshold voltage
level of the n-channel transistor 1034, bitline sense amplifier 1014 will
fully latch and drive BL
to the H_EN logic level and BL* to the L_EN logic level. The advantage of this
present
scheme is that no timing control over reference charge circuit 1502 is
required. Preferably,
the bitline sense amplifier 1014 is activated either at the same time, or
shortly after the
selected wordline WLO and the proper steering signal are activated.
[00112] In contrast, if memory cell 1004 is a programmed anti-fuse memory
cell having
gate to drain conduction channel (Case 2 shown in Figure 22b), BL* will rise
to the threshold
voltage level of n-channel transistor 1032 first. In Case 2 of Figure 22b, the
addition of the
charge from the wordline WLO memory cell 1004 will provide a positive offset
on BL*. Once
the bitline sense amplifier 1014 is activated, the p-channel transistors 1028
and 1030 will pull
BL and BL* towards E_EN. While the rising rate of BL* is still slower than
that of BL due to
the added capacitance means 1504, the positive voltage offset is sufficient
such that BL* will
reach the n-channel transistor threshold voltage first. Hence, the bitline
sense amplifier 1014
latches to a state opposite to the one in Case 1.
[00113] One issue with testing unprogrammed anti-fuse memory cells in a
two cell/bit
mode of operation, is that the bitline sense amplifiers will latch to
unpredictable logic states.
Since both BL and BL* start at a precharged VSS value, minor voltage
variations or
manufacturing variations can affect the bitline voltages, and hence sensing by
the bitline
sense amplifiers. Hence, the present scheme of adding capacitance to the data
bitline will
ensure that properly fabricated memory cells operating in a two cell/bit mode
will be
consistently sensed.
[00114] The previously described embodiments of the high speed sensing
scheme for
a folded bitline anti-fuse memory array, precharged the bitlines to VSS,
followed by the
application of a reference charge to a reference bitline or application of
capacitance to a data
bitline for sensing by a bitline sense amplifier. According to further
embodiments of the
present invention, the bitlines can be precharged to VCC instead of VSS.
[00115] The precharge-to-VCC sensing method according to an embodiment of
the
invention, can be executed with the folded bitline anti-fuse memory array of
Figure 16, and is
similar to the sensing method outlined in Figure 17a. The timing diagram of
Figure 23 shows
- 34 -
CA 02807739 2013-03-01
traces for the control signals of Figure 16 and of the bitlines BL and BL* for
two different
cases. In Case 1, the accessed memory cell connected to BL* is programmed. In
Case 2, the
accessed memory cell connected to BL* is unprogrammed.
[00116] The precharge-to-VCC embodiment using Case 1 is now described with
reference to the timing diagram of Figure 23. After both bitlines are
precharged to a first
voltage supply, such as VCC for example, a wordline such as WLO is driven to a
second
voltage supply V1, such as VCC + 1.5 volts for example. If the anti-fuse
memory cell 1004 is
programmed, then the wordline will pull bitline BL* up to a voltage of about
VCC + 100
millivolts. Then a reference charge is added to the reference bitline BL by
activating E_REF,
raising it to about VCC + 50 millivolts for example. When the bitline sense
amplifier is
activated, the differential between the two bitlines is sensed and fully
latched.
[00117] On the other hand, if the accessed memory cell 1004 is non-
conductive as in
Case 2, then the data bitline BL* will remain at VCC, which is lower than the
reference (or
unselected) bitline BL voltage of VCC+50 millivolts. Hence the bitline sense
amplifier will
latch the opposite state.
[00118] In the previously described embodiment, a reference charge was
added to the
reference bitline. One disadvantage of this scheme is a high precharge voltage
required for a
reference charge. This is solved in an alternate precharge-to-VCC embodiment
of the
present invention, where a negative reference charge is added to the data
bitline, which
requires precharging the reference capacitor to ground. Figure 24 is a timing
diagram
illustrating the relative voltage levels of BL and BL* of the present sensing
embodiment for
two different cases.
[00119] In Case 1, after both bitlines are precharged to a first voltage
supply, such as
VCC for example, a wordline such as WLO is driven to a second voltage supply
V1, such as
VCC + 1.5 volts for example. If the anti-fuse memory cell 1004 is programmed,
then the
wordline will pull bitline BL* up to a voltage of about VCC + 100 millivolts.
Then a negative
reference charge is added to the data bitline BL* by activating O_REF,
reducing it by 50
millivolts for example. The reference bitline BL remains at VCC. Therefore,
when the bitline
sense amplifier is activated, the differential between the data bitline and
the reference bitline
is sensed and fully latched.
- 35 -
CA 02807739 2013-03-01
[00120] On the other hand, if the accessed memory cell 1004 is non-
conductive as in
Case 2, then the data bitline BL* will drop to about VCC - 50 millivolts,
which is lower than
the reference (or unselected) bitline BL voltage of VCC. Hence the bitline
sense amplifier will
latch the opposite state
[00121] The previously illustrated sensing/testing scheme embodiments have
been
described with respect to memory arrays consisting of single transistor anti-
fuse memory
cells. Those skilled in the art will understand that the sensing/testing
embodiments can be
applied to memory arrays consisting of memory cells having two transistors,
such as those
illustrated in Figures 2 and 3, with the appropriate control over the cell
plate voltage Vcp.
[00122] All the previously described embodiments are directed to circuits
and methods
for sensing data on bitlines of a memory array, and in particular folded
bitlines of a memory
array. Advances in semiconductor manufacturing and scaling allows for tight
packing of
bitlines in the memory array, thereby reducing the spacing between adjacent
bitlines. This
leads directly to an increase in capacitive coupling between the tightly
packed bitlines, which
can potentially cause read errors. An example of the bitline capacitive
coupling effect is
described with reference to Figure 25.
[00123] Figure 25 is a circuit schematic of four metal bitlines, BLO, BL1,
BL2 and BL3
in a tight packing arrangement, and memory cells connected to each of the
bitlines. Figure
25 is merely one example of a possible bitline configuration which uses the
previously
described single transistor anti-fuse transistor embodiment of the present
invention, and
those skilled in the art will understand that any memory cell, including the
two transistor anti-
fuse memory cell, can be used. In the presently shown example of Figure 25,
there are four
anti-fuse memory cells 1750, of only one which is labeled, each having a drain
diffusion
terminal connected to a respective bitline, and gates connected to a wordline
WL. The
memory cells connected to BLO, BL1 and BL3 have been programmed, while the
memory
cell 1750 connected to BL2 is not programmed. In Figure 25, a programmed anti-
fuse
memory cell 1750 has a resistor element 1752 connected between WL and its
respective
source terminal, to functionally illustrate the conductive link formed during
programming of
the anti-fuse cell.
[00124] According to one of the previously described sensing embodiments,
the
bitlines are precharged to VSS prior to a read operation. Then the wordline WL
is driven to a
- 36 -
CA 02807739 2013-03-01
high voltage level, and any memory cell 1750 having the conductive link
(programmed) will
charge its corresponding bitline towards the high voltage level. This will
happen to bitlines
BLO, BL1 and BL3. However, the memory cell connected to BL2 is not programmed,
therefore BL2 should remain at the precharge voltage of VSS. Unfortunately,
due to the
capacitive coupling between adjacent bitlines, shown illustrated as capacitor
1754, the rising
voltage of BL1 and BL3 adjacent to BL2 will pull BL2 towards the high voltage
level.
Therefore, sensing the data on BL2 will be erroneous. While having both
bitlines adjacent to
the data bitline represents the worst-case scenario, having even one adjacent
bitline rising to
the high voltage level can result in the same effect. Therefore, a new
precharging scheme is
required for reducing this bitline coupling effect.
[00125] Figure 26 is a circuit schematic of an OTP memory array 1800
having a novel
bitline precharge circuit for mitigating the above described bitline coupling
effects, according
to an embodiment of the present invention. In the present embodiment, bitlines
adjacent to a
data bitline for sensing by a bitline sense amplifier are precharged to a
voltage level
corresponding to the opposite logic state of the precharge voltage of the data
bitline. The
reference bitlines and the data bitlines can be called selected bitlines,
while the remaining
bitlines can be called unselected bitlines. In other words, if the data
bitline is precharged to
VSS, which corresponds to a logic "0", then its adjacent unselected bitlines
are precharged to
a high voltage level which corresponds to a logic "1". Alternately, the
adjacent unselected
bitlines can be precharged to a voltage level different than the previously
described high
voltage level. Therefore during sensing, the data bitline will rise towards
the high voltage
level if its corresponding memory cell is programmed, or it will stay at the
precharged VSS
voltage level, regardless of the programmed/unprogrammed states of memory
cells
connected to the adjacent bitlines.
[00126] In Figure 26, OTP memory array 1800 includes n-channel single
transistor
anti-fuse memory cells 1802 as previously described in the embodiments of the
present
invention, preferably arranged in the folded bitline scheme. It is noted that
OTP memory
array 1800 is illustrated differently than in the previous figures, but is
still functionally
representative of a folded bitline configuration. It will be apparent to those
skilled in the art
that the proposed precharge scheme is applicable to any type of memory cell
and bitline
architecture. Complementary bitlines BLO/BLO*, BL1/BL1*, BL2/BL2* and BL3/BL3*
are
selectively coupled to a bitline sense amplifier 1804 through column select
circuit 1806.
- 37 -
CA 02807739 2013-03-01
Column select circuit 1806 is configured with n-channel column select devices
1808, 1810,
1812, 1814, 1816, 1818, 1820 and 1822. It is noted that the column select
devices are paired
due to the folded bitline configuration. For example, column select devices
1808 and 1822
are controlled by the same column select signal Y-SEL[0].The remaining column
select
device pairs are controlled by column select signals Y-SEL[1], Y-SEL[2] and Y-
SEL[3].The
operation of column select circuit 1806 and its n-channel column select
devices is well known
in the art. Based on a column address, a pair of column select devices are
activated to
couple one complementary bitline pair to bitline sense amplifier 1804 for
sensing.
[00127] In order to selectively control precharge to particular bitlines
according to the
presently described embodiment of Figure 26, a selective precharge circuit
1824 is provided.
Selective precharge circuit 1824 is similar in configuration to column select
circuit 1806, and
includes n-channel column precharge devices 1826, 1828, 1830, 1832, 1834,
1836, 1838
and 1840 for coupling the bitlines to a precharge voltage circuit 1842.
Similarly, the column
precharge devices are paired such that one precharge selection signal, such as
PC_S[0], will
activate the pair of column precharge devices connected to a complementary
pair of bitlines.
For example, column precharge devices 1826 and 1840 form one such pair. The
remaining
pairs of column precharge devices are controlled by PC_S[1], PC_S[2] and
PC_S[3]. For the
present embodiment, the signals controlling each pair of column precharge
devices and each
pair of column select devices connected to the same bitlines are based on
complementary
column address signals (not shown). More specifically, PC_S[0] to PC_S[3] and
Y-SEL[0] to
Y-SEL[3] are generated with different decoding circuits, which use
complementary column
address signals and with different timing.
[00128] In one embodiment, the precharge voltage circuit 1842 can provide
a
predetermined precharge voltage level prior to a read operation. In another
embodiment, the
precharge voltage circuit 1842 can simply be the VCC voltage supply. In either
embodiment,
a primary precharge circuit similar to precharge circuit 1010 of Figure 16 can
integrated with
the bitline sense amplifier circuit 1804 for precharging only the selected
bitlines to VSS prior
to the read operation.
[00129] According to a method of precharge operation according to an
embodiment of
the present invention, the column precharge devices of selective precharge
circuit 1824 and
the column select devices are activated simultaneously in a precharge phase
such that the
selected bitlines are precharged to VSS while the bitlines adjacent to the
selected bitlines are
- 38 -
CA 02807739 2013-03-01
precharged to the high voltage level. The control over the specific bitlines
to precharge to the
high voltage level during the precharge phase can be achieved by controlling
signals
PC_S[0] to PC_S[3]. Following the precharge phase is a read phase where the
selected
wordline is activated, the appropriate reference charge is added to the
reference bitlines, and
both the data bitlines and the reference bitlines are coupled to the bitline
sense amplifier
1804 for data sensing.
[00130] An example operation of the selective precharge circuit 1824
according to a
preferred embodiment of the invention will now be described with reference to
the circuit of
Figure 26, and the flow chart of Figure 27. It is assumed that WL1 will be
activated for a read
operation, and that the memory cells connected to WL1 and to BL3*, BL2* and
BLO* are
programmed while the memory cell connected to WL1 and to BL1* is not
programmed. In
step 1900, all the column precharge devices of selective precharge circuit
1824, except
devices 1828 and 1838 are activated to precharge all bitlines except BL1 and
BL1* to the
high voltage level.
[00131] Occurring concurrently at step 1902, only column select devices
1810 and
1820 will be turned on by driving Y-SEL[1] to a high logic level while the
precharge to VSS
circuit in BLSA 1804 is activated. Due to the column decoding scheme based on
complementary column addresses, devices 1828 and 1838 are turned off while
devices
1826, 1830, 1832, 1834, 1836 and 1838 are turned on. Therefore, the unselected
bitlines
adjacent to selected bitlines BL1/BL1* are driven to the high voltage level
while the selected
bitlines are driven to VSS. Now WL1 can be driven to the high voltage level at
step 1904.
BL1 can be the reference bitline in a single ended sensing scheme, but can be
the
complementary bitline in a two cell per bit sensing scheme. Then at step 1906,
the bitline
sense amplifier 1804 can be activated to sense the voltage differential on
BL1/BL1*.
[00132] As previously noted, signals PC_S[0] to PC_S[3] and Y-SEL[0] to Y-
SEL[3]
are signals that are decoded in complementary fashion, but they are not the
inverse of each
other. In a practical implementation of the embodiments of the invention,
precharging of the
unselected bitlines should end before activation of the wordlines by turning
off the column
precharge devices, while keeping the proper column select devices turned on.
Once sensing
is finished, precharging of the unselected bitlines can then resume.
Therefore, appropriate
timing control can be implemented to achieve this desired operation.
Furthermore, control
over signals PC_S[0] to PC_S[3] and Y-SEL[0] to Y-SEL[3] can be based in part
on changes
- 39 -
CA 02807739 2013-03-01
,
to the column address. For example, in circumstances where subsequent read
cycles use
the same column address, the selected bitlines would be precharged to VSS
while the
remaining unselected bitlines are precharged to the high voltage level.
Conversely, if the
column address is changing between read cycles, all the bitlines can be
precharged to the
high voltage level at the end of one read cycle. Then the selected bitlines
are precharged
from the high voltage level to VSS when the new column address signal (Y-
SEL[0] to Y-
SEL[3]) has been activated.
[00133] It should be understood that the presently described
bitline precharge
embodiment can be used in combination with any of the previously described
bitline sensing
schemes.
[00134] Therefore, as illustrated in the embodiment of Figure 26,
precharging all
bitlines except the data bitline and the reference bitline to the high voltage
level will minimize
the bitline capacitance coupling effect, since the unselected bitlines will
remain at the
precharged high voltage level regardless of the programmed/unprogrammed states
of the
memory cells connected thereto. In the presently described embodiment, of a
group of four
bitlines, three bitlines will be precharged to the high voltage level. This
can be a source of
power consumption since many of the bitlines are precharged from VSS to VDD in
preparation for the next read operation. Since only the bitlines immediately
adjacent to
selected bitlines need to be precharged to the high voltage level, any non-
adjacent and
unselected bitlines can remain precharged to VSS during the first and the
second precharge
phases. An alternate bitline precharge embodiment for conserving bitline power
consumption
is shown in Figure 28.
[00135] The OTP memory array 2000 is identical to the OTP memory
array 1800
shown in Figure 26, except for the control connections of the column precharge
devices. In
particular, the gate terminals of column precharge devices 1826, 1830, 1836
and 1840 are
connected to even precharge select signal PC_S[EVEN] decoded for even columns,
and the
gate terminals of column precharge devices 1828, 1832, 1834 and 1838 are
connected to
odd precharge select signal PC_S[ODD] decoded for odd columns. This simplified
decoding
scheme will minimize the number of bitlines that need to be precharged to the
high voltage
level during the precharge phase. Therefore, power consumption is reduced.
Using the same
example described above for Figure 26, when PC_S[ODID] is driven to the low
logic level,
column precharge devices 1828, 1832, 1834 and 1838 will turn off. Although
bitlines
- 40 -
CA 02807739 2013-03-01
BL3/BL3* are unselected, they are not driven to the high voltage level during
the precharge
phase.
[00136] Persons skilled in the art will understand that column address
decoding can
easily be configured for achieving the previously described control
functionality for the
column access devices and precharge access devices. The precharge voltage
levels can be
further optimized to minimize power consumption while providing enough
protection against
the bitline coupling effect.
[00137] The previously described embodiments of the invention can be
combined with
each other, to realize the benefits and advantages afforded by each circuit or
method. For
example, the bitline precharge scheme shown in Figures 25 to 27 can be
combined with the
sensing scheme shown in Figure 16.
[00138] The previously described embodiments of the anti-fuse transistor
can be
fabricated using standard CMOS processes, where its specific structures can be
formed by
simple mask manipulation. Accordingly, the above-described anti-fuse
transistors and
memory array can be manufactured at low cost either as p-type or n-type
antifuses.
[00139] While the embodiments of the present invention are described with
respect to
single polysilicon gate anti-fuse transistor cells, the aforementioned
teachings can apply to
metal gate devices, and dual-gate structures similar to that shown in Figures
2 and 3. In such
an embodiment, the gate 14 would be formed over a thick gate oxide portion,
while top plate
16 would be formed over a thin gate oxide portion. Oxide breakdown is enhanced
through
the previously discussed techniques, such as high voltage diffusion doping and
salicidation
with RPO formation. Accordingly, the fusible edge would be located at the
common edge of
the thin gate oxide under top plate 16 and diffusion region 22, while the
access edge would
be located at the common edge of the thick oxide under gate 14 and diffusion
region 24.
[00140] According to another embodiment of the present invention, memory
arrays
consisting of unprogrammed two transistor anti-fuse memory cells such as the
one shown in
Figure 2 by example, and unprogrammed single transistor anti-fuse memory cells
such as
the one shown in Figures 4 and 5 can be tested to validate the presence and
quality of the
anti-fuse device. More specifically, the presently described testing
embodiments takes
advantage of the capacitive nature of the unprogrammed anti-fuse device of the
memory cell,
- 41 -
CA 02807739 2013-03-01
such as anti-fuse device 12 of Figure 12 and the anti-fuse device consisting
of the thin gate
oxide of variable thickness gate oxide 102 of transistor 100 of the embodiment
of Figure 4.
[00141] Embodiments of the unprogrammed anti-fuse device testing schemes
is to
identify potentially defective cells in the memory array due to fabrication
defects. In some
embodiments for example, unprogrammed anti-fuse device testing schemes are
used to
confirm the presence of the anti-fuse device in the cells. The absence of the
anti-fuse device
in the cell, or a fabrication defect where the anti-fuse device is not
electrically connected to a
corresponding bitline, renders the cell unprogrammable.
[00142] Following is a description of two unprogrammed anti-fuse device
testing
embodiments, which can be used for testing both two transistor anti-fuse
memory cells such
as the one shown in Figure 2 by example, and single transistor anti-fuse
memory cells such
as the one shown in Figure 4 by example. The first test is a WL to BL
Capacitive Coupling
Test, to confirm if a bitline (BL) or word line (WL) connection to a non-
defective,
unprogrammed anti-fuse cell is present. The second test referred to as a
Capacitive Load
Test, confirms if the bitline connection to a non-defective unprogrammed OTP
cell and/or the
anti-fuse device is present. Generally, these tests can determine at least the
following
semiconductor manufacturing defects:
[00143] i) No connection between the polysilicon gate and its connection
to a wordline
signal conductor;
[00144] ii)No connection between the bitline and the drain of an access
transistor; and
[00145] iii) Lack of the thin gate oxide anti-fuse area due to the low
(coarse) tolerance
of the oxide definiton mask (OD).
[00146] Each of the two unprogrammed anti-fuse device testing embodiments
can be
used with the any of the previously shown anti-fuse memory arrays, provided
additional test
cells are included. Figure 29 is a circuit schematic of a two-transistor anti-
fuse memory array
having test cells, according to a present embodiment. Figure 30 is a circuit
schematic of a
single transistor anti-fuse memory array having test cells, according to a
present
embodiment. Prior to a discussion of the testing schemes, the anti-fuse memory
arrays of
Figure 29 and Figure 30 is first described.
- 42 -
CA 02807739 2013-03-01
[00147] Figure 29 is a circuit schematic of a portion of a folded bitline
anti-fuse
memory array 2000, similar to the folded bitline anti-fuse memory array 1200
shown in Figure
18. A complementary pair of bitlines BL and BL* are connected to a bitline
precharge circuit
2002 and isolation devices 2004 and 2006 which are also connected to a sense
amplifier
2008. A reference charge circuit 2010 is connected to the bitline segments
connecting the
isolation devices 2004 and 2006 to the sense amplifier 2008. Two transistor
anti-fuse
memory cells are connected to the bitlines BL and BL*, such as anti-fuse
memory cell 2012
having an access transistor 2014 connected to BL* and in series with an anti-
fuse device
2016. The gate terminal of access transistor 2014 is connected to wordline WL1
while the
gate terminal of anti-fuse device 2016 is connected to the cell plate voltage
VCP1. Similar
two-transistor anti-fuse memory cells are connected to the first wordline and
cell plate
voltage WLONCPO up to the last wordline and cell plate voltage WLnNCPn. Up to
this point,
the anti-fuse memory array 2000 is no different than the previously shown and
described
anti-fuse memory arrays, except that two-transistor anti-fuse cells are used
instead of single
transistor anti-fuse cells.
[00148] In Figure 29, a first unprogrammed dummy cell 2020 is connected to
BL* and
a second unprogrammed dummy cell 2022 is connected to BL. The dummy access
transistor
2024 of dummy cell 2020 is identical to the access transistors of the normal
anti-fuse
memory cells, such as access transistor 2014. According to present
embodiments, the
dummy anti-fuse device 2026 of dummy cell 2020 is the same as a normal memory
cell anti-
fuse device, or it can be larger in area than anti-fuse device 2016 of the
normal anti-fuse
memory cell by a predetermined factor. In one present embodiment, this factor
is 2 such that
the dummy anti-fuse device 2026 has a capacitance roughly 2 times that of anti-
fuse device
2016. For example, if the capacitance of anti-fuse device 2016 is 1 femto
farad, then the
capacitance of dummy anti-fuse device 2026 is about 2 femto farads. The dummy
access
transistor 2024 has a gate terminal connected to a dummy wordline D_WL1, while
the
dummy anti-fuse device 2026 has a gate terminal connected to a dummy cell
plate voltage
D_VCP1. Similarly, the dummy access transistor and dummy anti-fuse device of
dummy cell
2022 are connected to D_WL0 and D_VCP0. The dummy cells 2020 and 2022 are used
for
normal read operations, similar to the read operation shown in Figure 19b. In
this particular
embodiment, one of the dummy cells 2020 and 2022 is connected to an unselected
bitline
while a normal memory cell is connected to a selected bitline. It is noted
that each of the
- 43 -
CA 02807739 2013-03-01
normal memory cells has an inherent coupling capacitance between its cell
plate voltage
VCP and word line WL, to a corresponding bitline. Accordingly, an unprogrammed
normal
memory cell will increase its VSS precharged bitline positively by a small
amount. Therefore,
the dummy cell compensates for the WL and VCP coupling capacitance of the
normal cell by
adding its own WL and VCP coupling capacitance to the unselected bitline
during a read
operation. The reference circuit 2010 can be operated as outlined in the
previously disclosed
embodiments.
[00149] The anti-fuse memory array 2000 includes additional test cells
having only a
test access transistor and no anti-fuse device. In Figure 29, a first test
cell 2028 is connected
to BL* and a second test cell 2030 is connected to BL. Test cell 2028 includes
just a test
access transistor 2032, which is identical to the access transistors of the
normal anti-fuse
memory cells, such as access transistor 2014. Test access transistor 2032 has
its gate
terminal connected to a test wordline T_WL1, and can optionally include a
floating source
diffusion region. Similarly, the second test cell 2030 includes just a test
access transistor,
having its gate terminal connected to another test wordline T_WLO. The test
cells 2028 and
2030 are used for some of the unprogrammed anti-fuse device testing scheme
embodiments
In summary, it is noted that the test cells add less capacitance to a bitline
than a normal two-
transistor anti-fuse cell could. In the presently shown embodiment of Figure
29, all the
memory cell transistors and anti-fuse devices are n-type.
[00150] Figure 30 is a circuit schematic of a portion of a folded bitline
anti-fuse
memory array 2100, similar to the folded bitline anti-fuse memory array 2000
shown in Figure
29. A complementary pair of bitlines BL and BL* are connected to a bitline
precharge circuit
2102 and isolation devices 2104 and 2106 which are also connected to a sense
amplifier
2108. A reference charge circuit 2110 is connected to the bitline segments
connecting the
isolation devices 2104 and 2106 to the sense amplifier 2108. Single transistor
anti-fuse
memory cells are connected to the bitlines BL and BL*, such as anti-fuse
memory cell 2112
having a variable thickness gate oxide transistor connected to BL*. The gate
terminal of
variable thickness gate oxide transistor 2112 is connected to wordline WL1.
Similar single
transistor anti-fuse memory cells are connected to the first wordline WLO up
to the last
wordline WLn. Up to this point, the anti-fuse memory array 2000 is no
different than the
previously shown and described anti-fuse memory arrays. In Figure 30, a first
unprogrammed dummy cell 2120 is connected to BL* and a second unprogrammed
dummy
- 44 -
CA 02807739 2013-03-01
cell 2122 is connected to BL. The dummy cells 2120 and 2122 are substantially
identical to
the normal anti-fuse memory cells and have a variable thickness gate oxide. In
the present
embodiments, the thin gate oxide portion has an area that is the same as that
of a normal
memory cell, or it can be larger than that of anti-fuse transistor 2112 by a
predetermined
factor. In the present embodiment, this factor is 2 such that the anti-fuse
device of anti-fuse
cell 2120 has a capacitance roughly 2 times that of anti-fuse device of anti-
fuse cell 2112.
Dummy cell 2120 has a gate terminal connected to a dummy wordline D_WL1, dummy
cell
2122 has a gate terminal connected to D_WLO. The dummy cells of Figure 30 can
be used in
the same manner as previously discussed for the dummy cells of Figure 29.
[00151] The anti-fuse memory array 2100 includes additional test cells,
similar to the
ones shown in Figure 29. In Figure 30, a first test cell 2128 is connected to
BL* and a second
test cell 2130 is connected to BL. Test cell 2128 includes just an access
transistor portion
thereof, which is identical to the access transistor portion of the normal
variable thickness
anti-fuse memory cell 2112. More specifically, the access transistor portion
of the variable
thickness gate oxide transistor is formed by the thick portion between the
bitline contact and
the thin gate portion, accordingly the test cells 2128 and 2130 are formed
without the thin
gate oxide portion. The first test cell 2128 has its gate terminal connected
to a test wordline
T_WL1. The second test cell 2130 has its gate terminal connected to another
test wordline
T_WLO. The test cells 2128 and 2130 are used for some of the unprogrammed anti-
fuse
device testing scheme embodiments and dummy cells 2120 and 2122 are used for
other
unprogrammed anti-fuse device testing scheme embodiments. In summary, the test
cells can
add less capacitance to a bitline than a normal single transistor anti-fuse
cell could. In the
presently shown embodiment of Figure 30, all the single transistor anti-fuse
cells are n-type.
[00152] With this understanding of the test cells, the unprogrammed anti-
fuse device
testing embodiments are now described in detail.
[00153] Figure 31 is a flow chart showing a method of testing for the
presence of a
bitline connection to an anti-fuse cell. This method, also referred to as a
Capacitive Load
Test, can be executed for both the two transistor anti-fuse memory array 2000
of Figure 29
and the single transistor anti-fuse memory array 2100 of Figure 30, and uses
the test cells
connected to either T_WL0 or T_WL1. This method is now described with
reference to
memory array 2000 of Figure 29 by example. The method starts at 2200 by
precharging a
bitline pair BL and BL* to a first voltage level, such as VSS for example.
Following at 2202, a
- 45 -
CA 02807739 2013-03-01
normal cell to be tested and a test cell are simultaneously activated. In
Figure 29, it is
assumed that the cell connected to WLn-1 and VCPn-1 is the memory cell to be
tested, and
the test cell 2028 connected to T_WL1 is the test cell to be used. In the two-
transistor
embodiment of Figure 29, activation includes driving WLn-1 and T_WL1 to a test
voltage
Vtest that is higher than the read voltage Vread typically used during a read
operation. In one
embodiment, Vtest is higher than Vread by at least a threshold voltage of the
n-channel
access transistor of the two-transistor memory cell in order to compensate for
its threshold
voltage drop. During this test, VCPn-1 is driven to VSS anytime before the
wordline WLn-1 is
driven to Vtest. Assuming that the normal anti-fuse memory cell being tested
is free of
manufacturing defects and functional, it will have a higher capacitance than
test cell 2028
which does not have any capacitor portion. On the other hand, if the access
transistor is
electrically disconnected from the bitline due to a random manufacturing
defect, then the test
cell 2028 will have a higher capacitance than the memory cell being tested.
[00154] At 2204, the bitline pair of BL and BL* are driven with and
towards a second
voltage level, which in the present example can be a positive voltage such as
VDD. This can
be done with additional circuits connected to bitlines BL and BL*, however to
minimize
memory array area overhead, the sense amplifier 2008 can be used to drive the
bitlines.
More specifically, if the circuit of sense amplifier circuit 2008 has the
configuration of sense
amplifier 1014 shown in Figure 21, then the positive voltage of H_EN can be
provided to the
p-channel transistors 1028 and 1030 while L_EN is at VSS. In otherwords, sense
amplifier
circuit 2008 only needs to be turned on to initiate driving of the bitline
pair towards the
second voltage H_EN. Any difference in the capacitance level of BL relative to
BL* will cause
a different rate in the voltage increase on BL relative to BL*. Then at 2206
the bitline pair is
sensed by sense amplifier 2008. In the present example, if the cell being
tested is connected
to BL, then BL will rise at a lower rate than BL* due to the extra capacitance
it adds to BL.
This can be sensed to provide a positive determination that the cell is
connected to BL and
that an anti-fuse device is present. Otherwise, if BL rises at a faster rate
than BL*, this
condition can be sensed to provide a positive determination that the cell
under test is missing
a connection to BL because BL* would have more capacitance added to it than
BL. It is
noted that the sensing scheme is similar to the one previously described in
Figure 22b where
additional capacitance is added to the same bitline (also referred to as a
selected bitline) as
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CA 02807739 2013-03-01
the memory cell being accessed. For the present testing embodiment, the
sensing scheme of
Figure 22B is modified in that the test cells are always connected to the
unselected bitline.
[00155] The Capacitive Load Test embodiment of Figure 31 can be used with
memory
array 2100 of Figure 30, where the only difference is that there is no VCP to
keep at the VSS
level. In Figure 31 by example, if the cell being tested is connected WLn-1
then the test cell
to be used is test cell 2118. Accordingly, if the cell being tested is
connected to BL, BL will
rise to the positive voltage level at a rate that is slower than BL*, which
can be sensed
according to the previously described sensing embodiments. Otherwise, BL will
rise to the
positive voltage of the sense amplifier at a rate that is faster than BL* to
provide a positive
determination that the cell being tested is missing a connection to BL.
[00156] Figure 32 is a flow chart showing an alternate method of testing
for the
presence of a bitline connection to an anti-fuse cell. This method is similar
to the method of
Figure 31, and can be executed for both the two transistor anti-fuse memory
array 2000 of
Figure 29 and the single transistor anti-fuse memory array 2100 of Figure 30,
except that no
test cells are used. This method is now described with reference to memory
array 2000 of
Figure 29 by example. The method starts at 2300 by precharging a bitline pair
BL and BL* to
a first voltage level, such as VSS for example. At 2302, a normal cell to be
tested is activated
by driving its wordline to a test voltage Vtest that is greater than Vread
used for normal read
operations. For example, WLn-1 is driven to Vtest and VCPn-1 is maintained at
VSS.
However, no cells connected to BL* are activated in this test embodiment. At
this time, a
small reference capacitance can be added to BL* that is selected to be less
than the
capacitance of a normal memory cell.
[00157] At 2304, the bitline pair of BL and BL* are driven with and
towards a second
voltage level, which in the present example can done by activating the sense
amplifier 2008
which applies a positive voltage H_EN to the bitline pair. Any difference in
the capacitance
level of BL relative to BL* will cause a different rate in the voltage
increase on BL relative to
BL*. Then at 2306 the bitline pair is sensed by sense amplifier 2008. In the
present example,
if the cell being tested is connected to BL, then BL will rise at a lower rate
than BL* due to the
extra capacitance added by the memory cell. This can be sensed to provide a
positive
determination that the cell is connected to BL. Otherwise, BL will rise at a
higher rate than
BL*, which can be sensed to provide a positive determination that the cell
under test is
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CA 02807739 2013-09-09
missing a connection to BL. This test embodiment can also be executed on
memory array
2100 of Figure 30, where the only difference is that there is no VCP to keep
at the VSS level.
1[00158] Both the Capacitive Load Test embodiments of Figure 31 and
Figure 32 can
be summarized generically as follows. After the bitline pair is precharged to
a first voltage
level, an anti-fuse cell to be tested is activated and the rate at which its
BL rises to a second
voltage level is compared the other BL having a predetermined rate. This
predetermined rate
is set either by activating a test cell having no anti-fuse device, or by
adding a small
capacitance less than the capacitance of a normal memory cell. In either case,
the bitline pair
is sensed by a sense amplifier to determine.if the memory cell being tested
includes or omits
a connection to its respective bitline_
[00159] Figure 33 is a flow chart showing a WL to BL Capacitive
Coupling Test,
according to a present embodiment. An particular, this test validates the
presence of word
line or bitline contacts to the memory cell_ This test can be executed for
both the two
transistor anti-fuse memory array 2000 of Figure 29 and the single transistor
anti-fuse
memory array 2100 of Figure 30. This method is now described with reference to
memory
array 2000 of Figure 29 by example. The method starts at 2400 by precharging a
bitline pair
BL and BL* to a first voltage level, such as VSS for example. Following at
2402, a normal cell
to be tested and a test cell are simultaneously activated. In Figure 29, it is
assumed that the
cell connected to WLn-1 and VCPn-1 is the memory cell to be tested, and the
test cell 2028
connected to T_WL1 is the other cell to be used. For this test, activation
includes driving
WLn-1, VCPn-1 and T_WL1 to the read voltage Vread typically used during a read
operation.
If all connections to the bitline, word line, and cell plate voltage VCP of
the memory cell have
been properly formed, the word line and cell plate voltages will be
capacitively coupled to the
bitline. In this situation, the selected bitline BL will have a larger voltage
level than the
unselected bitline BL* which only has T WL1 capacitively coupled to it.
Accordingly, sense =
amplifier 2008 is activated and the voltage difference between BL and BL* is
sensed at 2406.
On the other hand, if the bitline or word line contact for the normal memory
cell is missing, or
the cell plate voltage is missing, BL will have a lower voltage than BL*.
[00160] The previously described tests of Figure 31, Figure 32, and
Figure 33 can be
summarized with a generic method as shown in Figure 34, as they all share
common steps.
The bitline pair consisting of a first bitline and a second bitline are
precharged to a first
voltage level at 2500. This first voltage level can be VSS for example. At
2502 a normal
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CA 02807739 2013-03-01
memory cell, such as a two-transistor anti-fuse memory cell or a single
transistor anti-fuse
memory cell connected to the first bitline, is activated. Examples of this
step have been
shown as steps 2202, 2302 and 2402 in the previous testing embodiments, which
include
driving the wordline, or wordline and VCP line to a read voltage or a voltage
higher than the
read voltage used during normal read operations. At 2504 a second voltage is
coupled to
both the first bitline and the second bitline. This second voltage can be a
positive voltage
provided to by the sense amplifier, by an additional voltage circuit, or by
the wordlineNCP
line. Examples of this step have been shown as steps 2204 and 2304 where the
sense
amplifier provides the second voltage, and step 2402 where the wordline or VCP
line
provides the second voltage via the anti-fuse device of the normal memory cell
and the test
cell.
[00161] Finally at 2506, a voltage characteristic of the first bitline is
compared to a
predetermined voltage characteristic of the second bitline, which acts as a
reference bitline,
after the second voltage is coupled to the first and second bitlines. This
voltage characteristic
of the first bitline can include a capacitance of the bitline as described for
the embodiments of
Figures 31 and 32 by example, or capacitive coupling of the bitline to the
wordline and/or
VCP line as described for the embodiment of Figure 33. Accordingly, the
predetermined
voltage characteristic of the second bitline corresponding to a capacitance of
the first bitline
can be provided by connecting the test cell or a reference capacitance to the
second bitline.
[00162] Accordingly, methods have been described for testing an
unprogrammed OTP
memory array without having to program any normal memory cells or test memory
cells.
[00163] Those skilled in the art will understand that the embodiments of
the invention
equally applies to all other bulk MOS, thin film and SOI technologies
including DRAM,
EPROM, EEPROM and Flash, using either Si02 or other gate dielectrics.
Furthermore,
persons of skill in the art can easily adopt the previously described p-
channel devices to n-
channel devices, either using isolated p-well and negative bias, or utilizing
positive voltages
only.
[00164] The anti-fuse structures of present invention can be utilized in
all one time
programmable applications, including RF-ID tags. RF-ID tagging applications
are gaining
more acceptance in the industry, particularly in sales, security, transport,
logistics, and
military applications for example. The simplicity and full CMOS compatibility
of the presently
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CA 02807739 2013-03-01
described anti-fuse transistor invention allows for application of the RF-ID
tag concept to
integrated circuit manufacturing and testing process. Therefore, IC
manufacturing
productivity can be increased by utilizing the split-channel anti-fuse tag in
combination with
an RF communication interface on every wafer and/or every die on the wafer
allowing for
contact-less programming and reading chip specific or wafer specific
information during IC
manufacturing and packaging, as well as during printed circuit board assembly.
[00165] The
above-described embodiments of the present invention are intended to be
examples only. Alterations, modifications and variations may be effected to
the particular
embodiments by those of skill in the art without departing from the scope of
the invention,
which is defined solely by the claims appended hereto.
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