Note: Descriptions are shown in the official language in which they were submitted.
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ADAPTIVE AUDIO CODEC SYSTEM, METHOD, APPARATUS AND MEDIUM
CROSS-REFERENCE TO RELATED APPLICATIONS
This application for patent claims priority to, and incorporates herein by
reference,
U.S. Patent Application Serial No. 15/151.109, U.S. Patent Application Serial
No.
15/151,200, U.S. Patent Application Serial No. 15/151,211, and U.S. Patent
Application
Serial No. 15/151,220, all entitled Adaptive Audio Codec System, Method and
Article and all
filed on 5/10/2016, with the United States Patent and Trademark Office.
TECHNICAL FIELD
The description relates to systems, methods and articles to encode and decode
audio
signals.
BACKGROUND
Differential pulse code modulation (DPCM) may be used to reduce the noise
level or
the bit rate of an audio signal. A difference between an input audio signal
and a predictive
signal may be quantized to produce an output encoded data stream of a reduced
energy. The
predictive signal of an encoder may be generated using a decoder including an
inverse
quantizer and a prediction circuit. Adaptive differential pulse code
modulation (ADPCM)
varies a size of a quantization step of the quantizer (and inverse quantizer)
to increase the
efficiency in view of a varying dynamic range of an input signal.
BRIEF SUMMARY
In an embodiment, an apparatus comprises: a low-pass filter having determined
filter
coefficients and configured to filter an input signal. an encoder configured
to generate a
quantized signal based on a difference signal and including: an adaptive
quantizer. and a
decoder configured to generate a feedback signal and having an inverse
quantizer and a
predictor circuit, the predictor circuit having determined control parameters
based on a
frequency response of the low-pass filter. In an embodiment, the determined
filter
coefficients of the low-pass filter are fixed filter coefficients of the low-
pass filter, the
predictor circuit comprises a finite impulse response (FIR) filter and the
determined control
parameters of the predictor circuit comprise fixed filter coefficients of the
FIR filter. In an
embodiment, the apparatus comprises: an adaptive noise shaping filter coupled
between the
low-pass filter and the encoder, the adaptive noise shaping filter being
configured to flatten
signals within a frequency spectrum corresponding to a frequency spectrum of
the low-pass
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filter. In an embodiment, the adaptive noise shaping filter is configured to
not flatten
frequencies above an edge frequency of the low-pass filter. hi an embodiment,
the edge
frequency is 25 kHz. In an embodiment, the adaptive noise shaping filter
generates a signal
indicative of filter coefficients of the adaptive noise shaping filter, the
signal indicative of
filter coefficients of the adaptive noise shaping filter being included in a
bit stream output by
the encoder. In an embodiment, the encoder includes coding circuitry
configured to generate
code words based on quantized signal words generated by the adaptive
quantizer. In an
embodiment, the coding circuitry is configured to generate an escape code in
response to at
least one of: a quantized signal word not being associated with a
corresponding coding code
word: an end of a signal channel of a signal to be encode& and an end of the
signal to be
encoded. In an embodiment, the coding circuitry is configured to use Huffman
coding to
generate the code words. In an embodiment, the adaptive quantizer is a
variable rate
quantizer. In an embodiment, a step size and bit rate of the quantized signals
generated by the
adaptive quantizer are variable. In an embodiment, the adaptive quantizer is
configured to
control a step size according to:
dn+1 = !kin M(CniLfactor),
where co is a current quantized signal word, do corresponds to a current step
size in a log
factor domain, L i .S a loading
factor, m(co/Lfactor) õS i a log multiplier selected based on the current
quantized signal co and the loading factor L factor. 13 is a leakage
coefficient, and don
corresponds to a step size in the log domain to be applied to a next quantized
signal word
Cn+ 1. In an embodiment, the adaptive quantizer is configured to control a
step size according
to:
= max(pdo + m(co/L factor), ¨min),
where cn is a current quantized signal word, tin corresponds to a current step
size in a log
domain, Lrocior is a loading factor, m(co/Lrocior) is a log multiplier
selected based on the current
quantized signal co and the loading factor L factor, 13 is a leakage
coefficient, door] is a threshold
step size in the log domain, and do-n corresponds to a step size in the log
domain to be applied
to a next quantized signal word con.
In an embodiment, a method comprises: filtering an input signal, the filtering
including using a low-pass filter having determined filter coefficients: and
encoding the
filtered input signal using a feedback loop, the encoding including:
generating a quantized
signal based on a difference signal using an adaptive quantizer; generating a
feedback signal
based on the quantized signal using an inverse quantizer and a predictor
circuit having
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determined control parameters based on a frequency response of the low-pass
filter: and
generating the difference signal based on the feedback signal and the filtered
input signal. In
an embodiment, the determined filter coefficients of the low-pass filter are
fixed filter
coefficients of the low-pass filter, the predictor circuit comprises a finite
impulse response
(FIR) filter and the determined control parameters of the predictor circuit
comprise fixed
filter coefficients of the FIR filter. In an embodiment, the filtering
includes using an adaptive
noise shaping filter to filter a signal output by the low-pass filter, the
adaptive noise shaping
filter flattening signals within a frequency spectrum corresponding to a
frequency spectrum
of the low-pass filter. In an embodiment, the method comprises: generating a
signal
indicative of filter coefficients of the adaptive noise shaping filter and
including the signal
indicative of filter coefficients of the adaptive noise shaping filter in an
encoded bit stream. In
an embodiment, the method comprises: generating code words based on quantized
signal
words generated by the adaptive quantizer. In an embodiment, the method
comprises:
generating an escape code in response to at least one of: a quantized signal
word not being
associated with a corresponding coding code word: an end of a signal channel
of a signal to
be encoded: and an end of the signal to be encoded. In an embodiment, the
method
comprises: controlling a step size of the adaptive quantizer according to:
do+i = max(fido + m(coil factor), ¨ d min),
where co is a current quantized signal word, do corresponds to a current step
size in a log
factor .S factor, .S domain. L
i a loading factor, m(co/L i a log multiplier selected based on the current
quantized signal co and the loading factor Lfactor, ri is a leakage
coefficient, dmin is a threshold
step size in the log domain, and dill corresponds to a step size in the log
domain to be applied
to a next quantized signal word co-l-1.
In an embodiment, a non-transitory computer-readable medium's contents
configure
signal processing circuitry to perform a method, the method comprising:
filtering an input
signal, the filtering including low -pass filtering using determined filter
coefficients: and
encoding the filtered input signal using feedback. the encoding including:
generating a
quantized signal based on a difference signal: generating a prediction signal
based on the
quantized signal using determined control parameters based on a frequency
response of the
low-pass filtering: and generating the difference signal based on the
prediction signal and the
input signal. In an embodiment, the determined filter coefficients of the low-
pass filtering are
fixed filter coefficients of a low-pass filter, the generating the predictor
signal comprises
using a finite impulse response (FIR) filter and the determined control
parameters comprise
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fixed filter coefficients of the FIR filter. In an embodiment, the filtering
includes adaptive
noise shaping to flatten signals within a frequency spectrum corresponding to
a frequency
spectrum of the low-pass filter. In an embodiment, the method comprises:
controlling a step
size of the generating of the quantized signal according to:
dn+i = max ( [kin + m(crt/L factor), ¨min),
where cn is a current quantized signal word. di, corresponds to a current step
size in a log
domain, Leacior is a loading factor, m(cnILfactor) .S i a log multiplier
selected based on the current
quantized signal cn and the loading factor Lfactor, [3 is C.Inin a
leakage coefficient, / i .S a threshold
step size in the log domain, and cin+i corresponds to a step size in the log
domain to be applied
to a next quantized signal word cn 1.
In an embodiment, a system comprises: an encoder, including: a low-pass filter
having determined filter coefficients and configured to filter an input
signal: an adaptive
quantizer configured to generate a quantized signal based on a difference
signal: an inverse
quantizer: and a predictor circuit, the inverse quantizer being coupled
between the adaptive
quantizer and the predictor circuit with the predictor circuit having
determined control
parameters based on a frequency response of the low-pass filter: and a decoder
configured to
decode signals encoded by the encoder. In an embodiment, the determined filter
coefficients
of the low-pass filter are fixed filter coefficients of the low-pass filter,
the predictor circuit
comprises a finite impulse response (FIR) filter and the determined control
parameters of the
predictor circuit comprise fixed filter coefficients of the FIR filter. In an
embodiment, the
system comprises: an adaptive noise shaping filter coupled between the low-
pass filter and
the adaptive quantizer, the adaptive noise shaping filter being configured to
flatten signals
within a frequency spectrum corresponding to a frequency spectrum of the low-
pass filter. In
an embodiment, the adaptive noise shaping filter generates a signal indicative
of filter
coefficients of the adaptive noise shaping filter, the signal indicative of
filter coefficients of
the adaptive noise shaping filter being included in a bit stream output by the
encoder to the
decoder. In an embodiment, the encoder includes coding circuitry configured to
generate
code words based on quantized signal words generated by the adaptive quantizer
and the
decoder includes decoding circuitry configured to generate quantized signal
words based on
code words generated by the coding circuitry. In an embodiment, the coding
circuitry and the
decoding circuitry are configured to use escape coding.
In an embodiment, a system comprises: an input filter having determined
control
parameters and configured to limit a bandwidth of an input signal to less than
seventy-five
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percent of the available bandwidth based on a sampling frequency of the input
signal; an
encoder configured to generate quantized signals based on a difference signal
and including:
an adaptive quantizer; and feedback circuitry configured to generate feedback
signals and
having an inverse quantizer and a predictor circuit, the predictor circuit
having determined
control parameters based on a frequency response of the input filter. In an
embodiment, the
system comprises: a decoder configured to decode signals encoded by the
encoder. In an
embodiment, the input filter is a low-pass filter, the determined control
parameters of the
low-pass filter are fixed filter coefficients of the low-pass filter, the
predictor circuit
comprises a finite impulse response (FIR) filter and the determined control
parameters of the
predictor circuit comprise fixed filter coefficients of the FIR filter. In an
embodiment,
wherein the input filter is a band-pass filter, the determined control
parameters of the band-
pass filter are fixed filter coefficients of the band-pass filter, the
predictor circuit comprises a
finite impulse response (FIR) filter and the determined control parameters of
the predictor
circuit comprise fixed filter coefficients of the FIR filter.
In an embodiment, a system comprises: means for low-pass filtering an input
signal
using determined filtering parameters: means for generating a quantized signal
based on a
difference signal; means for generating a prediction signal based on the
quantized signal
using determined control parameters based on a frequency response of the means
for low -
pass filtering; and means for generating the difference signal. In an
embodiment, the system
comprises: means for decoding coded signals. In an embodiment, the means for
low-pass
filtering comprises a low-pass filter having fixed filter coefficients and the
means for
predicting comprises a finite impulse response (FIR) filter having fixed
filter coefficients
based on the filter coefficients of the low-pass filter.
BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 is a functional block diagram of an embodiment of an ADPCM encoder.
Figure 2 is a functional block diagram of an embodiment of an ADPCM decoder.
Figure 3 is a functional block diagram of an embodiment of a quantizer step
size
control circuit.
Figure 4 is a functional block diagram of an embodiment of an ADPCM encoder.
Figure 5 illustrates an example frequency response of an embodiment of a low
pass
filter.
Figure 6 illustrates an embodiment of a method of controlling changes in
adaptive
quantizer step sizes.
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Figure 7 is a functional block diagram of an embodiment of an ADPCM decoder.
Figure 8 is a functional block diagram of an embodiment of a quantizer step
size and
bit rate control circuit.
Figure 9 illustrates an embodiment of a method of generating code words and
controlling changes in adaptive quantizer step sizes.
Figure 10 illustrates an embodiment of a method of generating a quantized
signal
value from a code word.
DETAILED DESCRIPTION
In the following description, certain details are set forth in order to
provide a thorough
understanding of various embodiments of devices, systems, methods and
articles. However,
one of skill in the art NN ill understand that other embodiments may be
practiced without these
details. In other instances, well known structures and methods associated
with, for example,
finite impulse response filters, encoders, decoders, audio and digital signal
processing
circuitry, etc., such as transistors, multipliers, integrated circuits, etc.,
have not been shown or
described in detail in some figures to avoid unnecessarily obscuring
descriptions of the
embodiments.
Unless the context requires otherwise, throughout the specification and claims
which
follow, the word -comprise- and variations thereof, such as "comprising,- and
"comprises,-
are to be construed in an open, inclusive sense, that is, as 'including, but
not limited to.-
Reference throughout this specification to -one embodiment,- or -an
embodiment"
means that a particular feature, structure or characteristic described in
connection with the
embodiment is included in at least one embodiment. Thus, the appearances of
the phrases "in
one embodiment,- or -in an embodiment- in various places throughout this
specification are
not necessarily referring to the same embodiment, or to all embodiments.
Furthermore, the
particular features, structures, or characteristics may be combined in any
suitable manner in
one or more embodiments to obtain further embodiments.
The headings are provided for convenience only. and do not interpret the scope
or
meaning of this disclosure.
The sizes and relative positions of elements in the drawings are not
necessarily drawn
to scale. For example, the shapes of various elements and angles are not drawn
to scale, and
some of these elements are enlarged and positioned to improve drawing
legibility. Further,
the particular shapes of the elements as drawn are not necessarily intended to
convey any
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information regarding the actual shape of particular elements, and have been
selected solely
for ease of recognition in the drawings.
Figure 1 is a functional block diagram of an embodiment of audio signal
encoder 100
which may employ adaptive differential pulse-code modulation (ADPCM). As
illustrated in
Figure 1, the encoder 100 has an adder circuit 110, an adaptive quantizer
circuit 120, a
decoder circuit 130 including an inverse quantizer circuit 134 and a predictor
circuit 138, a
quantizer step size control circuit 140. and an optional coder circuit 150.
In operation of an embodiment, an analog input audio signal to be encoded is
received
at a positive input 112 of the adder 110 of the encoder 100. A negative input
114 of the adder
110 receives a prediction signal generated by the decoder 130 as a feedback
signal. The adder
110 generates a difference signal which is provided to the adaptive quantizer
circuit 120. The
adaptive quantizer circuit 120 may be an analog to digital converter which
samples the
received difference signal and generates an output signal representing the
difference signal as
a series of quantized signals representing different signal levels. For
example, 8-bit words
may be used to represent 256 different signal levels (e.g., 256 different
steps having a
uniform step size); 4 bits words may be used to represent 16 different signal
levels; etc.
Optionally, coding, such as Huffman coding and/or arithmetic coding, may be
employed on
the quantized signal in an embodiment, by coding circuit 150, generating a
coded signal
output. The quantized signal output by the adaptive quantizer circuit 120 (or
of the optional
coder 150 when a coder is employed) is the output quantized signal or code
words of the
encoder 100. The quantizer step size control circuit 140 generates control
signals to control a
size of the quantization steps employed by the quantizer 120 (and the inverse
quantizer 134),
which max' be varied to facilitate efficient transmission, storage, etc., in
view of an input
audio signal having a varying dynamic range.
The inverse quantizer 134 of the decoder 130 generates a signal, such as an
analog
signal, based on the quantized signal output by the adaptive 25 quantizer and
the current step
size control signal set by the quantizer step size control circuit 140. The
predictor circuit 138
may generate the prediction signal based on the output signal of the inverse
quantizer 134 and
historical data, such as recent quantized signal values and recent prediction
signal values.
One or more filters and one or more feedback loops may be employed by the
predictor circuit
138.
As illustrated, the encoder 100 of Figure 1 comprises one or more processors
or
processor cores P. one or more memories M. and discrete circuitry DC, which
may be used
alone or in various combinations to implement the functionality of the encoder
100. In
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operation, an embodiment of the encoder 100 generates quantized and,
optionally, coded data
from an input analog audio signal. In operation of an embodiment, a digital
audio signal to be
encoded (e.g., to a reduced bitstream, may be received at the positive input
112 instead of an
analog signal (e.g, an 8-bit digital audio signal may be encoded as a 4-bit
digital audio
signal).
Although the components of the encoder 100 of Figure 1 are illustrated as
separate
components, the various components may be combined (e.g.. the quantizer step
size control
circuit 140 may be integrated into the adaptive quantizer 120 in some
embodiments) or split
into additional components (e.g., the predictor circuit 138 may be split into
multiple predictor
circuits, may be split into separate components, such as filters, adders,
buffers, look-up
tables, etc.) and various combinations thereof
Figure 2 is a functional block diagram of an embodiment of an audio signal
decoder
200 which may employ adaptive differential pulse-code modulation (ADPCM). The
decoder
200 may be employed, for example. as the decoder 130 of Figure 1, as a
separate decoder to
decode a received encoded signal, etc. As illustrated in Figure 2. the decoder
200 has optional
decoding circuitry 250, an inverse quantizer circuit 234. a predictor circuit
238. an inverse
quantizer step size control circuit 240 and an adder 270.
In operation of an embodiment, a coded signal is received by the decoding
circuitry
250. which converts the coded signal into a quantized signal. The quantized
signal to be
decoded is provided to the inverse quantizer 234 and to the inverse quantizer
step size control
circuit 240. When the decoder 200 is employed in an encoder, such as the
encoder 100 of
Figure 1. the decoding circuitry 250 may typically be omitted and the same
step size control
circuit may be used to provide a step size control signal to the quantizer and
to the inverse
quantizer (see. Figure 1). The inverse quantizer 234 generates a signal, such
as an analog
signal, based on the quantized signal output by the decoding circuitry 250 (or
received from a
quantizer (see quantizer 120 of Figure 1)) and the current step size set by
the inverse
quantizer step size control circuit 240. The output of the inverse quantizer
234 is provided to
a first positive input of the adder 270. The output of the adder is provided
to the predictor
238. which as illustrated comprises a Finite Impulse Response (FIR) filter. An
output of the
FIR filter is provided to a second positive input of the adder 270.
When the decoder 200 is employed as a decoder to provide a decoded signal as
an
output, the output of the decoder 200 is the output of the adder 270. When the
decoder 200 is
employed in an encoder as part of a feedback loop, such as the decoder 130
used in the
encoder 100 of Figure 1, the output of the predictor circuit 238 provides the
prediction signal
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to the encoder (see the prediction signal provided to the negative input 114
of the adder 110
of Figure 1).
The inverse quantizer 234, the inverse quantizer step size control circuit 240
and the
predictor circuit 238 may typically operate in a similar manner to the
corresponding
components of an encoder, such as the encoder 100 of Figure 1. For example.
with reference
to Figures 1 and 2, having the corresponding components operate in a similar
manner in the
encoder 100 and the decoder 200 facilitates using the quantized signal to
generate the
prediction signal and to control the step size in both the encoder 100 and the
decoder 200,
without needing to exchange additional control signals between the encoder 100
and the
decoder 200.
As illustrated, the decoder 200 of Figure 2 comprises one or more processors
or
processor cores P. one or more memories M. and discrete circuitry DC, which
may be used
alone or in various combinations to implement the functionality of the decoder
200. Although
the components of the decoder 200 of Figure 2 are illustrated as separate
components, the
various components may be combined (e.g., the inverse quantizer step size
control circuit 240
may be integrated into the inverse quantizer 234 in some embodiments) or split
into
additional components (e.g., the predictor circuit 238 may be split into
separate components,
such as filters, adders, buffers, look-up tables, etc.) and various
combinations thereof.
Figure 3 is a functional block diagram of an embodiment of a quantizer step
size
control circuit 340, which may be employed, for example, in the embodiment of
the encoder
100 of Figure 1 as the quantizer step size control circuit 140, or in the
embodiment of the
decoder 200 of Figure 2 as the inverse quantizer step size control circuit
240. As illustrated,
the quantizer step size control circuit 340 comprises a log multiplier
selector 342 NA, hich
selects a log multiplier based on a current quantized signal word, as
illustrated a word output
by an adaptive quantizer 320. In some embodiments, the current quantized
signal word may
be included in a bit stream being decoded by a decoder (see Figure 2). The log
multiplier
selector 342 may select a log multiplier based on historical data, such as
previous quantized
signal words, and may comprise a look-up table LUT, which may be updatable,
for example,
based on historical data, in a update download, etc. The log multiplier
selector 342 may select
a log multiplier based on statistical probabilities based on current and
previous quantized
signal words. The quantizer step size control circuit 340 comprises an adder
344 which
receives at a first positive input the selected log multiplier, and provides
an output to a delay
circuit 346. The output of the delay circuit 346 is provided to a multiplier
348 and to an
exponential circuit 350. The multiplier 348 multiplies the output of the delay
circuit 346 by a
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scaling or leakage factor 13, which may typically be close to and less than 1,
and provides the
result to a second positive input of the adder 344. The leakage factor may
typically be a
constant, but may be variable in some embodiments, for example, based on the
previous step
size control signal or other historical data. The selection of a scaling
factor 13 as close to and
less than 1 facilitates reducing the impact of selection of an incorrect step
size, for example
due to a transmission error, as the introduced error will decay away.
The exponential circuit 350, in operation, generates a step-size control
signal based on
the output of the delay circuit 346. As illustrated, the step-size control
signal is provided to
the adaptive quantizer 320 and to an inverse quantizer 334. As illustrated,
the quantizer step
size control circuit 340 operates in a logarithmic manner, which may simplify
the
calculations. Some embodiments may operate in a linear manner, and may, for
example,
employ a multiplier instead of the adder 244, and an exponential circuit
instead of the
multiplier 246. The quantizer step-size control circuit 340 as illustrated
operates in a
logarithmic manner, and the step sizes selected based on the step size control
signal vary in
an exponential manner.
In an embodiment, the quantizer step size control circuit 340 may operate in
accordance with equation 1, below:
dni-i = fidn+ M(Cn) Equation 1
where cin is the step size in the log domain. m(cn) is the log multiplier
selected based on the
current quantized signal, and fi is the scaling factor or leakage coefficient.
As illustrated,
Figure 3 comprises one or more processors P. one or more memories M, and
discrete
circuitry DC, which may be used alone or in various combinations to implement
the
functionality of the quantizer step size control circuit 340.
Although the components of Figure 3 are illustrated as separate components,
the
various components may be combined (e.g., the adder 344 and the multiplier 348
may be
integrated into an arithmetic processor in some embodiments) or split into
additional
components, and various combinations thereof
Figure 4 is a functional block diagram of an audio signal encoder 400 which
may
employ adaptive differential pulse-code modulation (ADPCM). The audio signal
encoder 400
of an embodiment provides added bandwidth control, facilitates avoiding
quantizer overload,
and includes adaptive noise shaping. As illustrated in Figure 4, the encoder
400 has a low
pass filter 475, an adaptive noise shaping filter 480, an adder circuit 410, a
variable-rate
adaptive quantizer circuit 420, a decoder circuit 430 including an inverse
quantizer circuit
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434 and a predictor circuit 438. a quantizer step size and average bit rate
control circuit 440, a
coder 450 and bit stream assembler 485.
In operation of an embodiment, an analog input audio signal to be encoded is
received
at an input of an input filter, as illustrated the low pass filter 475. The
low pass filter 475
facilitates improving the signal to noise ratio. The low pass filter 475 may,
for example, be a
FIR filter having a 25 kHz edge and a 30 kHz stop band, which has been found
to provide
excellent results for data sampled at 88.2 or 96 kHz. Figure 5 illustrates an
example
frequency response of an embodiment of the low pass filter 475 applied to a
sampling rate of
96 kHz. Using a low-pass filter and a corresponding fixed predictor filter
employing control
parameters based on the control parameters of the input filter (e.g., the
predictor employing
filter coefficients based on the frequency response of the input filter)
facilitates obtaining a
substantial prediction gain for an input signal \hen a sufficiently high
sampling rate is
employed, which in turn facilitates obtaining a desired minimum signal to
noise ratio. In
testing, sampling rates below 48 kHz (e.g., 44.1 and 48 kHz) generally do not
provide a
sufficient improvement in the gain.
The output of the low pass filter 475 is provided to the adaptive noise
shaping filter
480. In some embodiments, the low pass filter 475 may be omitted, and the
signal to be
encoded may be input to the adaptive noise shaping filter 480 instead of to
the low pass filter
475. In some embodiments. the adaptive noise shaping filter 480 may be omitted
or
selectively bypassed. For example, the adaptive noise shaping filter 480 may
be omitted or
bypassed when high bit rate signal encoding is employed. In some embodiments,
a band pass
filter may be employed instead of a low pass filter, with correspond
adjustments to the
predictor filter. For example. an input filter (e.g.. a band pass filter)
having fixed control
parameters and configured to limit a bandwidth of an input signal to less than
seventy-five
percent of the available bandwidth based on the sampling frequency may be
employed in an
embodiment, and the corresponding decoder may include a predictor circuit
having fixed
control parameters based on a frequency response of the filter. Limiting the
bandwidth of the
input signal using the input filter and setting the control parameters of the
predictor circuit
based on a frequency response of the input filter facilitates obtaining a
substantial prediction
gain for an input signal when a sufficiently high sampling rate is employed,
which in turn
facilitates obtaining a desired minimum signal to noise ratio.
The adaptive noise shaping filter 480 may be, for example, a low-order all-
zero linear
prediction filter. Real (not complex) coefficients may be employed. In an
embodiment, the
adaptive noise shaping filter 480 is an all zero adaptive noise shaping filter
which flattens the
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spectrum of the signal received from the low pass filter 475, while
maintaining the overall
spectral slope and sufficient masking to maintain a transparent codec (e.g.,
the compression
artifacts are generally imperceptible). In a corresponding decoder (see
decoder 700 of Figure
7), an all-pole filter using the same coefficients may be used to restore the
original spectral
shape. In an embodiment, the adaptive noise shaping filter 480 preserves the
whiteness
criteria for the predictor circuit 438. For example, the low-order noise
shaping filter 480 may
be adjusted to not flatten signals over an edge frequency of a low-pass filter
(e.g. 25 kHz.
which may not exist in a signal filtered by a low pass filter 475). As noted
above, the missing
energy at high frequencies facilitates a higher prediction gain. Filters other
than linear
prediction filters may be employed as the noise shaping filters.
The adaptive noise shaping filter 480 provides a filtered output signal to a
positive
input 412 of the adder 410. In an embodiment, the adaptive noise shaping
filter 480 also
provides a signal including adaptive noise filter setting information and/or
synchronization
information, which may be used to communicate adaptive noise filter setting
and
synchronization information to a decoder, such as the decoder 700 of Figure 7,
which
includes a corresponding inverse noise shaping filter 780. The setting and
synchronization
information may be transmitted periodically, such as once for every 512 sample
block. In
some embodiments, the adaptive noise shaping filter control information may be
implicit in
the code words of the bit stream. For example, when the code words of the bit
stream indicate
an average bit rate above a threshold average bit rate is being employed, this
may also
indicate that adaptive noise shaping is being bypassed.
A negative input 414 of the adder 410 receives a prediction signal generated
by the
decoder 430 as a feedback signal. The adder 410 generates a difference signal
which is
provided to the variable rate adaptive quantizer circuit 420.
The variable rate adaptive quantizer circuit 420 generates an output signal
representing the difference signal as a series of quantization signals or
words. The size of the
quantization signals is not fixed, and the average length may be adjusted
using the output of a
multiplier table of a step size and average bit rate controller 440, as
discussed in more detail
below. The output of the variable rate adaptive quantizer circuit 420 is
provided to the step
size and average bit rate controller 440, the inverse quantizer 434 and the
coder 450.
The quantizer step and average bit rate control circuit 440 generates one or
more
control signals to control a size of the quantization steps. This implicitly
determines an
average length of the quantization signal employed by the quantizer 420 (and
the inverse
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quantizer 434). which may be varied by adjustment of the multiplier table to
facilitate
efficient coding in view of an input audio signal having a varying dynamic
range.
Figure 6 illustrates an embodiment of a method 600 of generating code words
and
controlling changes in step sizes and average bit rate that may be employed,
for example, by
the encoder 400 of Figure 4. For convenience, the method 600 will be described
with
reference to the encoder 400 of Figure 4. The method starts at 602 and
proceeds to 604. At
604, the variable rate adaptive quantizer 420 generates a current quantization
signal or word
based on the difference signal and the current quantization step size control
signal. This may
be done, for example. in accordance with equation 2, below:
cn -4(en/exp(dn))] Equation 2
where co is the current quantized signal, en is the error or difference
signal. and dn corresponds
to the current step size in the log domain.
The method proceeds from 604 to 606. At 606, the quantizer step size and
average bit
rate control circuit 440 generates one or more control signals to set the step
size for the next
quantization signal word. This may be done, for example, in accordance with
equation I.
above, or in accordance with equation 3 or 4, below:
d+i = + M(Crafactor) Equation 3
where cn is the current quantization signal, dr, corresponds to the current
step size and
responsively the bit length, Lfactor .s i a loading factor which is used to
control the average bit
length (and hence the average bit rate), m(c/Lfactor) .s i the log multiplier
selected based on the
current quantized signal and the loading factor. and (3 is the leakage
coefficient. In some
embodiments, a minimum step size drilla in the log domain may be set, as
follows:
fin I = MaX(I3fin M(Casactor), dmin) Equation 4
The loading factor L factor may be selected so as to maintain a desired
average bit rate.
The load factor may typically be between 0.5 and 16. In some embodiments. a
maximum step
size may be employed. Changing the log multiplier m(cn/Lractor) changes the
bit rate and step
size, and the values stored in the look-up-table of the log multiplier
selector (see Figure 8)
may be selected so as to cause the adaptive quantizer 420 and inverse
quantizer 434 to
implement the desired changes in the step size and bit rate. For example,
higher log
multipliers may indicate an increased step size and lower bit rate to the
quantizer 420 and
inverse quantizer 434. The look-up table may be indexed based on the result of
the current
quantization value cn divided by the loading factor Lfactor. Different lookup
tables may be
employed instead of or in addition to different loading factors in lieu of
Leacior. In an
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embodiment, values in a look-up-table may be selected such that the log
multiplier
monotonically increases as the current quantization value cn increases, and
the table of
multipliers may go from a negative value for small Cn to a positive value for
large cn.
The method 600 proceeds from 606 to 608. At 608 the encoder 400 determines
whether to continue encoding of a received signal. When it is determined at
608 to continue
encoding of a received signal, the method returns to 604 to process the next
quantized signal
NN, ord. When it is not determined at 608 to continue encoding of a received
signal, the method
proceeds to 610, where other processing may occur, such as generating an
escape code to
indicate the received signal has terminated, etc. The method proceeds from 610
to 612, where
the method 600 terminates.
Some embodiments of an encoder 400 may perform other acts not shown in Figure
6,
may not perform all of the acts shown in Figure 6. or may perform the acts of
Figure 6 in a
different order.
With reference to Figure 4, the inverse quantizer 434 of the decoder 430
generates a
signal, such as an analog signal, based on the quantized signal output cn by
the variable rate
adaptive quantizer 420 and the current step size dn. The predictor circuit 438
may generate
the prediction signal based on the output signal of the inverse quantizer 434
and historical
data, such as recent coded data and recent prediction values, as discussed in
more detail
below with reference to Figure 7. The predictor circuit 438 may employ a FIR
filter with
coefficients selected based on the frequency response of the low-pass filter
475, as discussed
in more detail below with reference to Figure 7. These coefficients may be
fixed, and may be
selected so as to facilitate maintaining a sufficient signal to noise ratio
for anticipated input
signal characteristics. Testing has shown using fixed coefficients for the FIR
filter in the
predictor circuit 438 based on the frequency response of the low-pass filter
475 resulted in a
significant improvement in the signal to noise ratio for signals at and above
64 kHz. For
example, attenuating the energy above 25 kHz in the low-pass filter 475 and
selecting fixed
coefficients of the FIR filter based on the frequency response of the low-pass
filter may result
in a prediction gain of 45 dB in an embodiment. Using an eight-bit quantizer
(see adaptive
quantizer 120 of Figure 1, which may be an eight-bit quantizer. a four-bit
quantizer. etc.),
may result in a signal to noise ratio comparable to encoding without using an
adaptive noise
shaping filter (see Figure 1), but without including frequencies above 25 kHz.
In an embodiment, the quantized signal output by the variable rate adaptive
quantizer
circuit 420 (or of the optional coder 450 when a coder is employed) is the
output quantized
signal of the encoder 400. Optionally, coding, such as Huffman coding and/or
arithmetic
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coding, may be employed on the quantized signal in an embodiment, by coding
circuit 450,
generating a coded signal output of the encoder 400. The coder 450 converts
quantized signal
words into code words, for example, using one or more look-up tables.
Quantized signal
words which are used less frequently may be assigned to larger code words, and
quantized
signal words which are used more frequently may be assigned to smaller code
words to
increase the efficiency of the coder 400.
The coder 450 optionally provides escape coding in an embodiment. For example.
for
a quantized value which is not included in the code book employed (e.g.. a
Huffman
codebook), an escape code may be sent instead of a code word from the code
book, with the
escape coding indicating how the quantized signal value or information will be
transmitted
(e.g, that the actual quantized signal is being transmitted, that the next
code word is the
quantized signal value instead of a code word. that a difference between a
maximum/minimum level is being transmitted, etc.). In another example. an
escape code may
indicate that a channel of an encoded signal is being discontinued or is not
present (e.g, only
one channel of a stereo signal is being encoded). In another example, an
escape code may
indicate an end of an encoded signal.
The bit stream assembler 485 receives the code words output by the coder 450
and the
adaptive noise shaping filter control/synchronization information output by
the adaptive noise
shaping filter 480 and assembles a bit stream for transmission to a decoder
and/or storage. In
some embodiments, data packets may be assembled by the bit stream assembler
485, such as
packets including a 512 sample block and adaptive noise shaping filter
control/synchroniza-
tion information for the sample block.
Figure 7 is a functional block diagram of an embodiment of an audio signal
decoder
700 which may employ adaptive differential pulse-code modulation (ADPCM). The
decoder
700 may be employed, for example, as the decoder 430 of Figure 4, as a
separate decoder to
decode a received encoded signal, etc. As illustrated in Figure 7, the decoder
700 has a bit
stream disassembler 785, optional code word decoding circuitry 750, an inverse
quantizer
circuit 734, a predictor circuit 738, an inverse quantizer step size and
average bit rate control
circuit 740, an adder 770, an inverse adaptive noise shaping filter 780 and a
low pass filter
775.
In operation of an embodiment, an assembled signal is received by the bit
stream
disassembier 785 and split into a coded signal component and an adaptive noise
shaping filter
control and synchronization signal component. The coded signal component is
provided to
the decoding circuitry 750, which converts the coded signal into a quantized
signal cn. Escape
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coding may be used in an embodiment, as discussed above with reference to the
coder 450 of
Figure 4. The quantized signal to be decoded is provided to the inverse
quantizer 734 and to
the inverse quantizer step size and average bit rate control circuit 740. When
the decoder 700
is employed in an encoder, such as the encoder 400 of Figure 4, the decoding
circuitry 750
may typically be omitted and the same step size and average bit rate control
circuit may be
used to provide a step size control signal to the quantizer and to the inverse
quantizer (see,
Figure 4).
The inverse quantizer 734 generates a signal, such as an analog signal, based
on the
quantized signal output by the decoding circuitry 750 (or received from a
quantizer (see
quantizer 420 of Figure 4)) and the current step size set by the inverse
quantizer step size and
average bit rate control circuit 740. The output of the inverse quantizer 734
is provided to a
first positive input of the adder 770. The output of the adder 770 is pros
ided to the predictor
738. which as illustrated comprises a Finite Impulse Response (FIR) filter. An
output of the
FIR filter is provided to a second positive input of the adder 770.
When the decoder 700 is employed as a decoder to provide a decoded signal as
an
output, the output of the decoder 700 is provided to an inverse filter, as
illustrated an inverse
adaptive noise shaping filter 780. The inverse adaptive noise shaping filter
780 may be, for
example, a low-order all pole linear prediction filter. In an embodiment, the
inverse adaptive
noise shaping filter 780 is an all-pole adaptive noise shaping Filter which
restores the
spectrum of the signal using the using the same coefficients used by a
corresponding adaptive
noise shaping filter of a corresponding encoder (e.g., the adaptive noise
shaping filter 480 of
Figure 4) as the coefficients of the all-pole filter. This information may be
conveyed in the
bitstream and provided to the inverse adaptive noise shaping filter 780 by the
disassembler
785. The setting and synchronization information may be provided periodically,
such as once
for every 512 sample block. In some embodiments, the inverse adaptive noise
shaping filter
control information may be implicit in the code words of the bit stream, for
example, as
discussed above with reference to Figure 4.
The output of the inverse adaptive noise shaping filter 780 is optionally
filtered by a
low-pass filter 775. This facilitates removing high-frequency energy restored
when the
original spectrum of the signal is restored by the inverse adaptive noise
shaping filter 780. In
an embodiment, the low-pass filter 775 of the decoder 700 may employ the same
coefficients
used by a corresponding low-pass filter of an encoder (e.g., the low-pass
filter 475 of Figure
4).
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When the decoder 700 is employed in an encoder as part of a feedback loop,
such as
the decoder 430 used in the encoder 400 of Figure 4, the output of the
predictor circuit 738
provides the predictiOn signal to the encoder (see the prediction signal
provided to the
negative input 414 of the adder 410 of Figure 4).
The inverse quantizer 734. the inverse quantizer step and average bit rate
control
circuit 740 and the predictor circuit 738 may typically operate in a similar
manner to the
corresponding components of an encoder, such as the encoder 400 of Figure 4.
For example,
NNi t h reference to Figures 4 and 7, having the corresponding components
operate in a similar
manner in the encoder 400 and the decoder 700 facilitates using the quantized
signal to
generate the prediction signal and to control the step size and average bit
rate in both the
encoder 400 and the decoder 700, without needing to exchange additional
control signals
bete en the encoder 400 and the decoder 700. For example, a system including
an
embodiment of the encoder 400 and an embodiment of the decoder 700 may operate
using
the same control parameters for the corresponding components (e.g., using the
same filter
coefficients).
As illustrated, the decoder 700 of Figure 7 comprises one or more processors
or
processor cores P. one or more memories M. and discrete circuitry DC, which
may be used
alone or in various combinations to implement the functionality of the decoder
700. Although
the components of the decoder 700 of Figure 7 are illustrated as separate
components, the
various components may be combined (e.g., the inverse quantizer step and
average rate
control circuit 740 may be integrated into the inverse quantizer 734 in some
embodiments) or
split into additional components (e.g., the predictor circuit 738 may be split
into separate
components, such as filters, adders, buffers, look-up tables_ etc.) and
various combinations
thereof.
Figure 8 is a functional block diagram of an embodiment of a quantizer step
size and
average rate control circuit 840, which may be employed, for example, in the
embodiment of
the encoder 400 of Figure 4 as the quantizer step size and average bit rate
control circuit 440,
or in the embodiment of the decoder 700 of Figure 7 as the inverse quantizer
step size and
average bit rate control circuit 740. As illustrated, the quantizer step size
and average bit rate
control circuit 840 comprises a multiplier 852, which receives a current
quantized signal
word cn and an inverse of a loading factor L facto r, and a log multiplier
selector 842 which
selects a log multiplier based on the current quantized signal word and the
loading factor. As
illustrated the current quantized signal word is a word output by variable
rate adaptive
quantizer 820. In some embodiments, the current quantized signal word may be
included in a
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bit stream being decoded by a decoder (see Figure 7). The log multiplier
selector 842 may
select a log multiplier based on historical data, such as previous quantized
signal words, and
may comprise a look-up table LUT, which may be updatable, for example, based
on
historical data, in a update download, etc. The log multiplier selector 842
may select a log
multiplier based on statistical probabilities based on current and previous
quantized signal
words. The quantized step size and average bit rate control circuit 840
comprises an adder
844 which receives at a first positive input the selected log multiplier, and
provides an output
to a delay circuit 846. The output of the delay circuit 846 is provided to a
multiplier 848 and
to an exponential circuit 850. The multiplier 848 multiplies the output of the
delay circuit 846
by a scaling or leakage factor [3, which may typically be close to and less
than 1, and provides
the result to a second positive input of the adder 844. The leakage factor may
typically be a
constant, but may be variable in some embodiments, for example, based on the
previous step
size control signal or other historical data. The selection of a scaling
factor [3 as close to and
less than 1 facilitates reducing the impact of selection of an incorrect step
size, for example
due to a transmission error, as the introduced error will decay away.
The exponential circuit 850, in operation, generates a step-size control
signal based on
the output of the delay circuit 846. As illustrated, the step-size and average
bit rate control
signal is provided to a variable rate adaptive quantizer 820 and to an inverse
quantizer 834.
As illustrated. the quantizer step size and average bit rate control circuit
840 operates in a
logarithmic manner, which may simplify the calculations. Some embodiments may
operate in
a linear manner, and may, for example, employ a multiplier instead of the
adder 844, and an
exponential circuit instead of the multiplier 846, etc. The step-size and
average bit rate
control circuit as illustrated operates in a logarithmic manner, and the step
sizes selected
based on the step size control signal vary in an exponential manner. In an
embodiment, the
quantizer step size and average bit rate control circuit 840 may operate in
accordance with
equations 3 or equation 4, and select log multiplier values to populate the
look-up tables as
discussed above in more detail with reference to Figures 4 and 6.
As illustrated, Figure 8 comprises one or more processors P, one or more
memories
M. and discrete circuitry DC, which may be used alone or in various
combinations to
implement the functionality of the quantizer step size and average bit rate
control circuit 840.
The illustrated components, such as adders, multiplier, etc., may be
implemented in various
ways, such as, using discrete circuitry, executing instructions stored in a
memory, using look-
up tables, etc., and various combinations thereof.
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Figure 9 illustrates an embodiment of a method 900 of generating code NN ords
from an
audio signal and controlling changes in quantizer step sizes and average bit
rate that may be
employed, for example, by the encoder 400 of Figure 4 when escape coding is
employed. For
convenience, the method 900 will be described with reference to the encoder
400 of Figure 4.
The method starts at 902 and proceeds to 904. At 904. the encoder 400 collects
a block of
audio samples and proceeds to 906. At 906, the encoder 400 processes a sample
of each
channel. Parallel processing of the samples of the channels may be employed.
At 906a, the adaptive quantizer 420 determines whether the channel has an
audio
sample to be processed. If the channel has an audio sample, the method 900
proceeds from
906a to 908. At 908 the coder 450 determines whether a quantized sample has a
corresponding symbol in a code book, as illustrated. a Huffman code book. When
it is
determined that the quantized sample has a corresponding symbol in the code
book, the
method proceeds from 908 to 910. At 910, the coder 450 writes the
corresponding symbol
into the bitstream. The method 900 proceeds from 910 to 914.
When it is not determined at 908 that the quantized sample has a corresponding
symbol in the code book, the method 900 proceeds from 908 to 912. At 912, the
coder writes
an embed escape code and a quantized sample value into the bitstream. as
illustrated an
embed escape code followed by a 16 bit quantized sample value. Other methods
of
transmitting a quantized sample value without a corresponding code word in the
code book
may be employed, as discussed in more detail above. The method proceeds from
912 to 914.
At 914, the step-size and average bit rate control circuit 440 updates the
step size
control signal for the corresponding channel, as discussed in more detail
above. For example,
the equations 1, 3 and 4 may be employed. The method 900 proceeds from 914 to
906 to
process the next sample for the channel.
At 906b, the adaptive quantizer determines whether the channel had audio data.
but
has no more samples in the block to be processed. For example, a channel may
have ended
prematurely. When it is determined that the channel has no more samples in the
block, the
method 900 proceeds from 906b to 916. At 916. the coder 450 writes an end-of-
channel
escape code into the bitstream and processing of the channel in the current
block terminates.
The method 900 proceeds from 916 to 906.
At 906c, the encoder 400 determines whether all the audio data in the block
for all of
the channels has been processed. When it is determined at 906c that all the
audio data in the
block has been processed, the method 900 proceeds from 906c to 918. At 918,
the encoder
400 determines whether there is more data to start a new block. When it is
determined at 918
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that there is more data to start a new block, the method 900 proceeds from 918
to 904, where
the next block of audio samples is processed. When it is not determined at 918
that there is
data to start a new block, the method proceeds to 920. At 920, the coder 450
writes an end of
stream escape code into the bit stream. The method proceeds from 920 to 930,
where
processing of the audio signal terminates.
Some embodiments of an encoder 400 may perform other acts not shown in Figure
9,
may not perform all of the acts shown in Figure 9, or may perform the acts of
Figure 9 in a
different order.
Figure 10 illustrates an embodiment of a method 1000 of generating a quantized
signal value from a code word that may be employed. for example. by the
decoder 700 of
Figure 7 when escape coding is employed. The method 1000 may process code
words for
multiple channels of a signal in parallel. For convenience, the method 1000
will be described
NN-ith reference to the decoder 700 of Figure 7. The method starts at 1002 and
proceeds to
1004. At 1004, the decoding circuitry 750 receives a code word (or code words
when
multiple channels are being processed in parallel) and proceeds to 1006.
At 1006, the decoding circuitry 750 determines whether the code word (symbol)
has a
corresponding quantized sample value in a code book, such as a Huffman code
book. When it
is determined that the code word (symbol) has a corresponding quantized sample
value in a
code book, the method 1000 proceeds from 1006 to 1008, where the corresponding
quantized
sample value is output by the decoding circuitry 750 as the current quantized
signal value co.
The method 1000 proceeds from 1008 to 1004 to process the next code word of
the channel
(and code words of other channels of the coded signal). When it is not
determined at 1006
that the code word (symbol) has a corresponding quantized sample value in a
code book, the
method 1000 proceeds from 1006 to 1010.
At 1010, the decoding circuitry 750 determines whether the code word is an
embed
escape code. When it is deteimined at 1010 that the code word is an embed
escape code, the
method 1000 proceeds from 1010 to 1012. where the next code word of the
channel is output
by the decoding circuitry 750 as the current quantized signal value cn. The
method 1000
proceeds from 1012 to 1004 to process the next code word of the channel (and
code words of
other channels of the coded signal). When it is not determined at 1010 that
the code word is
an embed escape code, the method 1000 proceeds from 1010 to 1014.
At 1014, the decoding circuitry 750 determines whether the code word is an end
of
channel escape code. When it is determined at 1014 that the code word is an
end of channel
escape code, the method 1000 proceeds from 1014 to 1016, where processing of
the signal
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channel is terminated. The method 1000 proceeds from 1016 to 1004 to process
the next code
word of the remaining channels of the signal. When it is not determined at
1014 that the code
word is an end of channel escape code, the method 1000 proceeds from 1014 to
1018.
At 1018, the decoding circuitry 750 determines whether the code word is an end
of
signal escape code. When it is determined at 1018 that the code word is an end
of signal
escape code, the method 1000 proceeds from 1018 to 1020, where processing of
the signal is
terminated. The method 1000 proceeds from 1020 to 1022 where the method 1000
terminates. When it is not determined at 1018 that the code word is an end of
signal escape
code, the method 1000 proceeds from 1018 to 1004 to process the next code word
(or block)
of the channel (and code words of other channels of the coded signal).
Some embodiments of a decoder 700 may perform other acts not shown in Figure
10,
may not perform all of the acts shown in Figure 10, or may perform the acts of
Figure 10 in a
different order.
Some embodiments may take the form of or comprise computer program products.
For example, according to one embodiment there is provided a computer readable
medium
comprising a computer program adapted to perform one or more of the methods or
functions
described above. The medium may be a physical storage medium, such as for
example a
Read Only Memory (ROM) chip. or a disk such as a Digital Versatile Disk (DVD-
ROM),
Compact Disk (CD-ROM). a hard disk, a memory, a network, or a portable media
article to
be read by an appropriate drive or via an appropriate connection, including as
encoded in one
or more barcodes or other related codes stored on one or more such computer-
readable
mediums and being readable by an appropriate reader device.
Furthermore, in some embodiments, some or all of the methods and/or
functionality
may be implemented or provided in other manners, such as at least partially in
firmware
and/or hardware, including, but not limited to, one or more application-
specific integrated
circuits (ASICs), digital signal processors, discrete circuitry, logic gates,
standard integrated
circuits. controllers (e.g, by executing appropriate instructions, and
including
microcontrollers and/or embedded controllers), field-programmable gate arrays
(FPGAs),
complex programmable logic devices (CPLDs). etc., as well as devices that
employ RFID
technology, and various combinations thereof.
The various embodiments described above can be combined to provide further
embodiments. Aspects of the embodiments can be modified, if necessary to
employ concepts
of the various patents, applications and publications to provide yet further
embodiments.
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These and other changes can be made to the embodiments in light of the above-
detailed description. In general. in the following claims, the terms used
should not be
construed to limit the claims to the specific embodiments disclosed in the
specification and
the claims, but should be construed to include all possible embodiments along
with the full
scope of equivalents to which such claims are entitled. Accordingly. the
claims are not
limited by the disclosure.
22
