1
RECEIVING APPARATUS USING LOW-DENSITY PARITY CHECK CODE AND
BIT DEINTERLEAVING AND RECEIVING METHOD THEREOF
This application is a divisional of Canadian patent application No. 2940011
filed on February 23,
2015.
[Technical Field]
Apparatuses and methods consistent with exemplary embodiments relate to a
transmitting
apparatus and an interleaving method thereof, and more particularly, to a
transmitting apparatus
which processes and transmits data, and an interleaving method thereof.
[Background Art]
In the 21st century information-oriented society, broadcasting communication
services are
moving into the era of digitalization, multi-channel, wideband, and high
quality. In particular, as
high quality digital televisions, portable multimedia players and portable
broadcasting equipment
are increasingly used in recent years, there is an increasing demand for
methods for supporting
various receiving methods of digital broadcasting services.
In order to meet such demand, standard groups are establishing various
standards and are
providing a variety of services to satisfy users' needs. Therefore, there is a
need for a method for
providing improved services to users with high decoding and receiving
performance.
[Disclosure]
[Technical Problem]
Exemplary embodiments of the inventive concept may overcome the above
disadvantages and
other disadvantages not described above. However, it is understood that the
exemplary embodiment
are not required to overcome the disadvantages described above, and may not
overcome any of the
problems described above.
The exemplary embodiments provide a transmitting apparatus which can map a bit
included in a
predetermined bit group from among a plurality of bit groups of a low density
parity check (LDPC)
codeword onto a predetermined bit of a modulation symbol, and transmit the
bit, and an interleaving
method thereof.
[Technical Solution]
According to an aspect of an exemplary embodiment, there is provided a
transmitting apparatus
including: an encoder configured to generate an LDPC codeword by LDPC encoding
Date Recue/Date Received 2021-10-07
2
based on a parity check matrix; an interleaver configured to interleave the
LDPC codeword; and
a modulator configured to map the interleaved LDPC codeword onto a modulation
symbol,
wherein the modulator is further configured to map a bit included in a
predetermined bit group
from among a plurality of bit groups constituting the LDPC codeword onto a
predetermined bit
of the modulation symbol.
Each of the plurality of bit groups may be formed of M number of bits. M may
be a common
divisor of Nicipc and KAN and may be determined to satisfy Qiripc=(Niapc-
Kicipc)/M. In this case,
Qjdpc may be a cyclic shift parameter value regarding columns in a column
group of an
information word submatrix of the parity check matrix, Nidpc may be a length
of the LDPC
codeword, and Kid may be a length of information word bits of the LDPC
codeword.
The interleaver may include: a parity interleaver configured to interleave
parity bits of the
LDPC codeword; a group interleaver configured to divide the parity-interleaved
LDPC
codeword by the plurality of bit groups and rearrange an order of the
plurality of bit groups in bit
group wise; and a block interleaver configured to interleave the plurality of
bit groups the order
of which is rearranged.
The group interleaver may be configured to rearrange the order of the
plurality of bit groups
in bit group wise by using the following equation:
= X,(1)(0 LC j <Ns,.,,,õ),
where Xj is a jth bit group before the plurality of bit groups are
interleaved, Yi is a jth bit group
after the plurality of bit groups are interleaved, Ngroup is a total number of
the plurality of bit
groups, and 7t(j) is a parameter indicating an interleaving order.
Here, 7t(j) may be determined based on at least one of a length of the LDPC
codeword, a
modulation method, and a code rate.
When the LDPC codeword has a length of 64800, the modulation method is 16-QAM,
and
the code rate is 6/15,71(j) may be defined as in table 11.
When the LDPC codeword has a length of 64800, the modulation method is 16-QAM,
and
the code rate is 10/15, 7t(j) may be defined as in table 14.
When the LDPC codeword has a length of 64800, the modulation method is 16-QAM,
and
the code rate is 12/15, 7t(j) may be defined as in table 15.
When the LDPC codeword has a length of 64800, the modulation method is 64-QAM,
and
the code rate is 6/15, 7r(j) may be defined as in table 17.
Date Recue/Date Received 2021-10-07
3
When the LDPC codeword has a length of 64800, the modulation method is 64-QAM,
and
the code rate is 8/15, n(j) may be defined as in table 18.
When the LDPC codeword has a length of 64800, the modulation method is 64-QAM,
and
the code rate is 12/15, n(j) may be defined as in table 21.
The block interleaver may be configured to interleave by writing the plurality
of bit groups in
each of a plurality of columns in bit group wise in a column direction, and
reading each row of
the plurality of columns in which the plurality of bit groups are written in
bit group wise in a row
direction,
The block interleaver may be configured to serially write, in the plurality of
columns, at least
some bit groups which are writable in the plurality of columns in bit group
wise from among the
plurality of bit groups, and then divide and write the other bit groups in an
area which remains
after the at least some bit groups are written in the plurality of columns in
bit group wise.
According to an aspect of another exemplary embodiment, there is provided an
interleaving
method of a transmitting apparatus, including: generating an LDPC codeword by
LDPC
encoding based on a parity check matrix; interleaving the LDPC codeword; and
mapping the
interleaved LDPC codeword onto a modulation symbol, wherein the mapping
comprises
mapping a bit included in a predetermined bit group from among a plurality of
bit groups
constituting the LDPC codeword onto a predetermined bit of the modulation
symbol.
Each of the plurality of bit groups may be formed of M number of bits, and M
may be a
common divisor of Niapc and Icipc and may be determined to satisfy
Qidpc=(Nidpc-Kidpc)/M. In this
case, Qtdpc may be a cyclic shift parameter value regarding columns in a
column group of an
information word submatrix of the parity check matrix, Nwpc may be a length of
the LDPC
codeword, and Kidp, may be a length of information word bits of the LDPC
codeword.
The interleaving may include: interleaving parity bits of the LDPC codeword;
dividing the
parity-interleaved LDPC codeword by the plurality of bit groups and
rearranging an order of the
plurality of bit groups in bit group wise; and interleaving the plurality of
bit groups the order of
which is rearranged.
The rearranging in bit group wise may include rearranging the order of the
plurality of bit
groups in bit group wise by using the following equation:
Yi X,r(i)(0 <N80)
where N is a j Lb bit group before the plurality of bit groups are
interleaved, Yj is a jth bit group
Date Recue/Date Received 2021-10-07
4
after the plurality of bit groups are interleaved, N gro up s a total number
of the plurality of bit
groups, and it(j) is a parameter indicating an interleaving order.
Here, 7r(j) may be determined based on at least one of a length of the LDPC
codeword, a
modulation method, and a code rate.
When the LDPC codeword has a length of 64800, the modulation method is 16-QAM,
and
the code rate is 6/15, 7r(j) may be defined as in table 11.
When the LDPC codeword has a length of 64800, the modulation method is 16-QAM,
and
the code rate is 10/15, 7r(j) may be defined as in table 14.
When the LDPC codeword has a length of 64800, the modulation method is 16-QAM,
and
the code rate is 12/15, 7r(j) may be defined as in table 15.
When the LDPC codeword has a length of 64800, the modulation method is 64-QAM,
and
the code rate is 6/15, 7z(j) may be defined as in table 17.
When the LDPC codeword has a length of 64800, the modulation method is 64-QAM,
and
the code rate is 8/15, 7r(j) may be defined as in table 18.
When the LDPC codeword has a length of 64800, the modulation method is 64-QAM,
and
the code rate is 12/15, 7r(j) may be defined as in table 21.
The interleaving the plurality of bit groups may include interleaving by
writing the plurality
of bit groups in each of a plurality of columns in bit group wise in a column
direction, and
reading each row of the plurality of columns in which the plurality of bit
groups are written in bit
group wise in a row direction.
The interleaving the plurality of bit groups may include serially writing, in
the plurality of
columns, at least some bit groups which are writable in the plurality of
columns in bit group wise
from among the plurality of bit groups, and then dividing and writing the
other bit groups in an
area which remains after the at least some bit groups are written in the
plurality of columns in bit
group wise.
According to an embodiment, there is provided a transmitting apparatus
comprising: an
encoder configured to encode input bits to generate parity bits based on a low
density parity
check (LDPC) code according to a code rate of 6/15 and a code length of 64800;
an interleaver
configured to interleave the parity bits, split a codeword into a plurality of
bit groups, and
interleave the plurality of bit groups to provide an interleaved codeword,
wherein the codeword
comprising the input bits and the interleaved parity bits; and a mapper
configured to map bits of
the interleaved codeword onto constellation points for 16-quadrature amplitude
Date Recue/Date Received 2021-10-07
4a
modulation(QAM), wherein the plurality of bit groups are interleaved based on
a following
equation: = X for j
(0 < < Ng""P) , where Xi is a jth bit group among the plurality of
bit groups, Yi is a ith bit group among the interleaved plurality of bit
groups, Ngroup is a total
number of the plurality of bit groups, and z(j) denotes a permutation order
for the
interleaving of the plurality of bit groups, and wherein the a(j) is defined
as follows:
Order of interleaving
it(j) (0 j < 180)
0 1 2 3 4 5 6 7 8 9 10 11 12
13 14 15 16 17 18 19 20 21 22
23 24 25 26 27 23 29 30 31 32 33 34
25 36 37 38 39 40 41 42 43 44 47
611 46 47 48 49 50 51 52 53 54 55 56 57
58 59 60 61 62 63 64 65 66 67 68
.81181c
¨
69 70 71 72 73 74 75 76 77 78 70 80
81 82 83 84 85 86 87 88 89 90 91
92 93 94 95 96 97 98 99 100 101 102
103 104 10.5 106 107 108 109 110 111 112 113
114
115 116 117 118 119 120 121 122 123 124
125 126 127 128 129 130 131 132 133 134 135
136 137
138 139 140 141 142 143 144 145 146 147
148 149 150 151 152 153 154 155 156 157 158
159 160
161 162 163 164 165 166 167 168 169 170
171 172 173 174 175 176 177 178 179
55 146 83 52 62 176 160 68 53 56 81 97 79 113 163 61 58 69 133 108 66 71 86
144 57 57 116 79 70 156 172 65 149 155 82 138 136 141 111 96 170 90 140 64 159
15
14 37 54 44 63 43 18 47 7 25 34 29
30 26 39 16 41 45 36 0 23 32 28
27 38 48 33 22 49 51 60 46 21 4 3 20 13 50 35 24 40 17 42 6 112 93
6115 n(j)
127 101 94 115 105 31 19 177 74 ID 145 162 102 120 126 93 73 152 129 174 125
72 128
78 171 8 142 178 154 85 107 75 12 9 151 77 117 109 80 106 134 98 1 122 173 161
150 110 175 166 131 119 103 139 148 157
114 147 87 158 121 164 104 89 179 123 118 09
88
11 92 165 84 168 124 169 2 130 167 153 137 143 91 100 5 76 132 135
4
In another embodiment there is a receiving apparatus comprising a receiver
configured to
receive a signal from a transmitting apparatus; a demodulator configured to
demodulate
the signal to generate values according to a 16-quadrature amplitude
modulation(QAM); a
deinterleaver configured to split the values into a plurality of groups,
deinterleave the
plurality of groups and deinterleave one or more values among the
deinterleaved plurality
of groups to provide deinterleaved values; and a decoder configured to decode
the
deinterleaved values based on a low density parity check (LDPC) code having a
code rate
being 6/15 and a code length being 64800 bits, wherein the plurality of groups
are
deinterleaved based on a following equation:
Date Recue/Date Received 2021-10-07
4b
Y7r(j) = Xj for (0 j < Ngroup)
where Xi is a ith group among the plurality of groups, Yi is a jth group among
the
deinterleaved plurality of groups, Ngroup is a total number of the plurality
of groups, and
n(j) denotes a deinterleaving order for the deinterleaving, and wherein the
n(j) is
represented as follows:
Order of deinterleaving
z(j) (0 j < 180)
0 1 2 3 4 5 6 7 8 9 10 11 12
13 14 15 16 17 18 19 20 21 22
23 24 25 26 27 28 29 30 31 32 33 34
35 36 37 38 39 40 41 42 43 44 45
CodclZatc 46 47 48 49 50 51 92 53 54 55 56
57 58 59 60 61 62 63 64 65 66 67 68
69 70 71 72 73 74 75 76 77 78 79 80
81 82 83 84 85 86 87 88 89 90 91
92 93 94 95 96 97 98 99 100 101 102
103 104 105 106 107 108 109 110 111 112 113
114
115 116 117 118 119 120 121 122 123 124
125 126 127 128 129 130 131 132 133 134 135
136 137
130 139 140 141 142 143 144 145 146 147
148 149 150 151 152 153 154 155 156 157 158
159 160
161 162 163 164 165 166 167 168 169 170
171 172 173 174 175 176 177 178 179
55 146 83 52 62 176 160 68 53 56 81 97 79 113 163 61 58 69 133 100 66 71 86
144 57 67 116 59 70 156 172 65 149 155 02 130 136 141 111 96 170 90 140 64 159
15
14 37 54 44 63 43 18 47 7 25 34 29
30 26 39 16 41 45 36 0 23 32 29
27 38 49 33 22 49 51 60 46 21 4 3 20 13 50 35 24 40 17 42 6 112 93
9/15 7r(j)
127 101 94 115 105 31 19 177 74 10 145 162 102 120 126 93 73 152 129 174 125
72 128
78 171 8 142 178 154 85 107 73 12 9
151 77 117 109 80 106 134 90 1 122 173 161
150 110 175 166 131 119 103 139 148 157
114 147 87 158 121 164 104 89 179 123 118 99
88
11 92 165 04 168 124 169 2 130 167 153 137 143 91 100 5 76 132 135
=
In another embodiment there is a receiving method comprising receiving a
signal from a
transmitting apparatus; demodulating the signal to generate values according
to a 16-
quadrature amplitude modulation(0AM); splitting the values into a plurality of
groups;
deinterleaving the plurality of groups; deinterleaving one or more values
among the
deinterleaved plurality of groups to provide deinterleaved values; and
decoding the
deinterleaved values based on a low density parity check (LDPC) code having a
code rate
being 6/15 and a code length being 64800 bits, wherein the plurality of groups
are
dcinterleavcd based on a following equation:
YTc(j) = Xj for (0 < N group)
f
Date Recue/Date Received 2021-10-07
4c
where X, is a jth group among the plurality of groups, Y, is a jth group among
the
deinterleaved plurality of groups, Ngroup is a total number of the plurality
of groups, and n(j) denotes a
deinterleaving order for the deinterleaving, and wherein the n(j) is
represented as follows:
Order of deinterleaving
rc(j) (0 < j < 180)
1 2 3 4 5 6 7 8 9 10 11 12 13
14 15 16 17 18 19 20 21 22
23 24 25 26 27 28 29 30 31 32 33 34
35 36 37 38 39 40 41 42 43 44 45
46 47 48 49 50 51 52 53 54 55 56 57
58 59 60 61 62 63 64 65 66 67 68
Code Rate
69 70 71 72 73 74 75 76 77 78 79 80
81 82 83 84 85 86 87 88 89 90 91
92 93 94 95 96 97 98 99 100 101 102
103 104 105 106 107 108 109 110 111 112 113
114
115 116 117 118 119 120 121 122 123 124
125 126 127 128 129 130 131 132 133 134 135
136 137
138 139 140 141 142 143 144 145 146 147
148 149 150 151 152 153 154 155 156 157 158
159 160
161 162 163 164 165 166 167 168 169 170
171 172 173 174 175 176 177 178 179
55 146 83 52 62 176 160 68 53 56 81
97 79 113 163 61 58 69 133 108 66 71 86
144 57 67 116 59 70 156 172 65 149 155
82 138 136 141 111 96 170 90 140 64 159 15
14 37 54 44 63 43 18 47 7 25 34 29
30 26 39 16 41 45 36 0 23 32 28
27 38 48 33 22 49 51 60 46 21 4 3
20 13 50 35 24 40 17 42 6 112 93
6/15 n(j)
127 101 94 115 105 31 19 177 74 10 145
162 102 120 126 95 73 152 129 174 125 72 128
78 171 8 142 178 154 85 107 75 12 9
151 77 117 109 80 106 134 98 1 122 173 161
150 110 175 166 131 119 103 139 148 157
114 147 87 158 121 164 104 89 179 123 118 99
88
11 92 165 84 168 124 169 2 130 167 153
137 143 91 100 5 76 132 135
In another embodiment there is provided a transmitting apparatus comprising a
parity interleaver configured to
interleave parity bits which are generated by encoding input bits based on a
low density parity check (LDPC) code, a
code rate of the LDPC code being 6/15 and a code length of the LDPC code being
64800; a group interleaver
configured to split a codeword comprising the input bits and the interleaved
parity bits into a plurality of bit groups,
and interleave the plurality of bit groups; a mapper configured to demultiplex
bits of the interleaved plurality of bit
groups to generate cells and map the cells to constellation points for 16-
quadrature amplitude modulation(QAM); and
a transmitter configured to transmit a signal which is based on constellation
points, wherein the plurality of bit groups
gr
are interleaved based on a following equation Yi = X "to) for oup (0 j < N
) , where N is a j-th bit group among
the plurality of bit groups, Y, is a j-th bit group among the interleaved
plurality of bit groups, Ngroup is a number of the
plurality of bit groups, and n(j) denotes an interleaving order, and wherein
the n(j) is represented as follows:
Date Recue/Date Received 2021-10-07
4d
Order of interleaving
7c(j) (0 j < 180)
1 2 3 4 5 6 7 8 9 10 11 12 13
14 15 16 17 18 19 20 21 22
23 24 25 26 27 28 29 30 31 32 33 34
35 36 37 38 39 40 41 42 43 44 45
46 47 48 49 50 51 52 53 54 55 56 57
58 59 60 61 62 63 64 65 66 67 68
Code Rate
69 70 71 72 73 74 75 76 77 78 79 80
81 82 83 84 85 86 87 88 89 90 91
92 93 94 95 96 97 98 99 100 101 102
103 104 105 106 107 108 109 110 111 112 113
114
115 116 117 118 119 120 121 122 123 124
125 126 127 128 129 130 131 132 133 134 135
136 137
138 139 140 141 142 143 144 145 146 147
148 149 150 151 152 153 154 155 156 157 158
159 160
161 162 163 164 165 166 167 168 169 170
171 172 173 174 175 176 177 178 179
55 146 83 52 62 176 160 68 53 56 81
97 79 113 163 61 58 69 133 108 66 71 86
144 57 67 116 59 70 156 172 65 149 155
82 138 136 141 111 96 170 90 140 64 159 15
14 37 54 44 63 43 18 47 7 25 34 29
30 26 39 16 41 45 36 0 23 32 28
27 38 48 33 22 49 51 60 46 21 4 3
20 13 50 35 24 40 17 42 6 112 93
6/15 it(j)
127 101 94 115 105 31 19 177 74 10 145
162 102 120 126 95 73 152 129 174 125 72 128
78 171 8 142 178 154 85 107 75 12 9
151 77 117 109 80 106 134 98 1 122 173 161
150 110 175 166 131 119 103 139 148 157
114 147 87 158 121 164 104 89 179 123 118 99
88
11 92 165 84 168 124 169 2 130 167 153
137 143 91 100 5 76 132 135
In another embodiment there is provided a transmitting method comprising:
interleaving parity bits which are
generated by encoding input bits based on a low density parity check (LDPC)
code, a code rate of the LDPC code
being 6/15 and a code length of the LDPC code being 64800; splitting a
codeword comprising the input bits and the
interleaved parity bits into a plurality of bit groups; interleaving the
plurality of bit groups; demultiplexing bits of the
interleaved plurality of bit groups to generate cells; mapping the cells to
constellation points for 16-quadrature
amplitude modulation(QAM); and transmitting a signal which is based on
constellation points, wherein the plurality
of bit groups are interleaved based on a following equation Yi = X'0) for (0 j
< N
gr oup) , where X is a j-th bit
group among the plurality of bit groups, Y., is a j-th bit group among the
interleaved plurality of bit groups, Ngroup is a
number of the plurality of bit groups, and n(j) denotes an interleaving order,
and wherein the n(j) is represented as
follows:
Date Recue/Date Received 2021-10-07
4e
Order of interleaving
7c(j) (0 j < 180)
2 3 4 5 6 7 8 9 10 11 12 13
14 15 16 17 18 19 20 21 22
23 24 25 26 27 28 29 30 31 32 33 34
35 36 37 38 39 40 41 42 43 44 45
46 47 48 49 50 51 52 53 54 55 56 57
58 59 60 61 62 63 64 65 66 67 68
Code Rate
69 70 71 72 73 74 75 76 77 78 79 80
81 82 83 84 85 86 87 88 89 90 91
92 93 94 95 96 97 98 99 100 101 102
103 104 105 106 107 108 109 110 111 112 113
114
115 116 117 118 119 120 121 122 123 124
125 126 127 128 129 130 131 132 133 134 135
136 137
138 139 140 141 142 143 144 145 146 147
148 149 150 151 152 153 154 155 156 157 158
159 160
161 162 163 164 165 166 167 168 169 170
171 172 173 174 175 176 177 178 179
55 146 83 52 62 176 160 68 53 56 81
97 79 113 163 61 58 69 133 108 66 71 86
144 57 67 116 59 70 156 172 65 149 155
82 138 136 141 111 96 170 90 140 64 159 15
14 37 54 44 63 43 18 47 7 25 34 29
30 26 39 16 41 45 36 0 23 32 28
27 38 48 33 22 49 51 60 46 21 4 3
20 13 50 35 24 40 17 42 6 112 93
6/15
7E0) 127 101 94 115 105 31 19 177 74 10 145
162 102 120 126 95 73 152 129 174 125 72
128
78 171 8 142 178 154 85 107 75 12 9
151 77 117 109 80 106 134 98 1 122 173 161
150 110 175 166 131 119 103 139 148 157
114 147 87 158 121 164 104 89 179 123 118 99
88
11 92 165 84 168 124 169 2 130 167 153
137 143 91 100 5 76 132 135
[Advantageous Effects]
According to various exemplary embodiments, improved decoding and receiving
performance can be provided.
[Description of Drawings]
The above and/or other aspects will be more apparent by describing in detail
exemplary embodiments, with reference
to the accompanying drawings, in which:
Date Recue/Date Received 2021-10-07
5
FIG. 1 is a block diagram to illustrate a configuration of a transmitting
apparatus, according
to an exemplary embodiment;
FIGs. 2 to 4 are views to illustrate a configuration of a parity check matrix,
according to
exemplary embodiments;
FIG. 5 is a block diagram to illustrate a configuration of an interleaver,
according to an
exemplary embodiment;
FIGs. 6 to 8 are views to illustrate an interleaving method, according to
exemplary
embodiments;
FIGs. 9 to 14 are views to illustrate an interleaving method of a block
interleaver, according
to exemplary embodiments;
FIG. 15 is a view to illustrate an operation of a demultiplexer, according to
an exemplary
embodiment;
FIGs. 16 and 17 are views to illustrate a method for designing an interleaving
pattern,
according to exemplary embodiments;
FIG. 18 is a block diagram to illustrate a configuration of a receiving
apparatus according to
an exemplary embodiment;
FIG. 19 is a block diagram to illustrate a configuration of a deinterleaver,
according to an
exemplary embodiment;
FIG. 20 is a view to illustrate a deinterleaving method of a block
deinterleaver, according to
an exemplary embodiment; and
FIG. 21 is a flowchart to illustrate an interleaving method, according to an
exemplary
embodiment.
[Mode for Invention]
Hereinafter, various exemplary embodiments will be described in greater detail
with reference
to the accompanying drawings.
In the following description, same reference numerals are used for the same
elements when
they are depicted in different drawings. The matters defined in the
description, such as detailed
construction and elements, are provided to assist in a comprehensive
understanding of the
exemplary embodiments. Thus, it is apparent that the exemplary embodiments can
be carried out
without those specifically defined matters. Also, functions or elements known
in the related art
are not described in detail since they would obscure the exemplary embodiments
with
Date Recue/Date Received 2021-10-07
6
unnecessary detail.
FIG. 1 is a block diagram to illustrate a configuration of a transmitting
apparatus according to
an exemplary embodiment. Referring to FIG. 1, the transmitting apparatus 100
includes an
encoder 110, an interleaver 120, and a modulator 130 (or a constellation
mapper).
The encoder 110 generates a low density parity check (LDPC) codeword by
performing
LDPC encoding based on a parity check matrix. To achieve this, the encoder 110
may include an
LDPC encoder (not shown) to perform the LDPC encoding.
Specifically, the encoder 110 LDPC-encodes information word(or information)
bits to
generate the LDPC codeword which is formed of information word bits and parity
bits (that is,
LDPC parity bits). Here, bits input to the encoder 110 may be used as the
information word bits.
Also, since an LDPC code is a systematic code, the information word bits may
be included in the
LDPC codeword as they are.
The LDPC codeword is formed of the information word bits and the parity bits.
For example,
the LDPC codeword is formed of Nidpc number of bits, and includes Kid number
of information
word bits and Npanty=Nicipc-KkiN number of parity bits.
In this case, the encoder 110 may generate the LDPC codeword by performing the
LDPC
encoding based on the parity check matrix. That is, since the LDPC encoding is
a process for
generating an LDPC codeword to satisfy H=CT=0, the encoder 110 may use the
parity check
matrix when performing the LDPC encoding. Herein, H is a parity check matrix
and C is an
LDPC codeword.
For the LDPC encoding, the transmitting apparatus 100 may include a memory and
may pre-
store parity check matrices of various formats.
For example, the transmitting apparatus 100 may pre-store parity check
matrices which are
defined in Digital Video Broadcasting-Cable version 2 (DVB-C2), Digital Video
Broadcasting-
Satellite-Second Generation (DVB-S2), Digital Video Broadcasting-Second
Generation
Terrestrial (DVB-T2), etc., or may pre-store parity check matrices which are
defined in the North
America digital broadcasting standard system Advanced Television System
Committee (ATSC)
3.0 standards, which are currently being established. However, this is merely
an example and the
transmitting apparatus 100 may pre-store parity check matrices of other
formats in addition to
these parity check matrices.
Hereinafter, a parity check matrix according to various exemplary embodiments
will be
Date Recue/Date Received 2021-10-07
7
explained in detail with reference to the drawings. In the parity check
matrix, elements other than
elements having 1 have 0.
For example, the parity check matrix according to an exemplary embodiment may
have a
configuration of FIG. 2.
Referring to FIG. 2, a parity check matrix 200 is formed of an information
word submatrix(or
an information submatrix) 210 corresponding to information word bits, and a
parity submatrix
220 corresponding to parity bits.
The information word submatrix 210 includes Kid number of columns and the
parity
submatrix 220 includes Nparity=Niapc-Kidpc number of columns. The number of
rows of the parity
check matrix 200 is identical to the number of columns of the parity submatrix
220, Nparityr---N
- IOC
Kldpc=
In addition, in the parity check matrix 200, NI* is a length of an LDPC
codeword, Kidpc is a
length of information word bits, and Nparity=Nupc-Kidpc is a length of parity
bits. The length of the
LDPC codeword, the information word bits, and the parity bits mean the number
of bits included
in each of the LDPC codeword, the information word bits, and the parity bits.
Hereinafter, the configuration of the information word submatrix 210 and the
parity
submatrix 220 will be explained in detail.
The information word submatrix 210 includes Kid number of columns (that is,
0th column to
(Kidpe-1)th column), and follows the following rules:
First, M number of columns from among Kidp, number of columns of the
information word
submatrix 210 belong to the same group, and Klapc number of columns is divided
into Kkipe/M
number of column groups. In each column group, a column is cyclic-shifted from
an
immediately previous column by Chip, That is, Qidp, may be a cyclic shift
parameter value
regarding columns in a column group of the information word submatrix 210 of
the parity check
matrix 200.
Herein, M is an interval at which a pattern of a column group, which includes
a plurality of
columns, is repeated in the information word submatrix 210 (e.g., M=360), and
Qidpc is a size by
which one column is cyclic-shifted from an immediately previous column in a
same column
group in the information word submatrix 210. Also, M is a common divisor of
Nidpc and '<AWN, and
is determined to satisfy Chapc=(Niapc-Kwpc)/M. Here, M and Qmpc are integers
and Kidp,,/M is also
an integer. M and ORIN may have various values according to a length of the
LDPC codeword
Date Recue/Date Received 2021-10-07
8
and a code rate (CR)(or, coding rate).
For example, when M,--360 and the length of the LDPC codeword, NI*, is 64800,
Qidpc may
be defined as in table 1 presented below, and, when M=360 and the length Nidpc
of the LDPC
codeword is 16200, Oldpe may be defined as in table 2 presented below.
[Table 1]
Code Rate Nidpc M Qidpc
5/15 64800 360 120
6/15 64800 360 108
7/15 64800 360 96
8/15 64800 360 84
9/15 64800 360 72
10/15 64800 360 60
11/15 64800 360 48
12/15 64800 360 36
13/15 64800 360 24
[Table 2]
Code Rate Nidpo M Qiepc
5/15 16200 360 30
6/15 16200 360 27
7/15 16200 360 24
8/15 16200 360 21
9/15 16200 360 18
10/15 16200 360 15
11/15 16200 360 12
12/15 16200 360 9
13/15 16200 360 6
Second, when the degree of the 0th column of the ith column group (i=0, 1,
..., Kidp,./M-1) is Di
(herein, the degree is the number of value 1 existing in each column and all
columns belonging
to the same column group have the same degree), and a position (or an index)
of each row where
1 exists in the Oth column of the ith column group is AT = =,R1)
, an index Ri(,kj)of a row
where kth 1 is located in the ith column in the ith column group is determined
by following
Equation 1:
=Co) +adix mod(N )
lalx Pc (1),
where k=0, 1, 2, ...D1-1; i---0, 1, ..., Kidpc/M-1; and j=1, 2, ..., M-1.
Equation 1 can be expressed as following Equation 2:
Date Recue/Date Received 2021-10-07
9
= = ¨3)
+ jmodM)x Qop, mod(N ¨ K,pc) ... (2),
where k=0, 1,2, ...D,-l; i=0, 1, ..., &ape/M-1; and j=1, 2, ..., M-1. Since
j=1, 2, ===, M-1, 0
mod M) of Equation 2 may be regarded as j.
In the above equations, Ri(ki) is an index of a row where kth 1 is located in
the jth column in the
=th
column group, Nidpc is a length of an LDPC codeword, Kid is a length of
information word
bits, Di is a degree of columns belonging to the ith column group, M is the
number of columns
belonging to a single column group, and ()Mix is a size by which each column
in the column
group is cyclic-shifted.
As a result, referring to these equations, when only Ri(ko) is known, the
index Ri(kj) of the row
where the kth 1 is located in the jth column in the ith column group can be
known. Therefore,
when the index value of the row where the kth 1 is located in the Oth column
of each column
group is stored, a position of column and row where 1 is located in the parity
check matrix 200
having the configuration of FIG. 2 (that is, in the information word submatrix
210 of the parity
check matrix 200) can be known.
According to the above-described rules, all of the columns belonging to the
ith column group
have the same degree Di. Accordingly, the LDPC codeword which stores
information on the
parity check matrix according to the above-described rules may be briefly
expressed as follows.
For example, when Nape is 30, Kidpe is 15, and Qkipc is 3, position
information of the row
where 1 is located in the Oth column of the three column groups may be
expressed by a sequence
of Equations 3 and may be referred to as "weight-1 position sequence".
RJ =1,R(20)
= 2, R,(30) = 8, k40) ¨10,
RTo = 0, R12r; 9, R132 =13,
4.)0 =0,Rfd =14.
= = = (3),
where Rj) is an index of a row where V' 1 is located in the jth column in the
th column group.
The weight-1 position sequence like Equation 3 which expresses an index of a
row where 1 is
located in the Oth column of each column group may be briefly expressed as in
Table 3 presented
below:
[Table 3]
=
Date Recue/Date Received 2021-10-07
10
1 2 8 10
0 9 13
014:
Table 3 shows positions of elements having value 1 in the parity check matrix,
and the ith
weight-1 position sequence is expressed by indexes of rows where 1 is located
in the 0th column
belonging to the ith column group.
The information word submatrix 210 of the parity check matrix according to an
exemplary
embodiment may be defined as in Tables 4 to 8 presented below, based on the
above descriptions.
Specifically, Tables 4 to 8 show indexes of rows where 1 is located in the Oth
column of the ith
column group of the information word submatrix 210. That is, the information
word submatrix
210 is formed of a plurality of column groups each including M number of
columns, and
positions of 1 in the 0th column of each of the plurality of column groups may
be defined by
Tables 4 to 8.
Herein, the indexes of the rows where 1 is located in the 0th column of the
ith column group
mean "addresses of parity bit accumulators". The "addresses of parity bit
accumulators" have the
same meaning as defined in the DVB-C2/S2/T2 standards or the ATSC 3.0
standards which are
currently being established, and thus, a detailed explanation thereof is
omitted.
For example, when the length Nidpc of the LDPC codeword is 64800, the code
rate is 6/15,
and M is 360, the indexes of the rows where 1 is located in the 0th column of
the ith column group
of the information word submatrix 210 are as shown in Table 4 presented below:
[Table 4]
Date Recue/Date Received 2021-10-07
11
'ex of row where-11s locatedthe Oth column of the'dh r.olumn group.
0 1606 3402 49516751 7132 11516 12300 12482 12592 13342 13764 14123
21576 23946 24533 2537625667 25836 31799 34173
35442 36153 36740 37085 37152 ma 176S8
1 4621 5007 6410 6732 9757 11506 13093 25513 26335 18052 1.9512
21319 23653 25628 27208 31333 32219 33003 33239 33447
362003647336938 37201 37283 37495 38642
2 16 1094 2020 3080 4194 5098 5631 6877 7889 8237 9804 10067 11017
11356 13136 23354 15379 18934 20199 24522 26272
28666 30386 3271436390 370/5 37162
3 700 297 1708 6017 6490 7372 7825 9546 10398 1660518561.18745 21625
22137 23693 24340 24966 25015 26935 26586 26895
20687 33438 3452034958 37056 38297
4 159 1010 2573 3617 4452 4958 5556 5832 648/ 8227 9924 10836 14954
15594 16623 18065 19249 22334 22677 23408 23731
24075 24776 27007 28222 30343 38371
3118 3545 4768 4932 5227 6732 8170 9397 10522 11506 15536 20218 21921 28599
29445 29758 29968 31014 32027 33695
34378 35667 36323 36722 3687038335 38623
6 1264 4254 69369165 9436 9950 10861 11653 13697 13961 15164 15665
18444 19470 2031.3 21139 24371 26431 26999 28086
28251 29261 3198134015 3585036129 37186
7 131 1,307 1628 2041 2524 5358 7988 8191 10322 11905 12919 14127
15515 15711 17051, 19024 21195 22902 23727 24401
24508 25111 25228,27338 35398 37794 38195
8 962 3035 7174 7948 13355 13607 14371 18189 18339 18666 18875 19142
20615 21136 21309 21758 23366 24745 25849 25982
27583 30006 31118 32106. 36469 36583 37920
9 2490 3549 4273 4808 5707 6021 6509 7456 8240 10044 12262 12660
13085 14750 15660 16049 21587 23997 25803 28343
23503 14193 348603549035021 37737 38295
955 4323 .51.456885 8123 9730 11840 12216 19194 25313 23146 24248 24830 25268
26617 26801 36557 251753 30745 31450
3197332839 33025 33296 35710 3736637509
11 264 605 4181 4483 5156 7238 8853 10939 11251 12964 16254 17511
20017 22395 22818 23261 23422 24064 26329 27723
28186 30434 31456 33971 34372 36764 38123
12 520 2562 2794 3528 3860 4402 5676 6963 8655901* 9783 11933 15336
17193 17320 19035 20605 23579 23769 24123 24956
27866 32457 34011 34499 36620 37526
13 10106 106371090634241
34 1856 15100 1937821848
1$ 943 11191 2780629411
16 4575 6359 13629 19383
17 4476 4953 18782 24313
18 5441 6381 21840 35943
19 9538 gno 1254630120
9587 10626 1104725700
21 40138 15298 26768 35047
21 2332 6363 8782 28863
23 4525 4933 28298 30289
24 3542 491818257 31746
Date Recue/Date Received 2021-10-07
12
25 1221 25233 2675734892
26 also 16477 27934 30021
27 850025016 33043 38070
28 7374 10207 16189 35811
29 611 18480 20064 38261
30 25416 27352 36039 38469
31 1567 17614 25839 32775
32 4113 12481 21912 37945
33 5573 13222 23619 31271
34 18271 26251 27182 30587
35 1469026430 26799 34355-
36 13688 16040 20716 34558
37 2740 24957 23435 32540
38 3491 14365 14681 36858
39 4796 6238 25203 visa
40 1731 12816 1344 26025
41 19182 21662 23742 27672
42 6502 13641 17509 34713 õ
43 12246 12372 16746 27432
44 1589 21521 30621 34001
45 12328 20515 30651 31432
46 3415 22656 23427 36395
47 632520925958 31085
48 619 3690 19648 37778
49 9528 13581 26965 36447
50 2147 26249 26968 28776
t 15698 18209 30683
52 1132 1988834111
53 4508 25513 38874
54 475 2729 34100
55 7318 32277 38587
56 182 16473 33082
57 38659673 21265
58 444720151 27618
59 6315 14371 39711
60 704 9695 28858
61 48669757 30546
62 2933 19361 30732
63 756 28000 29138
64 3821 24076 31813
65 4611 12326 31291
66 7618 21515 34995
67 124623294 30068
68 646633233 35865
69 1448423274 38150
70 21269 36411 37450
71 nuo 26195 37653
In another example, when the length Niapc of the LDPC codeword is 64800, the
code rate is
8/15, and M is 360, the indexes of the rows where 1 is located in the Oth
column of the ith column
group of the information word submatrix 210 are as shown in Table 5 presented
below:
[Table 5]
Date Recue/Date Received 2021-10-07
13
Index of row where 1 is located in the 0th column of the ith column group
0 2768 3039 4059 585662.45 7013 $1579341 9802 10470 11521 12083
16610 113361 20321 24601 27420 28206 29788
1 2739 8244 81391 9157 12624. 12973 15534 16622 16919 18402 18780
19854 20220 20543 2230625540 27478 27678 28053
2 1727 2268 6246 7815 90109556 1013410472 11389 14599 1571916204
17342 17666 18850 2205S 25579 2586029207
3 28 1346 3721 5565 7019924012355 1310914800 1604016339 17369 17631
19357 19473 19891 20381 23911 29633
4 869 24504386 $316 6160 7107 10362 11132 11271 13149 16397 16532
17113 1989422043 22784 27363 28615 28804
508 4292 5831 8559 10044.10412 11283 14410 15888 17243 17518 19903 20528 22090
22652 27235 27384 28208 28485
6 3892248 5840 6043 7000 9054 1107$ 11760 12217 1256$ 13387 15403
19422 19$28 21493 25142 27777 28566 28702
7 1015 2002 5764 6777 9346 9629 11039 11153 12690 13068 13990 16841
17702 2002t 24106 2630029332 30081 30196
_8 1480 3084 3467 4401 4796 I$ 77S51 11368 12323 14325 14546 16360
17158 1801021333 2561226536 2690627005
9 6925 8876 12392 14529 15253 15437 19226 19950 20321 23021 23651
24393 24653 26668 27205 28269 28529 29041 29292
2547 3404 3538 4666 5126 5468 7695 8799 14732 15072 15881 1741013971
1960919717 2215024941 27908 29018
11 688 1581 2311 5511 72189107 10454 12252 13662 15714 15894 17025
18671 24304 2531625556 2846928977 29212
12 1047 1454 1718 4645 5030 6811 7868 8146 10611 15767 17682
183912261423021 23763 2547826491 .2908829757
13 59 1781 1900 38 /4 4121 804489069175 11156 14841 15789 16033 1675$
17292 18550 19310 22505 29567 19850
14 1952 3057 4399 9476 10171 10769 1133$ 11569 15002 19301 20621
2264223452 24360 25109 25290 25828 28505 29122
2695 3070 3437 4764 4905 66709244 11645 13352 13573 1397$ 14600 15871
1799619672 20079 20579 25327 27958
16 612 1523 2004 4244 45994926 5843 7684 10122 10443 12267 143613
18413 19058 22985 24257 26202 26596 27899
17 1361 2195 4146 6708 7158 7538 9138 9998 14862 15359 16076 18925
21401 21573 22503 2414624247 27778 29312
18 52296235 7134 7655 9139 13527 15408 16058 16705 18320 19909 20901
2223822437236542513l 2755028247 29903
19 69720354887 5275 6909 9166 11805 15338 16381 18403 20425 20683
21547 2459025171 26726 28848 2922429412
5379 17329 22659 23062
21 11314 14759 22329 22936
22 2423 2821 10296 12727
23 8460 15260 16769 17290
24 14191 14608 29536 30187
7203 M069 20111 22850
26 4285 15413 2644 29069
27 5482137 91891092S
28 4581 7077 23382 23949
=
29 394 17248 19486 27922 ,
8668 10230 16922 26678
31 6158 998013788 28198
32 12422 16076 24206 29887
33 8778 10649 18747 22111
34 21029 22677 27150 28980
7918 15423 27672 27803
36 5927 18086 23525
37 , 3397 15053 30224
.38 24016 25880 26268 ,
39 1096 4775 7912
3259 17301 20802
41 129 8396 15132
42 17825 28119 26676
= 43 2343 838228840
44 3907 18374 20939
1132 129013736
=
46 1481 4710 23846
47 2185 3705 26834
48 5496 15681 21854
44 12697 13407 22178
12788 21227 22894
51 629 2854 6232
52 2n9 18227 27458
53 7593 21935 2300 t
54 3836 708L 12282
7925 184402313$
56 497 6342 9717
57 11199 22046 30067
SS 12572 28045 28990
59 1240 2023 10933
19566 20629 25186
Date Recue/Date Received 2021-10-07
14
61 6442 13303 28813
62 4765 10572 16180
63 352 19301 24286
63 6782 1848021383
65 11267 12288 15756
66 771 5652 15531
67 16131 20047 25649
63 13227 23033 2s430
69 4839 1346'7 2748S
70 2852 4077 22993
71 2504 26116 29324
72 12518 1737424267
73 1222 11859 27922
74 9660 17286 18261
7$ 232 11296 29978
76 9750 11165 16295
77 4394 9505 23622
78 10861 11980 14110
79 2128 15883 22836
80 6274 17243 21989
81 10866 13202 22517
82 11159 16111 21608 _
83 3719 1.$787 22100
84 1756 2020 23901
8$ 209U2947330103
86 2729 15091 26976
87 4410 8217 12963
SS 5395 24564 28235
89 3859 17909 23051
90 5733 26005 29797
91 1935 3492 29773
92 11903 21380 29914
93 6091 1046929997
94 2895 8930 15594
95 1827 10028 20070
In another example, when the length N1 of of the LDPC codeword is 64800, the
code rate is
th
10/15, and M is 360, the indexes of rows where 1 exists in the Oth column of
the -column group
of the information word submatrix 210 are defined as shown in Table 6 below.
[Table 6]
Date Recue/Date Received 2021-10-07
15
_ _ . _ -= = . Index of row
where 1 is located in the Oth column of the ith column grou.p .
0 97914234156 4609 63418259 10354 10549140961451417952 1733317653 7830
27990
. 1 2559 4029634465109167972811312 148551710417721 mm018791
1907619697 191340
2 3243 6894 79501053912042 1323323938 14762 M44916727 27025 1.82972.9796
2040021877
3 S2723574 6341 67229191 10909 iiisis'71.ssi fiogiiksact 28631717007 27309
1041519945'
= 4=* 1554598 10201109751109611296 12713.15564,15978 16395 1754228164111451
1861226617
* 11281999 3926 4069 555860856337 838610693 12450 1543816223163701730918634
. 6 2408 2929 56504357 5852 73298536 86951060311003 14304 14937
1576718402 21502
I 199 3066 6446 6949 um 953610452 128571367615915 16717 1765419802 20115 22
579
a na 67G 00105 2696 5537 639657377311 7369 /3045 1639419576 20149 11424-
21697
. 9 9351591 3248 3509 3706313476274 62767864 903323818.1567516446
M35318643
975 37744083 5825 61541 us 7639 0657.2.0203 2305214240 17320 19126 196442020e
,
11 , 1795 2961 25442418 6148 8091 9066 922340676 10752 21512
18171179251492.2.2.058
267 925 1824 2325 264028636070 5597 701511109 9915 1160R 28142.175L219625.
_1.5 229318963039 4303 4690878712241 1.3400 144792949224601 2711517913294M
20597
= 14 = 5883895 804566148131 84049590 90599246 umo lassi 18687 18841
1921821506
222 1889 29692299 301150749044 7598769995341024410697 11691 17902 21419
, 1310157917392294 3701 3965 5713 68777263 22172121431276517121 2001121436
2.7 301 1668 2501 4925 577859859635 10140 10820 11779 118491203815650 26426
20527
5932484 3071 321940544125 5563 593969297085 80541217316280 1794519302'
19 222 1,619 39494902 743861460/ /7 9.23919131135211734717439 18193
1958,619929
29 123721 62546909 7860813510437 12252 /3928 1406914149 2503215694
15264182783
31 4212 915 1548 1637 66879332 1012311753 11970 1.5524 13295 1733519787
19210 19340
' ,12 ' 1291 25004109,4511 509551941001413125 3.328613972 1140916113
1621418584 209913
23 176147997444 7740 812983419911 9156 920710005 106791393917678 18194
20000 -
*24 30893522-5361 5692 6833 8342 8792 1102511211 11548 1191413987 15442
1554219707
13222349 29705632 6349.7577 8782 91139267 937612042 12943 16680 16970 21321
. 26 67361196021455
27 212315672.19550'
18 5975 11635 20395,
29 2818938715317
19 27633554113102
' 52 67392148918997
32 sue 35779 20674,
33 2220 1783818533'
m 3025 9342 9922..
35. 2728.5359 12142
. , 252966669264 , . .
41 128921530720912
38 107361239316539'
30' 1075 240713858
40 49215411 19202
. 41 9355 1544716839
42 1-1.3a43.033419286
43 .41010421.11286
44 .4880 10431 12208.'
45 292011993 12442*
= 46 7356 28362
18772. =
414t 79011494d'.
49 45646714 7379
49 4639 865248871. =
*__16787.130422,29246*___ _
Date Recue/Date Received 2021-10-07
16
st '.524111079 11640
.12 ; 15592916 1511-1
93 71737 664350881
54 ' 1039415161717073
55 :1107.5049125741
56 ; 78051881817905
57 11891576717764:
'.5ai 582312921 14316
59 i 11080 2039020924
. 10 ; 56611265 '17411.
-it 12459457 Gisz
:62. 28601093514756
_
13 XIII 14228 21517
54 152912955.15902.
.55 I 41517593735
16 6784120921642/
.57 ili232915794153195
53 12588 1537817171
$3 8067 14589 18804
70 , 12445877 6085
71 up9728349 &KW
72 026739412734
23 !_ 34M5693112076
74¨ ' 135421527320581------
73 1 9(15813552 28798
76 70517626141081
'77 I 42804507 15517
76 417010569 14855
79 i 3$33754I5575
SO 1468812915 13712
31 489436
la 105.544512912
13 228047547311
14 66618128 12681
15. C-9758-10621 19814"
: 1.593911318 19941
JR 17/6505721566
13 2021323911452
39 44456489330
56 4510148416754
=
=
1.463.41756218289
:92 .54559 11119 17447 ,
.93 1182 Ot372.16516
94 655817115.111100
95 177651579520016
so '21331190717587
'97 65491442845175
98 97712055140K
99 1396545811321
Ice S941914 12003
101 '17825419 12448 ¨
1.02 177E17946 52,44,
50],õ: 7.314 /2139 14519
Date Recue/Date Received 2021-10-07
17
lot JAM MI6 20959
3.05 7943 145490.1591137
5005-8153, MOSS
107 3.773o is Os 2tsa
1og, 4723,8134330312
tti36,5716264511)&76
110 1444037a53
sit 12634B-334774
33,z 25221081345157
la 3, 15,75234B49=18959
114. 7,13,43,23 ms3:
115.=3365143311SW
Lis 2,601X14111623
117 IA1221672416792,
ti-. 421 Pee 18171
3.3.31* 5901937920721
In another example, when the length Nidric of the LDPC codeword is 64800, the
code rate is
10/15, and M is 360, the indexes of rows where 1 exists in the 0th column of
the ith column group
of the information word submatrix 210 are defined as shown in Table 7 below.
[Table 7]
Date Recue/Date Received 2021-10-07
18
i Index of row where 1 is located in the 0th column of the ith column
group
0 316 1271 3692 9495 12147 12849 14928 16671 16938 17864 19108 20502
21097 21115
1 2341 2559.2643 2816 2865 5137 5331 7000 7523 8023 10439 10797 13208
15041
2 5556 6858 7677 10162 10207 11349 12321 12398 14787 15743 15859 15952 19313
20879
3 349 573 910 2702 3654 6214 9246 9353 10638 11772 14447 14953 16620
19888
4 204 1390 2887 3835 6230 6533 7443 7876 9299 10291 10896 13960 18287
20086
541 2429 2838 7144 8523 8637 10490 10585 11074 12074 15762 16812 17900 18548
6 733 1659 3838 5323 5805 7882 9429 10682 13697 16909 18846 19587
19592. 20904
7 1134 2136 4631 4653 4718 5197 10410 11666 14996 15305 16048 17417
18966 20303
8 734 1001 1283 4959 10016 10176 10973 11578:12051 15550 15915 19022
19430 20121
9 745 4057 5855 9885 10594 10989 13156 13219 .13351 13631 13685 14577
17713 20386
968 1446 2130 2502 3092 3787 5323 8104 8418 9998 11681 13972 17747 17929
11 3020 3857 5275 5786 6319 8608 11943 14062 17144 17752 18001 18453
19311 21414
12 709 747 1038 2181 5320 8297 10584 10659 13964 15009 15277 16953
20675 21509
13 1663 3247 5003 5760 7186 7360 10346 1421114717 147.92 15155 16128
17355 17970
14 516 578 1914 6147 9419 11148 11434 13289 13325 13332 19106 19257
20962 .21556
5009 5632 6531 9430 9886 10621 11765.13969 16178 16413 18110 18249 20616 20759
16 457 2686 3318 4608 5620 5858 6480 7430 9602 12691 14664 18777 20152
20848
17 33 2877 5334 6851 7907 8654 10688 15401 16123 17942 17969 18747
18931 20224
18 87 897 7636 8663 11425 12288 12672 14199 16435 17615 17950 18951
19667 20281
19 1042 1832 2545 2719 2947 3672 3700 6249 6398 6833 11114 14283 17694
20477
326 488 2662 2880 3009 5357 6587 8882 11604 14374 18781 19051 19057 20308
21 854 1294 2436.2852 4903 6466 7761 9072 9564 10321 13638 15658 16946
19119
22 194 899.1711 2408 27865391 7108 8079 8716.1145.3 17303 19484 20989
21389
23 1631 3111 3994 5005 7810 8850 10315 10589 13407 17162 18624 18758
19311 20301
24 736 2424 4792 5600 6370 10061 16053 16775 18600.
1254 8163 8876 9157 12141 14587 16545 17175 18191
26 388 6641 8974 10607 10716 14477 16825 17191 18400
27 5578 6082 6824 7360 7745 8655 11402 1166512428
28 3603 8729 13463 14698 15210 19112 19550 20727 21052
29 48 1732 3805 5158 15442 16909 19854 21071 21579
11707 14014 21531
31 1542 4133 4925
32 10083 13505 21198
33 14300 15765 16752 =
34 778 1237 11215
1325 3199 14534
36 :2007 14510 20599
37 1996 5881 16429
38 5111 15018 15980
39 4989 10681 12810
3763 10715 16515
41 2259 10080 15642
42 9032 11319 21305
43 3915 15213 20884
44 11150 15022 20201
1147 6749 19625
46 12139 12939 18870
47 3840 4634 10244
48 1010 10231 17720
49 2708 13056 13393
5781 11588,18888
Date Recue/Date Received 2021-10-07
19
51 1345 2036 5252
52 5908 8143 15141
53 1804 13693 18640
54 10433 13965 16950
_ 55 9568 10122 15945
56 547 6722 14015
57 -321 12844 14095
58 263210513 14936
59 6369 11995 20321
60 9920 19136 21529
61 1990 2726 10183
62 5763 12118 15467
63 503 10006 19564
64 9839 11942 19472
65 11205 13552 15389
66 8841 13797 19697
67 124 6053 18224
68 6477 14406 21146
69 1224 8027 16011
70 3046 4422 17717
71 739 12308 17760
72 4014 4130 7835
73 2266 5652 11981
74 2711 7970 18317
75 2196 15229 17217
76 8636 13302 16764
77 5612 15010 16657
78 615 1249 4639
79 3821 12073 18506
80 1 1066 16522 21536
81 11307 18363 19740
82 3240 8560 10391
83 3124 11424 20779
84 1604 8861 17394
85 2083 7400 8093
86 3218 7454 9155
87 9855 15998 20533
88 316 2850 20652
89 5583 9768 10333
90 7147 7713 18339
91 12607 17428 21418
92 14216 16954 18164
93 8477 15970 18486
94 1632 8032 9751
95 4573 Ne0 13507
96 11747 12441 13876
97 1183 15605 16675
98 4408 10264 17109
99 5495 7882 12150
100 1010 3763 5065
101 9828 18064 21599
102 6342 7353 15358
103 6362 9462 19999
Date Recue/Date Received 2021-10-07
20
104 7184 13693 17622
105 4343 4654 10995
106 7D99 8466 18520
107 11505 14395 15118
108 6779 16691 18726
109 7146 12644 20196
110 5865 16728 19634
111 4657 8714 21246
112 4580 5279 18750
113 3767 6620 18905
114 9209 13093 17575
115 12486 15875 19791
116 8046 14636 17491
117 2120 4643 13206
118 6186 9675 12601
119 784 5770 21585
In another example, when the length Nmpc of the LDPC codeword is 64800, the
code rate is
12/15, and M is 360, the indexes of rows where 1 exists in the Oth column of
the lth column group
of the information word submatrix 210 are defined as shown in Table 8 below.
[Table 8]
Date Recue/Date Received 2021-10-07
21
I Index of row where 1 k located in the 0th column of the ith column Toup
. _
0 534147162:1 .1857.3338 3568 2723 41855126 5889 7737 .8632 8949 9726.
1 22144.5 590 3779-3835 6919 7743 8280. 8448. 3491 9967 10042 1124112917
2 46524837 49005029 5449 5637 5751 8684 9935 11681 11811 11885 12089,12900
2 24181012. 3647 4210 4473 7449.7502 9490 10067 11092 11139 11256 12201
11183
4. 2591 2947 33492405.44174519 51766672.84913 8863 9201 11291 12.376 12134
2:7101197 290 871 1727 3911 5411 '6076 8.701. 93501.0316.1079812439
6 1755 2.897 2923-3584 3901 4048 5953 70547132 9155 10184113824 11278 12669
7 21833740 4803 52175660'6375'6987 8219 8466 9019 10353 10583 11118 12762.
8 731594, 2145 271.52501 3572 3639 3725 6859.7187 810610120.10507 10691.
9 246 732 121511852788 2830 3499 3881 4199 4991:6425 7061 9956 10491
. 10 3115681828:34244319 4515 1539 1018 9702 10293 1043311249 11918 12458;
11 2024 2970 3048 3638 36704132 5224 5774 5926.9426 9943 10873 1178711837'
22 10491218 1551 2328 3493 4353 5750,6433 7613 87132 9738 9503 11744 12.937
13 1193.2060 2229 2964 3473 4592 47906709 7162.8211 8326 11140 11908'12243
14 9732121 2438.3332 385045396557.8745.9556 97601016110542 10711 12539
24632939' 3117.3247 3711 5393 5844 5932 7801 101.92 10228 11498 1216212941
26. 1781 22292276 3523 3582 3951 5279 5774 7920 9324 10920 11038 17340 12449
17 2.83 184-1681 2230;3464 3811.5958 26562942 9003 10195 11425.11945 12916
la 155 354 1090 13302002.2236.3559 3705 4922 5958'6675 6564 9972 12750
19 303 876 2059 2142 5244
5330 6644 7576 8614 9398 /0410 107181103112957 --
3449 3617 4408 4602 4727,6182 8835:8928 9372 9644 10237 10747 11655 12745
21 81.1 2565 28202677
8974 963241069.'11548 11839 12107 12411.12695 12812 12890' .
22. 9724123,1943 1385 1149 7339 7477 8379 5177 9359 10074 11709 '12552 12831
342.9731541 2262'2905 5276 5758'7099 7894 8128 8325 8663 887510090'
= 24 -.474791 958 3902 4924.4955.5085 5908 5105 6329 7931 9138 3401 10563
25 13974451 4698 5911. 6037 7127,73M 8678 8924 9000 9473 9602 10446 12692
26 1314.7371 12801 .
27 1a914447 7972:
28 633 125710597'
29 .1843 5101.110313
3294.802Z 10513.
31 110-8 10374 lams.
31 5353 7224 20112.-
33 33983674 8569
' 34 77329473 206031
. 35 29979418.9581.
36 5iri 6523.1122r
37 19665214 9899. . . . . . .
38. 540385327
39 8369248 9612
=483 7229 7548; .
, 42 7865 8239 9804
42 191511093 11.400
43 5180 7096 9481' _
Date Recue/Date Received 2021-10-07
22
44 '1431.5786 8924
45 7435757 6525
46 33114475 7204
47 1152 8958 11020
48 -1915'2903 4005
49 577610885 12531
50. "2594 9998 22742
51 159 260212879
52 853. 3281 3762
51 5201 5798 6413
1.=
54 .3682 6662 12047
55 , 4133 5775 9657
55 228,6874 11183
57 7433172311)304
58 7735 &an 12734
69 26444611 11179
60 '3909 7163 12804
61 60029704 11060
_
62 5864 6856 7681
_
63 3552 5368 7605
64 2645 1667 446%
65 2423 4203 1111
66 244 1355 4691.
67 1106 2/78 5371
68 391151J10125
OW '250925910603
70 3435 4514 5924
71 1742 8045 9521
72 7661=8875,11451,
'73 4023 61086911
74 8621 10184 21550 .
¨
75 '67261886112348
16 3223 5201 1368
77 =1 1137 5358 ,
78 391.2424 8537
79 3256 7508 18044
80 1980 2219 4569
81 2463 5669 20319
82 '28033114,12808
33 9578 9642 11539. . . .
84 _829 4585 7923-
85, 5.97.379. 55.76
85 10675709 6867
87 . ,1175 4744,17719 _
38 .2092518.6756:.
85 '2105 10526 11153
90 5192166961.0749
M .6260 7641 6233
92 2998 3094 11234
=
Date Recue/Date Received 2021-10-07
23
93 3398 6465 11494
94 65741044* 12160
95 zri41.075.5 12780
96 1028 7958 10825
97 8545 8602 10793
9i 392 3338 21417
99 5539 9291 12571
100 1067 791* 8934
101 1064 2648 22753
102 5075 6656 12598
log 5504 6/93 16/71
104 1951 7256 7355
4389 4780 7889
106 5264804 9141
107 1238 3548 10464
108 2587M24 12557
109 5560 5903 11963
110 1134 2570 3297
111 10841 11583 12157
112 1253 9585,12912
113 37447898 10646.
114 45 9074 10315
115 1051 6168 10039
116 2242 8394 12712
117 3598 9025 12651
118 2295 1540 5520
/15 19144378 12423
120 11663635 12759
121 5177 958611143
122 943 3590 11649
123 4664 6905 10454
124 5852 604218421
,125 60956265 12349
120 2070 7171 6561
127 71812234 12716
128 S12 10667 11353
129 3629 6485 7045
130 2880 8865 11456
131 4490 10220 12795
132 54408519 9103
133 5252 7543.12411
134 516 7/79 3.0940
135 2515 5843 9202
136 4664 9994 10666
137 573 2270 3324
130 78708117 van
135 68567638 12909
140 15837659 10791
141 ai41 9035 12555
142 3903 5485 999,2
143 446711998 12904
In the above-described examples, the length of the LDPC codeword is 64800 and
the code
rate is 6/15, 8/15, 10/15, and 12/15. However, this is merely an example and
the position of 1 in
Date Recue/Date Received 2021-10-07
24
the information word submatrix 210 may be defined variously when the length of
the LDPC
codeword is 16200 or the code rate has different values.
According to an exemplary embodiment, even when the order of numbers in a
sequence
corresponding to the ith column group of the parity check matrix 200 as shown
in the above-
described Tables 4 to 8 is changed, the changed parity check matrix is a
parity check matrix used
for the same code. Therefore, a case in which the order of numbers in the
sequence
corresponding to the it column group in Tables 4 to 8 is changed is covered by
the inventive
concept.
= According to an exemplary embodiment, even when the arrangement order of
sequences
corresponding to each column group is changed in Tables 4 to 8, cycle
characteristics on a graph
of a code and algebraic characteristics such as degree distribution are not
changed. Therefore, a
case in which the arrangement order of the sequences shown in Tables 4 to 8 is
changed is also
covered by the inventive concept.
In addition, even when a multiple of Qicipc is equally added to all sequences
corresponding to a
certain column group in Tables 4 to 8, the cycle characteristics on the graph
of the code or the
algebraic characteristics such as degree distribution are not changed.
Therefore, a result of
equally adding a multiple of Okipc to the sequences shown in Tables 4 to 8 is
also covered by the
inventive concept. However, it should be noted that, when the resulting value
obtained by adding
the multiple of Qkipc to a given sequence is greater than or equal to (Nlidpc-
Kidp,), a value obtained
by applying a modulo operation for (N1dpe-Ktdpe) to the resulting value should
be applied instead.
Once positions of the rows where 1 exists in the Oth column of the ith column
group of the
information word submatrix 210 are defined as shown in Tables 4 to 8,
positions of rows where 1
exists in another column of each column group may be defined since the
positions of the rows
where 1 exists in the Oth column are cyclic-shifted by Qidpc in the next
column.
For example, in the case of Table 4, in the 0th column of the 0th column group
of the
information word submatrix 210, 1 exists in the 1606th row, 3402nd row, 4961st
In this case, since Qidpc.,--(Nidpc-Kidr.c)/M464800-25920)/360=108, the
indexes of the rows
where 1 is located in the 1st column of the Oth column group may be
1714(=1606+108),
3510(=3402+108), 5069(=4961-F108),..., and the indexes of the rows where 1 is
located in the
2hd column of the Oth column group may be 1822(=1714+108), 3618(.3510+108),
5177(=5069+108),....
Date Regue/Date Received 2021-10-07
25
In the above-described method, the indexes of the rows where 1 is located in
all rows of each
column group may be defined.
The parity submatrix 220 of the parity check matrix 200 shown in FIG. 2 may be
defined as
follows:
The parity submatrix 220 includes N1-K1 number number of columns (that is,
Kkipcth column to
(Nipdc-1)th column), and has a dual diagonal or staircase configuration.
Accordingly, the degree of
columns except the last column (that is, (Nidpc-1)6 column) from among the
columns included in
the parity submatrix 220 is 2, and the degree of the last column is 1.
As a result, the information word submatrix 210 of the parity check matrix 200
may be
defined by Tables 4 to 8, and the parity submatrix 220 of the parity check
matrix 200 may have
a dual diagonal configuration.
When the columns and rows of the parity check matrix 200 shown in FIG. 2 are
permutated
based on Equation 4 and Equation 5, the parity check matrix shown in FIG. 2
may be changed to
a parity check matrix 300 shown in FIG. 3.
(0 i <m,05. j Qkõ,c)... (4)
K ldpc Qldpc k +1 K !roc + M = 1+ k (0 < M ,0 1 < Qupc) (5)
The method for permutating based on Equation 4 and Equation 5 will be
explained below.
Since row permutation and column permutation apply the same principle, the row
permutation
will be explained by the way of an example.
In the case of the row permutation, regarding the Xth row, i and j satisfying
X = adpc X i + fare calculated and the VI' row is permutated by assigning the
calculated i and j to
Mx j+i. For example, regarding the 7th row, i and j satisfying 7 = 2 x i + j
are 3 and 1,
respectively. Therefore, the 7th row is permutated to the 136 row (10 x1+ 3
=13 ).
When the row permutation and the column permutation are performed in the above-
described
method, the parity check matrix of FIG. 2 may be converted into the parity
check matrix of FIG.
3.
Referring to FIG. 3, the parity check matrix 300 is divided into a plurality
of partial blocks,
and a quasi-cyclic matrix of M xM corresponds to each partial block.
Accordingly, the parity check matrix 300 having the configuration of FIG. 3 is
formed of
matrix units of M x M. That is, the submatrices of M x M are arranged in the
plurality of partial
Date Recue/Date Received 2021-10-07
26
blocks, constituting the parity check matrix 300.
Since the parity check matrix 300 is formed of the quasi-cyclic matrices of
MxM, M
number of columns may be referred to as a column block and M number of rows
may be referred
to as a row block. Accordingly, the parity check matrix 300 having the
configuration of FIG. 3 is
formed of Nqc ediumn=NidpciM number of column blocks and Nq,=Npuity/M number
of row
blocks.
Hereinafter, the submatrix of M xM will be explained.
First, the (Nqc_column-1) th column block of the Oth row block has a form
shown in Equation 6
presented below:
0 0 ... 0 0
10.,.00
A = 0 1 ... 00
0 0 ... 1 0
As described above, A 330 is an MxM matrix, values of the 0th row and the (M-
1)th column
are all "0", and, regarding 0< i<(M-2), the (i+1)th row of the ith column is
"1" and the other
values are "0".
Second, regarding 0<i<(Nidpe-Kidp,)/M-1 in the parity submatrix 320, the ith
row block of the
(KidixiM
+i)111 column block is configured by a unit matrix /,õõõ, 340. In addition,
regarding
0<i<(Nidpc-Kidpc)/M-2, the (i-i-1)th row block of the (Kidpc/M+i)th column
block is configured by a
unit matrix /,õ, 340.
Third, a block 350 constituting the information word submatrix 310 may have a
cyclic-shifted
format of a cyclic matrix P, P 41 , or an added format of the cyclic-shifted
matrix P of the
cyclic matrix P (or an overlapping format).
For example, a format in which the cyclic matrix P is cyclic-shifted to the
right by 1 may be
expressed by Equation 7 presented below:
0 1 0 0
001...0
P=
000...1
1 0 0 0
- = = = (7)
Date Recue/Date Received 2021-10-07
27
The cyclic matrix P is a square matrix having an M xM size and is a matrix in
which a
weight of each of M number of rows is 1 and a weight of each of M number of
columns is 1.
When aki is 0, the cyclic matrix P, that is, P indicates a unit matrix 'M','
and when aij is co, 13 is
a zero matrix.
A submatrix existing where the ith row block and the jth column block
intersect in the parity
check matrix 300 of FIG. 3 may be Pa" . Accordingly, i and j indicate the
number of row blocks
and the number of column blocks in the partial blocks corresponding to the
information word.
Accordingly, in the parity check matrix 300, the total number of columns is
INlidpc=Mx Nqc_cdurnm
and the total number of rows is Npanty=M x Nqc_row. That is, the parity check
matrix 300 is formed
of Nqc_cotumn number of "column blocks" and Nqc_row number of "row blocks".
Hereinafter, a method for performing LDPC encoding based on the parity check
matrix 200
as shown in FIG. 2 will be explained. An LDPC encoding process when the parity
check matrix
200 is defined as shown in Table 4 by way of an example will be explained for
the convenience
of explanation.
First, when information word bits having a length of Kid are [io, 2, =
iKwe_1], and parity
bits having a length of Nidpc-Kkipc are [Po, P17 ], the
LDPC encoding is performed
by the following process.
Step 1) Parity bits are initialized as '0'. That is, po= pi= 132=...= Pkix-
Kko,..1 =0.
Step 2) The 0th information word bit io is accumulated in a parity bit having
the address of the
parity bit defined in the first row (that is, the row of i=0) of table 4 as
the index of the parity bit.
This may be expressed by Equation 8 presented below:
Date Recue/Date Received 2021-10-07
28
P1606 = P16060 0 P24533= P 24533 0 i 0
P3402= P3402e1 0 P25376= P25376 0 i 0
P4961 = P4961010 P25667= P25667010
P6751 = P6751010 P26836.= P= 26836 0 i
P7132= P7132010 P31799= P31799810
P11516 = P11516 e'0 P34173= P34173 0 i 0
P12300= P12300 Oi 0 P35462= P35462 0 i
P12482= P1248210 P36153= P= 36153@0
P12592= P12592 0 i 0 P36740= P 36740 0 i 0
l3342= P13342 0 i 0 P37085= P37085010
P13764= P13764 e10 P37152= P37152810
P14123= P14123 I0 P37468= P37468010
P21576= P21576 010 P37658= P= 37658010
P23946= P23946 0 0 =
= = .(8)
Herein, io is a 0th information word bit, p, is an ith parity bit, and e is a
binary operation.
According to the binary operation, le 1 equals 0, 1 ED 0 equals 1, 0 e 1
equals 1, 0 0 equals 0.
Step 3) The other 359 information word bits in, (m=1, 2, ..., 359) are
accumulated in the
parity bit. The other information word bits may belong to the same column
group as that of io. In
this case, the address of the parity bit may be determined based on Equation 9
presented below:
(x + (m mod 360) x adr)MOC(N K idpc) . . . (9)
Herein, x is an address of a parity bit accumulator corresponding to the
information word bit
je, and (Li, is a size by which each column is cyclic-shifted in the
information word submatrix,
and may be 108 in the case of table 4. In addition, since m=1, 2, ..., 359, (m
mod 360) in
Equation 9 may be regarded as m.
As a result, information word bits in, (m=1,2,..., 359) are accumulated in the
parity bits
having the address of the parity bit calculated based on Equation 9 as the
index. For example, an
operation as shown in Equation 10 presented below may be performed for the
information word
bit
Date Recue/Date Received 2021-10-07
29
P1714 = P1714 1 P24641= P24641 i 1
P3510 P35100 1 P25484= P25484 0 1
P5059 = P50690 i 1 P25775= P25775 e i 1
P6859 = P68590 i 1 P25944= P25944 1
P7240 = P72400 i 1 P31907= P31907 011
P11624= P11624 0 i 1 P34281= P34281 0 i 1
P12408= P12408 0 i 1 P35570= P35570 011
P12590= P12590 011 P36261= 36261e'1P
P12700= P12700 ei 1 P36848= P36848 i 1
P13450= P13450 0 i 1 P37193= P37193 011
P13872= P13872 eil P37260= P37260 0 i 1
P14231= P14231 011 P37576= P37576 0 i 1
P21684 P21684 0i 1 P37766= P37766 0i 1
P24054= P24054 0 i 1
...(10)
Herein, i is a 1st information word bit, pi is an ith parity bit, and is a
binary operation.
According to the binary operation, 19 1 equals 0, 14: 0 equals 1, 0 8 1 equals
1, oe 0 equals 0.
Step 4) The 360th information word bits 1360 is accumulated in a parity bit
having the address
of the parity bit defined in the 2nd row (that is, the row of i=1) of table 4
as the index of the parity
bit.
Step 5) The other 359 information word bits belonging to the same group as
that of the
information word bit i360 are accumulated in the parity bit. In this case, the
address of the parity
bit may be determined based on Equation 9. However, in this case, x is the
address of the parity
bit accumulator corresponding to the information word bit i360.
Step 6) Steps 4 and 5 described above are repeated for all of the column
groups of table 4.
Step 7) As a result, a parity bit pi is calculated based on Equation 11
presented below. In this
case, i is initialized as 1.
pi= pie) N ¨ tdp, ¨1... (11)
In Equation 11, pi is an ith parity bit, Nidpc is a length of an LDPC
codeword, Kit is a length
of an information word of the LDPC codeword, and ED is a binary operation.
As a result, the encoder 110 may calculate the parity bits according to the
above-described
Date Recue/Date Received 2021-10-07
30
method.
In another example, a parity check matrix according to an exemplary embodiment
may have a
configuration as shown in FIG. 4.
Referring to FIG. 4, the parity check matrix 400 may be formed of 5 matrices
A, B, C, Z, and
D. Hereinafter, the configuration of each matrix will be explained to explain
the configuration of
the parity check matrix 400.
First, M1, M2, Qt, and Q2, which are parameter values related to the parity
check matrix 400
as shown in FIG. 4, may be defined as shown in table 9 presented below
according to the length
and the code rate of the LDPC codeword.
[Table 9]
Rate. Length Sizes
1/15 16200 2520 12600 7 35
64800 1080 59400 3 165
2/16 16200 3240 10800 9 30
64800 1800 54360 5 151
1080 11.880 3 33
3115 6416820000
1800. 50040 5 139
/ 16200 1080 10800 3 30
415
64800 1800 45720 5 127
16200, 720 10080. 2 28
5/15 64800
1440 41760 4 116
= 16200 1080 8640 3 24
6/15 ' 64800 1080 . 37800 3 105
The matrix A is formed of K number of columns and g number of rows, and the
matrix C is
formed of K+g number of columns and N-K-g number of rows. Herein, K is a
length of
information word bits, and N is a length of the LDPC codeword.
Indexes of rows where 1 is located in the 0th column of the ith column group
in the matrix A
and the matrix C may be defined based on table 10 according to the length and
the code rate of
the LDPC codeword. In this case, an interval at which a pattern of a column is
repeated in each
of the matrix A and the matrix C, that is, the number of columns belonging to
the same group,
may be 360.
For example, when the length N of the LDPC codeword is 64800 and the code rate
is 6/15,
the indexes of rows where 1 is located in the 0th column of the ith column
group in the matrix A
and the matrix C are defined as shown in table 10 presented below:
[Table 10]
Date Recue/Date Received 2021-10-07
31
Index of row where us located in the 0th column of the ith column group
:0 712733566867.11964 1737a 13159 26410 284642E477
1 257322 672 253 5316 65785037 10131 13845 36497
'2 233765 904 1366 3875 1314515405 18620 2391930825.
'3 100224 405 127761386814787 16781 23886 29099 31419
.4 23496.891 2512 12589 14074 19392-20339 27658 28684:
. 5 47371/75912854374 98981255113814 24242 32728
511557 31511823 17106-17500 19138 22315 zoos 26448
7 45 733 8.36 1923 3727174M 25746 3380535995 35657
8 = 17417 675267039125145'13609 239953107536624
9 72751773 153,71732428512 30666-30934 3101631849
,2S734594'14041 1914124914 26864 28809 32Q55 34753
ii .99 241 491 26509670 17433 177391898322235 30742.
= 12 198299 655 5737830410917 16092 19387 2075537690'
13 351 916 926 18151 21708 23216 30321 33578 3405237949
14 54332 3732010 3332 562316301 34337.36451 37851
139257106811090'20189 2.9694:29732.3264035133 36404
= 13 457 8859021154956 5422 5949 1757026671 32387
- 17 137571)5195006 6099797514429 1550 25443 32789
r 18 46282 287162581831520258 27186 2745428429 18266
19 4454881058 13689978112.54 20354 2469.5 31382835330
134 9C0 93112518 14644 17715.19523 21111. 33858 34570
-21 6266 5868020-.20270 23831 31041 31965 32224 35189
22 174290 7846740 1467317642 2628627382 3344734E79
23 332 675 1033 183312004 15439 20765 31721 3471598E63
= .24 527 558332 3867 5311 8317108E3 18466 1E42725377
431 780 10211112 23757675 13059 17793 2057020771
= W. = 339 536 1015 57266916 1054614487 21156 21123 32614
, 27 453830 10787511 1116112152 1.2705 1746128367 44632.
= /5 /12515 9595591E022 33E21400823445 25127 2901/.
19 . 37 19378110257738 11157 22276 227612E23130394
_30 .234 257 1045 1307 2908 6337 26530 28142 3412935997:
.31 _35'46978991299781256717843 24194 34187 35206
-32 39969987 502710347 1465718859 28075 28214-36323:
33. 275477823 11376180712899730521 31661 3194112116
34 115580 966 11733 12013 12760 13351 19372.12534 35504
^ 35 7-608911046 11150 203513 21631.29930 3101433050.34340
, 36; = 3=60389 10575316 5918 14186 16404r5144534021 35771
t 37 306344679 52246674 10105 18751 255833058836943".
38 103 171 10168701174112144 1947(120955 22495 27377
.39 818832 884 3883 14279 14487 22505 28129'28719 31246-
40 .2.1541L7505886 25612 28556 322131214)4 35901 36130
. 41 229489 106723855SW 2Mfis 23431 243102 30147 32859'
42 288664 980 8138 8531 21676.23187 26708 28798.34490'
43 -89552 847 56589889 23949 2622517089.31236 3÷23
44 '6642443 3339%13 1477 14944-1546419185 25963
45 605875 93i15662 175692560 28220.3343235738 37382
' 46 346 423 806 56697668 8789 9928 19724 24039 21693
; 47 = 46 450 1055.3512.7389 754920216 221602822135431
48 18m3&- 824 1516450813568 19683 21150.30311 33480
.2575893528568187 9052.21850 29941'8321714293
50 34952411.625981895 6435897410649 1532.1.7378
Date Recue/Date Received 2021-10-07
32
51 3364117871 3582 9630 10885=14392 18027-19203 36659,
52 1768010g 17301937927064 .2.8164 28720 3225725495
55.. 234 a9py1i75 9431.9605-9760 0113 11332 12679 24266.
54 . 516 638733585119871'22740 2579136152 3266935566'
55 ,253 8,30.879 2066 15885 22952 23765253891465637293
56' 94954.99820O33369 6870 732119856.31373 3488W
57: :79 350933 4853 525211932.12058 21631 24552 24876
58' :246647778 4936 19391,10656 13194 32335.32360.34179,
59! :149 33 9436 6971-835687151157722376 226134 31249
=
Ee. = 36 149 220 6936 1840B 19192 1928623063,28411 35312'
61:, 273 6831042 6327.10011 18041 21704 2O97 3,6791,33.4.4
6.1' 46 138 7222701 10164 13002 19930 26625 2E4%28165";
62: . 121009 1040 1990 2130 5392. 21215226251201129288
64. 125 241'811.2245 3199 841521133 267862722638838
65' 45476 1075-739615.141'20414 31244 33336 35004 38391
66 :432578667.-1343 10466 11.314 115O723314 2772034465
67. .248.291.555.1971.3989 891212000 19998 23932-34652
68., :68 694 837 2246747278711107512868 2093735591
= 272924 94/.2030 4360:62039737,19705 1902.5E09
70:' 21314.979 2311:26324109:19527 2192031413:34277
= 71 197 253104:1249,4315 1002114358 20559:270993057_5;
72 = . 9802 16164 17,499 22378 2240322704 26742 25108.
73: . 9064 10104 12305 14157:16156. 2600 2.2613.24326
. 74- 5178 631910239.193462562B 30577 31110:32291'
In the above-described example, the length of the LDPC codeword is 64800 and
the code rate
6/15. However, this is merely an example and the indexes of rows where 1 is
located in the Oth
column of the ith column group in the matrix A and the matrix C may be defined
variously when
the length of the LDPC codeword is 16200 or the code rate has different
values.
Hereinafter, positions of rows where 1 exists in the matrix A and the matrix C
will be
explained with reference to table 10 by way of an example.
Since the length N of the LDPC codeword is 64800 and the code rate is 6/15 in
table 10,
M1=1080, M2=37800, Qi=3, and 02=105 in the parity check matrix 400 defined by
table 10 with
reference to table 9.
Herein, Qi is a size by which columns of the same column group are cyclic-
shifted in the
matrix A, and 02 is a size by which columns of the same column group are
cyclic-shifted in the
matrix C.
In addition, 01=Mi/L, 02=M2/L, Mi=g, and M2=N-K-g, and L is an interval at
which a
pattern of a column is repeated in the matrix A and the matrix C, and for
example, may be 360.
The index of the row where 1 is located in the matrix A and the matrix C may
be determined
based on the Mi value.
For example, since M1=1080 in the case of table 10, the positions of the rows
where 1 exists
Date Recue/Date Received 2021-10-07
33
in the 0th column of the ith column group in the matrix A may be determined
based on values
smaller than 1080 from among the index values of table 10, and the positions
of the rows where
1 exists in the 0th column of the ith column group in the matrix C may be
determined based on
values greater than or equal to 1080 from among the index values of table 10.
Specifically, in table 10, the sequence corresponding to the Oth column group
is "71, 276, 856,
6867, 12964, 17373, 18159, 26420, 28460, 28477". Accordingly, in the case of
the 0th column of
the 0th column group of the matrix A, 1 may be located in the 71st row, 276th
row, and 856th row,
and, in the case of the Oth column of the 0th column group of the matrix C, 1
may be located in
the 6867th row, 12964th row, 17373'I row, 18159th row, 26420th row, 28460'
row, and 28477th
row.
Once positions of 1 in the 0th column of each column group of the matrix A are
defined,
positions of rows where 1 exists in another column of each column group may be
defined by
cyclic-shifting from the previous column by Q1. Once positions of 1 in the 0th
column of each
column group of the matrix C are defined, position of rows where 1 exists in
another column of
each column group may be defined by cyclic-shifting from the previous column
by Q2.
In the above-described example, in the case of the 0th column of the 0th
column group of the
matrix A, 1 exists in the 71st row, 276th row, and 856th row. In this case,
since Q1=3, the indexes
of rows where 1 exists in the 1st column of the 0th column group are
74(=71+3), 279(.276+3),
and 859(=856+3), and the index of rows where 1 exists in the 2'1 column of the
0th column group
are 77(=74+3), 282 (=279+3), and 862(=859+3).
In the case of the Oth column of the 0th column group of the matrix C, 1
exists in the 6867th
row, 12964th row, 17373"1 row, 18159th row, 26420th row, 28460th row, and
28477th row. In this
case, since 02=105, the index of rows where 1 exists in the lst column of the
Oth column group
are 6972(=6867+105), 13069(.12964+105), 17478(=17373+105), 18264(=18159+105),
26525(=26420+105), 28565(=28460+105), 28582(=28477+105), and the indexes of
rows where
1 exists in the ri column of the 0th column group are 7077(.6972+105),
13174(.13069+105),
17583(.17478+105), 18369(=18264+105), 26630(=26525+105), 28670(=28565+105),
28687(=28582+105).
In this method, the positions of rows where 1 exists in all column groups of
the matrix A and
the matrix C are defined.
The matrix B may have a dual diagonal configuration, the matrix D may have a
diagonal
Date Recue/Date Received 2021-10-07
34
configuration (that is, the matrix D is an identity matrix), and the matrix Z
may be a zero matrix.
As a result, the parity check matrix 400 shown in FIG. 4 may be defined by the
matrices A, B,
C, D, and Z having the above-described configurations.
Hereinafter, a method for performing LDPC encoding based on the parity check
matrix 400
shown in FIG. 4 will be explained. An LDPC encoding process when the parity
check matrix 400
is defined as shown in Table 10 by way of an example will be explained for the
convenience of
explanation.
For example, when an information word block S=(so, SKI) is
LDPC-encoded, an
LDPC codeword A =
A.õ...,2,,,_,)=(sõsõ...,Sõ,p0,pi,...,Pm,,m2_1) including a parity bit
P=(1)43,P1,¨,Pmi+m2-0 may be generated.
M1 and M2 indicate the size of the matrix B having the dual diagonal
configuration and the
size of the matrix C having the diagonal configuration, respectively, and
Mi=g, M2=N-K-g.
A process of calculating a parity bit is as follows. In the following
explanation, the parity
check matrix 400 is defined as shown in table 10 by way of an example, for the
convenience of
explanation.
Step 1) X and p are initialized as ?1=s1 (i=0,1,..., K-1), pi=0 (j=0,1,...,
M1+M2-1).
Step 2) The Oth information word bit X0 is accumulated in the address of the
parity bit defined
in the first row (that is, the row of i=0) of table 10. This may be expressed
by Equation 12
presented below:
P71= P710 0 P17373= P173730 X0
P276= P276 0 0 P18159= Pi8iss0Xo
PM= P lt P26420= P26420 0 A- 0
p6867= p681 ,0 P28460= P284600 X0
P12984= P12964 0)\-0 P28477= P284770x0
...(12)
Step 3) Regarding the next L-1 number of information word bits X,.õ (m=1, 2,
..., L-1), X,õ is
accumulated in the parity bit address calculated based on Equation 13
presented below:
(x +mx Qi)modMi (if x <MO
M1 +{(¨M1 +m x Q2)modM2} (if x )...(13)
Herein, x is an address of a parity bit accumulator corresponding to the 0th
information word
bit 4.
Date Recue/Date Received 2021-10-07
35
In addition, Qi=MilL and Q2=M2/L. In addition, since the length N of the LDPC
codeword is
64800 and the code rate is 6/15 in table 10, M1=1080, M2=37800, Qi=3, Q2=105,
and L=360
with reference to table 9.
Accordingly, an operation as shown in Equation 14 presented below may be
performed for
the 1st information word bit
P74= P740 A, 1 P17478= P17478 A. 1
P2791.7* P279 A-1 P18264= P18264 OA- 1
P859= P859 A-1 P26525= P26525 A- 1
P6972 = P69720A- 1 P28565= P28565 0 A- 1
P13069= P13069 0 A- 1 P28582= P28582 e ...(14)
Step 4) Since the same address of the parity bit as in the second row (that is
the row of i=1) of
table 10 is given to the Lth information word bit XL, in a similar method to
the above-described
method, the address of the parity bit regarding the next L-1 number of
information word bits A,
(m=L+1, L+2, 2L4) is
calculated based on Equation 13. In this case, x is the address of the
parity bit accumulator corresponding to the information word bit XL, and may
be obtained based
on the second row of table 10.
Step 5) The above-described processes are repeated for L number of new
information word
bits of each group by considering new rows of table 10 as the address of the
parity bit
accumulator.
Step 6) After the above-described processes are repeated for the codeword bits
Xo to 44,
values regarding Equation 15 presented below are calculated in sequence from
i=1:
P, = ED P,i(i =1,2,...,M, ¨1) ...(15)
Step 7) Parity bits /LK to
corresponding to the matrix B having the dual diagonal
configuration are calculated based on Equation 16 presented below:
2K+Lxt+s = PQ,xS+t (0 s <L,0 t <Q1) ...(16)
Step 8) The address of the parity bit accumulator regarding L number of new
codeword bits
A.K to 2K+mi_1 of each group is calculated based on table 10 and Equation 13.
Step 9) After the codeword bits Xic to Ax+mi_i are calculated, parity bitsKM
to .11e+m1+m24
corresponding to the matrix C having the diagonal configuration are calculated
based on
Date Recue/Date Received 2021-10-07
36
Equation 17 presented below:
il'IC+Mi+Lxt+s = P (0 5_ s <L,0 5_ t <Q2) ...(17)
As a result, the parity bits may be calculated in the above-described method.
Referring back to FIG. 1, the encoder 110 may perform the LDPC encoding by
using various
code rates such as 3/15, 4/15, 5/15, 6/15, 7/15, 8/15, 9/15, 10/15, 11/15,
12/15, 13/15, etc. In
addition, the encoder 110 may generate an LDPC codeword having various lengths
such as
16200, 64800, etc., based on the length of the information word bits and the
code rate.
In this case, the encoder 110 may perform the LDPC encoding by using the
parity check
matrix, and the parity check matrix is configured as shown in FIGS. 2 to 4.
In addition, the encoder 110 may perform Bose, Chaudhuri, Hocquenghem (BCH)
encoding
as well as LDPC encoding. To achieve this, the encoder 110 may further include
a BCH encoder
(not shown) to perform BCH encoding.
In this case, the encoder 110 may perform encoding in an order of BCH encoding
and LDPC
encoding. Specifically, the encoder 110 may add BCH parity bits to input bits
by performing
BCH encoding and LDPC-encodes the information word bits including the input
bits and the
BCH parity bits, thereby generating the LDPC codeword.
The interleaver 120 interleaves the LDPC codeword. That is, the interleaver
120 receives the
LDPC codeword from the encoder 110, and interleaves the LDPC codeword based on
various
interleaving rules.
In particular, the interleaver 120 may interleave the LDPC codeword such that
a bit included
in a predetermined bit group from among a plurality of bit groups constituting
the LDPC
codeword (that is, a plurality of groups or a plurality of blocks) is mapped
onto a predetermined
bit of a modulation symbol. Accordingly, the modulator 130 may map a bit
included in a
predetermined group from among the plurality of groups of the LDPC codeword
onto a
predetermined bit of the modulation symbol.
To achieve this, as shown in FIG. 5, the interleaver 120 may include a parity
interleaver 121,
a group interleaver (or a group-wise interleaver 122), a group twist
interleaver 123 and a block
interleaver 124.
The parity interleaver 121 interleaves the parity bits constituting the LDPC
codeword.
Specifically, when the LDPC codeword is generated based on the parity check
matrix 200
having the configuration of FIG. 2, the parity interleaver 121 may interleave
only the parity bits
Date Recue/Date Received 2021-10-07
37
of the LDPC codeword by using Equations 18 presented below:
ci for 0<i<ICIdpc, and
= c,c, ., for 05_s<M, 05_t<Q1dp, ... (18),
where M is an interval at which a pattern of a column group is repeated in the
information word submatrix 210,
that is, the number of columns included in a column group (for example,
M=360), and Oidp. is a size by which each
column is cyclic-shifted in the information word submatrix 210. That is, the
parity interleaver 121 performs parity
interleaving with respect to the LDPC codeword c=(co, CN,oci), and
outputs Uquo, UN4).
The LDPC codeword parity-interleaved in the above-described method may be
configured
such that a predetermined number of continuous bits of the LDPC codeword have
similar
decoding characteristics (cycle distribution, a degree of a column, etc.).
For example, the LDPC codeword may have the same characteristics on the basis
of M
number of continuous bits. Herein, M is an interval at which a pattern of a
column group is
repeated in the information word submatrix 210 and, for example, may be 360.
Specifically, a product of the LDPC codeword bits and the parity check matrix
should be "0".
This means that a sum of products of the ith LDPC codeword bit, c,;(i=0, 1,
..., N1dpc-1) and the ith
column of the parity check matrix should be a "0" vector. Accordingly, the ith
LDPC codeword
bit may be regarded as corresponding to the ith column of the parity check
matrix.
In the case of the parity check matrix 200 of FIG. 2, M number of columns in
the information
word submatrix 210 belong to the same group and the information word submatrix
210 has the
same characteristics on the basis of a column group (for example, the columns
belonging to the
same column group have the same degree distribution and the same cycle
characteristic).
In this case, since M number of continuous bits in the information word bits
correspond to the
same column group of the information word submatrix 210, the information word
bits may be
formed of M number of continuous bits having the same codeword
characteristics. When the
parity bits of the LDPC codeword are interleaved by the parity interleaver
121, the parity bits of
the LDPC codeword may be formed of M number of continuous bits having the same
codeword
characteristics.
However, regarding the LDPC codeword encoded based on the parity check matrix
300 of
FIG. 3 and the parity check matrix 400 of FIG. 4, parity interleaving may not
be performed. In
this case, the parity interleaver 121 may be omitted.
The group interleaver 122 may divide the parity-interleaved LDPC codeword into
a plurality
Date Recue/Date Received 2021-10-07
38
of bit groups and rearrange the order of the plurality of bit groups in bit
group wise (or bit group
unit). That is, the group interleaver 122 may interleave the plurality of bit
groups in bit group
wise.
To achieve this, the group interleaver 122 divides the parity-interleaved LDPC
codeword into
a plurality of bit groups by using Equation 19 or Equation 20 presented below.
Xi ={, i 1 =[---k ,0 5 k < A T 4}for0 5 j < N ealip
360 ... (19)
Xj = tuk 1360 x j k < 360 x (j +1),0 k < . I s I upcj for 5. j < N grõõp ...
(20)
where Ngroup is the total number of bit groups, X is the jth bit group, and uk
is the kth LDPC codeword bit input to
the group interleaver 122.1n addition, ¨k is the largest integer below k/360.
i
360
Since 360 in these equations indicates an example of the interval M at which
the pattern of a
column group is repeated in the information word submatrix, 360 in these
equations can be
changed to M.
The LDPC codeword which is divided into the plurality of bit groups may be as
shown in FIG.
6.
Referring to FIG. 6, the LDPC codeword is divided into the plurality of bit
groups and each
bit group is formed of M number of continuous bits. When M is 360, each of the
plurality of bit
groups may be formed of 360 bits. Accordingly, the bit groups may be formed of
bits
corresponding to the column groups of the parity check matrix.
Specifically, since the LDPC codeword is divided by M number of continuous
bits, Kldpc
number of information word bits are divided into (Kidpc/M) number of bit
groups and Nicipc-Kidpc
number of parity bits are divided into (Nicipc-Kkipc)/M number of bit groups.
Accordingly, the
LDPC codeword may be divided into (Nidpc/M) number of bit groups in total.
For example, when M=360 and the length INIkipc of the LDPC codeword is 16200,
the number
of groups Ngroupg constituting the LDPC codeword is 45(.16200/360), and, when
M=360 and the
length Nidpc of the LDPC codeword is 64800, the number of bit groups Ngroup
constituting the
LDPC codeword is 180(=64800/360).
As described above, the group interleaver 122 divides the LDPC codeword such
that M
number of continuous bits are included in a same group since the LDPC codeword
has the same
codeword characteristics on the basis of M number of continuous bits.
Accordingly, when the
Date Recue/Date Received 2021-10-07
39
LDPC codeword is grouped by M number of continuous bits, the bits having the
same codeword
characteristics belong to the same group.
In the above-described example, the number of bits constituting each bit group
is M. However,
this is merely an example and the number of bits constituting each bit group
is variable.
For example, the number of bits constituting each bit group may be an aliquot
part of M. That
is, the number of bits constituting each bit group may be an aliquot part of
the number of
columns constituting a column group of the information word submatrix of the
parity check
matrix. In this case, each bit group may be formed of aliquot part of M number
of bits. For
example, when the number of columns constituting a column group of the
information word
submatrix is 360, that is, M=360, the group interleaver 122 may divide the
LDPC codeword into
a plurality of bit groups such that the number of bits constituting each bit
group is one of the
aliquot parts of 360.
In the following explanation, the number of bits constituting a bit group is M
by way of an
example, for the convenience of explanation.
Thereafter, the group interleaver 122 interleaves the LDPC codeword in bit
group wise.
Specifically, the group interleaver 122 may group the LDPC codeword into the
plurality of bit
groups and rearrange the plurality of bit groups in bit group wise. That is,
the group interleaver
122 changes positions of the plurality of bit groups constituting the LDPC
codeword and
rearranges the order of the plurality of bit groups constituting the LDPC
codeword in bit group
wise.
Herein, the group interleaver 122 may rearrange the order of the plurality of
bit groups in bit
group wise such that bit groups including bits mapped onto the same modulation
symbol from
among the plurality of bit groups are spaced apart from one another at
predetermined intervals.
In this case, the group interleaver 122 may rearrange the order of the
plurality of bit groups in
bit group wise by considering at least one of the number of rows and columns
of the block
interleaver 124, the number of bit groups of the LDPC codeword, and the number
of bits
included in each bit group, such that bit groups including bits mapped onto
the same modulation
symbol are spaced apart from one another at predetermined intervals.
To achieve this, the group interleaver 122 may rearrange the order of the
plurality of groups
in bit group wise by using Equation 21 presented below:
Yi = X,01)(0 j < N )
gr "P . . . (21),
Date Recue/Date Received 2021-10-07
40
where Xi is the jth bit group before group interleaving, and Yi is the jth bit
group after group
interleaving. In addition, n(j) is a parameter indicating an interleaving
order and is determined by
at least one of a length of an LDPC codeword, a modulation method, and a code
rate. That is,
7r(j) denotes a permutation order for group wise interleaving.
Accordingly, X,0 is a m(j)th bit group before group interleaving, and Equation
21 means that
the pre-interleaving it(j)th bit group is interleaved into the jth bit group.
According to an exemplary embodiment, an example of 7r(j) may be defined as in
Tables 11
to 22 presented below.
In this case, x(j) is defined according to a length of an LPDC codeword and a
code rate, and a
parity check matrix is also defined according to a length of an LDPC codeword
and a code rate.
Accordingly, when LDPC encoding is performed based on a specific parity check
matrix
according to a length of an LDPC codeword and a code rate, the LDPC codeword
may be
interleaved in bit group wise based on 'E(j) satisfying the corresponding
length of the LDPC
codeword and code rate.
For example, when the encoder 110 performs LDPC encoding at a code rate of
6/15 to
generate an LDPC codeword of a length of 64800, the group interleaver 122 may
perform
interleaving by using Ir(j) which is defined according to the length of the
LDPC codeword of
16200 and the code rate of 6/15 in tables 11 to 22 presented below.
For example, when the length of the LDPC codeword is 64800, the code rate is
6/15, and the
modulation method(or modulation format) is 16-Quadrature Amplitude Modulation
(QAM), n(j)
may be defined as in table 11 presented below. In particular, table 11 may be
applied when
LDPC encoding is performed based on the parity check matrix defined by table
4.
[Table 11]
Order of bit groups to be block interleaved
n(j) (0 j <180)
j-th
1 1 1 1 1 1 I 1 1
1 2 2 2
block of 0 1 2 3 4 5 6 7 8 9
0 1 2 3 4 5 6 7 8 9 0 1 2
group-
2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3
4 4 4 4 4 4
2,
4 5 6 7 8 9 0 I 2 3 4 5 6 7
8 9 0 I 2 3 4 5
wise
46 4 4 4 5 5 5 5 5 5 5 5 5 5 6 6
6 6 6 6 6 6 6
interleaver 7 8 9 0 1 2 3 4 5 6 7 8 9
0 1 2 3 4 5 6 7 8
7 7 7 7 7 7 7 7 7 7 8 8 8 8 8 8
8 8 8 8 9 9
output 69
0 1 2 3 4 5 6 7 8 9 0 1 2 3
4 5 6 7 8 9 0 1
9 9 9 9 9 9 9 1 1 1 1 1 1 1 1 1
1 1 1 I 1 1
923 4 5 6 7 8 9 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14
Date Recue/Date Received 2021-10-07
41
11 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
13 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
8 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
16 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1
1 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79
1 8 5 6 1 1 6 5 5 8 9 7 1 1
6 5 6 1 1 6 7 8
46 3 2 2 76 60 8 3 6 1 7 9 13 63 1 8 9 33 08 6 1 6
14 5 6 1 5 7 1 1 6 1 t 8 1 1
1 1 9 19 1 6 1 1
4 7 7 16 9 0 56 72 5 49 55 2 38 36 41 11 6 70 0 40 4 59 5
716)-th 3 5 14 4 6 4 1 4 2 3 2 3 2 3
1 4 4 3 2 3 2
7 0
7 4 4 3 3 8 7 5 4 9 0 6 9 6
1 5 6 3 2 8
block of
3 27 4 3 2 4 5 6 4 2 2 1 5 3 2
4 1 4 1 9
4 3 group- 8 8 3 2 9 1 0 6 1 0 3
0 5 4 0 7 2 6 12 3
wise 12 1 9 1 1 3 1 1 7 1 1 1 1 1
1 9 7 I 1 1- 1 7 1
7 01 4 15 05 1 9 77 4 0 45 62 02 20 26 5 3 52 29 74 25 2 28
interleaver 1 1 1 I 8 1 7 1 1 7 1 1 8
1 1 9 1 1 1
78 8 9 1
input 71 42 78 54 5 07 5 2 51 7 17 09 0 06 34 8 22
73 61
15 1 1 1 1 1 1 1 1 1 1 1 8 1 1
1 1 8 1 1 1 9 8
0 10 75 66 31 19 03 39 48 57 14 47 7 58 21 64 04 9 79 23 18 9 8
9 1 8 1 1 1 1 1 1 1 1 9 1 7
1 1
11 2 5
2 65 4 68 24 69 30 67 53 37 43 1 00 6
32 35
In the case of Table 11, Equation 21 may be expressed as Y0=X,0)=X55, Y1=-
X710)=X146,
Y2=X11(2)=X83, ===, Y178=Xx(178)=X132, and Y179=Xit(t79)=X1,35. Accordingly,
the group interleaver
122 may rearrange the order of the plurality of bit groups in bit group wise
by changing the 55th
bit group to the 0th bit group, the 146th bit group to the lot bit group, the
83rd bit group to the 21
bit group, ..., the 132hd bit group to the 178th bit group, and the 135th bit
group to the 179th bit
group.
In another example, when the length of the LDPC codeword is 64800, the code
rate is 8/15,
and the modulation method is 16-QAM, x(j) may be defined as in table 12
presented below. In
particular, table 12 may be applied when LDPC encoding is performed based on
the parity check
matrix defined by table 5.
[Table 12]
j-th Order of bit groups to be block
interleaved
block of 71(j) (0 SJ < 180)
group- 1 2 3 4 5 6 7 8 9 1 1 1 1 1
1 1 1 1 1 2 2 2
0 1 2 3 4 5 6 7 8 9 0 1 2
wise
23 2- 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4
interleaver 4 5 6 7 8 9 0 1 2 3 4 5 6
7 8 9 0 1 2 3 4 5
4 4 4 5 5 5 5 5 5 5 5 5 5
output 6 6 6 6 6 6 6 6 6
7 8 9 0 1 2 3 4 5 6 7 8 9 0
1 2 3 4 5 6 7
Date Recue/Date Received 2021-10-07
42
7 7 7 7 7 7 7 7 7 7 69 8 8 8 8 8
8 8 8 8 8 9 9
0 1 2 3 4 5 6 7 8 9 0 1 2 3
4 5 6 7 8 9 0 1
9 9 9 9 9 9 9 1 1 1 1 1 1 I 1 I
1 1 1 1 I 1
92
3 4 5 6 7 8 9 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14
11 1 1 1 1 1 1 1 1 1 1 1 1 1
I 1 1 1 1 1 1 1 1
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
13 1 1 1 1 1 - 1 1 1 1 I 1 1 1
1 1 1 1 1 1 I I 1
8 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
16 1 1 1 t 1 1 1 1 1 1 1 1 1
1 1 1 I I
62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79
5 1 7 1 8 1 7 1 4 4 1 1 6 1 9 8
1 I 8 6 5 8
58
5 11 3 50 7 10 1 72 5 1 13 15 9 20 5 8 78 23 0 6 3 2
11 3 8 9 8 7 7 8 6 6 4- 7 1 7
8 1 4 9 3 7 4 6 5
8 8 9 9 5 9 5 3 8 3 0 7 17 0 1 12 3 4 7 2 6 7 1
it(j)-th 92 1 6 6 2 2 2 2 6 5 7 5 4
6 7 8 3 9 4 4 9 2 2
7 5 0 5 9 3 8 1 9 4 7 9 2 8
6 0 3 2 4 0 2 6
block of
2 9 4 1 5 5 2 3 4 0 3 2 5 1 3 7
2 3 5 8 1 1
33
group- 4 1 7 0 2 0 0 1 8 9 7 4 5 2
6 1 6 6 4 8 69
wise 1 1 3 1 1 1 1 1 1 1 1 1
1 1 1 1
7 5 8 3 4 1 6
1 36 5 65 06 59 38 9 28 68 66 44 49
79 41 3
interleaver ______________________________________________________________
1 9 3 1 1 1 1 1 1 I 1 1 1 1 1 1
1 1 1 1
2 9
input o 42 6 4 61 70 34 56 2 54 74 45 46 4 24 6 02 33 76 32 35
11 1 1 1 1 1 I 1 9 1 1' 1 1 1
1 6 1 1 1 1 1 1 9
6 30 77 60 29 08 25 47 7 48 62 73 63 22 04 4 43 67 03 40 58 39 8
10 1 1 1 1 1 1 1 1 1 1 1 1 I
1 1 1 1 I
5 26 09 19 01 21 07 31 52 64 75 51 27 14 37 57 53 71 55
In the case of Table 12, Equation 21 may be expressed as Y0=X.(0)=X5s,
Yi=X41)=X55,
Y2=X7,(2)=Xiii, =-=, Yi78=X/07s)=X171, and Yi79=X7079)=X155. Accordingly, the
group interleaver
122 may rearrange the order of the plurality of bit groups in bit group wise
by changing the 58th
bit group to the 0th bit group, the 55th bit group to the 1st bit group, the
1111h bit group to the 2nd
bit group, ..., the 17166 bit group to the 178th bit group, and the 155th bit
group to the 179th bit
group.
In another example, when the length of the LDPC codeword is 64800, the code
rate is 10/15,
and the modulation method is 16-QAM, n(j) may be defined as in table 13
presented below. In
particular, table 13 may be applied when LDPC encoding is performed based on
the parity check
matrix defined by table 6.
[Table 13]
j-th Order of bit groups to be block
interleaved
block of n(j) (0 j < 180)
1 1 1 I' I 1 1 1
1 1 2' 2 2
group- 1 2 3 4 5 6 7 8 9
0 1 2 3 4 5 6 7 8
9 0 1 2
Date Recue/Date Received 2021-10-07
43
wise 2 2 2 2 2 2 3 3 3 3 3 3 3
3 3 3 4 4 4 4 4 4
23
4 5 6 7 8 9 0 1 2 3 4 5 6 7
8 9 0 1 2 3 4 5
interleaver -
4 4 4 5 5 5 5 5 5 5 5 5 5 6 6 6
6 6 6 6 6 6
46
output 7 8 9 0 1 2 3 4 5 6 7 8 9 0
1 2 3 4 5 6 7 8
7 7 7 7 7 7 7 7 7 7 8 8 8 8 8 8
8 8 8 8 9 9
69
0 1 2 3 4 5 6 7 8 9 0 1 2 3
4 5 6 7 8 9 0 1
_ .
9 9 9 9 9 9 9 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1
92
3 4 5 6 7 8 9 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14
11 1 1 1 I 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
13 1 1 r 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 I 1 1
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
16 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 -
1 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79
5 8 1 2 1 9 6 4 5 1 9 1 2 4 2 3
8 6 8 7
74 1 8
3 4 09 8 03 9 5 1 0 2 5 15 9 8 5 5 9 2 0 1
7 8 5 1 4 4 4 3 4 9 1 9 8 1 4 9
1 3 9 1 5 1
34
7 1 8 13 4 9 5 3 0 1 7 4 2 6 6 3 04 6 2 11 7 16
n(j)-th 10 8 3 7 3 8 7 6 5 7 1 4 1 -
8 1 9 1 3 6 2 6 1 6
7 6 8 2 I 3 6 1 4 3 02 2 08 5 10 7 4 0 0 7 6 18 9
block of
56
1 1 3 3 7 1 1 5 4 1 1 1 5 3 9 8
1 6 1
4 7 5
group- 05 19 9 2 0 01 14 2 7 5 17 3 5 7 6 8 12 8 06
wise 16 7 1 5 2 6 1 7 1 6 2 2 1
3 9
2 1 7 2 9 2
9 1
0 8 8 9 3 4 9 9 34 3 4 (1 56 0 0 5 1 8 6 28
interleaver
14 1 1 1 1 1 1 1 1 2 8 1 1 1
1 4 5 6 1 1 1
6 0
input 7 1 61 62 23 38 73 77 00 2 7 37 32 69 58 3 1
7 68 43 31
14 1 I 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1
6 44 39 76 64 55 75 70 25 71 52 54 57 27 24 29 42 35 72 51 53 22 66
16 1 1 1 1 1- 1 1 1" 1 1 1 1 1
1 1 1 1 1
5 49 36 45 30 20 50 67 26 78 40 33 21 74 41 48 79 59 63
In the case of Table 13, Equation 21 may be expressed as Y0=Xn(0)=X74,
Y1=Nto)=X53,
Y2=X(2)=X84, = = 5 Y178=XX(178)=X159) and Yi79--.X,(l79)=X163. Accordingly,
the group interleaver
122 may rearrange the order of the plurality of bit groups in bit group wise
by changing the 74th
bit group to the 0th bit group, the 53'd bit group to the 1St bit group, the
84th bit group to the 2nd bit
= =
group, ..., the 159th bit group to the 178th bit group, and the 163rd bit
group to the 1791h Pit group.
In another example, when the length of the LDPC codeword is 64800, the code
rate is 10/15,
and the modulation method is 16-QAM, rt(j) may be defined as in table 14
presented below. In
particular, table 14 may be applied when LDPC encoding is performed based on
the parity check
matrix defined by table 7.
[Table 14]
j-th Order of bit groups to be
block interleaved
block of n(j) (0 j < 180)
Date Recue/Date Received 2021-10-07
44
group- 1 2 3 4 5 6 7 8 9 1 1 1 1 1
1 1 1 1 1 2 2 2
0 1 2 3 4 5 6 7 8
9 0 1 2
wise
2 2 2 2 2 2 3 3 3 3 3 3 3 3
3 3 4 4 4 4 4 4
23
interleaver 4 5 6 7 8 9 0 1 2 3 4 5 6
7 8 9 0 1 2 3 4 5
4 4 4 01143111 46 5 5 5 5 5 5 5 $
5 5 6 6 6 6 6 6 6 6 6
7 8 9 0 I 2 3 4 5 6 7 8 9 0
1 2 3 4 5 6 7 8
7 7 7 7 7 7 7 7 7 7 8 8 8 8
8 8 8 8 8 8 9 9
69
0 1 2 3 4 5 6 7 8 9 0 1 2 3
4 5 6 7 8 9 0 I
9 9 9 9 9 9 9 1 1 1 1 1 1 1
1 1 I 1 1 1 1 1
92
3 4 5 6 7 8 9 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14
11 I 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
13 1 1 1 1 1 1 I 1 1 1 1 1 1 1
1 I 1' 1 - 1 1 1
8 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
16 1 1 1 1 1 1 1 1 1 1 1 1 1 I
1 1 1 1
1 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79
7 5 1 2 2 I 3 1 2 I 7 5 8 1
9 6 9 8 4 8 5 4
68
1 4 9 5 1 02 2 05 9 6 9 3 2 07 1 7 4 5 8 3 8 2
2- 7 3 2 9 6 1 1 1 1 8 4 1 9 7 4 8 1 6 4 6
57 9
8 6 1 6 6 5 19 14 09 25
1 3 03 3 0 6 9 12 1 5 6
_
7CW-lh 38 7 1 5 8 1 1 7 7 6 4 9 3 9
5 6 4 2 8 7 9
4 3
7 15 6 7 13 00 5 2 0 7 2 6 8 9 4 0 6 3 5
block of
to 3 8 2
8 1 3 3 6 5 8 4 9 1 6 6
7 6 1 1 1 1
0
group- 4 4 4 II 5 0 4 5 0 0 7 01 9 3
4 2 18 10 59 8
wise 3 1 5 1 1 1 8 1 1 1 1 1 1
1 1 3 1 1 9 3 1
50 7
3 75
1 31 06 34 8 40 17 32 47 53 16 61 0 9 26 36 0 7 74
interleaver
1 1 5 9 1 1 7 1 1 1 1 1 1
1 I 1 1 1 2 4
41 5
11113111 58 20
2 2 9 46 44 8 55 28 65 41 79 50 57 71 43 08 70 2 9
2 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
11
7 60 78 33 42 21 68 73 23 3 5 54 27 39 51 63 72 38 76 45 29 62
1 1 1 1 1 1 1 1 1 I 1 1 1 2 1
1 2 - -
2 77 37 49 67 4 69 24 48 64
30 7 56 22 3 66 35 4
In the case of Table 14, Equation 21 may be expressed as 170=Xõ(0)=X68,
Yi=X,0)=X7i,
Y2=X*2)=X54, = = =, Y178=X/078)=X135, and Yi79=X7079)=X24. Accordingly, the
group interleaver
122 may rearrange the order of the plurality of bit groups in bit group wise
by changing the 68th
bit group to the Oth bit group, the 71st bit group to the 1st bit group, the
54th bit group to the 2"1 bit
group, ..., the 1351h bit group to the 178th bit group, and the 24th bit group
to the 179th bit group.
In another example, when the length of the LDPC codeword is 64800, the code
rate is 12/15,
and the modulation method is 16-QAM, Ir(j) may be defined as in table 15
presented below. In
particular, table 15 may be applied when LDPC encoding is performed based on
the parity check
matrix defined by table 8.
[Table 15]
Date Recue/Date Received 2021-10-07
45
Order of bit groups to be block
interleaved
Ir(j) (0 j < 180)
1 1 1 1 1 1 1 1 1
1 2 2 2
0 1 2 3 4 5 6 7 8 9
0 1 2 3 4 5 6 7 8 9 0 1 2
j-th
2 2 2 2 2 - 2 3 3 3 3 3 3 3 3
3 .. 3 .. 4 .. 4 .. 4 .. 4 .. 4 .. 4
23
4 5 6 7 8 9 0 I 2 3 4 5 6 7
8 9 0 1 2 3 4 5
block of 46 4 4 4 5 5 5 5 5 5 5 5 5
5 6 6 6 6 6 6 6 6 6
group- 8 9 0 1 2 3 4 5 6 7 8 9 0
1 2 3 4 5 6 7 8
7 7 7 7 7 7 7 7 7 7 8 8 8 8
8 8 8 8 8 8 9 9
wise 69
0 1 2 3 4 5 6 7 8 9 0 I 2 3
4 5 6 7 8 9 0 1
_
interleaver 9 9 9 92 9 9 9 9 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1
3
output 4 5
6 7 8 9 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14
11 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 31 34 35 36 37
13 1 1 1 1 1 1 1 I 1 1 1 1 1 1 1
1 1 1 1 1 1 1
8 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
16 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1
1 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79
12 3 3 1 7 3 6 1 3 1 1 6 2 8-* 1 1 8 7 7 8 I 4 3
0 2 8 13 1 1 5 09 6 06 34 6 9 6 36 08 3 0 9 1 05 8 0
12 1 4 9 7 6 7 5 9 8 4 6 5 1 1 1
8 7 1 8 1 5
3
5 07 4 9 5 4 8 1 5 8 9 0 4 22 40 37 9 4 29 2 64 9
9 67 9 4 7 2 1 8 1 2 9 7 1 1 2 9
5 9 1 1 9 6
8
2 8 2 7 8 21 7 8 1 3 2 42 12 0 0 39 4 7 3
block of
1 1 5 2 1 3 9 4 6 8 1 1 1 1
5 .. 1 .. 1 .. 9 .. 6 .. 1 .. 3
85 5
group- 04 24 2 0 18 4 4 1
8 0 10 2 33 31 3 16 23 6 1 11 3
wise 17 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 4 1 1 3 1
3 65 75 66 69 74 59 48 58 55 45 78 26 00 54 56 79 57 6 49 71 7 53
interleaver
16 1 1 1 1 1 1 7 1 1 1 1 1 1 I 1
1 1 1 1 4 2 1
input 3 52 46 77 03 60 47 6 72 44 50 32 76 68 67 62 70 38 51 61 0 6 30
11 1 1 1 8 5 6 1 4 2 1 6 1 1 1 1
2 9 7 3
0 7 4
9 14 17 15 4 7 2 3 7 4 0 9 9 27 7 6 7 1 3 5
1 5 2 2 1 5 4 5 1 4 1 1 1 2 1 3
6
2 5 5 3 5 1 6 5 8 28 3 35 43 41 2 01 9
In the case of Table 15, Equation 21 may be expressed as Yo=-----xxorXi2o,
Yi=Xxo)=X32,
Y2=XA(2)=X38, = = =, Yi78=X1078)=Xioi, and Yr9=X7079)=X39. Accordingly, the
group interleaver
122 may rearrange the order of the plurality of bit groups in bit group wise
by changing the 120th
bit group to the 0th bit group, the 32nd bit group to the lst bit group, the
38th bit group to the 2"d
bit group, ..., the 101st bit group to the 178th bit group, and the 39t bit
group to the 179th bit
group.
In another example, when the length of the LDPC codeword is 64800, the code
rate is 6/15,
and the modulation method is 16-QAIVI, it(j) may be defined as in table 16
presented below. In
particular, table 16 may be applied when LDPC encoding is performed based on
the parity check
Date Recue/Date Received 2021-10-07
46
matrix defined by table 10.
[Table 16]
Order of bit groups to be block interleaved
n(j) (0 j <180)
I 1 1 1 1 1 1 1
1 2 2 2
0 1 2 3 4 5 6 7 Et 9
0 1 2 3 4 5 6 7 8 9 0 1 2
2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3
4 4 4 4 4 4
j-th 23
4 5 6 7 8 9 0 1 2 3 4 5 6 7
8 9 0 1 2 3 4 5
block of
4 4 4 46 5 5 5 5 5 5 5 5 5 5 6 6
6 6 6 6 6 - 6 6
group- 7 8 9 0 1 2 3 4 5 6 7 8 9 0
1 2 3 4 5 6 7 8
7 7 7 7 7 7 7 7 7 7 8 8 8 8 8 8
8 8 8 8 9 9
wise 69
0 1 2 3 4 5 6 7 8 9 0 1 2 3
4 5 6 7 8 9 0 1
interleaver 9 9 9 9 9 9 9 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1
92
output
3 4 5 6 7 8 9 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14
_
11 1 1 1 1 I 1 1 I 1 1 1 1 1 1 1
1 1 1 , 1 1 1 1
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
=13 1 1 1 1 1 1 1 1 1 1 1 1 1
I 1 1 1 1 1 1' 1 1
8 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
- 16 1 1 1 1 1 I 1¨ 1 1 1 1 1 1 1 1 1 1 1
1 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79
16 1 1 1 8 1 1 1 9 1 1 I - 1 7 1
1 1 1 I 7 1 1 9
3 60 38 43 5 08 211 21 1 47 40 42 31 9 09 26 11 62 44 5 10 18 7
1 1 1 9 1 8 1 1 1 1 1 1 1 1 1 1
1 1 1 9 1 2
81
68 57 67 0 03 0 50 25 05 29 46 41 52 64 30 14 23 34 07 6 73 0
It(j)-th 6 1 1 4 1 1 6 6 8 3 1 6 8
1 2 5 5 5 6
44 5
4 9 6 8 13 5 16 I 3 6 4 9 0 9 8 35 5
5 4 8 1
block of
5 5 1 1 I 2 5 3 2 4 6 1 4 5 3 2
1 2 1 4
3 0
group- 33 7 9 6 8 55 1 6 6 9 8 2 54 3 1 4
7 2 4 7 2
wise 14 3 2 2 1 3 6 1 1 3 5 9 1 1
2 7 1 4 1 8 1
1 9
5 8 8 12 1 0 79 3 0 0 5 4 5 6 1
32 0 04 9 06
interleaver
1 4 1 1 4 2 4 1 6 5 9 1 1
1 1 2 1 1 1 1
46 4 7
input 66 7 61 74 9 3 1 39 8 2 9 49 15 01 27 2 58 69
53 22
11 - 1 9 1 8 1 1 6 9 1 7 - 7 7 7 8 7
1 3 3 3 1' 8 1
7 59 3 00 2 51 71 7 4 36 2 3 4 0 6 6 37 5 7 2 77 7 70
17 7 1 1 1 5 1 1- 1 6 8 I 9 7 1
1' 1 1 9 `
8 7 75 20 65 3 72 33 76 5 3 24 2 8 19 02 56 48 8
In the case of Table 16, Equation 21 may be expressed as Y0=X0)=X163,
Yi=Xxo)=Xioo,
Y2=X742)=X138, 11178=Xx(178)=X148, and Yr79=X70.79)=X98. Accordingly, the
group interleaver
122 may rearrange the order of the plurality of bit groups in bit group wise
by changing the 163rd
bit group to the 0th bit group, the 160th bit group to the 1st bit group, the
138th bit group to the 2nd
bit group, ..., the 148th bit group to the 178th bit group, and the 981h bit
group to the 179th bit
group.
In another example, when the length of the LDPC codeword is 64800, the code
rate is 6/15,
Date Recue/Date Received 2021-10-07
47
and the modulation method is 64-QAM, x(j) may be defined as in table 17
presented below. In
particular, table 17 may be applied when LDPC encoding is performed based on
the parity check
matrix defined by table 4.
[Table 171
Order of bit groups to be block
interleaved
rt(j) (0 j <180)
1 1 1 1 1 1 1 1 1
1 2 2 2
0 1 2 3 4 5 6 7 8 9
0 1 2 3 4 5 6 7 8 9 0 1 2
2 2 2 2 2 2 3 3 3 3 3 3 3 3
3 3 4 4 4 4 4 4
j-th 23
4 5 6 7 8 9 0 1 2 3 4 5 6 7
8 9 0 1 2 3 4 5
block of
4 4 4 5 5 5 5 5 5 5 5 5 5 6
6 6 6 6 6 6 6 6
46
group- 7 8 9 0 I 2 3 4 5 6 7 8 9 0
1 2 3 4 5 6 7 8
7 7 7 7 7 7 7 7 7 7 8 8 8 8
8 8 8 8 8 8 9 1 9
wise 69
(1 I 2 3 4 5 6 7 8 9 0 1 2 3
4 5 6 7 8 9 0 I 1
interleaver 9 9 9 9 9 9 9 1 1 1 1 1 1
1 1 1 1 1 1 1 I 1
92
3 4 5
output 6 7
8 9 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14
11 1 1 r 1 1 - 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
13 1 I 1 1 1 1 1 1 1 1 1 1 I 1
1 I 1 1 1 1 1 1
a 39 40 41 42 43 44 45 46 47 48 49 SO 51 52 53 54 55 56 57 58 59 60
16 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1
1 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79
1 3 3 2 4 3 3 I 4 4 2 3 4 I
1 1 1 2 4 5
29 9 1
7 8 7 7 3 1 5 6 6 4 3 4 5
4 8 56 9 2 0 0
5 4 2 4 6 4 5 6 6 5 6 6 6 5
1 6 1 5 7 4 2
24 5
6 9 6 2 9 7 9 1 6 2 4 5 7 4 70 8 32 1 0 1 1
716)-th 16 I 5 6 5 6 5 - I 7 5 1 6 3
2 7 3 3 7 8 8 1
7 3
0 3 5 2 3 3 8 67
1 7 51 0 6 5 4 9 2 2 5 6 07
block of
11 4 8 1 1 2 7 1 7 7 1 1 1 1 2
1 9 1 3 1 1 1
group- 3 8 8 229 37 0 3 66 5 7 42 74 5 49 8 45 2 69 0 33 63 19
wise 82 1 1 1 1 1 9 I 1 8 1 1 1 1
1 1 9 1 9 9 1
0
76 52 34 39 48 64 9 73 04 3 06 12 35 53 28
44 8 71 4 7 43
interleaver
8 7 1 1 1 - 9 1 9 r 1 1 1 1
1 1 1 1 8 1
4
input o 18 27 4 9 08 26 31 3 11 1 25 62 57 58 09 40 23 54 50 0 1
,
1 9 8 1 8 1 I 1 1 1 1 1 7 1
1 1 I 1 1 1
12 8 6
46 6 1 65 9 38 05 41 03 00
61 72 8 01 15 79 47 16 36 22
3 87 1 1 1 I 9 1 1 1 1 7 1 1 1
I 9 1 I
3 30 24 75 20 0 02 0 14 59 6 77 78 21 68 5 17 55
In the case of Table 17, Equation 21 may be expressed as Yo.--X/0)--A29,
Yi=Xx(1)=X17,
Y2=X142)=X38, = = =, Y178=X1,078)=X117, and Y179=X71079)=X155. Accordingly,
the group interleaver
122 may rearrange the order of the plurality of bit groups in bit group wise
by changing the 291h
bit group to the Oth bit group, the 17th bit group to the 1St bit group, the
38th bit group to the 2nd bit
group, ..., the 117th bit group to the 178111 bit group, and the 155th bit
group to the 179th bit group.
Date Recue/Date Received 2021-10-07
48
In another example, when the length of the LDPC codeword is 64800, the code
rate is 8/15,
and the modulation method is 64-QAM, n(j) may be defined as in table 18
presented below. In
particular, table 18 may be applied when LDPC encoding is performed based on
the parity check
matrix defined by table 5.
[Table 18]
Order of bit groups to be block
interleaved
n(j) (0 <180)
1 1 1 1 1 1 1 1 1
1 2 2 2
0 1 2 3 4 5 6 7 8 9
0 1 2 3 4 5 6 7 8 9 0 1 2
2 2 2 2 2 2 3 3 3 3 3 3 3 3
3 3 4 4 4 4 4 4
j-th 23
4 5 6 7 8 9 0 1 2 3 4 5 6 7
8 9 0 1 2 3 4 5
block of 4 4 4 5 5 5 5- 5 5 5 5 5 5
6 6- 6 6 e 6 6 - 6- 6
46
group- 7 8 9 0 1 2 3 4 5 6 7 8 9 0
1 2 3 4 5 6 7 8
7 7 7 7 7 7 7 7 7 7 8 8 8 8
8 8 8 8 8 8 9 9
wise 69
0 1 2 3 4 5 6 7 8 9 0 1 2 3
4 5 6 7 8 9 0 1
interleaver 9 9 9 9 9 9 9 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1
92
output 3 4 5 6 7 8 9 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14
11 C 1 1 1 1 1 1 C 1 - 1 1 I 1 1
1 1 1 1 1 1 - 1 1-
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 17
_
13 1 1 1 1 1 1 1 1 1 1 1 I 1 1 1
1 1 1 1 1 1 1
8 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
16 1 1 1 1 I 1 1 1 1 1 1 1 1 1 1
1 1 1
62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79
7 5 4 8 9 4 8 6 4 8 3 5 - 6 3
5 5 9 6 8 7" 7 4
86
1 1 8 9 4 6 1 7 9 0 7 5 1 6
7 2 2 0 2 6 2 4
9 6 5 9 4 7 5 5 4 8 7 6 4 5
8 9 3 6 1
42 4 8 6
1 2 0 0 0 8 3 8 7 5 0 9 3 4
4 3 8 4 8
n(j)-th 9 6 5 8 7 1 8 7 6 8 7 1 1 1
3 2 1 3 3 1 1
77 3
5 6 9 3 3 7 7 5 5
8 9 4 51 17 2 2 23 0 3 62 44
block of
1 1 1 I 2 3 2 1 1 1 1 2 1 1
1 1 1 3 1 3 1 2
9
group- 21 08 39 42 4 4 0 57 59 36 43 9 40 63 50 75 14 1 2 5 45 8
wise 2 1 9 1 1 1 1 2 2 1 1 4 1 2
1 1 5 1 1 1
27 5 1
6 6 8 02 03 33 61 1 5 07 53 5 56 3 25 41 6 66 70
19
interleaver ______________________________________________________________
1 4 7 1 1 1 1 9 1 1 1 1 1 1
1 1 1 1 1 1
68 2
input 34 1 4 79 29 69 01 9 09 27 68 76 1
22 10 13 46 32 65 9
. -
3 1 1 1 1 1 1 1 1 1 6 1 I
1 1 1 1 1 I 1 1
13 7
9 64 06 72 54 49 0 73 31 67 3 47 55 00 71 58 60 5 78 48 52
1 1 9 1 1 1 1 I 1 1 1 1 1 9 1 1
1 I
4 24 77 7 30 18 37 11 26 20 05 15 36 12 6 35 16 74 28
In the case of Table 18, Equation 21 may be expressed as Y0=X710)=X86,
Yi=X1r0)=-X71,
Y2=X(2)=X5i, ===9 Y178=Xx(178)=X174, and Yi79---X[079)=X12.8. Accordingly, the
group interleaver
122 may rearrange the order of the plurality of bit groups in bit group wise
by changing the 861
bit group to the Oth bit group, the 711' bit group to the 11' bit group, the
5111 bit group to the 2nd bit
Date Recue/Date Received 2021-10-07
49
group, ..., the 174th bit group to the 1781h bit group, and the 1281h bit
group to the 1791h bit group.
In another example, when the length of the LDPC codeword is 64800, the code
rate is 10/15,
and the modulation method is 64-QAM, 7c(j) may be defined as in table 19
presented below. In
particular, table 19 may be applied when LDPC encoding is performed based on
the parity check
matrix defined by table 6.
[Table 19]
Order of bit groups to be block
interleaved
rt(j) (0 j <180)
1 1 1 1 1 1 1 1 1
1 2 2 2
0 1 2 3 4 5 6 7 8 9
0 1 2 3 4 5 6 7 8 9 0 1 2
2 2 2 2 2 2 3 3 3 3 3 3 3 3
3 3 4 4 4 4 4 4
j-th 23
4 5 6 7 8 9 0 1 2 3 4 5 6 7
8 9 0 1 2 3 4 5
block of 4 4 4 5 5 5 5 5 5- 5 5 5 5
6 6 6 6 6 6 6 6 6
46
group- 7 8 9 0 1 2 3 4 5 6 7 8 9 0
1 2 3 4 5 6 7 8
7 7 7 7 7 7 7 7 7 7 8 8 8 8
8 8 8 8 8 8 9 9
wise 69
(1 1 2 3 4 5 6 7 8 9 0 1 2 3
4 5 6 7 8 9 0 1
interleavcr 9 9 9 9 9 9 9 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1
92
output
3 4 5 6 7 8 9 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14
_
11 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
13 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 -
1 1 1 1 1 1 1
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
16 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1
1 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79
3 2 5 3 7 1 1 8 7 4 7 1 - 5 5
4 1 4 4 9 3- 4 1
73
6 1 3 7 8 02 19 2 5 0 7 04 9 8 1 8 6 5 3 0 9 14
- _
9 6 3 1 1 9 1 2 3 2 7 8 1
6 -- 5 -- 5 -- 9 -- 1 -- 5 -- 5 -- 8
79 1
7 6 3 15 12 9 07 6 9 3 0 9 16 2 5 0 6 08 7 1 6
rr(j)-th 8 5 6 7 1 8 1 6 1 1 6 4 - 1 8
3- 1 2- 1 9 9
28 6
8 2 9 4 13 4 09 5 01 11 1 4 05 3 5 30 7 06 0 2
block of -
8 3 3 8 6 1 6 1 7 9 3 1 4
4 -- 6 -- 7 -- 6 -- 9 -- 6 -- 1 -- 1
54
group- 7 7 8 1 5 3 17 7 10 2 4 2 18 7 8
8 6 0 1 4 7 42
wise 15 2 1 4 5 1 1 I 3 1 2 1 2 1
1 I 4 9 1 1 9
4 5
6 4 2 2 6 70 72 6 4 52 9 1 0
36 58 34 3 8 41 60 $
interleayer -
1 8 1 7 1 1 1 1 1 2 1 1 I 1
1 -- 1- -- 1 -- 1 -- 1 -- 1 -- 1
= 0 9
input 54 1 69 1 71 62 39 75 29 5 67 31
23 65 40 24 78 0 4 45 64
1 1 1 1 2 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1
3 2
5 43 73 76 2 61 53 9
51 50 74 44 57 63 22 47 32 37 28 59 55
12 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
8 1 1
7 38 03 00 20 46 68 66 48 3 25 77 33 26 21 79 0 49 35
In the case of Table 19, Equation 21 may be expressed as Yo=X70)=X73, Yi.--
Xxo)=X36,
Y2=Xx(2)=X2i, = = 11178=Xx(178)=X1491 and Yi79,---X7079)=X135. Accordingly,
the group interleaver
122 may rearrange the order of the plurality of bit groups in bit group wise
by changing the 73rd
Date Recue/Date Received 2021-10-07
50
bit group to the 0th bit group, the 361h bit group to the 1St bit group, the
21' bit group to the 2nd bit
group, ..., the 1491h bit group to the 178th bit group, and the 135th bit
group to the 179th bit group.
In another example, when the length of the LDPC codeword is 64800, the code
rate is 10/15,
and the modulation method is 64-QAM, n(j) may be defined as in table 20
presented below. In
particular, table 20 may be applied when LDPC encoding is performed 'based on
the parity
check matrix defined by table 7.
[Table 20]
Order of bit groups to be block interleaved
n(j) (0 5_ j < 180)
I I 1 1 1 1 1 1
1 2 2 2
0 1 2 3 4 5 6 7 8 9
0 1 2 3 4 5 6 7 8 9 0 1 2
2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3
4 4 4 4 4 4
j-th 23
4 5 6 7 8 9 0 1 2 3 4 5 6 7
8 9 0 1 2 3 4 5
block of 4 4 4 5 5 5 5 5 5 5 5 5 5 6
6 6 6 6 6 6 6 6
46
group-
7 8 9 0 1 2 3 4 5 6 7 8 9 0
1 2 3 4 5 6 7 8
7 7 7 7 7 7 7 7 7 7 8 8 8 8 8 8
8 8 8 8 9 9
wise 69
0 1 2 3 4 5 6 7 8 9 0 1 2 3
4 5 6 7 8 9 0 1
interleaver 9 9 9 9 9 9 9 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1
92
output 3 4
5 6 7 8 9 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14
11 1 1 1 1 1 1 1 1 1 1 1 1 1 I 1
1 1 1 1 1 1 1
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
13 - 1 1 1 1 1 1 1 1 1 1 1 I 1 1 1
1 1 1 1 1 1 1
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
16 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1
1 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79
11 1 4 1 3 8 3 8 3 8 1 8 4 1 1 5
7 7 9 1 5 1 9
3 15 7 11 5 4 4 3 1 8 09 6 6 77 03 7 7 3 5 50 2 07 8
6 5 5 4 7 1 7 2 3 9 4 7 7 6 9 5
1 2 1 5 1
43 6
6 5 6 9 2 18 8 7 9 7 0 5 9
8 3 9 19 0 0 1 08
7C(jD-th 1 6 1 1 3 1 5 1 3 9 7 9 1 8
9 1 6 1 1 4 1
65 7
14 9 16 0
01 0 4 8 9 1 6 28 2 2 66 0 78 17 5 57
block of
1 6 3 9 8 5 1 5 9 1 1 6 1 1 7 6
1 1 1 8 2 1
46
group- N 7
7 4 9 3 00 4 1 73 69 3 49 04 0 1 02 10 24 0 9 8
2 3 2 5 6 3 6 4 2 2 1 8 7 1 2 1
4 8 7
Wise 19 0 8 5
4 6 2 8 2 3 4 2 8 6
12 5 4 3 1 05 4 7 6
interleaver
2 8 9 1 1 1 1 1 1 1 1 2 1 1 I I
1 1 1 1
3 9
input 6 5 1 0 1 68 21 53 40 52 35 74
3 39 2 6 46 64 42 5 47
1 1 I 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1
4
61 20 33 55 23 58 67 54 48 37 60 45 59 7
26 43 51 62 56 72 71
13 4 1 1 1 3 1 1 1 1 1 1 1 1 1 1
1 1 1
1 1 79 32 36 2 75 63 65 41 38 22 27 25 44 70 34 30
In the case of Table 20, Equation 21 may be expressed as Yo=XE(0)=X113,
Y1=Xx(i)=Xiis,
Y2=Xn(2)=X47, == Yi78=X7078)=X13o, and Yr9=X7079)=X176. Accordingly, the group
interleaver
Date Recue/Date Received 2021-10-07
51
122 may rearrange the order of the plurality of bit groups in bit group wise
by changing the 113th
bit group to the 0th bit group, the 115th bit group to the 11' bit group, the
47th bit group to the 2nd
bit group, ..., the 130th bit group to the 178th bit group, and the 1761h bit
group to the 179th bit
group.
In another example, when the length of the LDPC codeword is 64800, the code
rate is 12/15,
and the modulation method is 64-QAM, n(j) may be defined as in table 21
presented below. In
particular, table 21 may be applied when LDPC encoding is performed based on
the parity check
matrix defined by table 8.
[Table 21]
Order of bit groups to be block interleaved
n(j) (0 j <180)
t 1 1 I 1 1 1 1 1
1 2 2 2
1 2 3 4 5 6 7 8 9
0 1 2 3 4 5 6 7 8 9 0 1 2
2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 4- 4 4 4 4 4
j-th 23
4 5 6 7 8 9 0 1 2 3 4 5 6 7
8 9 0 1 2 3 4 5
block of 4 4 4 46 5 5 5 5 5 5 5 5 5 5
6 6 6 6 6 6 6 6 6
group- 7 8 9 0 1 2 3 4 5 6 7 8 9 0
1 2 3 4 5 6 7 8
7 7 7 7 7 7 7 7 7 7 8 8 8 8 8 8
8 8 8 8 9 9
wise 69
0 1 2 3 4 5 6 7 8 9 0 1 2 3
4 5 6 7 8 9 0 1
interleaver 9 9 9 9 9 9 9 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1
92
output 3 4
5 6 7 8 9 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14
11 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
13 1 1 1 1 1 - 1 1 1 1 f 1 1 1
1 1 1 1 1 1 1 1 1
8 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
16 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1
1 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79
9 9 4 5 4 3 7 1 1 8 6 1 7 3 3 9
5 7 1 1 7 6
83
3 4 7 5 0 8 7 10 24 7 1 02 6 3 S 2 9 4 1 38 2 7
1 9 1 1 4 5 9 5 1 1 1 8 1 2 1 7
6 1 6 1
37 0 9
0 5 39 31 4 7 7 3 42 36 43 6 00 1 5 5 2 9 5 29
71(i)-th 10 7 2 6 7 2 1 8 9 1 8 1 1
2 .. 4 .. 1 .. 5 .. 9 .. 2 .. 1 .. 4 .. 9 .. 4
1 9 2 8 3 3 8 1 8 12 28 03 5 3 26 4 0 8 09 6 1 1
block of
8 2 1 1 5 1 7 2 1 9 5 1 6 6 8 3
1 1 6 4 6 1 8 3
group- 13
34 2 05 8 7 35 6 6 40 4 6 9 4 20 08 3 5 9 21 8 9
wise 29
1 1 1 1 3 4 5 7 1 5-- 8 8 8 1 1 1 3 2 4 5 3 1
33 06 17 27 2 2 8 1 18 1 4 5 0 04 32 11 0 6 8 0 1 41
interleaver
1 7 1 1 1 1 3 1 1 1 1 1 1
9 1 1 2 1 1 1 1
input 6 23 14 0 07 78 45 73 6 44 30 76 71 75 25 9 62 59 0 64 15 69 72
16 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 4 1
4 6
5 61 51 19 22 52 57 37 =48 53 70 54 66 3 50 6 67 74 63 9
68
14 1 1 1 1 1 1 1 6¨ 2 1 1 1
1 5 7 3 2
7 46 49 58 79 2 60 77 D 4 56 55 7 4
Date Recue/Date Received 2021-10-07
52
In the case of Table 21, Equation 21 may be expressed as Y0=X.(0)=X83,
Yi=,c0)=X93,
Y2=Xx(2)=X94, = = Y178=Xz(178)=X2, and Yr9=X7,079)=X14. Accordingly, the group
interleaver 122
may rearrange the order of the plurality of bit groups in bit group wise by
changing the 831d bit
group to the 0th bit group, the 93th bit group to the 1' bit group, the 941h
bit group to the 2nd bit
group, ..., the 2nd bit group to the 1781h bit group, and the 14th bit group
to the 179th bit group.
In another example, when the length of the LDPC codeword is 64800, the code
rate is 6/15,
and the modulation method is 64-QAM, a(j) may be defined as in table 22
presented below. In
particular, table 22 may be applied when LDPC encoding is performed based on
the parity check
matrix defined by table 10.
[Table 22]
Order of bit groups to be block
interleaved
7r(j) (0 j <180)
1 1 1 1 1 1 1 1 1
1 2 2 2
1 2 3 4 5 6 7 8 9
0 1 2 3 4 5 6 7 8 9 0 1 2
2 2 2 2 2 2 3 3 3 3 3 3 3 3
3 3 4 4 4 4 4 4
j-th 23
4 5 6 7 8 9 0 1 2 3 4 5 6 7
8 9 0 1 2 3 4 5
block of 4 4 4 5 5 5 5 - 5 5 5 5 5 5 6
6 6 6 6 6 - 6 6- 6
46
group- 7 8 9 0 1 2 3 4 5 6 7 8 9 0
1 2 3 4 5 6 7 8
_ -
7 7 7 7 7 7 7 7 7 7 8 8 8 8
8 8 8 8 8 8 9 9
wise 69
0 1 2 3 4 5 6 7 8 9 0 1 2 3
4 5 6 7 8 9 0 1
interleaver 9 9 9 9 9 9 9 1 1 1 1 1 1
1 1 1 1 1 1 I 1 1
92
3 4 5
output 6 7
8 9 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14
- 11 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1' 1 1- 1 I 1
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
13 1 1 1 1 1 I I 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1
8 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
16 1 - 1 1 1 1 1 1 1 1 1 1 1 1 - 1
1 1 - 1 1
1 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79
17 1 1 1 8 3 1 8 8 3 1 1 9 1 8 1
1 1 1 1 1 4
4
5 77 73 25 9 7 65 5 2 4 7 62 2 61 8 37 49 15 13 72 23 3
7 1 9 1 2 1 1 5 5 2 2 1 1 1 5 1
8 1 2 5 1 8
2 6 43 8 39 0 50 3 2 0 5 4 53 33 22 5 0 3 8 7 1 5
n(j)-th
1 1 8 1 5 1 2 4 6 1 5 2 1 5
1 2 1 1 6 1
46 7 1
block of 64 55 1 02 3 1 1 7 1 26 7 6
48 6 71 2 66 01 7 19
17 1 1 9 8 9 6 1 9 6 1 3 1 1 8 1
1 5 6 6 9
group- 8 5 3
21 18 6 0 9 8 67 0 2 47 6 40 03 7 57 76 9 6 4 1
wise 7 1 7 1 4 3 3 2 1 4 6 4 1 3
1 4 1 1 5 1 1
29 0
interleaver 1 07 7 11 2 5 8 3 00 5 9 0 29 3 63 9 12 45 4 05 17
10 9 7 1 1 1 6 3 1 2 7 9 7 1 8 5
1 9 1 1 1 4
input 8
4 9 2 9 06 0 9 04 8 23 7 5 54 4 8 44 5 36 6 70 4
_
15 7 6 4 1 1 4 1 1 8 1 1 7 1 1 1
6 1 1 9 3
9 6
1 0 3 8 28 14 1 74 16 6 41 09 8 27 42 59 5 30 24 3 0
11 3 1 1 1 1 1 1 7 1 1 1 1 1 1 1
1 3 7 ,
Date Recue/Date Received 2021-10-07
53
I 2 1 60 1 35 1 32 1 34 4 46 1 4 1 " 1 " 1 " 1 " " 1 31 " 1 1 1 2
7177-71
In the case of Table 22, Equation 21 may be expressed as Y0=X140)=X175,
Y1=X710)=X177,
Y2=Xõ(2)=X173, Yi78=Xic78)=X3i, and YI-T9=a7,(l79)=X72. Accordingly, the
group interleaver
122 may rearrange the order of the plurality of bit groups in bit group wise
by changing the 175th
bit group to the 0th bit group, the 177th bit group to the 1st bit group, the
173rd bit group to the 21th
bit group, ..., the 31st bit group to the 178th bit group, and the 72" bit
group to the 179th bit group.
In the above-described examples, the length of the LDPC codeword is 64800 and
the code
rate is 6/15, 8/15, 10/15, and 12/15. However, this is merely an example and
the interleaving
pattern may be defined variously when the length of the LDPC codeword is 16200
or the code
rate has different values.
As described above, the group interleaver 122 may rearrange the order of the
plurality of bit
groups in bit group wise by using Equation 21 and Tables 11 to 22.
"j-th block of Group-wise Interleaver output" in tables 11 to 22 indicates the
j-th bit group
output from the group interleaver 122 after interleaving, and "rt(j)-th block
of Group-wise
Interleaver input" indicates the rc(j)-th bit group input to the group
interleaver 122.
In addition, since the order of the bit groups constituting the LDPC codeword
is rearranged by
the group interleaver 122 in bit group wise, and then the bit groups are block-
interleaved by the
block interleaver 124, which will be described below, "Order of bit groups to
be block
interleaved" is set forth in Tables 11 to 22 in relation to it(j).
The LDPC codeword which is group-interleaved in the above-described method is
illustrated
in FIG. 7. Comparing the LDPC codeword of FIG. 7 and the LDPC codeword of FIG.
6 before
group interleaving, it can be seen that the order of the plurality of bit
groups constituting the
LDPC codeword is rearranged.
That is, as shown in FIGs. 6 and 7, the groups of the LDPC codeword are
arranged in order of
bit group X0, bit group X1, ..., bit group XNgr0up-1 before being group-
interleaved, and are
arranged in an order of bit group Yo, bit group Y1, ..., bit group Y
- Ngroup.1 after being group-
interleaved. In this case, the order of arranging the bit groups by the group
interleaving may be
determined based on Tables 11 to 22.
The group twist interleaver 123 interleaves bits in a same group. That is, the
group twist
interleaver 123 may rearrange the order of the bits in the same bit group by
changing the order of
Date Recue/Date Received 2021-10-07
54
the bits in the same bit group.
In this case, the group twist interleaver 123 may rearrange the order of the
bits in the same bit
group by cyclic-shifting a predetermined number of bits from among the bits in
the same bit
group.
For example, as shown in FIG. 8, the group twist interleaver 123 may cyclic-
shift bits
included in the bit group Y1 to the right by 1 bit. In this case, the bits
located in the 0th position,
the 1st position, the 2'1 position, ..., the 3586 position, and the 3591h
position in the bit group Yi
as shown in FIG. 8 are cyclic-shifted to the right by 1 bit. As a result, the
bit located in the 359th
position before being cyclic-shifted is located in the front of the bit group
Y1 and the bits located
in the 0th position, the 1.5t position, the 2n1 position, ..., the 358"
position before being cyclic-
shifted are shifted to the right serially by 1 bit and located.
In addition, the group twist interleaver 123 may rearrange the order of bits
in each bit group
by cyclic-shifting a different number of bits in each bit group.
For example, the group twist interleaver 123 may cyclic-shift the bits
included in the bit
group Y1 to the right by 1 bit, and may cyclic-shift the bits included in the
bit group Y2 to the
right by 3 bits.
However, the above-described group twist interleaver 123 may be omitted
according to
circumstances.
In addition, the group twist interleaver 123 is placed after the group
interleaver 122 in the
above-described example. However, this is merely an example. That is, the
group twist
interleaver 123 changes only the order of bits in a certain bit group and does
not change the order
of the bit groups. Therefore, the group twist interleaver 123 may be placed
before the group
interleaver 122.
The block interleaver 124 interleaves the plurality of bit groups the order of
which has been
rearranged. Specifically, the block interleaver 124 may interleave the
plurality of bit groups the
order of which has been rearranged by the group interleaver 122 in bit group
wise (or bits group
unit). The block interleaver 124 is formed of a plurality of columns each
including a plurality of
rows and may interleave by dividing the plurality of rearranged bit groups
based on a
modulation order determined according to a modulation method.
In this case, the block interleaver 124 may interleave the plurality of bit
groups the order of
which has been rearranged by the group interleaver 122 in bit group wise.
Specifically, the block
Date Recue/Date Received 2021-10-07
55
interleaver 124 may interleave by dividing the plurality of rearranged bit
groups according to a
modulation order by using a first part and a second part.
Specifically, the block interleaver 124 interleaves by dividing each of the
plurality of columns
into a first part and a second part, writing the plurality of bit groups in
the plurality of columns of
the first part serially in bit group wise, dividing the bits of the other bit
groups into groups (or
sub bit groups) each including a predetermined number of bits based on the
number of columns,
and writing the sub bit groups in the plurality of columns of the second part
serially.
Herein, the number of bit groups which are interleaved in bit group wise may
be determined
by at least one of the number of rows and columns constituting the block
interleaver 124, the
number of bit groups and the number of bits included in each bit group. In
other words, the block
interleaver 124 may determine the bit groups which are to be interleaved in
bit group wise
considering at least one of the number of rows and columns constituting the
block interleaver
124, the number of bit groups and the number of bits included in each bit
group, interleave the
corresponding bit groups in bit group wise, and divide bits of the other bit
groups into sub bit
groups and interleave the sub bit groups. For example, the block interleaver
124 may interleave
at least part of the plurality of bit groups in bit group wise using the first
part, and divide bits of
the other bit groups into sub bit groups and interleave the sub bit groups
using the second part.
Meanwhile, interleaving bit groups in bit group wise means that the bits
included in the same
bit group are written in the same column. In other words, the block
interleaver 124, in case of bit
groups which are interleaved in bit group wise, may not divide the bits
included in the same bit
groups and write the bits in the same column, and in case of bit groups which
are not interleaved
in bit group wise, may divide the bits in the bit groups and write the bits in
different columns.
Accordingly, the number of rows constituting the first part is a multiple of
the number of bits
included in one bit group (for example, 360), and the number of rows
constituting the second
part may be less than the number of bits included in one bit group.
In addition, in all bit groups interleaved by the first part, the bits
included in the same bit
group are written and interleaved in the same column of the first part, and in
at least one group
interleaved by the second part, the bits are divided and written in at least
two columns of the
second part.
The specific interleaving method will be described later.
Meanwhile, the group twist interleaver 123 changes only the order of bits in
the bit group and
Date Recue/Date Received 2021-10-07
56
does not change the order of bit groups by interleaving. Accordingly, the
order of the bit groups
to be block-interleaved by the block interleaver 124, that is, the order of
the bit groups to be
input to the block interleaver 124, may be determined by the group interleaver
122. Specifically,
the order of the bit groups to be block-interleaved by the block interleaver
124 may be
determined by z(j) defined in Tables 11 to 22.
As described above, the block interleaver 124 may interleave the plurality of
bit groups the
order of which has been rearranged in bit group wise by using the plurality of
columns each
including the plurality of rows.
In this case, the block interleaver 124 may interleave the LDPC codeword by
dividing the
plurality of columns into at least two parts. For example, the block
interleaver 124 may divide
each of the plurality of columns into the first part and the second part and
interleave the plurality
of bit groups constituting the LDPC codeword.
In this case, the block interleaver 124 may divide each of the plurality of
columns into N
number of parts (N is an integer greater than or equal to 2) according to
whether the number of
bit groups constituting the LDPC codeword is an integer multiple of the number
of columns
constituting the block interleaver 124, and may perform interleaving.
When the number of bit groups constituting the LDPC codeword is an integer
multiple of the
number of columns constituting the block interleaver 124, the block
interleaver 124 may
interleave the plurality of bit groups constituting the LDPC codeword in bit
group wise without
dividing each of the plurality of columns into parts.
Specifically, the block interleaver 124 may interleave by writing the
plurality of bit groups of
the LDPC codeword on each of the columns in bit group wise in a column
direction, and reading
each row of the plurality of columns in which the plurality of bit groups are
written in bit group
wise in a row direction.
In this case, the block interleaver 124 may interleave by writing bits
included in a
predetermined number of bit groups, which corresponds to a quotient obtained
by dividing the
number of bit groups of the LDPC codeword by the number of columns of the
block interleaver
124, on each of the plurality of columns serially in a column direction, and
reading each row of
the plurality of columns in which the bits are written in a row direction.
Hereinafter, the group located in the th position after being interleaved by
the group
interleaver 122 will be referred to as group Y.
Date Recue/Date Received 2021-10-07
57
For example, it is assumed that the block interleaver 124 is formed of C
number of columns
each including RI number of rows. In addition, it is assumed that the LDPC
codeword is formed
of Ngroup number of bit groups and the number of bit groups Ngroup is a
multiple of C.
In this case, when the quotient obtained by dividing Ngr pup number of bit
groups constituting
the LDPC codeword by C number of columns constituting the block interleaver
124 is A
(./igroup/C) (A is an integer greater than 0), the block interleaver 124 may
interleave by writing A
(=Ngroup/C) number of bit groups on each column serially in a column direction
and reading bits
written on each column in a row direction.
For example, as shown in FIG. 9, the block interleaver 124 writes bits
included in bit group
Yo, bit group Y1,..., bit group YA-1 in the 1st column from the 1st row to the
Rid' row, writes bits
included in bit group YA, bit group YA+15 = = bit group Y2A-1 in the 2nd
column from the 1st row
to the Rith row, ..., and writes bits included in bit group YcA-A, bit group
YCA-A+1, bit group
YCA...1 in the column C from the 1st row to the Rid' row. The block
interleaver 124 may read the
bits written in each row of the plurality of columns in a row direction.
Accordingly, the block interleaver 124 interleaves all bit groups constituting
the LDPC
codeword in bit group wise.
However, when the number of bit groups of the LDPC codeword is not an integer
multiple of
the number of columns of the block interleaver 124, the block interleaver 124
may divide each
column into 2 parts and interleave a part of the plurality of bit groups of
the LDPC codeword in
bit group wise, and divide bits of the other bit groups into sub bit groups
and interleave the sub
bit groups. In this case, the bits included in the other bit groups, that is,
the bits included in the
number of groups which correspond to the remainder when the number of bit
groups constituting
the LDPC codeword is divided by the number of columns are not interleaved in
bit group wise,
but interleaved by being divided according to the number of columns.
Specifically, the block interleaver 124 may interleave the LDPC codeword by
dividing each
of the plurality of columns into two parts.
In this case, the block interleaver 124 may divide the plurality of columns
into the first part
and the second part based on at least one of the number of columns of the
block interleaver 124,
the number of bit groups of the LDPC codeword, and the number of bits of bit
groups.
Here, each of the plurality of bit groups may be formed of 360 bits. In
addition, the number of
bit groups of the LDPC codeword is determined based on the length of the LDPC
codeword and
Date Recue/Date Received 2021-10-07
58
the number of bits included in the bit group. For example, when an LDPC
codeword in the
length of 16200 is divided such that each bit group has 360 bits, the LDPC
codeword is divided
into 45 bit groups. Alternatively, when an LDPC codeword in the length of
64800 is divided
such that each bit group has 360 bits, the LDPC codeword may be divided into
180 bit groups.
Further, the number of columns constituting the block interleaver 124 may be
determined
according to a modulation method. This will be explained in detail below.
Accordingly, the number of rows constituting each of the first part and the
second part may
be determined based on the number of columns constituting the block
interleaver 124, the
number of bit groups constituting the LDPC codeword, and the number of bits
constituting each
of the plurality of bit groups.
Specifically, in each of the plurality of columns, the first part may be
formed of as many rows
as the number of bits included in at least one bit group which can be written
in each column in
bit group wise from among the plurality of bit groups of the LDPC codeword,
according to the
number of columns constituting the block interleaver 124, the number of bit
groups constituting
the LDPC codeword, and the number of bits constituting each bit group.
In each of the plurality of columns, the second part may be formed of rows
excluding as many
rows as the number of bits included in at least some bit groups which can be
written in each of
the plurality of columns in bit group wise. Specifically, the number rows of
the second part may
be the same value as a quotient when the number of bits included in all bit
groups excluding bit
groups corresponding to the first part is divided by the number of columns
constituting the block
interleaver 124. In other words, the number of rows of the second part may be
the same value as
a quotient when the number of bits included in the remaining bit groups which
are not written in
the first part from among bit groups constituting the LDPC codeword is divided
by the number
of columns.
That is, the block interleaver 124 may divide each of the plurality of columns
into the first
part including as many rows as the number of bits included in bit groups which
can be written in
each column in bit group wise, and the second part including the other rows.
Accordingly, the first part may be formed of as many rows as the number of
bits included in
bit groups, that is, as many rows as an integer multiple of M. However, since
the number of
codeword bits constituting each bit group may be an aliquot part of M as
described above, the
first part may be formed of as many rows as an integer multiple of the number
of bits
Date Recue/Date Received 2021-10-07
59
constituting each bit group.
In this case, the block interleaver 124 may interleave by writing and reading
the LDPC
codeword in the first part and the second part in the same method.
Specifically, the block interleaver 124 may interleave by writing the LDPC
codeword in the
plurality of columns constituting each of the first part and the second part
in a column direction,
and reading the plurality of columns constituting the first part and the
second part in which the
LDPC codeword is written in a row direction.
That is, the block interleaver 124 may interleave by writing the bits included
in at least some
bit groups which can be written in each of the plurality of columns in bit
group wise in each of
the plurality of columns of the first part serially, dividing the bits
included in the other bit groups
except the at least some bit groups and writing in each of the plurality of
columns of the second
part in a column direction, and reading the bits written in each of the
plurality of columns
constituting each of the first part and the second part in a row direction.
In this case, the block interleaver 124 may interleave by dividing the other
bit groups except
the at least some bit groups from among the plurality of bit groups based on
the number of
columns constituting the block interleaver 124.
Specifically, the block interleaver 124 may interleave by dividing the bits
included in the
other bit groups by the number of a plurality of columns, writing each of the
divided bits in each
of a plurality of columns constituting the second part in a column direction,
and reading the
plurality of columns constituting the second part, where the divided bits are
written, in a row
direction.
That is, the block interleaver 124 may divide the bits included in the other
bit groups except
the bit groups written in the first part from among the plurality of bit
groups of the LDPC
codeword, that is, the bits in the number of bit groups which correspond to
the remainder when
the number of bit groups constituting the LDPC codeword is divided by the
number of columns,
by the number of columns, and may write the divided bits in each column of the
second part
serially in a column direction.
For example, it is assumed that the block interleaver 124 is formed of C
number of columns
each including R1 number of rows. In addition, it is assumed that the LDPC
codeword is formed
of Ngroup number of bit groups, the number of bit groups Ngroup is not a
multiple of C, and
AxC +1= N smip (A is an integer greater than 0). In other words, it is assumed
that when the
Date Recue/Date Received 2021-10-07
60
number of bit groups constituting the LDPC codeword is divided by the number
of columns, the
quotient is A and the remainder is 1.
In this case, as shown in FIGs 10 and 11, the block interleaver 124 may divide
each column
into a first part including R1 number of rows and a second part including R2
number of rows. In
this case, R1 may correspond to the number of bits included in bit groups
which can be written in
each column in bit group wise, and R2 may be R1 subtracted from the number of
rows of each
column.
That is, in the above-described example, the number of bit groups which can be
written in
each column in bit group wise is A, and the first part of each column may be
formed of as many
rows as the number of bits included in A number of bit groups, that is, may be
formed of as
many rows as Ax M number.
In this case, the block interleaver 124 writes the bits included in the bit
groups which can be
written in each column in bit group wise, that is, A number of bit groups, in
the first part of each
column in the column direction.
That is, as shown in F1Gs. 10 and 11, the block interleaver 124 writes the
bits included in
each of bit group Yo, bit group Y1, = = =, group YA.1 in the 1' to Rid' rows
of the first part of the 1m
column, writes bits included in each of bit group 'IA, bit group YA+1, =..,
bit group Y2A.1 in the 15'
to Rid' rows of the first part of the 2n1 column, ..., writes bits included in
each of bit group YCA-A,
bit group YcA.A.Ei, ..., bit group Yci in the 1g to Rith rows of the first
part of the column C.
As described above, the block interleaver 124 writes the bits included in the
bit groups which
can be written in each column in bit group wise in the first part of each
column.
In other words, in the above exemplary embodiment, the bits included in each
of bit group
(YO), bit group bit
group (YA.1) may not be divided and all of the bits may be written in
the first column, the bits included in each of bit group (YA), bit group
(YA+1),..., bit group (Y2A-1)
may not be divided and all of the bits may be written in the second column,õ,
and the bits
included in each of bit group (YcA.A), bit group (YcA.A+1),... , group (Yok.i)
may not be divided
and all of the bits may be written in the C column. As such, all bit groups
interleaved by the first
part are written in the same column of the first part.
Thereafter, the block interleaver 124 divides bits included in the other bit
groups except the
bit groups written in the first part of each column from among the plurality
of bit groups, and
writes the bits in the second part of each column in the column direction. In
this case, the block
Date Recue/Date Received 2021-10-07
61
interleaver 124 divides the bits included in the other bit groups except the
bit groups written in
the first part of each column by the number of columns, so that the same
number of bits are
written in the second part of each column, and writes the divided bits in the
second part of each
column in the column direction.
In the above-described example, since A xC +1=N group when the bit groups
constituting the
LDPC codeword are written in the first part serially, the last bit group
YNg,õp_i of the LDPC
codeword is not written in the first part and remains. Accordingly, the block
interleaver 124
divides the bits included in the bit group YNgroup-i into C number of sub bit
groups as shown in
FIG. 10, and writes the divided bits (that is, the bits corresponding to the
quotient when the bits
included in the last group (YNgr0up-1) are divided by C) in the second part of
each column serially.
The bits divided based on the number of columns may be referred to as sub bit
groups. In this
case, each of the sub bit groups may be written in each column of the second
part. That is, the
bits included in the bit groups may be divided and may form the sub bit
groups.
That is, the block interleaver 124 writes the bits in the 1st to R2th rows of
the second part of the
1sE column, writes the bits in the 1st to R2th rows of the second part of the
2nd column, ..., and
writes the bits in the 1st to RP rows of the second part of the column C. In
this case, the block
interleaver 124 may write the bits in the second part of each column in the
column direction as
shown in FIG. 10.
That is, in the second part, the bits constituting the bit group may not be
written in the same
column and may be written in the plurality of columns. In other words, in the
above example, the
last bit group (YNgr0up-1) is formed of M number of bits and thus, the bits
included in the last bit
group (YNgToup-i) may be divided by M/C and written in each column. That is,
the bits included
in the last bit group (YNgroup_i) are divided by M/C, forming M/C number of
sub bit groups, and
each of the sub bit groups may be written in each column of the second part.
Accordingly, in at least one bit group which is interleaved by the second
part, the bits
included in the at least one bit group are divided and written in at least two
columns constituting
the second part.
In the above-described example, the block interleaver 124 writes the bits in
the second part in
the column direction. However, this is merely an example. That is, the block
interleaver 124 may
write the bits in the plurality of columns of the second part in the row
direction. In this case, the
block interleaver 124 may write the bits in the first part in the same method
as described above.
Date Recue/Date Received 2021-10-07
62
Specifically, referring to FIG. 11, the block interleaver 124 writes the bits
from the 1st row of
the second part in the 1st column to the 1st row of the second part in the
column C, writes the bits
from the 2" row of the second part in the 1st column to the 2nd row of the
second part in the
column C, etc.,
and writes the bits from the RP row of the second part in the 1st column to
the R2th row of the second part in the column C.
On the other hand, the block interleaver 124 reads the bits written in each
row of each part
serially in the row direction. That is, as shown in FIGs. 10 and 11, the block
interleaver 124
reads the bits written in each row of the first part of the plurality of
columns serially in the row
direction, and reads the bits written in each row of the second part of the
plurality of columns
serially in the row direction.
Accordingly, the block interleaver 124 may interleave a part of the plurality
of bit groups
constituting the LDPC codeword in bit group wise, and divide and interleave
some of the
remaining bit groups. That is, the block interleaver 124 may interleave by
writing the LDPC
codeword constituting a predetermined number of bit groups from among the
plurality of bit
groups in the plurality of columns of the first part in bit group wise,
dividing the bits of the other
bit groups and writing the bits in each of the columns of the second part, and
reading the
plurality of columns of the first and second parts in the row direction.
As described above, the block interleaver 124 may interleave the plurality of
bit groups in the
methods described above with reference to FIGs. 9 to 11.
In particular, in the case of FIG. 10, the bits included in the bit group
which does not belong
to the first part are written in the second part in the column direction and
read in the row
direction. In view of this, the order of the bits included in the bit group
which does not belong to
the first part is rearranged. Since the bits included in the bit group which
does not belong to the
first part are interleaved as described above, bit rrror rate (BER)/frame
error rate (FER)
performance can be improved in comparison with a case in which such bits are
not interleaved.
However, the bit group which does not belong to the first part may not be
interleaved as
shown in FIG. 11. That is, since the block interleaver 124 writes and reads
the bits included in
the group which does not belong to the first part in and from the second part
in the row direction,
the order of the bits included in the group which does not belong to the first
part is not changed
and the bits are output to the modulator 130 serially. In this case, the bits
included in the group
which does not belong to the first part may be output serially and mapped onto
a modulation
Date Recue/Date Received 2021-10-07
63
symbol.
In FIGs. 10 and 11, the last single bit group of the plurality of bit groups
is written in the
second part. However, this is merely an example. The number of bit groups
written in the second
part may vary according to the total number of bit groups of the LDPC
codeword, the number of
columns and rows, the number of transmission antennas, etc.
The block interleaver 124 may have a configuration as shown in tables 23 and
24 presented
below:
[Table 23]
tµimac--- 64800
QPSK 1.6 QAM QM .258 00.4 1.024 pAM 4096 04M-
G 2 4 = ip 8' 10 12
Rt 32400 16200 10800 7920 6480. 5400
R2 0 0 0 1.80 0 0,
_ .
[Table 24]
, .
= tikapetr. 16200:
OPSK 16 QAM 64 -QAM' 256 QAM .1024 QAM 4096 GAM
Z=. 4 6 8 '10. 12
7920 3960 2520 '1800 1.440 1080
R2 180. 90' 180 225 180 270
Herein, C (or Nc) is the number of columns of the block interleaver 124, R1 is
the number of
rows constituting the first part in each column, and R2 is the number of rows
constituting the
second part in each column.
Referring to Tables 23 and 24, the number of columns has the same value as a
modulation
order according to a modulation method, and each of a plurality of columns is
formed of rows
corresponding to the number of bits constituting the LDPC codeword divided by
the number of a
plurality of columns.
For example, when the length Nidpc of the LDPC codeword is 64800 and the
modulation
method is 16-QAM, the block interleaver 124 is formed of 4 columns as the
modulation order is
4 in the case of 16-QAM, and each column is formed of rows as many as
R1+R2=16200(=64800/4). In another example, when the length Nkip, of the LDPC
codeword is
64800 and the modulation method is 64-QAM, the block interleaver 124 is formed
of 6 columns
as the modulation order is 6 in the case of 64-QAM, and each column is formed
of rows as many
as R1+R2=10800(=64800/6).
Date Recue/Date Received 2021-10-07
64
Meanwhile, referring to Tables 23 and 24, when the number of bit groups
constituting an
LDPC codeword is an integer multiple of the number of columns, the block
interleaver 124
interleaves without dividing each column. Therefore, R1 corresponds to the
number of rows
constituting each column, and R2 is 0. In addition, when the number of bit
groups constituting an
LDPC codeword is not an integer multiple of the number of columns, the block
interleaver 124
interleaves the groups by dividing each column into the first part formed of
R1 number of rows,
and the second part formed of R2 number of rows.
When the number of columns of the block interleaver 124 is equal to the number
of bits
constituting a modulation symbol, bits included in a same bit group are mapped
onto a single bit
of each modulation symbol as shown in Tables 23 and 24.
For example, when N1dpc=64800 and the modulation method is 16-QAM, the block
interleaver
124 may be formed of four (4) columns each including 16200 rows. In this case,
the bits
included in each of the plurality of bit groups are written in the four (4)
columns and the bits
written in the same row in each column are output serially. In this case,
since four (4) bits
constitute a single modulation symbol in the modulation method of 16-QAM, bits
included in the
same bit group, that is, bits output from a single column, may be mapped onto
a single bit of
each modulation symbol. For example, bits included in a bit group written in
the 1st column may
be mapped onto the first bit of each modulation symbol.
In another example, when N1dpc=64800 and the modulation method is 64-QAM, the
block
interleaver 124 may be formed of six (6) columns each including 10800 rows. In
this case, the
bits included in each of the plurality of bit groups are written in the six
(6) columns and the bits
written in the same row in each column are output serially. In this case,
since six (6) bits
constitute a single modulation symbol in the modulation method of 64-QAM, bits
included in the
same bit group, that is, bits output from a single column, may be mapped onto
a single bit of
each modulation symbol. For example, bits included in a bit group written in
the lst column may
be mapped onto the first bit of each modulation symbol.
Referring to Tables 23 and 24, the total number of rows of the block
interleaver 124, that is,
R1-FR2, is NidrdC.
In addition, the number of rows of the first part, R1, is an integer multiple
of the number of
bits included in each group, M (e.g., M=360), and maybe expressed as LNgroup /
C iXM and the
number of rows of the second part, R2, may be Islidpc/C-Ri. Herein, LN p C is
the largest
Date Recue/Date Received 2021-10-07
65
integer below Ng.p/C. Since R1 is an integer multiple of the number of bits
included in each
group, M, bits may be written in R1 in bit groups wise.
In addition, when the number of bit groups of the LDPC codeword is not a
multiple of the
number of columns, it can be seen from Tables 23 and 24 that the block
interleaver 124
interleaves by dividing each column into two parts.
Specifically, the length of the LDPC codeword divided by the number of columns
is the total
number of rows included in the each column. In this case, when the number of
bit groups of the
LDPC codeword is a multiple of the number of columns, each column is not
divided into two
parts. However, when the number of bit groups of the LDPC codeword is not a
multiple of the
number of columns, each column is divided into two parts.
For example, it is assumed that the number of columns of the block interleaver
124 is
identical to the number of bits constituting a modulation symbol, and an LDPC
codeword is
formed of 64800 bits as shown in Table 28. In this case, each bit group of the
LDPC codeword is
formed of 360 bits, and the LDPC codeword is formed of 64800/360(.180) bit
groups.
When the modulation method is 16-QAM, the block interleaver 124 may be formed
of four
(4) columns and each column may have 64800/4(=16200) rows.
In this case, since the number of bit groups of the LDPC codeword divided by
the number of
columns is 180/4(=45), bits can be written in each column in bit group wise
without dividing
each column into two parts. That is, bits included in 45 bit groups which is
the quotient when the
number of bit groups constituting the LDPC codeword is divided by the number
of columns, that
is, 45x360(=16200) bits can be written in each column.
However, when the modulation method is 256-QAM, the block interleaver 124 may
be
formed of eight (8) columns and each column may have 64800/8(.8100) rows.
In this case, since the number of bit groups of the LDPC codeword divided by
the number of
columns is 180/8=22.5, the number of bit groups constituting the LDPC codeword
is not an
integer multiple of the number of columns. Accordingly, the block interleaver
124 divides each
of the eight (8) columns into two parts to perform interleaving in bit group
wise.
In this case, since the bits should be written in the first part of each
column in bit group wise,
the number of bit groups which can be written in the first part of each column
in bit group wise is
22, which is the quotient when the number of bit groups constituting the LDPC
codeword is
divided by the number of columns, and accordingly, the first part of each
column has
Date Recue/Date Received 2021-10-07
66
22x360(=7920) rows. Accordingly, 7920 bits included in 22 bit groups may be
written in the
first part of each column.
The second part of each column has rows which are the rows of the first part
subtracted from
the total rows of each column. Accordingly, the second part of each column
includes 8100-
7920(=180) rows.
In this case, the bits included in the other bit groups which have not been
written in the first
part are divided and written in the second part of each column.
Specifically, since 22x8(=176) bit groups are written in the first part, the
number of bit
groups to be written in the second part is 180-176 (=4) (for example, bit
group Y176, bit group
Y177, bit group Y178, and bit group Y179 from among bit group Yo, bit group
Yi, bit group Y2, = =
bit group Y178, and bit group Y179 constituting the LDPC codeword).
Accordingly, the block interleaver 124 may write the four (4) bit groups which
have not been
written in the first part and remains from among the groups constituting the
LDPC codeword in
the second part of each column serially.
That is, the block interleaver 124 may write 180 bits of the 360 bits included
in the bit group
Y176 in the 1st row to the 180th row of the second part of the 1" column in
the column direction,
and may write the other 180 bits in the 1" row to the 180th row of the second
part of the 2thi
column in the column direction. In addition, the block interleaver 124 may
write 180 bits of the
360 bits included in the bit group Yin in the 1" row to the 180th row of the
second part of the 31e1
column in the column direction, and may write the other 180 bits in the 1" row
to the 180th row
of the second part of the 4th column in the column direction. In addition, the
block interleaver
124 may write 180 bits of the 360 bits included in the bit group Y178 in the
1st row to the 180th
row of the second part of the 5t1i column in the column direction, and may
write the other 180
bits in the 1" row to the 180th row of the second part of the 6th column in
the column direction. In
addition, the block interleaver 124 may write 180 bits of the 360 bits
included in the bit group
Y179 in the 1st row to the 180th row of the second part of the 7th column in
the column direction,
and may write the other 180 bits in the 1" row to the 180th row of the second
part of the 8th
column in the column direction.
Accordingly, the bits included in the bit group which has not been written in
the first part and
remains are not written in the same column in the second part and may be
divided and written in
the plurality of columns.
Date Recue/Date Received 2021-10-07
67
Hereinafter, the block interleaver 124 of FIG. 5 according to an exemplary
embodiment will
be explained in detail with reference to FIG. 12.
In a group-interleaved LDPC codeword (vo, v1, ..., ), Yi
is continuously arranged like
V=(Yo, YI, = = = YN -11 -
The LDPC codeword after group interleaving may be interleaved by the block
interleaver 124
as shown in FIG. 12. In this case, the block interleaver 124 divide a
plurality of columns into the
first part(Part 1) and the second part(Part 2) based on the number of columns
of the block
interleaver 124 and the number of bits of bit groups. In this case, in the
first part, the bits
constituting the bit groups may be written in the same column, and in the
second part, the bits
constituting the bit groups may be written in a plurality of columns(i.e. the
bits constituting the
bit groups may be written in at least two columns).
Specifically, input bits vi are written serially from the first part to the
second part column
wise, and then read out serially from the first part to the second part row
wise. That is, the data
bits vi are written serially into the block interleaver column-wise starting
in the first aprt and
continuing column-wise finishing in the second part, and then read out
serially row-wise from
the first part and then row-wise from the second part. Accordingly, the bit
included in the same
bit group in the first part may be mapped onto a single bit of each modulation
symbol.
In this case, the number of columns and the number of rows of the first part
and the second
part of the block interleaver 124 vary according to a modulation format and a
length of the
LDPC codeword as in Table 25 presented below. That is, the first part and the
second part block
interleaving configurations for each modulation format and code length are
specified in Table 25
presented below. Herein, the number of columns of the block interleaver 124
may be equal to the
number of bits constituting a modulation symbol. In addition, a sum of the
number of rows of the
first part, Na and the number of rows of the second part, Na, is equal to
1=11dp,JNc (herein, Nc is
LNgrcup /Nd x 360
the number of columns). In addition, since N11(= )is a
multiple of 360, a multiple
of bit groups may be written in the first part.
[Table 25]
Date Recue/Date Received 2021-10-07
68
Rows in Part 1 No Rows in Part 2 N r2
Modulation Columns Ne
Nicipc =64800 Nidpc =16200 Noe =64800 Nicipc = 16200
QPSK 32400 7920 0 180 2
16-0AM 16200 3960 0 90 4
64-0AM 10800 2520 0 180 6
256-QAM 7920 1800 180 225 8 ,
1024-QAM 6480 1440 0 180 10
4096-QAM 5400 1080 0 270 12
Hereinafter, an operation of the block interleaver 124 will be explained in
detail.
Specifically, as shown in FIG. 12, the input bit vi (0 i <Nc xNõ) is written
in ri row of ci
column of the first part of the block interleaver 124. Herein, c,i and ri are
ci = [-U and ri=(i
Arri
mod Nri), respectively.
In addition, the input bit vi (N õxNõ i<N,õpc) is written in ri row of ci,
column of the
second part of the block interleaver 124. Herein, ci and ri satisfy ci = [0 -
NC x Nri )] and
Nõ
r,=Nõ+{(i-Nc x No, ) mod Nr2} , respectively.
An output bit q;(0j<N1cipc) is read from ci column of ri row. Herein, rj and
cj satisfy
i
r. = [ -.f-- and ci-.(j mod Nc), respectively.
For example, when the length Nidpc of an LDPC codeword is 64800 and the
modulation
method is 256-QAM, the order of bits output from the block interleaver 124 may
be
(9),qi,q2,===,q633579C163358)(163359,(163360,C163361)===,C164799)=
(Voy7920,Vismo,...,V47519,V554390763359,V63360,V63540)= -Y64799). Herein, the
indexes of the right side of
the foregoing equation may be specifically expressed for the eight (8) columns
as 0, 7920, 15840,
23760, 31680, 39600, 47520, 55440, 1, 7921, 15841, 23761, 31681, 39601, 47521,
55441, ... ,
7919, 15839, 23759, 31679, 39599, 47519, 55439, 63359, 63360, 63540, 63720,
63900, 64080,
64260, 64440, 64620, ... , 63539, 63719, 63899, 64079, 64259, 64439, 64619,
64799.
Hereinafter, the interleaving operation of the block interleaver 124 will be
explained in detail.
The block interleaver 124 may interleave by writing a plurality of bit groups
in each column
in bit group wise in a column direction, and reading each row of the plurality
of columns in
Date Recue/Date Received 2021-10-07
69
which the plurality of bit groups are written in bit group wise in a row
direction.
In this case, the number of columns constituting the block interleaver 124 may
vary according
to a modulation method, and the number of rows may be the length of the LDPC
codeword/the
number of columns.
For example, when the modulation method is 16-QAM, the block interleaver 124
may be
formed of 4 columns. In this case, when the length Moe of the LDPC codeword is
16200, the
number of rows is 16200 (=64800/4). In another example, when the modulation
method is 64-
QAM, the block interleaver 124 may be formed of 6 columns. In this case, when
the length IsTidpc
of the LDPC codeword is 64800, the number of rows is 10800 (-64800/6).
Hereinafter, the method for interleaving the plurality of bit groups in bit
group wise by the
block interleaver 124 will be explained in detail.
When the number of bit groups constituting the LDPC codeword is an integer
multiple of the
number of columns, the block interleaver 124 may interleave by writing the bit
groups as many
as the number of bit groups divided by the number of columns in each column
serially in bit
group wise.
For example, when the modulation method is 16-QAM and the length Mdi. of the
LDPC
codeword is 64800, the block interleaver 124 may be formed of four (4) columns
each including
16200 rows. In this case, since the LDPC codeword is divided into
(64800/360=180) number of
bit groups when the length Nidp, of the LDPC codeword is 64800, the number of
bit groups
(.180) of the LDPC codeword may be an integer multiple of the number of
columns (=4) when
the modulation method is 16-QAM. That is, no remainder is generated when the
number of bit
groups of the LDPC codeword is divided by the number of columns.
In this case, as shown in FIG. 13, the block interleaver 124 writes the bits
included in each of
the bit group Yo, bit group Y1....., bit group Y44 in the 1st row to 16200th
row of the first column,
writes the bits included in each of the bit group Y45, the bit group the
bit group Y89 in the
1st row to 16200th row of the second column, writes the bits included in each
of the bit group Y90,
the bit group Y91,..., the bit group Yi34 in the 1st row to 162001h row of the
third column, and
writes the bits included in each of the bit group Y135, the bit group
Y136,..., the bit group Y179 in
the 1st row to 16200th row of the fourth column. In addition, the block
interleaver 124 may read
the bits written in each row of the two columns serially in the row direction.
In another, when the modulation method is 64-QAM and the length N1 of of the
LDPC
Date Recue/Date Received 2021-10-07
70
codeword is 64800, the block interleaver 124 may be formed of six (6) columns
each including
10800 rows. In this case, since the LDPC codeword is divided into
(64800/360=180) number of
bit groups when the length I=lidpc of the LDPC codeword is 64800, the number
of bit groups
(=180) of the LDPC codeword may be an integer multiple of the number of
columns (.4) when
the modulation method is 64-QAM. That is, no remainder is generated when the
number of bit
groups of the LDPC codeword is divided by the number of columns.
In this case, as shown in FIG. 14, the block interleaver 124 writes the bits
included in each of
the bit group Yo, bit group Y1....., bit group Y29 in the 1" row to 10800th
row of the first column,
writes the bits included in each of the bit group Y30, the bit group Y31,...,
the bit group Y59 in the
1' row to 108001h row of the second column, writes the bits included in each
of the bit group Y60,
the bit group Y61,..., the bit group Y89 in the 1" row to 10800th row of the
third column, writes
the bits included in each of the bit group Y90, the bit group Y91,..., the bit
group Y119 in the 1"
row to 108001h row of the fourth column, writes the bits included in each of
the bit group Y120,
the bit group Y121,-=., the bit group Y149 in the 1" row to 10800th row of the
fifth column, and
writes the bits included in each of the bit group Y150, the bit group
Y151,..., the bit group Y179 in
the 1" row to 10800th row of the sixth column.. In addition, the block
interleaver 124 may read
the bits written in each row of the two columns serially in the row direction.
As described above, when the number of bit groups constituting the LDPC
codeword is an
integer multiple of the number of columns of the block interleaver 124, the
block interleaver 124
may interleave the plurality of bit groups in bit group wise, and accordingly,
the bits belonging to
the same bit group may be written in the same column.
As described above, the block interleaver 124 may interleave the plurality of
bit groups of the
LDPC codeword in the method described above with reference to FIGs. 13 and 14.
The modulator 130 maps the interleaved LDPC codeword onto a modulation symbol.
Specifically, the modulator 130 may demultiplex the interleaved LDPC codeword,
modulate the
demultiplexed LDPC codeword, and map the LDPC codeword onto a constellation.
In this case, the modulator 130 may generate a modulation symbol using the
bits included in
each of a plurality of bit groups.
In other words, as described above, the bits included in different bit groups
are written in each
column of the block interleaver 124, and the block interleaver 124 reads the
bits written in each
column in the row direction. In this case, the modulator 130 generates a
modulation symbol by
Date Recue/Date Received 2021-10-07
71
mapping the bits read in each column onto each bit of the modulation symbol.
Accordingly, each
bit of the modulation symbol belongs to a different bit group.
For example, it is assumed that the modulation symbol consists of C number of
bits. In this
case, the bits which are read from each row of C number of columns of the
block interleaver 124
may be mapped onto each bit of the modulation symbol and thus, each bit of the
modulation
symbol consisting of C number of bits belong to C number of different bit
groups.
Hereinbelow, the above feature will be described in greater detail.
First, the modulator 130 demultiplexes the interleaved LDPC codeword. To
achieve this, the
modulator 130 may include a demultiplexer (not shown) to demultiplex the
interleaved LDPC
codeword.
The demultiplexer (not shown) demultiplexes the interleaved LDPC codeword.
Specifically,
the demultiplexer (not shown) performs serial-to-parallel conversion with
respect to the
interleaved LDPC codeword, and demultiplexes the interleaved LDPC codeword
into a cell
having a predetermined number of bits (or a data cell).
For example, as shown in FIG. 15, the demultiplexer (not shown) receives the
LDPC
codeword Q.(q0, qi, q2, ...) output from the interleaver 120, outputs the
received LDPC
codeword bits to a plurality of substreams serially, converts the input LDPC
codeword bits into
cells, and outputs the cells.
In this case, the bits having the same index in each of the plurality of
substreams may
constitute the same cell. Accordingly, the cells may be configured like (yo,o,
Yi,o, = = noon-
1,0)=(q0, qi, ChMOD-1), (y0,1, Yi,i, = = =, YliMOD-1,0( q1MoD, 1:11M0D+1, = =
= , Cl2xtIMOD-1), = = = ==
Herein, the number of substreams, Nsubste, may be equal to the number of bits
constituting
a modulation symbol, Timm Accordingly, the number of bits constituting each
cell may be equal
to the number of bits constituting a modulation symbol (that is, a
modulationorder).
For example, when the modulation method is 16-QAM, the number of bits
constituting the
modulation symbol, Timm, is 4 and thus the number of substreams, Nsubstreams,
is 4, and the cells
may be configured like (y0,0, Y1,0) Y2,0) Y3,0)=(:10) qi, (12, q3), Y2,1,
y33).--(q4,445, q6,q7), (3'02,
Y1,2, Y2,2) Y3,2)4118, C191 (110, C111)) = = = =
In another example, when the modulation method is 64-QAM, the number of bits
constituting
the modulation symbol, 11MOD) is 6 and thus the number of substreams,
Nsubstreams, is 6, and the
cells may be configured like (y0,0, yi,o, yzo, Y3,0, ya,o, Y5,o)=(clo, Qi,
(12, (13, C14) CIA (370,1, yi,i, y2,1, Y3,1,
Date Recue/Date Received 2021-10-07
72
Y4,1, Y5,1)4146,q7, C18,C19,1410,(111), (Y0,2, y1,2, y2,2, Y3,2, y4,2, Y5,2)'-
'--(C112, C113,1=114, q15, (116/ q17),....
The modulator 130 may map the demultiplexed LDPC codeword onto modulation
symbols.
Specifically, the modulator 130 may modulate bits (that is, cells) output from
the
demultiplexer (not shown) in various modulation methods such as Quadrature
Phase Shift
Keying (QPSK), 16-QAM, 64-QAM, 256-QAM, 1024-QAM, 4096-QAM, etc. For example,
when the modulation method is QPSK, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, and
4096-
QAM, the number of bits constituting the modulation symbol, Timm (that is, the
modulation
order), may be 2, 4, 6, 8, 10 and 12, respectively.
In this case, since each cell output from the demultiplexer (not shown) is
formed of as many
bits as the number of bits constituting the modulation symbol, the modulator
130 may generate
the modulation symbol by mapping each cell output from the demultiplexer (not
shown) onto a
constellation point serially. Herein, the modulation symbol corresponds to a
constellation point
on the constellation.
However, the above-described demultiplexer (not shown) may be omitted
according to
circumstances. In this case, the modulator 130 may generate modulation symbols
by grouping a
predetermined number of bits from interleaved bits serially and mapping the
predetermined
number of bits onto constellation points. In this case, the modulator 130 may
generate the
modulation symbols by mapping rimoD number of bits onto the constellation
points serially
according to a modulation method.
The modulator 130 may modulate by mapping cells output from the demultiplexer
(not
shown) onto constellation points in a non-uniform constellation (NUC) method.
In the non-uniform constellation method, once a constellation point of the
first quadrant is
defined, constellation points in the other three quadrants may be determined
as follows. For
example, when a set of constellation points defined for the first quadrant is
X, the set becomes ¨
conj(X) in the case of the second quadrant, becomes conj(X) in the case of the
third quadrant,
and becomes ¨(X) in the case of the fourth quadrant.
That is, once the first quadrant is defined, the other quadrants may be
expressed as follows:
1 Quarter (first quadrant)=X
2 Quarter (second quadrant)=-conj(X)
=
3 Quarter (third quadrant)=conj(X)
4 Quarter (fourth quadrant)=-X
Specifically, when the non-uniform M-QAM is used, M number of constellation
points may
Date Reeue/Date Received 2021-10-07
73
be defined as z.(zo, z1, zm_il. In this case, when the constellation points
existing in the first
quadrant are defined as {xo, xi, x2, ..., xm/.4.1}, z may be defined as
follows:
from zo to zt,v44=from Xo to Xm/4
from zum to z2õ)&44.-conj(from xo to xh4/4)
from Z2x/w4 to z3.14/4-1=conj(from xo to xmf4)
from Z3**4/4 to Z4õw4_1=-(fIT)111 X0 to xmg)
Accordingly, the modulator 130 may map the bits [yo, ym_i] output from the
demultiplexer
(not shown) onto constellation points in the non-uniform constellation method
by mapping the
output bits onto zt, having an index of L = E (y x 2m1). An example of the
constellation
defined according to the non-uniform constellation method may be expressed as
in tables 26 to
30 presented below when the code rate is 5/15, 7/15, 9/15, 11/15, 13/15:
[Table 26]
Input data cell y Constellation point zi
(00) (1+10/.ff
(01) (1-10/4F
(10) (-1 +1i)/4-
(11)
[Table 27]
- . =
t= rist4., Asti , kits gaols- titifts owls. !RIVIs =
SA15304020131, L2111+0.50261 =12.4015+0,b751 0A104.1.20071 021731+0A11111
0.951140.95471. 11299110.71591 0.4517+055111
*I =
Ø1651+tu15101, 0.5014+111021. 0.2515+0.41101 1,110740.49011 0.157eminnu
0.164740.211041 0.15411+0.29141 -0.9514+050011
.2
2.200244251150,, 04624+406244 1.20Ø0....1511 1.244044130151, .114226+1.14451
.1.142t40.55521 0.299.44255401 L306744193144
e5115.t.7Oet0.252+1Ø16171 04451.1.211611 11.515340.24701 1.20011+0.5059+
12000+11.2921 11.1540.17.55401 0.31151.0345i1
[Table 28]
f5bp.014.054 , õ _01141_1115 1114_1(15 ,R44_204,15
R54....11/15 R04,17/1.3 ,4154_LV15 _
3.43117.1.63231, 43.432+11.61118r, 100241232.01 435117411.61Air, 1013000267111
.1.133174.ier1ai t0164+03,3941- 4.41.040.7477t
= 1J0210.043871,. 0:79774111.651141 1:3563.Ã1.04111 _0.1511411.85421.,
1219)Ø8113. a.issekliamt .0:703,4446.231 :01343.0:53054
0.1111.0182111' '1.021.1.8.22141 0.1.511141.22.11,' .t.5aford.0h4t = .
Oa5fl4444311,. ,2.647440.118.45t, 01206.1.112,10p=
11' = totorwitnor
0,103o4o,3o331- ,o.tross.mgat 4.1.13o4olroot ,O1eWcM14o 0,1P044.1.1721,..
071434015944- 01230Ø16051
*4, '0421)149.14,(11=:' 049003.405451' = 0.2920.1.4.376
04177.0,1010,1 0:35311.140651 -0,5142.049:41' 1,08013Ø140111 =
042115Ø46171
= 6./.111Ø113101 )6,0171,1020441, 01.111+1.21611. 0.225240.0161-
0.021041.52711 ;0:61/540.10151. ,,.11.2142+000721' Ø31/4140.15664
01049.004540 03022+1117111, oatit.toloo c45opoan6t.
:0106.1.05491, 0339740.3401r 14251.40.22211.' 0001740.15411,
er. 0,21135Ø13410 tii90211.01lddt 05545u,51a
4.372i4018361- 431117.1.0/11,-434doOJat 11,016:144.N1e3i
:70.3694Ø3.3one
,i17111.114.201.91 Ciales&a,2927, Ø3041H=0.14756,.. 0.56,394114B641-
:11A11.110,01170 .Ø8004+4652,7v.,. 0.1a92+441781 0.7261411.112010
41: 2354. eat:
02352+1.01301 0.3411140,14011. 0.1.61041.02774: 11.39914112511111.
0.11.200.1.12531 ailains0.42031 ..L14511.*to.54153
00. ' C1.7540.4.26531 01155-ti.2801 .
0.4161115Ø1.117111. 0.5193+1 25091 03442,6.15591 04994.507111
1140703.133,61 0416641.2733i.
tlt= 0.84560004W 0.2412+210545
0..9926r0.93631 '041601+1069111., .0150440A9367 '0.011.1-4051..
0A105+0.110111'. 0.511117+1.17911.
4/174Ø21751.. 5.9l39pc55199. =0.1429t019494 01654+0,10141 0,11460016/11.
0.0100145075+ 4.1510141.70579 115011+05140.1-
wW _ .03111.1142675r.. ,..1.5197.021511.. .0,1091=11.20201
101112=1221111 '0.1512Ø31L5+" o.srooicamot....0,41/74,7261k
"L771.1Ø5.151.
44 0.1110.02/011
14621140.1.571 Ø107140045111' = 1.21614014361_ 1.135049.74011,
312219+0.42601. = 0.101241.01101 = 4.9916+0.1711i
= 105.
*0220140554er '11.A2:14+11.75221. Ø5161+0.01161 a..406140.210)1+ catntotator
L oott:lotai, 0.2:107#1:30366 . 1341240.144M
[Table 29]
=
Date Recue/Date Received 2021-10-07
74
a/Shape ___ NU0_64 44013 fix It 105 tax_scalts taxj4 Wis N04_54_1003 MC 64 UM
NUC 91-12/15 1tUC &1-12/13
KO 0.4347+1.60231 033524160261 . 1.442740.24201 0.354740.61491
1.43111140.24722 03317+0.6970 1.01154.053941 413524 + 1.171.51
=
1.602340.43471 0.3177Ø65601 1.256340151111 0.156140,632)1 1.213310.21.331 0-
138648824 junSswIssai 1.1184 4. 0.44621 =
118753.108811 017114030261 1.021140.21741 0.15674027491 1.03664022191
01323404437i 1.047440.16951 C.2113+1.38431
93 ^ = 13291+087531 01556.030351 0.117944157021 0.1336441.27001,
0.84941061451 0101541.13721 0.724340.19341 0.7635 + 037071
94 0M02441.92381 0.602340.33451 02920+148271 0.617740.40301
_02931+1.46561 0.5682414556 1.069393.94621 117964 0.16611
4 0.201410.78181 , 0.65774020441 , 03410.125631 0.726240.17514
0323041.22781 , 0.67394.14354 0709240.80.731 1.0025 +0.48221
0304940.44541 0302141117111 021744102111 0356240.17111. 0.206941.06491
0.359740.34014 1.426140.22161 0.4101 0.14921
17 026534075401 _0.302640_1556i 05702441117931 0377140.11361
036774029711 036604112041 0.61064.17631 01482 0.44771
46 028184020191 055564039221 030404036754 0563840.44644
0.411340.11771 0.6006411/19221 0.139240.4073/ 0.1524=059431
=
0.9215+0.22011 41235241.01901 0.30264025911 0.19504102771 0.33950.25161
021200122531 042624042051 0.1482 0.66771
40 075930.26531 tianausim 0.685540.16711 0.11199.115151 0.7442411593
0.9594+10715 014074013364 04642 4. 1.02,531
41 1134544130493= 029224.44941. 0142640.33631 0.28544.469/1
0595440.432E6 03/29013995 0.4204013881 01992Ø73534
912 0.26754124791 0291900.55491 01,175409310 01165440.6055
011664016761 03439405675 0130640.70571 0.1572+4113191
LAU 024794076751 1.019740.23591 016914030281 13311240.2145
0.15824/33251 0.476900.19591 0.419740.72061 01458 40.40251
10011 026934027014 L26264136571 0.167140.6E551 12362404413 0.13554674061
L22390167601 0163241.03161 04763 +0.1407i
91.5 0.2701Ø28901 L4894.029221 0358840.61244 1.46634129731
0.32274062001 1.1653.412323 µ_ 02287+139141 0.4411+0.426T1
[Table 30]
=
Date Recue/Date Received 2021-10-07
75
/5641.9 14/15 117/15 14845 19/15 1110/15 511/15
512/15 51305
50 0.61004.69261 1.2905+1.30991 1.0104+1.37881 1.3331+1.15061
1.60974.15441 0.3105413111 1.101441.16701 0.355540.31971 '
01 0.3911+1.36451 105044.95771 1.041740.98621 0.9851+115111
1.554940.46051 0.43424.3360 0.15574.24211 0.35794045451
62 0.21914.75241 1.53294.19351 1.6444Ø74281 1.1439+0.89741
1.32260.12901 0.314940.41291 1195740.80391 0.5049+035711
43 0.2174+1.42081 , /157740.11161 3324540.94141 0.93434.92711
1.27724.35291 0.44004091071 1.0881+0.89561 0.5056/0.50631
046784.24871 1.7885*0.25091 0.7194424271 1.5398Ø79621
1.2753+1.02421 0181140.33751 0.5795+1.211W 0.2113434971
83 0.7175.1,16671 1.427530.14001 2.81064.00401 ,.03091.4255991
1.44344.75401 0.0633.034041_ 0.663741.42151 0.211540.49001
36 0.874741.04701 1.478440.52011 0.5595+1.03171 1.222100.65741
1.049140.84761 0.181840.48511 0.693041.00821 0.0713Ø34591
87 0.7930+1.04051 1.34084.43461 0.611840.97221 .
0.95790.53731 1.121614.62531 0.053140.48151 020494.96471
0.049040.49601
94 0.10560.97031 0.71074.58671 147684.20021 0.77414.58671
0.93264.09701 03084Ø19711 1.20634.51151 0.35274010861
0.2241+1.04541 010504.54551 0.999740.61441 0.68764.24891
0.89624.29041 0.435640.19931 1.010940.49521 0.3497Ø07131
410 0.18584096781 0.825640.56011 1.41/240.47691 0.599249200
1.1044411021 0.3091Ø06764 1.4171+0.59011 0.49604.21131
all 0.1901410650 0.877740.61101 1.147940.63121 0.6799+037431
1.06484.33671 0.4342Ø06911 1.0464+0.69351 0.497440 06981
012 0,5547.043121 1.008040.18431 060794.65661 1358364031170
0.7315Ø60711 0.1775.319831 0.66394.63881 5.208640.20791
013 03479415511 1.07594.17211 0.728440.69571 0.69154.5766
5.876040.45591 0.06404019791 0.53534.58511 0.20944006901
Ell 0.6073.011921 1.00560.17581 0.572440.70311 0.3251Ø705/1
0.874440.71531 0.17750.06761 0.68794.80221 5.06760.20791
515 0.595540.44201 1.0662Ø29641 0.6302.3.73591 0.68684.67931
0.98826053001 0.064740.06691 0.1634Ø76221 0.069840.06831
*16 1.407040.17901 021334+1.55541 0.145741.40101 1.6115.7.14971
0.164691.64071 0.74554.34111 0.1213.1.43661 0.358640.79591
417 1.7127.0290111 0.81139441.112921 0.1856+1.73461
0.951140.11401 0.4867.357431 0.58116133961 0.1077+3.20981
0.357110.63921
019 1.3246.025621 0.6091.1.27291 0.1174.1.10351 1.4700.12341
0.13634.35791 0.755640.46691 0.0651Ø90011 0.506.40.62751
919 13636.036541 0.6728+1.14561 0.1095+1.01321 1.0266411911
0.4021430761 0.5561447561 0.200941.01151 0.50634064001
120 1.3705.1.21341 0.306141.74651 00357+1.36361 1.58114.44961
114424.25841 0.9556Ø32101 0.3765+1.42641 0.21440.78621
321 1.67014.844131 0.132741.40561 0.585341.58201 0.932340.35861
0.7975+144501 1-176740.30911 0.3237+1.21301 0.210940.63401
422 1.161440.79091 0.35224114141 0.3439.1.06891 1.27964.38941
0.116874.04071 0.94730.47201 0.5205+0.98141 0.071340.60931
A3 1.22414.73671 0.2273+1.30811 0.3234Ø99621 1.01854.34471
0.650241.19111 1.2051Ø51351 0.3615+1.01631 0.069640.64671
124 0.976940.18631 0.500734.90981 0.1092Ø61741 0.594040.10591
0.09524097451 0.736740.20151 0.0715Ø65961 017994.08621
825 0.9451+0/0571 0.552810.83471 0.107440.63071 0.72150.11001
0.284210.93441 0.58112010151 0.211640.65971 018064117551
46 1.01004021821 0.4843.10.14561 0.111190.69961 0.58634.1130
011424.14481 0.73160.04691 0.0719Ø81311 0.43214099041
517 0.9795.014171 0.5304Ø87591 0.107640.73451 0.69094.1/661
0.3385.1.09731 0.578240.06691 0.21580.82461 0.4551+1.18121
320 0.1041404950 0.17150.91471 0.3191Ø82641 0.58434.36041
0.6062+0.74651 0.9062Ø19711 0.50364.64671 0.230940.94141
429 0.12324.41371 0.1540Ø95101 0.3126Ø63731 0.89704.35931
17.4607Ø853111 1.2829.011851 0.35160.65721 0.10774.31911
130 021799.053911 0.19544.94381 0.3392Ø69991 0.58080.31501
0.72634.117641 0.9155Ø07351 0.5115440861 00771.018511
031 0.11796Ø53561 0.171184.98321 0320140.72421 0.66784.32901
05450+1.00671 1.10114.67351 0.9593=45,82951 0.010241.17531
x32 0137640.33421 0.37514.15671 0.9552Ø10661 0.140641.61811
01655Ø07461 0.32444.10441 1.254540.10101 0.83014037271
.33 0.1383Ø31931 0.37344.16671 0.9075Ø16661 0.117241.29541
0.1664Ø07591 0.45894.12181 1.057640.09561 0.825640.52561
*34 0.13694.9322/ 0.3758415411 0.972440.11711 0.2211Ø9640
0.45724).03521 0.320740.44151 1.47524.1157/ 0.4593Ø36681
a35 0.13700.32711 0.374640.16491 0.918640.17511 0.1210+1.03931
0.451640.10621 0.4509Ø63711 0.89814.08821 0.56230.51821
.26 0.1655.032651 0.401334.12301 0.63410.13721 0.11244.61011
0.2559Ø17901 0.19204.51961 0.55184.06901 1.018610.36451
337 0.16564.31271 0.4001Ø12301 0.655040.14951 0.11774.60411
0.2586Ø17721 0.0633Ø81671 0.690340.05521 1.00010.51421
335 0.16344.31461 0.403740.12301 0.6290Ø13931 0.113640.74651
0.35924010111 0.18114.63711 0.57434193171 1.1115740.27351
439 0.163600.11081 0.40190.12161 0.6494Ø15041 0.1195+0.71601
0.37211426541 0.0640Ø64151 0.737440.15641 1.3928Ø34081
E40 0.1779+0.68411 0.602540.39141 131270.12401 0.432441.56791
0.7705Ø09121 0.3331.1.06691 1.23784.30491 02101140.22271
441 0.1828Ø68451 0.59464.392131 0957240.43441 0.3984+1.28151
0.7407Ø22401 0.4655+1.00871 1.05184030321 0.79810.07351
!42 0.1745Ø65261 0.6116+0.33791 1.1403Ø26311 0.376640.95341
0.6180Ø09271 0.343341.13651 1.4584Ø35111 0.645940.21951
443 0.179340.68391 0.60194.38371 1.0254Ø41301 0.365541.03011
0.60190.16581 0.500441.50621 0910740.24031 0 64304.57131
044 0.354730.60091 0.737740.1610 0.6096Ø41141 0.36674.59951
0.6007.0 49101 0.1971+1.00511 0432/4.47291 04481Ø13051
445 0.35934014111 0.719840.15821 0.677340.41841 0.332140.5960
0.667140.39181 0.07354.01951 0.78804.43921 0.9613Ø07351
946 0.357640.59901 0.72744.17821 05595Ø41011 0.36570.71941
0.4786.039351 0.1498+1.50181 1360450.32741 1332740.10391
47 0.362440.59941 0.716540.17461 0.653110.41011 0.33730.69641
0.517640.33911 0.0/6541.25531 0.7619019651 1.135910.08091
049 0.269740.14431 0.1509..33291 0.17517Ø21531 0.1065.9.11461
0,075740,10091 03811Ø710801 0.0596*0.07391 0.838140.87091
8*9 0.270430.14331 11.150341124001 0.125240.11581 0.11454.1100
0.0753Ø10041 0.61674211531 017670.07311 0.814540.69341
950 0164440.14421 0.1515+0.24371 0.1245Ø11521 010534.12741
0.07774047681 0.76364.62551 0.06170.21981 0.66460014801
x51 0.26504.14321 0.15034.14251 0.124740.11561 0.11340.1230
0.086740.47541 060004.63271 1110159321921 0.660040.67841
052 0.276340.16381 0.12154.13881 037650.12441 0.11114.38211
0.1021412431 0.98984.76901 0421840.07151 1./61140.69491
553 0.276840.16261 0.127940.24191 0.37070.12371 0.115640.35671
0.101040.21421 1.585540.14951 6297440.07251 0.974540.69421
x54 0.27150.16301 0.117940.24311 0.37790.12601 0.1080.2.34311
0.15504039191 0.94764.41751 04337Ø21151 1.3698Ø62591
x55 0.2719Ø16111 0.1279424061 0.3717411521 0.1177+0.34591
0.1881439691 1.46254.40151 0.30574.21671 1.210340.48411
056 0.648840.16961 0.3394Ø57641 0.11610.36931 0.354440.10801
0.093010.81221 0.827641.02251 0.066740.51241 0.7989+1.04981
057 0.546140.17001 0.336Ø97121 0.119700315451 0.32624.1100
012154011401 0.631341.03541 02700o0.5395 0.43954341031
458 01456E017431 03334.57501 0./1760034691 0.36814011731
0.093740.65141 0A1815+1.28551 0.06250.36581 0.61114.02461
.59 0.64314.17531 03303.034981 0.1171Ø14141 0.3159Ø11961
0.15404063461 0.63414.27051 0.111994.36421 0.63034114111
x60 0.58544.311161 0.14914.63161 035300.38991 0.36654.37581
0.4810.063061 1.042240.95931 0.481540.49461 1.055040.89241
061 0.5862+0.31671 0.1481+0.62801 0.34224.38081 033100.37951
0.3856Ø70371 1.2749+0.85381 0,3380Ø50501 0.861241.28001
062 0386430.31751 0.15090.62801 036144.37591 0.36724033531
0.35270.52301 1.15544.19471 0,457110.34991 1.269640.89691
453 038734032541 0.14734.62251 0.35094.36561 0.3336+0.34021
0.3100.055591 1.877146,67101 913510.0,35131 1.034241.12811
Table 26 indicates non-uniform QPSK, table 27 indicates non-uniform 16-QAM,
Tables 28
Date Recue/Date Received 2021-10-07
76
and 29 indicate non-uniform 64-QAM, and table 30 indicates non-uniform 256-
QAM.
Referring to these tables, the constellation point of the first quadrant may
be defined with
reference to tables 26 to 30, and the constellation points in the other three
quadrants may be
defined in the above-described method.
However, this is merely an example and the modulator 130 may map the output
bits outputted
from the demultiplexer (not shown) onto the constellation points in various
methods.
The interleaving is performed in the above-described method for the following
reasons.
Specifically, when the LDPC codeword bits are mapped onto the modulation
symbol, the bits
may have different reliability (that is, receiving performance or receiving
probability) according
to where the bits are mapped onto in the modulation symbol. The LDPC codeword
bits may have
different codeword characteristics according to the configuration of a parity
check matrix. That is,
the LDPC codeword bits may have different codeword characteristics according
to the number of
1 existing in the column of the parity check matrix, that is, the column
degree.
Accordingly, the interleaver 120 may interleave to map the LDPC codeword bits
having a
specific codeword characteristic onto specific bits in the modulation symbol
by considering both
the codeword characteristics of the LDPC codeword bits and the reliability of
the bits
constituting the modulation symbol.
For example, when the LDPC codeword formed of bit groups Xo to Xi79 is group-
interleaved
based on Equation 21 and Table 11, the group interleaver 122 may output the
bit groups in the
order of X55, X146, X83, = = = X132, X135.
In this case, when the modulation method is 16-QAM, the number of columns of
the block
interleaver 124 is four (4) and each column may be formed of 16200 rows.
Accordingly, from among the 180 groups constituting the LDPC codeword, 45 bit
groups
(X55, X146, X83, X52, X62, X176, X160, X68, X53, X56, X81, X97, X79, X113,
X163, X61, X58, X69, X133,
X108, X66, X71, )(86, X144, X57, X67, X116, X59, X70, X156, X172, X65, X149,
X155, X82, X138, X136, X141,
X111, X96, X170, X90, X140, X64, X159) may be inputted to the first column of
the block interleaver
124, 45 bit groups (X15, X14, X37, X54, X44, X63, X43, X18, X47, X7, X25, X34,
X29, X30, X26, X39,
X16, X41, X45, X36, X0, X23, X32, X213, X27, X38, X48, X33, X22, X49, X51,
X60, X46, X21, X1, X3, X20,
X13, X50, X35, X24, X40, X17, X42, X6) may be inputted to the second column of
the block
interleaver 124, 45 bit groups (X112, _93X , X _127, X101, X94, X115, X105,
X31, X19, X177, X74, X10, X145,
X1625 X102, X120, x126, X95, X73, X152, x1295 X1745 X125, X72, X128, X78,
X1715 X8, X142, X178, X154,
Date Recue/Date Received 2021-10-07
77
X85, X107, X75, X12, X9, X151/ X77, X117, X109, X80, X106, X134, X98, Xi) may
be inputted to the third
column of the block interleaver 124, and 45 bit groups (X122, X173, X161,
X150, X110, X175, X166,
X131, X119, X103, X139, X148, X157, X114, X147, X87, X158, X121, X164, X104,
X89, X179, X123, X118, X99,
X88, X11, X92, X165, X84, X168, X124, X169/ X2, X130, X167, X153, X137, X143,
X91, X100, X5, X761 X132,
X135) may be inputted to the fourth column of the block interleaver 124.
In addition, the block interleaver 124 may output the bits inputted to the
1.st row to the last
row of each column serially, and the bits outputted from the block interleaver
124 may be
inputted to the modulator 130 serially. In this case, the demultiplexer (not
shown) may be
omitted or the bits may be outputted serially without changing the order of
bits inputted to the
demultiplexer (not shown). Accordingly, the bits included in each of the bit
groups X55, X15, X112,
and Xi n may constitute the modulation symbol.
When the modulation method is 64-QAM, the number of columns of the block
interleaver
124 is six (6) and each column may be formed of 10800 rows.
Accordingly, from among the 180 groups constituting the LDPC codeword, 30 bit
groups
(X55, X146, X83, X52, X62, X176, X160, X68, X53, X56, X81, X97, X79, X113,
X163, X61, X58, X69, X133,
X108, X66, X71, X863 X144, X57, X67, X116, X59, X70, X156) may be inputted to
the first column of the
block interleaver 124, 30 bit groups (X172, X65, X149, X155, X82, X138, X136,
X141, X111, X96, X170,
X90, X140, X64, X159, X15, X14, X37, X54, X44, )(63, X43, X18, X47, X7, X25,
X34, X29, X30, X26) may
be inputted to the second column of the block interleaver 124, 30 bit groups
(X39, X16, X41, X45,
X36, X0, X23; X32, X28, X27, X38, X48, X33, X22, X49, X51, X60, X46, X21, X4,
X3, X20, X13, X50, X35,
X24, X40, X17, X42, X6) may be inputted to the third column of the block
interleaver 124, 30 bit
groups (X112, X93, X127, X101, X94, X115, X105, X31, X19, X177, X74, X10,
X145, X162, X102, X120, X126,
x95, X73, X152, X129, X174, X125, X72, X128, X78, X171, X8, X142, X178) may be
inputted to the fourth
column of the block interleaver 124, 30 bit groups (X154, X85, X107, X75, X12,
X9, X151, X77, X117,
X109, )(80, X106, X134, X98, Xi, X122, X173, X161, X150, X110, X175, X166,
X131, X119, X103, X139, X148,
X157, X114, X147) may be inputted to the fifth column of the block interleaver
124, and 30 bit
groups (X87, X158, X121, X164, X104, X89, X179, X1235 X118, X99, X88, X11,
X92, X165, X84, X168, X124,
X169, X2, X130, X167, X153, X137, X143, X91, X100, X5, X76, X132, X135) may be
inputted to the sixth
column of the block interleaver 124.
In addition, the block interleaver 124 may output the bits inputted to the 1st
row to the last
row of each column serially, and the bits outputted from the block interleaver
124 may be
Date Recue/Date Received 2021-10-07
78
inputted to the modulator 130 serially. In this case, the demultiplexer (not
shown) may be
omitted or the bits may be outputted serially without changing the order of
bits inputted to the
demultiplexer (not shown). Accordingly, the bits included in each of the bit
groups X55, X172, X39,
X112, X154 ,and X87 may constitute the modulation symbol.
As described above, since a specific bit is mapped onto a specific bit in a
modulation symbol
through interleaving, a receiver side can achieve high receiving performance
and high decoding
performance.
That is, when LDPC codeword bits of high decoding performance are mapped onto
high
reliability bits from among bits of each modulation symbol, the receiver side
may show high
decoding performance, but there is a problem that the LDPC codeword bits of
the high decoding
performance may not be received. In addition, when the LDPC codeword bits of
high decoding
performance are mapped onto low reliability bits from among the bits of the
modulation symbol,
initial receiving performance is excellent, and thus, overall performance is
also excellent.
However, when many bits showing poor decoding performance are received, error
propagation
may occur.
Accordingly, when LDPC codeword bits are mapped onto modulation symbols, an
LDPC
codeword bit having a specific codeword characteristic is mapped onto a
specific bit of a
modulation symbol by considering both codeword characteristics of the LDPC
codeword bits
and reliability of the bits of the modulation symbol, and is transmitted to
the receiver side.
Accordingly, the receiver side can achieve high receiving performance and
decoding
performance.
Hereinafter, a method for determining n(j), which is a parameter used for
group interleaving,
according to various exemplary embodiments, will be explained.
According to an exemplary embodiment, when the length of the LDPC codeword is
64800,
the size of the bit group is determined to be 360 and thus 180 bit groups
exist. In addition, there
may be 180! possible interleaving patterns (Herein, factorial means A!=Ax(A-1)
x ...x2x1)
regarding an integer A.
In this case, since a reliability level between the bits constituting a
modulation symbol may be
the same according to a modulationorder, many number of interleaving patterns
may be regarded
as the same interleaving operation when theoretical performance is considered.
For example,
when an MSB bit of the X-axis (or rear part-axis) and an MSB bit the Y-axis(or
imaginary part-
Date Recue/Date Received 2021-10-07
79
axis) of a certain modulation symbol have the same theoretical reliability,
the same theoretical
performance can be achieved regardless of the way how specific bits are
interleaved to be
mapped onto the two MSB bits.
However, such a theoretical prediction may become incorrect as a real channel
environment is
established. For example, in the case of the QPSK modulation method, two bits
of a symbol in a
part of a symmetric channel like an additive white Gaussian noise (AWGN)
channel theoretically
have the same reliability. Therefore, there should be no difference in the
performance
theoretically when any interleaving method is used. However, in a real channel
environment, the
performance may be different depending on the interleaving method. In the case
of a well-known
Rayleigh channel which is not a real channel, the performance of QPSK greatly
depends on the
interleaving method and thus the performance can be predicted somewhat only by
the reliability
between bits of a symbol according to a modulation method. However, there
should be a limit to
predicting the performance.
In addition, since code performance by interleaving may be greatly changed
according to a
channel which evaluates performance, channels should be always considered to
drive an
interleaving pattern. For example, a good interleaving pattern in the AWGN
channel may be not
good in the Rayleigh channel. If a channel environment where a given system is
used is closer to
the Rayleigh channel, an interleaving pattern which is better in the Rayleigh
channel than in the
AWGN channel may be selected.
As such, not only a specific channel environment but also various channel
environments
considered in a system should be considered in order to derive a good
interleaving pattern. In
addition, since there is a limit to predicting real performance only by
theoretical performance
prediction, the performance should be evaluated by directly conducting
computation experiments
and then the interleaving pattern should be finally determined.
However, since there are so many number of possible interleaving patterns to
be applied (for
example, 180!), reducing the number of interleaving patterns used to predict
and test
performance is an important factor in designing a high performance
interleaver.
Therefore, the interleaver is designed through the following steps according
to an exemplary
embodiment.
1) Channels C1, C2, Ck to be considered by a system are determined.
2) A certain interleaver pattern is generated.
Date Recue/Date Received 2021-10-07
80
3) A theoretical performance value is predicted by applying the interleaver
generated in step
2) to each of the channels determined in step 1). There are various methods
for predicting a
theoretical performance value, but a well-known noise threshold determining
method like density
evolution analysis is used according to an exemplary embodiment. The noise
threshold recited
herein refers to a value that can be expressed by a minimum necessary signal-
to-noise ratio
(SNR) capable of error-free transmission on the assumption that a cycle-free
characteristic is
satisfied when the length of a code is infinite and the code is expressed by
the Tanner graph. The
density evolution analysis may be implemented in various ways, but is not the
subject matter of
the inventive concept and thus a detailed description thereof is omitted.
4) When noise thresholds for the channels are expressed as THIN, TH2[i],
THk[i] for the
i-th generated interleaver, a final determination threshold value may be
defined as follows:
TH[i]=WixTHi[i]+W2xTH2N+ +WkxTHk[i],
where Wi+W2+.. = +Wk=1,Wi,W2, = = = 3 Wk> 0
Here, W1, W2, ¨, Wk are adjusted according to importance of the channels. That
is, W1, W2,
===, Wk are adjusted to a larger value in a more important channel and Wi, W2,
Wk are
adjusted to a smaller value in a less important channel (for example, if the
weight values of
AWGN and Rayleigh channels are W1 and W2, respectively, Wi may be set to 0.25
and W2 may
be set to 0.75 when one of the channels is determined to be more important.).
5) B number of interleaver patterns are selected in an ascending order of
TH[i] values from
among the tested interleaver patterns and are directly tested by conducting
performance
computation experiments. An PER level for the test is determined as 10" ¨3
(for example,
B=100).
6) D number of best interleaver patterns are selected from among the B number
of interleaver
patterns tested in step 5) (for example, D=5).
In general, an interleaver pattern which has a great SNR gain in the area of
FER=10" ¨3 may
be selected as a good performance interleaver in step of 5). However,
according to an exemplary
embodiment, as shown in FIG. 16, performance of FER required in the system
based on the
result of real computation experiments for the area of FER=10" ¨3 may be
predicted through
extrapolation, and then an interleaver pattern having good performance in
comparison with the
expected performance in the PER required in the system may be determined as a
good
interleaver pattern. According to an exemplary embodiment, the extrapolation
based on a linear
Date Recue/Date Received 2021-10-07
81
function may be applied. However, various extrapolation methods may be
applied. FIG. 16
illustrates an example of performance extrapolation predicted by the result of
computation
experiments.
7) The D number of interleaver patterns selected in step 6) are tested by
conducting
performance computation experiments in each channel. Herein, the PER level for
testing is
selected as FER required in the system (for example, FER=10^ ¨6 )
8) When an error floor is not observed after the computation experiments, an
interleaving
pattern having the greatest SNR gain is determined as a final interleaving
pattern.
FIG. 17 is a view schematically showing a process of determining B number of
interleaver
patterns in the steps 2), 3), 4), and 5) of the above-described method for
determining the
interleaving pattern in the case of AWGN and Rayleigh channels for example.
Referring to FIG. 17, necessary variables i, j, and etc. are initialized in
operation S1701, and a
noise threshold for the AWGN channel THIN and a noise threshold for the
Rayleigh channel
TH2[i] are calculated in operation S1702. Then, a final determination noise
threshold TH[i]
defined in step 4) is calculated in operation S1703, and is compared with a
previously calculated
final determination noise threshold TH[i-1J in operation S1704. When the final
determination
noise threshold TH[i] is smaller than the previously calculated final
determination noise
threshold TH[i-1], TH_S[i] is replaced with the TH[i] and is sotred in
operation S1706. Next, i, j
values increase by 1 in operation S1707 and this process is repeated until the
i value exceeds A
which is pre-defined in operation S1708. In this case, A is the total number
of interleaver
patterns to be tested in steps 2), 3), 4), and 5) and A is typically
determined to be greater than or
equal to 10000. When all operations described above are completed, interleaver
patterns
corresponding to TH_S[0], TH_S[1], TH_S[B-
1] which are stored in a descending order of
final noise thresholds values in operation S1709.
The transmitting apparatus 100 may transmit the signal mapped onto the
constellation to a
receiving apparatus (for example, 1200 of FIG. 18). For example, the
transmitting apparatus 100
may map the signal mapped onto the constellation onto an Orthogonal Frequency
Division
Multiplexing (OFDM) frame using OFDM, and may transmit the signal to the
receiving
apparatus 1200 through an allocated channel.
FIG. 18 is a block diagram to illustrate a configuration of a receiving
apparatus according to
an exemplary embodiment. Referring to FIG. 18, the receiving apparatus 1200
includes a
Date Recue/Date Received 2021-10-07
82
demodulator 1210, a multiplexer 1220, a deinterleaver 1230 and a decoder 1240.
The demodulator 1210 receives and demodulates a signal transmitted from the
transmitting
apparatus 100. Specifically, the demodulator 1210 generates a value
corresponding to an LDPC
codeword by demodulating the received signal, and outputs the value to the
multiplexer 1220. In
this case, the demodulator 1210 may use a demodulation method corresponding to
a modulation
method used in the transmitting apparatus 100. To do so, the transmitting
apparatus 100 may
transmit information regarding the modulation method to the receiving
apparatus 1200, or the
transmitting apparatus 100 may perform modulation using a pre-defined
modulation method
between the transmitting apparatus 100 and the receiving apparatus 1200.
The value corresponding to the LDPC codeword may be expressed as a channel
value for the
received signal. There are various methods for determining the channel value,
and for example, a
method for determining a Log Likelihood Ratio (LLR) value may be the method
for determining
the channel value.
The LLR value is a log value for a ratio of the probability that a bit
transmitted from the
transmitting apparatus 100 is 0 and the probability that the bit is 1. In
addition, the LLR value
may be a bit value which is determined by a hard decision, or may be a
representative value
which is determined according to a section to which the probability that the
bit transmitted from
the transmitting apparatus 100 is 0 or 1 belongs.
The multiplexer 1220 multiplexes the output value of the demodulator 1210 and
outputs the
value to the deinterleaver 1230.
Specifically, the multiplexer 1220 is an element corresponding to a
demultiplexer (not shown)
provided in the transmitting apparatus 100, and performs an operation
corresponding to the
demultiplexer (not shown). That is, the multiplexer 1220 performs an inverse
operation of the
operation of the demultiplexer (not shown), and performs cell-to-bit
conversion with respect to
the output value of the demodulator 1210 and outputs the LLR value in the unit
of bit. However,
when the demultiplexer (not shown) is omitted from the transmitting apparatus
100, the
multiplexer 1220 may be omitted from the receiving apparatus 1200.
The information regarding whether the demultiplexing operation is performed or
not may be
provided by the transmitting apparatus 100, or may be pre-defined between the
transmitting
apparatus 100 and the receiving apparatus 1200.
The deinterleaver 1230 deinterleaves the output value of the multiplexer 1220
and outputs the
Date Recue/Date Received 2021-10-07
83
values to the decoder 1240.
Specifically, the deinterleaver 1230 is an element corresponding to the
interleaver 120 of the
transmitting apparatus 100 and performs an operation corresponding to the
interleaver 120. That
is, the deinterleaver 1230 deinterleaves the LLR value by performing the
interleaving operation
of the interleaver 120 inversely.
To do so, the deinterleaver 1230 may include a block deinterleaver 1231, a
group twist
deinterleaver 1232, a group deinterleaver 1233, and a parity deinterleaver
1234 as shown in FIG.
18.
The block deinterleaver 1231 deinterleaves the output of the multiplexer 1220
and outputs the
value to the group twist deinterleaver 1232.
Specifically, the block deinterleaver 1231 is an element corresponding to the
block interleaver
124 provided in the transmitting apparatus 100 and performs the interleaving
operation of the
block interleaver 124 inversely.
That is, the block deinterleaver 1231 deinterleaves by writing the LLR value
output from the
multiplexer 1220 in each row in the row direction and reading each column of
the plurality of
rows in which the LLR value is written in the column direction by using at
least one row formed
of the plurality of columns.
In this case, when the block interleaver 124 interleaves by dividing the
column into two parts,
the block deinterleaver 1231 may deinterleave by dividing the row into two
parts.
In addition, when the block interleaver 124 writes and reads in and from the
bit group that
does not belong to the first part in the row direction, the block
deinterleaver 1231 may
deinterleave by writing and reading values corresponding to the group that
does not belong to the
first part in the row direction.
Hereinafter, the block deinterleaver 1231 will be explained with reference to
FIG. 20.
However, this is merely an example and the block deinterleaver 1231 may be
implemented in
other methods.
An input LLR NT; (0<i<N1dpc) is written in a ri row and a ci column of the
block deinterleaver
1231. Herein, ci=0 mod NO and r = ¨i , [
On the other hand, an output LLR qi(0.5i<Islex Mn) is read from a ci column
and a ri row of the
Date Recue/Date Received 2021-10-07
84
r
first part of the block deinterleaver 1231. Herein, cg = ¨ , ri.(i mod Nil).
[
Nrl
In addition, an output LLR qi(Ncx Nrii<Nidpc) is read from a c, column and a
ri row of the
0 ¨ NcxN,i)]
second part. Herein, c . [; , ri=1=1,1+{(i-Ncx Nri) mode Na}.
Nr2
The group twist deinterleaver 1232 deinterleaves the output value of the block
deinterleaver
1231 and outputs the value to the group deinterleaver 1233.
Specifically, the group twist deinterleaver 1232 is an element corresponding
to the group
twist interleaver 123 provided in the transmitting apparatus 100, and may
perform the
interleaving operation of the group twist interleaver 123 inversely.
That is, the group twist deinterleaver 1232 may rearrange the LLR values of
the same bit
group by changing the order of the LLR values existing in the same bit group.
When the group
twist operation is not performed in the transmitting apparatus 100, the group
twist deinterleaver
1232 may be omitted.
The group deinterleaver 1233 (or the group-wise deinterleaver) deinterleaves
the output value
of the group twist deinterleaver 1232 and outputs the value to the parity
deinterleaver 1234.
Specifically, the group deinterleaver 1233 is an element corresponding to the
group
interleaver 122 provided in the transmitting apparatus 100 and may perform the
interleaving
operation of the group interleaver 122 inversely.
That is, the group deinterleaver 1233 may rearrange the order of the plurality
of bit groups in
bit group wise. In this case, the group deinterleaver 1233 may rearrange the
order of the plurality
of bit groups in bit group wise by applying the interleaving method of Tables
11 to 22 inversely
according to a length of the LDPC codeword, a modulation method and a code
rate.
The parity deinterleaver 1234 performs parity deinterleaving with respect to
the output value
of the group deinterleaver 1233 and outputs the value to the decoder 1240.
Specifically, the parity deinterleaver 1234 is an element corresponding to the
parity
interleaver 121 provided in the transmitting apparatus 100 and may perform the
interleaving
operation of the parity interleaver 121 inversely. That is, the parity
deinterleaver 1234 may
deinterleave the LLR values corresponding to the parity bits from among the
LLR values output
from the group deinterleaver 1233. In this case, the parity deinterleaver 1234
may deinterleave
the LLR value corresponding to the parity bits inversely to the parity
interleaving method of
Date Recue/Date Received 2021-10-07
85
Equation 18.
However, the parity deinterleaver 1234 may be omitted depending on the
decoding method
and embodiment of the decoder 1240.
Although the deinterleaver 1230 of FIG. 18 includes three (3) or four (4)
elements as shown
in FIG. 19, operations of the elements may be performed by a single element.
For example, when
bits each of which belongs to each of bit groups Xa, Xb, X,, Xd constitute a
single modulation
symbol, the deinterleaver 1230 may deinterleave these bits to locations
corresponding to their bit
groups based on the received single modulation symbol.
For example, when the code rate is 6/15 and the modulation method is 16-QAM,
the group
deinterleaver 1233 may perform deinterleaving based on table 11.
In this case, bits each of which belongs to each of bit groups X55, X15, X112,
X122 may
constitute a single modulation symbol. Since one bit in each of the bit groups
X55, X15, X112, X122
constitutes a single modulation symbol, the deinterleaver 1230 may map bits
onto decoding
initial values corresponding to the bit groups X55, X15, X112, X122 based on
the received single
modulation symbol.
The decoder 1240 may perform LDPC decoding by using the output value of the
deinterleaver 1230. To achieve this, the decoder 1240 may include an LDPC
decoder (not
shown) to perform the LDPC decoding.
Specifically, the decoder 1240 is an element corresponding to the encoder 110
of the
transmitting apparatus 100 and may correct an error by performing the LDPC
decoding by using
the LLR value output from the deinterleaver 1230.
For example, the decoder 1240 may perform the LDPC decoding in an iterative
decoding
method based on a sum-product algorithm. The sum-product algorithm is one
example of a
message passing algorithm, and the message passing algorithm refers to an
algorithm which
exchanges messages (e.g., LLR value) through an edge on= a bipartite graph,
calculates an output
message from messages input to variable nodes or check nodes, and updates.
The decoder 1240 may use a parity check matrix when performing the LDPC
decoding. In
this case, the parity check matrix used in the decoding may have the same
configuration as that
of the parity check matrix used in the encoding of the encoder 110, and this
has been described
above with reference to FIGs. 2 to 4.
In addition, information on the parity check matrix and information on the
code rate, etc.
Date Recue/Date Received 2021-10-07
86
which are used in the LDPC decoding may be pre-stored in the receiving
apparatus 1200 or may
be provided by the transmitting apparatus 100.
FIG. 21 is a flowchart to illustrate an interleaving method of a transmitting
apparatus
according to an exemplary embodiment.
First, an LDPC codeword is generated by LDPC encoding based on a parity check
matrix
(S1410), and the LDPC codeword is interleaved (S1420).
Then, the interleaved LDPC codeword is mapped onto a modulation symbol
(S1430). In this
case, a bit included in a predetermined bit group from among a plurality of
bit groups
constituting the LDPC codeword may be mapped onto a predetermined bit in the
modulation
symbol.
Each of the plurality of bit groups may be formed of M number of bits, and M
may be a
common divisor of Nidpc and Kidp, and may be determined to satisfy Qtapc=-
(Nidpc-Kidpc)/M.
Herein, Qldpc is a cyclic shift parameter value regarding columns in a column
group of an
information word submatrix of the parity check matrix, Nidpc is a length of
the LDPC codeword,
and Kkipc is a length of information word bits of the LDPC codeword.
Operation S1420 may include interleaving parity bits of the LDPC codeword,
dividing the
parity-interleaved LDPC codeword by the plurality of bit groups and
rearranging the order of the
plurality of bit groups in bit group wise, and interleaving the plurality of
bit groups the order of
which is rearranged.
The order of the plurality of bit groups may be rearranged in bit group wise
based on the
above-described Equation 21 presented above.
As described above, n(j) in Equation 21 may be determined based on at least
one of a length
of the LDPC codeword, a modulation method, and a code rate.
For example, when the LDPC codeword has a length of 64800, the modulation
method is 16-
QAM, and the code rate is 6/15, it(j) may be defined as in table 11.
In addition, when the LDPC codeword has a length of 64800, the modulation
method is 16-
QAM, and the code rate is 10/15, n(j) may be defined as in table 14.
In addition, when the LDPC codeword has a length of 64800, the modulation
method is 16-
QAM, and the code rate is 12/15, n(j) may be defined as in table 15.
In addition, when the LDPC codeword has a length of 64800, the modulation
method is 64-
QAM, and the code rate is 6/15, it(j) may be defined as in table 17.
Date Recue/Date Received 2021-10-07
87
In addition, when the LDPC codeword has a length of 64800, the modulation
method is 64-
QAM, and the code rate is 8/15, 7c(j) may be defined as in table 18.
In addition, when the LDPC codeword has a length of 64800, the modulation
method is 64-
QAM, and the code rate is 12/15, n(j) may be defined as in table 21.
The interleaving the plurality of bit groups may include: writing the
plurality of bit groups in
each of a plurality of columns in bit group wise in a column direction, and
reading each row of
the plurality of columns in which the plurality of bit groups are written in
bit group wise in a row
direction.
In addition, the interleaving the plurality of bit groups may include:
serially write, in the
plurality of columns, at least some bit group which is writable in the
plurality of columns in bit
group wise from among the plurality of bit groups, and then dividing and
writing the other bit
groups in an area which remains after the at least some bit group is written
in the plurality of
columns in bit group wise.
A non-transitory computer readable medium, which stores a program for
performing the
interleaving methods according to various exemplary embodiments in sequence,
may be
provided.
The non-transitory computer readable medium refers to a medium that stores
data semi-
permanently rather than storing data for a very short time, such as a
register, a cache, and a
memory, and is readable by an apparatus. Specifically, the above-described
various applications
or programs may be stored in a non-transitory computer readable medium such as
a compact disc
(CD), a digital versatile disk (DVD), a hard disk, a Blu-ray disk, a universal
serial bus (USB), a
memory card, and a read only memory (ROM), and may be provided.
At least one of the components, elements or units represented by a block as
illustrated in
FIGs. 1, 5, 15, 18 and 19 may be embodied as various numbers of hardware,
software and/or
firmware structures that execute respective functions described above,
according to an exemplary
embodiment. For example, at least one of these components, elements or units
may use a direct
circuit structure, such as a memory, processing, logic, a look-up table, etc.
that may execute the
respective functions through controls of one or more microprocessors or other
control
apparatuses. Also, at least one of these components, elements or units may be
specifically
embodied by a module, a program, or a part of code, which contains one or more
executable
instructions for performing specified logic functions. Also, at least one of
these components,
Date Recue/Date Received 2021-10-07
88
elements or units may further include a processor such as a central processing
unit (CPU) that
performs the respective functions, a microprocessor, or the like. Further,
although a bus is not
illustrated in the above block diagrams, communication between the components,
elements or
units may be performed through the bus. Functional aspects of the above
exemplary
embodiments may be implemented in algorithms that execute on one or more
processors.
Furthermore, the components, elements or units represented by a block or
processing steps may
employ any number of related art techniques for electronics configuration,
signal processing
and/or control, data processing and the like.
The foregoing exemplary embodiments and advantages are merely exemplary and
are not to
be construed as limiting the present inventive concept. The exemplary
embodiments can be
readily applied to other types of apparatuses. Also, the description of the
exemplary
embodiments is intended to be illustrative, and not to limit the scope of the
inventive concept,
and many alternatives, modifications, and variations will be apparent to those
skilled in the art.
Date Recue/Date Received 2021-10-07
