Note : Les descriptions sont présentées dans la langue officielle dans laquelle elles ont été soumises.
18 Background of the Invention
19 This invention relates generally to large
scale integrated circuits and more particularly to read
21 only mcmories wherein binary information is permanently
22 stored.
23 A basic device for the operation of general
24 purpose computers and the operation of processor controlled
equipment where the use of permanent data is required is
26 the read only memory (ROM). .Low cost, compact read only
27 memories have made possible the use of many devices
28~ which can utilize extensive permanent data for more effective
29 operation, but cannot support a large overhead cost. The
3Q advent of large scale integration using field effect tran-
31 sistor (FET) circuitry has made permanent storage using
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1 such devices competitive with any other form o~ random
2 access storage.
3 To achieve high density ROM design it is
4 necessary that both the power consumption that results
in heat that must be dissipated be minimized and the over-
6 head circuits associated with the array which require
7 space or real estate on the chip and limit compactness
8 be eliminated. The use of dynamic circuits yield compact
9 size hence the relative size of diffusions is not a factor
and the circuitry can be designed for easy access and the
11 elimination of DC circuits that result in heat dissipat~on
12 problems. The limitation in regard to dynamic circuitry
13 is the necessity of clocked timing circuits and interfacing
14 with exterior static logic with which the device must be
connected and interact.
16 The ROM of the present invention utilizes
17 d~namic techniques for both an FET rray arranged in rows and
18 columns and the column address where a control electrode
19 interconnects the gate elements of a column of bit positions.
The array is composed of bit locations~each of which is an
21 F~T device capable of indicating either a logical one or a
22 logical zero at an ou-tput upon being addressed. A logical
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~23 one occurs when effective transistor action occurs because
24 of the pr~sence of a thin oxide gate and a logical zero
25 occurs when no transistor action results upon the bit loca- -
26 tion belng addressed as a consequence of the absence of a
27 thin oxide gate. Accordingly, each bit location is person-
28 alized by the presence or absence of such a gate or device.
2g Each bit location also has two output electrodes. A source
line addresses a row of devices by piacing a charge at the
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1 source of each FET in a selected row. A bit position is
2 selected by the intersection of a column or gate line and
3 a row address or source line. If a gate is present at the
4 bit location the charge from the source line is transferred
to the sense or drain line to indicate a logical one at an
6 associated output terminal. If a device or thin oxide
7 gate is absent, then a logical zero is indicated. The
8 array uses compact non-ratioed dynamic circuitry which
9 indicates logic levels through a charge transfer without
the use of DC current. The gate decode or column address
11 circuitry is also non-ratioed dynamic circuitry having
12 minimal space requirements. The remainder of the cir-
13 cuitry is composed of ratioed static circuits including
14 the gate decode address, source address and decode circuits,
chip or array address and decode circuits, the sense cir-
16 cuits and output latches. Each of the circuits that con-
17 nect with other devices are static and therefore may inter-
18 face with any static chip.
19 ~o coordinate the dynamic logic, two clock
pulses are utilized. A first clock pulse ~X is utilized
21 to time the charging of the selected gate decode line and
22 a second clock pUl5e p'P serves both to yround any residual
23 charge on an output or sense line from the previous cycle
24 and to time the source line select for the current cycle.
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When an address i5 received by the gate decode, the pre-
26 viously charged gate line is grounded if the same line is
27 not readdressed. ~owever, it is possible for a charge to
28 remain on the sense line from a previous cycle if provision
29 is not made for removal of the charge from the sense line
at the conclusion of the cycle or after the output has been
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1 latched. To remove any resident charge on the output line
2 an additional column of bit positions is provided in the
3 array each of which has a device or gate which is addressed
4 by the clock pulse +~P to provide a conductive path from
each sense line to the associated source line while an
~ additional FET in each source line decode circuit is also
7 activated by clock pulse +~P to complete the path to ground.
8 The output of the ROM cycle is latched when
9 ~P again returns to a + value and will remain valid while
~P continues to have a positive value, The output latches
11 are reset by removing the positive input charge from the
12 reset inverter while ~P continues to have a positive value.
13 By using the techniques described above it is possible to
14 achieve a density of 24,576 bits of read only storage along
with the associated address, array select and output sensing
16 and latching circuitry in a space }ess than Z00- mils
17 square.
18 It is an object of this invention to provide
19 an improved high density read only memory. It is a further
object of the invention to provide an increased density read -
21 only memory by optimizing placement of array elements and
22 reducing power consumption. It is also an object OL the -
23 invention to provide a read only memory that utilizes dynamic
logic Ln ~he array while using static logic for addressing
and sensing to enable ease of interface with static logic
26 chips. It is also an object of the invention to provide a
27 read only memory with means to remove any charge resident in
28 the sense line at the end of a memory cycle.
29 Brief Description of the Drawings
FIGURE 1 is a schematic plan view of a large
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1 scale integration chip illustrating the arrangement of
2 array, address, decode, array select and output sensing
3 circuitry.
4 FIGURE 2 is a plan view of a chip showing
source and sense line diffusions and an overlying gate line
6 including the position of a thin oxide gate device.
7 FIGURE 3 is a vertical section of the chip
8 structure of FIGURE 2 taken along line 3-3 of FIGURE 2.
9 FIGURE 4 is a timing chart showing the read
only memory cycle including the associated clock pulses,
11 reset and output timing.
12 FIGURES 5A-5C when arranged from left to
13 right as shown in FIGURE 5 present a logic diagram shcwing
14 the array and representative portions of addressing and
output sensing circuitry.
16 PIGURES 6A-6C when arranged from left to
17 right as shown in Fl&URE 6 is a schemati- cross-section of
18 the circuitry of FIGURE 5 showing representative address
19 ~ circuits, address decode circuits, array select and decode
~ circuits, output sensing and latch circuits and an inter-
21 ~ ruptec portion of tllc array including array one and array
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22 two portions of the rirst of eight divisions of the complete
23 array shown in FIGURE 5.
24 Detailed Description
1 :
FIGURE 1 illustrates the division of circuit
26 regions on a large scale integration chip 10 that provides
27 the read only memory function. The complete array 11 in-
28 cludes 24 ,576 addressable bit`locations arranged in 128
;~ 29~ ~ vertical columns and 192 horizontal rows. The rows are
selected by 96 source lines which are driven by decode cir-
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1 cuits in region 12 and the bit location within the rows
2 selected by one of 128 gate lines selected by decode cir-
3 cuits disposed in region 13. The gate decode circuits are
4 selected by a seven bit address implemented by a series of
seven double inverter circuits positioned in region 14.
6 The presence or absence of a device is sensed on 192 sense
7 or drain lines by a series of 16 circuits in region 15 that
8 provide latched outputs and a reset circuit at 16 resets
9 the output latches at the end of the cycle. One additional
column in the array region 11 provides for removal of a
11 charge transmitted to the output during a previous ROM
12 cycle. The array is partitioned into three addressable
13 divisions with the chip or array select circuits disposed
14 in region 17. -
As illustrated schematically in FIGURE5 2
16 and 3, the chip structure is formed of a silicone sub~
17 strate 20 which is doped with P type material. A diffusion
18 pa tern is formed in the upper surface of substate 20 by
19 selectively doping selected surface portions to form N
type regions 55, 90 and 91 in such substate. A coating
21 ~ of oxide 25 overlies the substate surface. Where it is
22 desired to have a gate or device 26 .o control or va;y the
.
23 conductivity between adjacent diffusions a portion of the
24 oxide layer is removed as shown at 27. A selected metal
pattern 28 is then applied to the upper surface to provide
26 a gate structure 26 where metal overlies the thin oxide
27 layer 27 extending between adjoining diffusions such as
28 source 55 and sense line 90. When a negative charge or
29 no charge is applied to the metal 28, the P type region
between diffusions 55 and 90 functions as an open circuit.
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1 When a plus charge is applied to the metal layer overlying
2 the thin oxide portion 27, a negative charge is lnduced in
3 the P type material intermediate diffusions 55 and 90
4 creating a conductive path. Accordingly, at a bit or device
location when a source diffusion is charged and a positive
6 charge is applied to the gate 26, an output charge is con-
7 ducted to the sense or drain line 90.
8 Referring to FIGUR~S 5 and 6, includins
9 FIGURES 5A-5C and 6A-6C, the memory array is for~ed of bit
locations 36 disposed in 192 rows and 128 columns. The
11 columns are addressed or selected by a series of 128 gate
12 lines 33 which establish one of two output levels by the
13 pre~ence or absence of a gate 34 at the selected bit or
14 device location 36. The gate or column select is effected
by a seven bit address on seven input lines 37, one of which
16 is shown. The input line 37 is directed to the gate of
17 transistor 40 of the first of a pair of inverters of gate
18 decode inverter 42. The output of the inverter formed of
19 transistors 40 and 41 yields the complement of the signal
.
on line 43 and the output of the inverter formed of tran-
21 sistoi^s 44 and 45 on line 46 yields the true output or the
22 same level as thc input line 37. The gate decode address
23 lines 37 being double inverted provide buffering and the
24 true and complement of each address. The true and comple-
ment lines of the seven gate decode inverters 42 are con-
26 nected to a series of 128 gate decode circuits 50, one of
27 which is shown. Circuits 50 are seven way binary decodes
28 which provide 128 unique combinations of the outputs of
29 ga e decode inverters 42 such that each combination of the
seven address bits on address lines 37 selects one output
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1 gate line 33. Of the 128 gate decode circuits 50, all but
2 the selected line will have the gate at at least one of the
3 seven transistors 52 active thereby causing all but the
4 selected gate line 33 to have a down level.
S The complete array 11 is divided into three
6 divisions which is effected as shown in FIGURE 5 each in-
7 cluding eight segments identified as array one, array two
8 or array three. The complete array is also organized into
9 eight sections each connected to two output bit positions ~
such as bit zero and bit one. The total array is further ~ -
11 divided into upper and lower halves including bits zero
12 through seven and eight through 15 respectively as schema-
13 tically shown in FIGURE 5 to permit addressing either half -
14 of the total array with a resulting eight bit output or as
will be described below, addressing both halves simultan-
16 eously to yield a 16 bit output. Each source line 55 is
17 capable of a~dre sing ~56 bit locations within one ~f the
18 eight array sections by being connected to two ad joining ,
19 rows of 128 bit location FET's 36. By further selecting
one of the 128 gate lines 33, two bit locations within
21 the section are addressed. There are three source address
~22 lines 56, 57 and 58 ~thich are double inverted to provide
23 buffering and true and complement outputs by three source
24 address d~code inverters 59, 60 and 61. Source address
decode inverter 59 is shown in FIGURE 6 and inverter 60
26 is identical thereto. Each source decode circuit 68 drives
27 four source lines 55.
28 Input line 56 is connected to the gate of
29 transistor 63 to generate an inverted or complement output
on line 64. Line 64 is also connected to the gate of tran-
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1 sistor 65 to yield the true output upon a second inversion
2 on the line 66. The outputs of the source address decode
3 inverters 59 and 60 are connected to source decode circuits
4 68 of which there are a total of 24, each having an output
line 69 that functions to select a group of four source lines
6 55. The third source address decode inverter 61 has two in-
7 puts on lines 58 and 71. The output line 72 is the comple-
8 ment of the signal on input line 58 and is supplied to the
9 source decode NOR circuits 68 having outputs connected to
the four array sections connected to output bits zero through
11 seven while the true output on line 73 is connected to NOR
12 circuit 68 which have outputs connected to the four array
13 sections connected to output bits eight through 15. When ~ -
14 it is elected to operate the total array as two halves,
input line 71 is grounded. Thereupon a positive condition
16 on line 58 causes a negative condition on output line 72
;7 ani a positive condition on output ine 73 that per~.its
18 selection of one of the three arrays in the upp~r half of
19 the total array while a negative input on line 58 causes a
positive condition on line 72 which de-selects the NOR cir-
21 cult B8 associated with total array upper half and a negative
22 condition on line 73 permitting selection of one of the
a3 three array divisions associated with the lcwer half of
24 the total array 11 where that portion with outputs at bits
eight through 15. When it is desired to address all eight
26 array sections s~multaneously, lines 58 and 71 are dotted
together causing a positive condition on line 58 to select
28 all eight sections and 16 output bits simultaneously.
29 Five chip or array select address bits on
five lines 75 are respectively supplied to five inverters
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1 76 (one of which is shown) to provide true and complement
2 outputs on lines 78 and 79 respectively. The five bit chip
3 select address bits or lines 75 are capable of identifying
4 32 unique combinations for transmission to each chip or
array select NOR circuit 80 to provide an inverted output
6 on line 81 when selection occurs. Since the five bit chip
7 select is capable of selecting 32 combinations and only three
8 are used for the selection of the desired one of the three
9 array divisions, the five bit chip select address is capable
of selecting arrays from 10 2/3 total arrays as shown. The ~ ~ -
11 true and complement outputs of the five chip select input
12 lines 75 are connected to three chip select decode circuits
13 83 which decode the unique five bit input combinations to ~ -
14 select one of the three array divisions of the total array
11. Each chip select decode circuit includes a five way NOR
16 85 and an inverter 86. When the true and complement values
17 of the five bit chip select address connected to one NOR 85
18 are all at a negative or down level, the output on line 87
19 connected to the gate inverter transistor 88 is at an up
level causing a negative or down level on line 81. The
21 output on each line 81 is connected to the eight source de-
.
22; code ~OR circui~s 68 associated with one of Lhe three array
23 divisions permitting selection of that array division.
24 A charge transfer to the array sense lines
90 and 91 on a previous ROM cycle can remain unless re-
26 moved. To assure removal of such charges an additional
27 column of bit locations 93 is provided with a gate or --
28 device between every source and drain or sense diffusion.
29 A11 the devices in the column are turned on and a plus
signal is delivered to each NOR circuit 68 by an auxiliary
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1 clock pulse, 1ush ~P on line 94, This clock pulse occurs
2 once each ROM cycle to ground any charge remaining on the
3 sense lines 90 and 91 of the array 11 from the previous
4 cycle.
There are 16 output bits, zero through 15
6 from the total array 11. A pair of sense lines 90 and 91
7 adjoins each source line 55 with the~presence or absence
8 of a device or gate at each bit or address location 36
9 causing charge transfer or the lack of a charge transfer
to the sense lines 90 or 91 to be indicated at the associated
11 output line 96 when a bit location is addressed. Of the
12 eight array divisions shown in FIGURE 5, FIGURE 6 illustrates
13 array one bits zero and one and array two bits zero and one
14 of the first array division (or 2/3 of one array division).
Adjoining each of the source lines 55 in the array are a pair
16 of sense lines 90 and 91. The output of each sense line 90
.
17 is double inverted (inverters 107 and 108) by being connected
18 to the gate of transistor 102 with the inverted output on
19 line 103 connected to the gate of transistor 104 to provide
the true output on line 105. The output on line 105 is
21 applied to the gate of one of the transistors 99 of NOR 101.
22 Each of the lines 105 (bus 98 in FIGURE 5) is connected to
23 the gate of one of the three transistors 99 which with tran-
24 sistor 100 function as a four way NOR circuit 101. Any of
~25 the transistors 99 associated wi~h a non-selected source
26 line will have a down level at the gate thereof. If upon
27 selection of a source line 55 associated with bit zero and
28 a gate line 33 a device is present at the addressed bit
~29 location 36, the source line 55 is coupled to the sense
(drain) line 90 and a plus charge is applied to the gate
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l of the associated transistor 102. The resulting output on
2 line 105 is applied to NOR 101. The negative output or
3 de-conditioning of NOR 101 is inverted by inverter 110 to
4 a positive charge applied to the transistor of NOR 101,
which forms a part of the output latch lll. Applying a plus
6 charge to any of the transistors 99 causes ~OR 101 to have
7 a positive output on line 96. The positive charge on line
8 96 is applied to the gate of transistor 114 causing output
9 terminal 113 to be grounded which is indicative of the
presence of an up or binary one condition at the addressed
ll bit location. The output on line 96 is also applied to
12 the gate of transistor 100 to retain NOR 101 in the condi-
13 tion wherein a negative output or down condition is main-
14 tained on line 115. The output condltion at terminal 113 -
is thereupon latched until reset. To reset all output
16 terminals a down or negative charge is applied to the gate
17 of transistor 116 of reset inverter 117. The resulting
18 positive output on line 118 is applied to the gate of tran-
19 sistor 119 (and to the corresponding transistor of each of
the other 15 output latches 120) causing line 96 to become
21 negative thereby resetin~ latch 120 and restoring all 16
.
22 output terminals 113 to a non-grounded condition in pre-
23 paration for a subsequent cycle. -
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24 As seen in FIGURES 4-6, during a ROM cycle
the read only store array is addressed by a seven bit decode
26 address on lines 37, a five bit chip or array select address
27 on lines 75 and a three bit source decode address on lines
28 56, 57 and 58. The outputs of the gate decode circuits 50
29 are pre-charged by the positive timing pulse ~X. Since all
of the gate decode circuits 50 except the one selected,
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1 will have one or more transistorY 52 which form the NOR
2 circuit conducting to ground, only the selected line will
3 remain charged after the fall of ~X. The selected line
4 33 remains charged until a new address which selects
another gate line 33 provides a path to ground for the
6 previously selected gate line. When the flush ~P clock
7 time falls to a minimum condition the source decode cir-
8 cuits 68 are no longer disabled and the source lines 55
9 selected by the three bit source decode address portion
and five bit chip or array select address portion become
11 energized. Thereupon, at those bit locations 36 addressed
12 by the selected source and gate lines at which a gate or
13 device is installed, an output charge is transferred to
14 the sense line 90 or 91, is double inverted and transmitted
through NOR 101 and inverter 110 to set the associated latch
16 120 and provide a grounded output at the associated output
17 terminal 113 indicating a binary one condition at the
18 addressed location. Flush ~P then supplies a positive
19 charge on line 94 to ground all sense lines 90 and 91 by
providing a path to ground through the dummy array tran-
21 sistors 93, the associated source lines and source decode
22 circuit transistor 122. Concurrently with the pos tive
23 condition of flush ~P, the input line to reset inverter
24~ 117 is driven to a minus value causing the output on line
-25 118 to be positive and reset all 16 latches 120 in pre-.
26 paration for the succeeding cycle.
27 While the invention has been particularly
28 shown and described with reference to a preferred em~odi-
29 ment thereof, it will be understood by those skilled in
the art the various chan~es in form and details may be
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1 made therein without departing from the spirit and scope
2 of the invention.
3 We claim:
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