Note : Les descriptions sont présentées dans la langue officielle dans laquelle elles ont été soumises.
lOS51~4
The present invention relates generally to the m~nufacture
of circuit board assemblies, and more particularly to a multi-
layer circuit board assembly and a method for generating tool
masters therefor.
The development of printed circuits has provided many ad-
vantages over previous techniques, including reliability, reduc-
tion of cost, and reproducibility of circuits. The multilayer
printed circuit board further extended the capabilities of the
art by allowing greater density of interconnections, shorter cir-
cuit runs, and conservation of space.
The methods of designing multilayer printed circuit boardsin the prior art are characterized by extended design time, long
léad time for fabrication and high cost, especially for short
production runs. This is due to the multiplicity of steps in-
volved in generating coordinated artwork for a plurality of cir-
cu~t layer~. Each step must maintain a high degree of accuracy
ant tolerances for each individual circuit layer in order to ~-
achieve the overall accuracy required for the a~sembled board.
Multilayer board artwork is generally custom-designed for only` 20 one printed circuit board type. Such custom designs are diffi-
cult to modify and virtually impossible to repair without special
facilities.
One prior art method of multilayer board design which suc-
~ ceeded in alleviating some of the above-mentioned problems
-~ utilized preconfigured internal circuit layers having a plurality
of multiterminal circuit paths crossing the board, and uniquely
~; designed outer circuit layers interconnected via the internally
di8POsed cross-board circuits. This prior art method confined
, circuit routing largely to the internally disposed layers and
constrained circuit design by producing internally disposed cir-
cuit stubs of substantial length which were potentially degrad-
ing to the operation of certain circuits.
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It is, therefore, a principal ob~ect of my invention to pro-
vide an improved multilayer circuit board.
Another object of my invention is to provide an improved
multilayer circuit board having internal universal circuit layers
predesigned in concert with a universal extern~l circuit pattern,
which external pattern is alterable to form unique circuits with-
out degrading the design.
A more specific ob~ect of the present invention is to pro-
vide an improved multilayer circuit board having a unique circuit
layer generated from a universal circuit pattern, and having pre-
dictable characteristic impedance, signal propagation delay,
crossover capacitance and cross talk among circuits.
Still another object of my invention is to provide an im-
proved multilayer circuit board in which the C08t and lead time
for fabrication is significantly reduced, as contrasted with
prior art devices.
It is another object of my invention to provide an improved
method for making artwork masters of multilayer printed circuit
patterns.
Another obJect of the present invention is to provide an
improved method for generating unique multilayer circuit board
artwork from universal artwork with predetermined circuit design
characteristics.
These and other ob~ects and features of my invention are
achieved in accordance with one aspect thereof by a multilayer
circuit board having internal circuit layers of universal design
which are fabricated utilizing a first degree of layout precision.
Circuit layers disposed on the major external surfaces of the
board include circuit patterns having a first portion thereof
generated utilizing the first degree of precision and including
a universal matrix of interconnection pads, a first set of
mutually parallel circuit runs extending across one of the
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external surfaces, and a second set of mutually parallel circuit
runs extending across the other external surface in a direction
transverse to the direction of the first set. A second portion
of the external circuit pattern is generated utilizing a second
degree of layout precision and includes relatively short-length
runs interconnecting selected points of the first pattern.
The method for formulating the above mentioned multilayered
circuit board comprises the steps of plotting an artwork master
of the internal circuit layer, then plotting a large layout
master of the univer~al patterns of the first and second external
circuit layers, then formulating an enlarged layout master of a
component matrix of the circuit board. There is then an altering
of each of the layout masters of the universal patterns to de-
fine unique interconnecting means associated therewithO
The invention is pointed out with particularity in the ap-
pended claims; however, other features of the invention will be-
come more apparent and the invention will be best understood by
referring to the following detailed descript~on in conjunction
with the accompanying drawing in which:
FIG~ 1 is a plan view of a portion of a printed c~rcuit
board in accordance with the present invention.
FIGo 2 is a sectional view taken generally along line 2-2
of FIGo lo
~i FIGSo 3 and 4 are illustrations of layout masters of printed
circuit layers in accordance w~th the process of the present in-
ventionO
FIGSo 5 through 10 are illustrations of artwork masters of
the various printed circuit layers, named below, of one embodi-
ment of the present invention~
FIGo 5 ~ Outer Layer, Signal Plane, Component SideO
FIGo 6 ~ Inner Layer, Signal Plane, Component SideO
FIGo 7 ~ Inner Layer, Voltage PlaneO
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FIGo 8 - Inner Layer, Ground Plane.
FIGo 9 - Inner Layer, Signal Plane, Solder SideO
FIG. 10 - Outer Layer, Signal Plane, Solder Side.
FIG~ 11 is an illustration of a layout master of a component
matrix in accordance with the process of the present invention.
FIGSo 12 through 15 illustrate the process of generating
artwork masters in accordance with the present invention.
Referring now to the figures by characters of reference,
FIGS. 1 and 2 illustrate a portion of a multilayer printed cir-
cuit board 1 made in accordance with the process of the presentinventionO The board 1 comprises a plurality of planar circuit
patterns or layers 5-10 of conductive material such as copper.
Each of the layers 5-10 i8 separated from the ad~acent circuit
layer by one of a plurality of planar substrates 5'-9' inter-
posed therebetween. The substrates 5'-9' may be formed of epoxy-
glass or other suitable insulating material well known in the artO
Multilayer printed circuit boards generally comprise a num-
ber of circuit-bearing substrates such as the substrates 5'-9'
of FIG. 2 superposed in orderly registration and laminated or
otherwise bonded together to form an integral assembly or board
having internal as well as external circuit layers~ Electrical
interconnections between the layers may be established by various
means such as conductive pins or risers, plated-through holes, or
the likeO Normally, the internal circuit layers are formed and
the external layers are left as qolid copper to permit plating,
if plating is used as a means for interconnecting the several
circuit layers. Many processes are known for laminating and in-
terconnecting the layers of multilayer printed-circuit boardsO
The particular process utilized to assemble the circuit board of
the pre8ently described embod~ment i8 not germane to the present
invention and will not be described; however, reference is made
to Printed Circuits Handbook, edited by C. F. Coombs, Jr.,
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McGraw Hill, 1967, for a detailed description of multilayer
printed circuit board techniques.
The circuit board 1 of FIGS. 1 and 2 is shown including an
interconnecting element 12 comprising a plated-through hole 14
having a wall 16 plated with conductive material such as copper
and being disposed along a central axis coincident with the
center of an interconnecting pad 180 The pad 18 which forms a
part of the circuit layer 5 is registered with and overlies other
interconnecting pads 20, 22 which form parts, respectively, of
the circuit layers 6, 10. The plated-through hole 14 passes
through each of the pads 18, 20, 22 thereby establishing elec-
trical interconnection of the pads via the plated wall 16. The
plated wall 16 passes through voids 24, 26 formed, respectively,
in the internal circuit layers 7, 8.
In order to simplify the description and explanation of the
multilayer printed circuit board 1, the planar printed circuit
layers 5-10 illustrated in Figo 2 are each given a reference
number corresponding to a figure number of the drawing in the
present applicationO FIGS. 5-10 are illustrations of "artwork
masters" of the circuit layers 5-10 of FIG~ 20 An artwork master
is defined herein as an enlarged layout or drawing of a printed
circuit pattern which may be reduced photographically to make a
board-size "tool master"0 The tool master is utilized to repro-
, duce the circuit pattern in conductive metal such as copper on a
; substrate in ac~ordance with known processes. The pattern de-
i picted by the artwork master may be either unique to a particular
type board, or universal or generic to many board types. A "lay-
out master" is defined as an enlarged, precisely predefined lay-
out of a universal printed circuit pattern utilized by a des~gner
. 30 of printet circuit boards to make a unique artwork master. Both
i layout masters and artwork masters are most precisely generated
by apparatus such a~ X-Y plotters supplied with predetermined or
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calculated pattern parameters from an external source such as a
data processor.
Referring now to FIGo 5 in conjunction with FIGS. 1 and 2,
a unique artwork master of the external circuit layer 5 is shownO
The circuit pattern 5 overspreads a predetermined area bounded
by edges 28-31 of the circuit board 1. The circuit pattern 5 in-
cludes elements located in an input/output area (subtended by
reference numeral 34) of the board 1 disposed along and adjacent
the edge 31. The input/output area 34 includes a plurality of
conductive terminals 36 disposed along the edge 31 for transfer-
ring ~ignals and power between the board 1 and an electrical con-
nector (not shown) which receives the edge 31 of the board 1~ A
conductive strip 37 is provided for plating operations; it is
severed from the terminals 36 along the`edge 31 after the plating
operations are completed. The outer circuit pat~ern 5 includes a
plurality of mutually parallel traces such as the traces 38 of
FIGSo 1, 2 and 5, which are evenly distributed over the board and
extend substantially across the entire board from the input/
output area 34 to the edge 29. An array of interconnecting pad~
such as component pads 40 and signal pads 42 are also evenly
distributed over the board forming mutually parallel rows of pads
interspersed between the traces 38, as well as mNtually parallel
columns of pads extending across the board transveraely of the
-traces 38. A plurality of minor or short length traces such as
the minor traces 44-46 interconnect the parallel traces 38 and
the pads 40,42. For example, a first type of the minor traces 44
connects predetermined points of the traces 38 with adjacent pads;
a second type of the minor traces 45 interconnects predetermined
points of the traces 38 with other points of adjacent traces; and
a third type of the minor traces 46 interconnects adjacent pads.
Referring momentarily to ~IGS. 1 and 2, the minor trace 44 con-
nects the parallel trace 38' with the signal pad 180 The parallel
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trace 38' is longitudinally broken or interrupted in an area 48
adjacent a preselected point of connection 50 between the trace
38' and the pad 18. Returning to ~IG. 5, the input/output area
34 includes a plurality of I/O traces such as the trace 52 inter-
connecting selected ones of the conductive terminals 36 with the
parallel traces 380 The circuit layer 5 thus serves as a means
for selectively transerring signals across the board 1 in a
direction generally parallel to the traces 38. The minor traces
44-46 (including the attendant interruptions of the parallel
traces 38) and the I/0 traces 52 are the only portions of the
` circuit pattern S which are unique to a particular type of board.
Referring now to FlGo 10~ a unique artwork master of the
external circuit layer 10 shows a circuit pattern overspreading
the board and including a plurality of mutually parallel circuit
runs 54 evenly distributed over the board and extending virtually
across the entire board from edge 56 to edge 57 .in a direction
which is transverse the direction of the traces 38 of FIG. 5.
An array of interconnecting pad~ such as component pads 60 and
signal pads 62 are also evenly distributed over the board forming
mutually parallel columns of pads 60, 62 interspersed between the
parallel runs 54, as well as mutually parallel rows`of pads ex-
tending across the board transversely to the runs 54. The array
of pads 60, 62 of the circuit pattern 10 corresponds dimensional-
ly and is registered with the array of pads 40, 42 of the circu~t
.,` pattern 5 when the board 1 is assembled~ A plurality of minor or
..;
short length interconnecting runs such as the runs 64-66 function ~-
i similarly to the minor traces 44-46 of FIG. 5O Referring momen-
.`; tarily to FIGS~ 1 and 2, the parallel run 54' is connected from a
.,j
.` preselected point 68 thereon to the signal pad 62 via the minor
`~ 30 run 64. The parallel run 54' is longitudinally broken or inter-
rupted in an area 70 adjacent the point`of connection 68.
~' Returning to FIGo 10 the circuit layer 10 include~ edge
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terminals 71 and input/output runs such as the run 72 in the in-
put/output area 34 of the board 1. The minor runs 64-66 (in-
cluding the attendant interruptions of the parallel runs 54 are
the only portions of the circuit pattern lO which are unique to
a particular type of boardO Viewing FIGSo 5 and 10 together, it
is evident that a signal may conveniently be routed between any
selected point on the board and any other point thereon includlng
the edge terminals 36, 71 by a plurfllity of different routes
utilizing the transversely extending traces 38 and runs 54O
Referring now to FIGo 6 in con~unction with FIGS~ 1 and 2,
the internal circuit pattern 6 i8 a universal pattern common to
all board types and comprises a plurality of equal-length cross-
under runs such as the run 73 each interconnecting a pair of
cros~under signal pads 20, 20'. FIGSo 1 and 2 show a portion of
a typical crossunder run 73 connected to the signal pad 20. Re-
ferring momentarily to FIGo 14, another view of a typical cross-
under run 73 is shown in relation to the circuit layer 5O The
; rung 73 are oriented transversely to the parallel traces 38 of
the outer layer 5 and are separated therefrom by the layer 5' of
20 insulation of a predetermined thickness. The ~rossunder runs 73
are distributed over the area of the circuit layer 6 in accord-
ance with predetermined universal circuit parameters; the deter-
mination of the length and distribution of the crossunder runs
72 is discussed in a subsequent part of this specification.
- Referring to FIG~ 9 in conjunction with FIGSo 1 and 2, the
universal internal circuit pattern 9 comprises a plurality of
crossover runs such as the run 74 each interconnecting a pair of
crossover signal pads 76, 761o The runs 74 are oriented trans-
ver8ely to the parallel runs 54 of the circuit layer lO and are
30 separated therefrom by the layer 9' of insulation or predetermin-
ed thickne~s. The crossover runs 74 are distributed over the
area of the circuit layer 9 in accordance with the predetermined
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un~versal circuit parameters. Referring momentarily to ~IG. 15,
a pair of typical crossover runs 74 is shown superposed in rela-
tlon to the parallel runs 54 of the circuit layer 10. FIGS~ 1
and 2 show the crossover run 74 connected to the signal pad 76.
Both the crossunder runs 72 and crossover runs 74 are pro-
vided to augment the signal routing capability provided by the
outer circuit layers 5, 10, and need not be used unless required
for particularly dense circuit interconnect patterns.
FIG~ 7 depicts an artwork master of a voltage plane corres-
ponding to the internal circuit layer 7 of FIG~ 2. The voltageplane pattern of FIGo 7 is shown photographically negative, hav-
ing areas 80-82 of conductive material such as copper covering
substantially the entire surface of the layer 7. A plurality of
voids such as the voids 24 correspond generally with and are
aligned with virtually all of the conductive pads 40, 42; 20;
76; and 60, 62, respectively, of the other circuit layers 5; 6;
9; and 10. The voids 24 are provided to allow passage of the
interlayer conductors 12 (see ~IG~ 2) therethrough. Each of the
. . . -
conductive areas 80-82 of FIG~ 7 includes a plurality of voltage
bus interconnect areas such as the area 840 Each of the areas
.- . . .
84 is partially surrounded by a pair of thermal isolation voids
86. The locations of the bus interconnect areas 84 are pre-
selected to align with corresponding component pads such as the
i pad 88 of the circuit layers 5, 10 (FIGS~ 5 and 10).
FIG~ 8 depicts an artwork master of a ground plane corres-
ponding with the circuit layer 8 of FIGo 20 The ground plane
~ pattern of FIG~ 8 is shown photographically negative, having an
`~ area of conductive material 88 such as copper covering substan-
! tially the entire surface of the board. A matrix of voids such
`~ 30 as the voids 26 are provided for passage of the interlayer con-
ductors 12 therethrough (see FIGo 2). A plurality of ground-
plane lnterconnect areas such as the interconnect area 89 of
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FIG. 8 are provided for establishing ground connections to the
board components. The interconnect areas 89 are similar in form
to the interconnect areas 84 of the power-plane circuit pattern
7. The circuit layer 8 of the presently described embodiment,
FIG. 8, also includes voltage straps 90-93 to aid in the even
distribution of the voltages throughout the board without de-
grading the even distribution of the ground 88. Viewing FIGS~ 7
and 8 together, the straps 90-92 are provided for allowing se lec-
tive interconnection o~ the voltage buses 80, 82 of the voltage
lO plane 7~ The strap 92 provides further for the extension of
either of the voltage buses 80 or 82 to the area of the strap 92
for distribution via the centrally disposed interconnect areas
thereof, such as the interconnect area 94. The centrally dispos-
ed interconnect areas 94 are in registrat~on with voids such as
the void 96 of the voltage bus 81. The strap 93 provides for
even distribution of the voltage of bus 81 by shorting the inter-
connect areas 98, 99 thereof.
Recall now, that each of the outermost signal layers 5 and
lO includes both component pads 40, 60 and signal pads 42, 62.
20 The distinction is drawn by viewing FIG~ 11 in conjunction with
FIGS. 3 and 4. FIGo 11 depicts a layout master of a component
matr~c which includes representations or outlines of components
such as a sixteen-pin-dual-in-line package (DIP) 100, an eight-
pin single-in-line package (SIP) 102, and a discrete component
104o FIGS~ 3 and 4 depict layout masters from which artwork
masters of unique circuit layers such as, respectively, the lay-
ers 5 and lO may be generated utilizing the process of the pre-
sent inventionO The crosshatched areas lO0 of FIGS~ 3 and 4
represent the area bounded by the outline 100 of FIG~ 11 when the
30 three layout maRters are superposed and aligned. It iB evident
from FIG~ 3 that the sixteen outboard pads 40 to which the DIP
pins connect are component pad~, and the other pads 42 (including
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the central pads of the crosshatched area) within the area defin-
ed by dashed lines are signal pads.
The un~versal layout masters of FIGS. 3, 4, 6, 9 for the
presently described embodiment of a multilayer board were gen-
erated in accordance with parameters determined both by mathe-
matical design and by empirical testing of actual circuits. The
characteristic impedance of typical circuit runs; and signal prop-
agatiOn delay, crossover capacitance and crosstalk between cir-
cuit runs was calculated and measured in a test board having cir-
cuits of various length, thickness, width, population and mutual
proximity~ and with various dielectric thickness. The tests and
calculations yielded the following universal parameters for ECL
lOK logic:
1. Internal circuits 6, 9 are oriented transversely to the
ad~acent external circuits 5, 10.
2. Internal circuits 6, 9 are separated from external cir-
cuits 5, 10 by 2.5 mils (63.5 micrometers) of epoxy-glass
tielectric (er ~ 405)-
3. Internal circuits 6, 9 are separated from the adjacent
central circuits 7, 8 by 25 mils (0.635 mm) of epoxy-glass
dielectricO
4. Circuit runs are 10 mils (0.254 mm) wide.
5. Spaces between circuit elements are at least 40 m~ls
(10016 mm) wide.
6. No more than twenty circuit runs should cross a circuit
run of an adjacent layer.
7. The maximum length of crossover or crossunder runs is
1 inch or 2.54 cm. The crossover and crossunder runs may,
in some instances, form stubs, e.gO, when only one of the
pads interconnected thereby is drilled and plated.
The universal layout masters represented by FIGS~ 3, 4,
6, and 9 were digitized and plotted within the bound~ of the
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1 0 5 51 6 4
above-mentioned parameters for maximum precision in accordance
with known techniques. The application of the universal cir-
cuits, predesigned and tested as an assembled entity, to a
plurality of uses without the need to adhere to either calculated
or empirical design criteria frees the board designed of the com-
plex tasks usually associated with the generation of a unique
multilayer board. The viability of the process of the present
inventiOn lies in part in the standard lead configurations of
; modules such as DIP's which allows the formation of a predeter-
mined matrix of component and signal pads and a regular grid of
conductive runs for routing signals across the board, all prede-
signed and plotted to the highest degree of accuracy attainable
at the present state of the art.
Referring now to FIGSo 12-15, the process of generating art-
work masters in accordance with the present invention is explain-
ed. FIGo 12 represents a portion of the full scale (e.g., 4K)
layout masters of FIGS~ 3, 4 and 11 superposed to reveal a grid
formed by the traces 38 and runs 54. The module outline 100
; bisects the component pads 4Q, leaving the signal pads 42 clear.
The voltage and ground interconnect areas represented, respec-
tively, by the thermal isolation voids 107, 108 are shown only
for reference. Layout masters for the power and ground planes
need not be utilized for generating the outer-layer artwork
; masters. FIG~ 12 represents a portion of the scene viewed by
the designer of a unique circuit board prior to establishing the
plurality of short length runs and traces which render a particu-
lar type of board unique. It is noted that the layout masters
for thc circuit layers 6 and 7 are not shown in FIGo 12. The
embodiment of the invention described with reference to FIGS~ 5
ant 10 was assembled without using the crossunder runs 73 or
crossover runs 74; however, an example of their use is described
in the ensuing discussion.
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FIG. 13 depicts generally the composite of superposed lay-
out masters of FIGo 12 with an additional transparent overlay 110
such as vellum or mylar. In choosing conductor routes, the de-
signer marks the overlay 110 with representations of the minortraces 44-46 `(shown as dotted lines) associated with the circuit
layer 5, and with representations of the minor runs 64-66 (shown
as solid lines) associated with the circuit layer 10. Interrup-
tions of the circuit traces 38 and circuit runs 54 are represent-
ed in FIGo 13, respectively, by small x's 112 and 1140 The
representstions 44-46, 112 marked on the transp~rent overlay 110
are then utilized as an underlay to alter the layout master of
FIGo 3 to form a unique artwork master 5 (see also FIG. 5). This
step is illustrated by comparing the like reference numbers of
FIGS. 13 and 140 It is noted that the illustrative crossunder
run 73 shown in FIGo 14 does not form a part of the artwork
master 5.
In generating artwork masters for unique circuit boards in
accordance with the present invention there is no formal artwork
layout as it is currently known. The transparent overlay 110 if
viewed independently of the layout masters would appear as a
muddle of unrelated marks randomly placed on the overlay. When
the transparent overlay 110 is completed, it is aligned separate-
ly under each of the layout masters and the layout m~ster is then
altered in accordance with any of ~he techniques well known in
the art. The alterations required to generate a unique artwork
master of a circuit pattern such as the circuit pattern 5 are
minor in nature when compared with the design effort required to
generate full artwork. The alterations involve only relatively
short-length interconnections between adjacent circuit elements,
which elements are previously designed and precisely dimensioned
utilizing a first degree of lflyout precision which generally is
the highest precision ~ttainabl¢ in the multilflyer circuit board
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The alterations are effected utilizing a technique having a
second degree of layout precision which is less than the first
degreeO '~egree of precision" is a relative term. For the pur-
poses of this disclosure the maximum range between the first and
second degrees of precision is defined as that between the pre-
cision obtainable with sn automatic X-Y plotter, and that ob-
tainable by taped or inked artwork.
Comparing now FIGS~ 13 and 15, the representations 64-66,
114 marked on the transparent overlay 110 are utilized as an
underlay to alter the layout master of FIG~ 4 to form a unique
artwork master 10 (see also FIG~ 10)~ The word "ad~acent" used
in the context of the short interconnecting runs 44-46; 64-66
described with reference tO FIGS~ 5~ 10~ 14 and 15 means "reason-
ably close", eOg., the run 64 of FIGo 15 connects the signal pad
116 to a point 118 on the circuit run 120, which point is two
runs removed from the pad 116. It would not be unreasonable to
; assume that a short run could interconnect points three elements
` removed from each other; however, the ma~ority of the short runs
are between contiguous traces or pads and only occasionally be- ~ -
tween elements not contiguous. It is noted that the crossover
runs 74 shown in FlGo 15 do not form a part of the artwork master
,, 10.
The unique artwork masters 5 and 10 may be generated by
known methods such as the so-called "cut and tape" process. This
technique alters the predefined precision artwork by removing se-
lected portions of the traces as by scraping or otherwise remov- ~ -
ing the photographic emulsion and adding short lengths of photo-
graphically opaque substance such as ink or tape to form the re-
quired unique interconnects. A quicker, less precise, and con-
sequently less costly method is thus utili~ed to generate the
unique artwork for a multilayer circuit board, while retaining
the precision, high terminsl density, and uniform electrical
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impedance and coupling of much more expensive boards. This i8
made possible by the predefinition of layout masters utilizing a
high degree of precision commensurate with presently available
autOmatic plotting apparatus.
Photoreduction of the completed artwork masters is accomp-
lished using the ground or voltage plane 1:1 artwork masters for
dimensional control, assuring that all of the planes form a
matched set of board artwork with minimum dimensional deviations
among the various planesO
When the unique circuit routes have been established, a
drilling program may be prepared for establishing unique loca-
tions of the board interconnects. Viewing FIGSo 14 and 15, for
example, plated-through holes are established at the pad loca-
tions which are shown as solid; no interconnection is established
at the pad locations shown as open circlesO A drilling template
may be prepared for a unique circuit-board designO The required
number of preassembled universal boards may then be drilled and
the interconnects plated at the same time the outer circuit lay-
ers 5, 10 are plated. After the drilling and plating operations,
the components may be installed on the boardO Alternatively, a
master drill tape or template drilling all pads of the matrix may
be utilized. Further and substantial cost reduction is achieved
in the latter described embodiment by eliminating the unique hole
patternO The unique interconnections of the outermost layers
provide the desired interconnect pattern by selecting desired ones
of the pads for inclusion in the overall pattern of circuits,
leaving unneeded pads disconnected.
I have described herein a method of maklng multilayer cir-
cuit boards by predesigning the universal internal circuit pat-
terns and the universal exterior circuit patterns with establish-
ed clrcuit characteristics which will not be degraded by subse-
quent, randomly generated alterations of the exterior circuit
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patterns effected to establish a final board configuration. In-
stead of designing six separate circuit patterns for each unique
board as in the prior art, it is necessary only to provide minor
alterations of the two predesigned exterior circuit patterns.
The method has yielded significant savings of cost and time over
previous methods, while maintaining accuracy. The first design
of a unique production printed circuit board in accordance with
the invention was accomplished in a total time of two weeks and
two days, including time for an assembly drawing, marked-up
schematic for gate and componènt pin placement, three different
check steps, and photoreduction. All pads were drilled from the
universal drill tape. This first effort compared favorably with
established prior art techniques which, at best, required four
weeks for a less complex design.
The method of making multilayer circuit boards in accord-
ance with the present invention was found to be superior to prior
art techniques utilizing predefined interior circuit runs because
of the assembly design parameters considered in the present
methodO The synergistic results achieved by the present inven-
e~ide~t
tion are made e~dence, for example, by viewing FIGS. 5 and lO
and observing the uniform distribution of etched copper on the
outer layers of a completed designO
While the principles of my invention have now been made - --
clear in the foregoing description, it will be immediately ob-
vious to those skilled in the art that many modifications of
structure, arrangement, proportions, the elements, material and
components may be used in the practice of the invention which are
particularly adapted for specific environments without departing
from those principles. The appended claims are intended to cover
ant embrace any such modifications within the limits only of the
true spirit and scope of my inventionO
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