Note : Les descriptions sont présentées dans la langue officielle dans laquelle elles ont été soumises.
sackground and Summary of the Invention
This invention relates generally to the dynamic
comparison of two input signals to obtain an indi~ation of
which input signal is higher in frequency, and more particular-
ly to a circuit for obtaining a digital indication of the
frequency relationship independent of phase information.
Prior art circuits have determined the frequency
relationship between two input signals by sensing the variation
in phase difference between the two signals over a period of
time.
An object of an aspect of this invention is to sense
the frequency relationship between two input signals directly,
without the use of phase information, and to provide digital
ou$put information indicating either that the input signals
are equal or nearly equal in frequency or that one of the
input signals is higher in frequency than the other. A further
object of an aspect of this invention is to provide digital
output signals the duration of which are a function of the
frequency mismatch of the input signals.
These objects are accomplished in accordance with the
preferred embodiment of this invention by the use of edge-
triggered flip-flop configured to provide output signals
indicative of a frequency mismatch when at least two rising
edges of one input signal occur without an intervening rising
edg~ of the other input signal. The input signals are detect-
ed to be equal or nearly equal when rising edges of one input
signal continuoulsy alternate with rising edges of the other
input signal. The digital output signals indicative of a
frequency mismat~h between the two input signals are issued
for the integer number of periods of the input signal of
higher frequency that commence without an intervening edge of
the input signal or lower frequency.
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In accordance with one aspect of this invention
there is provided a frequency detector circuit for receiving
a first input signal and a second input signal and for
providing, through detection of selected edges of the first
Q,i~' input signal and the second input signal, digital output
d i ~ c ~
information indicative of the frequency 7r~ L~ between
the first and second input signals, the frequency detector
cixcuit comprising: first logic means for detecting and
counting consecutive selected edges of the first input signal
and for issuing a first output signal after at least two
consecutive selected edges of said first input signal have
been counted; second logic means for detecting and counting
consecutive selected edges of the second input signal and for
issuing a second output signal after at least two consecutive
selected edges of said second input signal have been counted;
first reset means coupled to the second input signal and,to
the first logic means for detecting selec~ed edges of said
second input signal and for resetting the first logic means
in response to detection of each selected edge of said second
input signal; and second res~t means coupled to the first
input signal and to the second logic means for detecting
selected edges of said first input signal and for resetting
the second logic means in response to detection of each select-
ed edge of said first input signal.
In accordance with another aspect of this invention
there is provided a method for measuring and indicating the
Q~ C~_.
frequency ro~4~s~p-between a first signal and a second
'signal, the method comprising: sensing the start and end
points of a selected cycle of the first signal; sensing the
start and end points of a selected cycle of the second signal;
1~
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~s~z~
detecting the order of occurrence of the start and end points
of the sensed cycles of the first and secong signals; indicat-
ing that the first signal is higher in frequency than the
second signal if the start point of the sensed cycle of the
first signal occurs after the start point of the sensed cycle
of the second signal and if the end point oE the sensed cycle
of the first signal occurs before the end point of the sensed
cycle of ~he second signal; and indicating that the second
signal is higher in frequency than the first signal i~ the
start point of the sensed cycle of the second signal occurs
after the start point of the sensed cycle of the first signal
and if the end point of the sensed cycle of the second signal
occurs before the end point of the sensed cycle of the first
signal. -
In accordance with another aspect of this invention
there is provided a method of measuring and indicating the
a~e~C e,
-` frequency ~e~-tler~*i~between a first signal and a second
signal, the method comprising: sensing the start points of
consecutive cycles of said first and second signals; and
indicating that the frequencies of the first and second
signals are approximately equal for so long as the start points
of the sensed cycles of the irst signal alternate with the
start points of the sensed cycles of the second signal;
In accordance with another aspect of this invention
there is provided a method for measuring and indicating the
e~C e,
frequency ~A~ rl~between a first signal and a second
signal, the method comprising: detecting and counting
consecutive cycles of the first signal; detecting and count-
ing consecutive cycles of the second signal; resetting the
counting of cycles of the first signal upon the occurrence
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3l~5~'~8~
of each counted cycle of the second signal; resetting the
counting of cycles of the second signal upon the occurrence
of each counted cycle of the first signal; indicating that
the first signal is higher in frequency than the second
signal if two or more cycles of the first cycle are counted
before such counting is reset; indicating that the first
signal is lower in frequency than the second signal if two
or more cycles of the second signal are countea before such
counting is reset; and indicating that the first and second
signals are approximately equal in frequency if no more than
one cycle of both first and second signals is counted before
such counting is reset.
Description of the Drawings
Figure 1 is a schematic diagram of a frequency detector
circuit employing edge-triggered flip-flops to detect the
frequency relationship between two input signals.
Figure 2 is a timing diagram illustating the relation-
ship of various signals within the frequency detector circuit
of Figure 1 that occur in response to the application of two
input signals.
Figure 3 is a flow diagram showing the logic states of
two outputs of the frequency detector circuit of Figure 1 as
edges of two input signals are sensed by the frequency
detector circuit.
Descri tion of the Preferred Embodiment
. ~ . . _ , .. .
Referring now to Figure 1, there is shown a frequency
detector circuit that compares an input signal 20 wi~h another
input signal 21 and produces binary output information at an
output 30 and an output 31 indicative of the fre~uency relation-
ship of the two input signals. If the frequency of input
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1~3S~38
signal 20 is higher than that of input signal 21, output 30
is set to a logical one, and output 31 is set to a logical
zero. If the frequency of input signal 20 is lower than
that of input signal 21, output 30 is set to a logical zero,
and output 31 is set to a logical one. If the frequencies of
input signals 20 and 21 are equal or nearly equal, outputs
30 and 31 are both
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~lC3~ 8 Z ~3~3
set to logical zero. Outputs 30 and 31 are also at logical zero when the fre-
quency detector circuit has not received sufficient information from înput
signals 20 and 21 to detect the frequency relationship. Outputs 30 and 31 may
simultaneously be set to logical one For a br;ef period if there is a sudden
change in the frequency relationship between the two input signals 20 and 21.
For example, if input signal 21 is initially lower in frequency than input sig-
nal 20, but then suddenly becomes higher in frequency than -input signal 20,
both outputs 30 and 31 may be at logical one until the end of the period of in-
put signal 20 during which the change in the frequency relationship is detected.Six edge-triggered D-type flip-flops 1 through 6 are configured to
implement a preferred embodiment of the invention. Each flip-flop, which
may-comprise one-half of a 74LS74 integrated circuit package, for example,
has a D input, a clock input, a clear input, and a preset input, as well as
complementary Q and Q outputs. The clear and preset inputs are negative
true logic. The D input and Q and Q complementary outputs are positive
true logic. The clock input responds to a positive-going edge of a signal
applied thereto. It will be appreciated by those persons skilled in the art
that the preferred embodiment of the invention can be implemente~ using other
types of flip-flops, such as J-K flip-flops, or by using flip-flops respon-
0 sive to other logic states or transitio~s.
The preset input of each flip-flop is connected to a 5-volt supply
10 through a resistor 12 to set the preset inputs to logical zero. The D in-
puts of flip-flops 1 through 4 are set to logical 1 by connection to the 5-
vo~t supply 10 through the resistor 12. A control signal 14 may be connec-
ted to the clear input of flip-flops 3 and 6 to allow outputs 30 and 31 to
be disabled.
Input signal 20 is-applied to the clock input of flip-flops 1, 5~
and 6. The Q output of flip-flop 6 serves as output 30 of the frequency de-
tector circuit. The Q output of flip-flop 1 is connected to the clear input
~0 of flip-flop 2. The Q output of flip-flop 2 is connected to the clear input
*~s~
of flip-flop 1 and to the D input of flip-flop 3.
Input signal 21 is applied to the clock input of flip-flops 2, 3,
and 4. The Q output of flip-flop 3 serves as output 31 of the Frequen~y de-
tector circuit. The Q output of flip-flop 4 is connected to the clear input
of flip-flop 5. The Q output of flip-flop 5 is connected to the clear input
of flip-flop 4 and to the D input of flip-flop 6.
Referring now to Figure 2, there is shown a timing diagram indicating
levels of outputs 30 and 31 and selected signals produced within ~he frequen-
cy detector circuit when the two input signals 20 and 21 are applied. Sever-
al points in time, designated T0 through T26, are referred to herein.
At time T~, the control signal 14 is held in its active state, thus
forcing outputs 30 and 31 low. Other levels shown in Figure 2 are assumed.
Between times T0 and Tl, control line 14 is set to its inactivestate to enable
flip-flops 3 and 6 to respond to logic signals applied at their D and clock
inputs. Time Tl corresponds to a rising edge of input signal 20. Hereinaf-
ter, any reference to an edge of input signals 20 and 21 means rising edges
of those input signals. It will be appreciated by those persons skilled in
the art that the frequency detector circuit o~ Figure 1 may easily be arran-
ged to respond to falling edges of input signals 20 and 21. The edge of in-
put signal 20 clocks the Q output of fl;p-flop 5 high. The edge of input
signal 20 also clocks flip-flop 6, but output 30 remains low because propa-
gation delay through flip-flop 5 delays the change in state of the signal
appearing at the D input to flip-flop 6 until after flip-flop 6 has been
clocked by the edge of input signal 20. At this point, the frequency detec-
tor circuit has sensed only one edge of input signal 20, and therefore no
determination of frequency relationship is possible. This status is reflec-
ted by outputs 30 and 31 both remainin~g low. Given the input slgnals 20 and
21 shown in Figure 2, the next edge sensed by the frequency detector occurs
at time T3 and is another edge of input signal 20. At time T3 the D input
to flip-flop 6 is already high, so that input signal 20 clocks output 30
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high. Two consecutive edges of input signal 20 have now been detected with-
out an intervening edge of input signal 21; thus, input signal 20 is higher
in frequency than input signal 21. Another edge of input signal 20 occurs at
time T5 without an intervening edge of input signal 21. The Q output of
flip-flop 5 remains high, thus causing output 30 to remain high when flip-
flop 6 is clocked by the edge of input signal 20 occurring at time T5.
Just prior to time T7, the first edge of input signal 21 occurs and
clocks flip-flop 2, thus setting the Q output of flip-flop 2 high. Output
31 remains low because propagation delay through flip-flop 2 delays the
change of state of the signal appearing at the D input of flip-flop 3 unt;l
after flip-flop 3 is clocked by the edge of input signal 21. This edge of
input signal 21 occurring prior to time T7 also clocks flip-flop 4 and sets
its Q output low, causing flip-flop 5 to be cleared and its output to be set
low. When the Q output of flip-flop 5 is set low, flip-flop 4 is immediately
cleared~ and its Q output returns high.
At time T7 an edge of input signal 20 occurs and clocks output 30
low, since the Q output of flip-flop 5 has been set low previously. Output
30 has remained constantly high for an integer number of periods ~f input
signal 20, the input signal of higher frequency from time T3 to time T7.
The number of periods of input signal 20 during which ou~put 30 is high is
determined by the number of edges of input signal 20 that occur without an
intervening edge of input signal 21, and, hence, the duration of a high sig-
nal at output 30 is a function of the frequency mismatch between input sig-
nals 20 and 21. Also at time T7, the edge of input signal 20 clocks flip-
flop 1, setting its Q output low. The low state of the Q output of flip-flop
1 clears flip-flop 2, setting its Q output low. Flip-flop 1 is then immed-
iately cleared by the Q output of flip-flop 2, and the Q output of flip-flop
1 returns high.
Another edge of input signal 20 occurs at time T9 without an inter-
1 vening edge of input signal 21. This edge causes output 30 to again be set
.
~ _5
~LC3 5~3~8~
high, where it remains for an integer number of periods of input signal 20until after another edge of input signal 21 occurs, in this case just prior
to time Tll. As long as input s;gnal 20 is higher in frequency than input.
signal 21 two edges of input signal 21 will never occur without at least one
intervening edge of input signal 20. Therefore, output 31 will remain low
during this condltion.
The above-described output pattern continues, as shown in Figure 2,
through time T15 with output 30 being set high for an integer number of per-
iods of input s;gnal 20, and returning low for one period of input signal 20
commencing after the occurrence of an intervening edge of input signal 21.
Between times T15 and T20 edges of input signals 20 and 21 occur alternately.
The edge of input signal 21 that occurs between times T13 and T14 causes out-
put 30 to go low in response to the edge of input signal 20 at time T15.
From times T15 to T20 outputs 30 and 31 both remain low. This condi.tion
exists because the Q output of flip-flop 2 is set high by the edge of input
signal 21, but is then reset by the interYening edge of input signal 20 due
to clocking of flip-flop 1 before the high Q output of flip-flop 2 can be
clockeu into flip-flop 3. Sim;larly, the Q output of flip-flop 5 ;s set
high by the edge of input signal 20 but is then reset by the intervening
edge of input signal 21 due to clocking of flip-flop 4 before the high Q
output of flip-flop 5 can be clocked into flip-flop 6~
Between times Tl9 and T20 an edge of input signal 21 occurs. This
edge clocks flip-flop 2 high while output 31 remains low. Input signal 21
is shown in Figure 2 as be;ng higher in frequency than input signal 20 after
time Tl9. As a result, a second edge of input signal 21 occurs between times
T20 and T21 without the occurrence of an intervening edge of input signal 20.
Therefore, output 31 is clocked high. 'Since the frequency difference between
input signa1s 20 and 21 is small at time T20, output 31 remains h;gh for only
one period of input signal 21. After one period of input signal 21, output
31 is reset low, since an intervening edge of input signal 20, occurring at
~L~3 5 8 2~
time T21, resets flip-flop 2, and causes output 31 to go low at the next edge
of input signal 21 for one period of input signal 21. This pattern is re-
peated between times T21 and T23.
Between times T23 and T25, the frequency of input signal 21 has in-
creased with respect to that of input signal 20 to the extent that two com-
plete periods of input signal 21, ev;denced by three consecutive edges of
input signal 21, occur without an intervening edge of input signal 20. Due
to this frequency difference, output 31 is set high upon the occurrence of
the second of these edges and remains high for two complete periods of input
signal 21. As input signal 21 continues to increase in frequency with res-
pect to input s;gnal 20, output 31 will be set high and remain high for an
increasing integer number of periods of input signal 21 as a result of the
occurrence of more edges of input signal 21 without an intervening edge of
input signal 2G. Thus, output 31 remains high for a time period which is a
function of the frequency difference between input signals 20 and 21~ As
long as the frequency of input signal 21 is greater than or equal to that of
input signal 20, output 30 will remain low due to edges of input signal 21
resetting flip-flop ~ by clocking flip-flop 4 with at least one edge of in-
put signal 21 interven;ng between edges of input signal 20.
The frequency detector circuit may be disabled at any time by se~ting
control line 14 to ;ts active state. Initialization of the frequency detec-
tor circuit by use of control line 14, or by any other means, is not required
for proper operation, however.
Referring now to Figure 3, there is shown a flow chart of the logical
operation of the frequency detector circuit of Figure 1. By setting control
line 14 to its inactive state the Frequency detector lo~ic advances to an
initial state A, in which outputs 30 and 31 are both at logical zero, but in
which these outputs may respond to input signals 20 and 21.
The frequency detector logic advances from state A to a state B when
the first signal sensed is an edge of input signal 20. The frequency
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_ ., .... ,, . , _.. ... . . ..
105828B
detector logic advances from state A to a state D when the first signal
sensed is an edge of input signal 21.
If the frequency detector logic is in state B and an edge of input
s;gnal 20 is then sensed, the frequency detector logic advances to a state
C, and output 30 is set to logical one to indicate that input signal 20 is
higher in frequency than input signal 21. The frequency detector logic re-
mains in state C as long as edges of input signal 20 are sensed without an
interYening edge of input signal 21. If the frequency detector logic is in
state B or C and an edge of input signal 21 is sensed, the frequency detec-
I tor logic advances to state D, and output 31 is set to a logical zero.lf the frequency detector logic is ;n state D and an edge of inputsignal 21 is then sensed, the frequency detector logic advances to a state
E and sets output 31 to logical one to indicate that input signal 21 is high-
er ~n frequency than input signal 20. The frequency detector logic will re-
main in state E with output 31 remaining set to logical one as long as edges
of input signal 21 are sensed without intervening edges of input signal 20.
If the frequency detector logic is in either state D or E and an edge of in-
put signal 20 is sensed, output 30 is set to logical zero3 and the frequency
detector logic advances to state B.
) If edges of input signal 20 occur alternately with edges of input
signal 21, the frequency detector logic will alternate between state B and
state D, and outputs 30 and 31 will remain at logical zero to indicate that
the frequencies of input signais 20 and 21 are equal or nearly equal.
By referring to this.flowchart, the logical states of outputs 30 and
31 can be determined for any sensed sequence of edges of input signals 20
and 21.
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