Note : Les descriptions sont présentées dans la langue officielle dans laquelle elles ont été soumises.
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The present invention relates to a method for trans-
mission of PCM words by means of memory arrangements which are
associated with one PCM link each and are included in a PCM
exhange which switches the PCM words from incoming channels in
incoming links to outgoing channels in outgoing links via a
bus arranged as a common time multiplex connection, the PCM
words being transferred on said links in link time slots and on
said bus in bus timeslots ~ saidmemory arrangementsstoring on
one hand the PCM words before and after being switched and on
the other hand switching information concerning the channels
which cooperate in the incoming and outgoing links, respectively.
; The invention, furthermore, relates to an exchange for executing
the method.
A time-multiplex-PCM-system is obtained if on each of
n links q analogous information signals are transferred, each
information signal being allotted a link time slot with length
Tl within a frame period F. In standardized systems F = 125 ~s
and q = 32 information channels, i.e. T1~4 ~s. During each
time slot the amplitude of the respective analogous signal is
indicated in coded form by a PCM word, ~or example by 8 pulses
in series each of which, by means of a negative or positive
polarity, indicates a binary condition. In this way the pulses ~ ;
in series are transferred with 0.5 ~s intervals, i.e. with a
pulse frequency of 2 MHz. In a synchronous system, full coinci-
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`~ dence exists for the frames and time slots and pulses, respect-
`~ ively, of all links.
A digital time multiplex exchange in the system has
as its task to switch an incoming channel signal during a first
link time slot on a corresponding link so that the signal is
30 outgoing on a link in an outgoing channel during a second link
time slot. As a consequence of space switching from one link to
the other link, time switching is required from the first time -~ `
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slot to the second time slots.
In Canadian Patent No. 1,000,424 a description is
given of how to carry out time switching by means of memory
arrangements. In this connection, word memories are used in
order to store the PCM words during the time between the first
and second time slots. Each of the word memories which is
associated with a link, has to be sufficiently large to store
all PCM words within a frame, and comprises, consequently, for
standardized systems 32 groups of 8 memory elements. In each
memory, the write operations (inclusive of the switching case
where the first and second time slots are equal) should never
collide with the read operations. According to the above
s~.andardized system, a demand of 0.25 ~s access times is obtained,
.~
corresponding to a pulse base frequency fa = 4 MHz, the operations
being controlled for example so that the writings and readings
occur during the first and second halves of the time slots,
respectively. The addressing operations of the word memories
for reading and writing are controlled by means of a cylical
,~
scanning arrangement and by means of a decoder which is fed with
a plurality of channel indexes cyclically read from an index
memory, as will be described hereinbelow.
While the time switching in this manner will be comp-
~'~ letely achieved without expensive gate multiplex switching arrange-
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ments, a space stage of a ~CM exchange comprising gate matrixes
which are activated by means of control signals obtained from a
control unit, the synchronization of the exchange often causes
great problems. In the Canadian Patent No. 1,000,424 an exchange
is described which comprises one space stage arranged between two
. time stages (time-space-time principle). By means of the two time
switchings executed in the two time stages, the space switching
can be made completely independent of the first and second time
slots, respectively as will be described hereinbelow.
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5~]~e l~ubl~cation "Col]o~ue Inter~ational ~e Com~utation
Electronique, Paris 1966" includes an article entitled "Switching,
synchronizing and signalling in PCM exchanges" by ~. Neu and
A. Kundig, which describes how space switching is avoidcd if
time switching is combined with a multiplex formation chan~e
so that all the r = n q chanllels of the system are associated
with just one con~on time multiplex connection, referred to
as a bus in tlle following dcscription, wllerein each information
is allotted a bus time slot with length T~ = tl/n. Even if it
is assumed that the signals are transferred by means of ~arallel
pulses on said bus which, according to the standard example
would then consist of 8 ~arallel lines, according to the
foregoing a force base frequency fb = 1000 4/8 = 500 M~z is
obtained for the example wherein n = lQ00 links. .~s no known
contemporary memories work with 2 ns-access times, such systems
with only time switching have hitherto been limited by
com~aratively small PCM exchanges~
An object of the present invention is to retain the
advantage of a PCM transit system not havlng space switching
and to reduce the demand which is put on the access times in - -
word and index memories.
Another object of the invention is to achieve access
times which are independent of the link number of the PCM y
transit system.
Accordingly, the present invention provides the method
~ of integrated switching and transmission of PCM words which are
; incoming and outgoing on links each link having a plurality of t channels, each channel being associated with a link time slot
in a frame, the switching being carried out by means of an
interhighwa~ bus acting as a com~on time multiplex connection
on which the PCM ~ords are transferred in bus time slots and
connected between inward and outward traffic memory arran~ements
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each being associated with one incoming and outgoing lin~ and
eacll including a PCM word memory and an index number memory,
respectively, said method comprising the steps of storing in
corresponding locations of the index number memories of the
; inward and outward memory arrangements associated with an
esta~lished connection in which the respective link is involved
a channel index number associated with the incoming channel
and a channel index number ~ssociated with the outgoing channel
of the connection as well as a t.ime index number which is the
same for the respective inward and outward memory arrangement,
`writing and reading cyclically the incoming and outgoing PC.~
.~ words into the PCM word memories of the inward and out of the
;~ outward memory arrangements, respectively, by means of a regular
scanning occurring at a fre~uency defined by the link time slots,
reading cyclically the channel and the time index numbers from
the index number memories by means of a regular scanning
occurring at a frequency defined'by index read out phases,
each phase comprising a plurality of the interhighway bus time
` slots and each frame includin~ at least so many phases as there
are link time slots, reading the PC~l wo~ds from the PC~ word
memory of the respective inward memory arrangement in an
irregular sequence determined by means of the channel index
numbers read from the index number memory of said inward
memory arrangement, transferring the PCM words of an actual
connection to and from the interhighway bus under the control
of the time index number associated with the connection and
, read from the index number memory of said inward memory
arrangement, and writing the PCM words in the respective outward
' memory arrangement in an irregular sequence determined by means
of the channel index numbers read from the index number memory
of said outward memory arrangement.
The invention will now be more particularly described
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with reference to einbodiments thereof shown, by way of example,
in the accompanying drawings, wherein:
Fig. 1 is a block diagram of a PCM exchange that
embodies the present invention;
Fig. 2 is a block diagram of a switching system,
according to the invention, for a large PCM exchange; and
Fig. 3 is a time diagram showing the relationship
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between pulse trains that are produced by a time generator
in the embodiment of Fig. 2.
` In order to achieve an easier understanding of the
invention, the switching principle of the invention is shown
in Fig. 1 which uses a bus IHW that connects the read output of
a inward word memory Wa to the write input of an outward word
memory Wb. By buffering storing the PCM words in the memories
Wa and Wb, by means of an inward index memory Ia and an outward
index memory Ib, for each transferred PCM word an inward and
outward time switching is obtained. As in a time-space-time `
system, due to the two time switchings, a bus time slot optional-
~, ly fixed by means of a time index number x can be chosen for
transferring PCM words onto the bus IHW. This feature will now
beexplained in greater detail in the following description of
Figs. 1 and 2.
The write inputs in the inward word memory Wa are
i connected to the links Lal to Lan. On each link the PCM words
1 to 32 are transferred within a frame period in which each word
is written into an allotted memory element group. In Fig. 1
the symbols 1.01 .... 1.32 indicate buffering stored PCM words
which have been transferred via the link Lal. The allotting
of each respective memory element group is carried out by means
of slowly working low-rate scanning arrangements LRS. The
scanning symbols of Fig. 1 indicate that cyclical scanning is
^ started by frame timing pulses fF and is stepped by timing pulses
fl in synchronism with the link time slots. It will be noted
that Fig. 1 makes no reference to either series or parallel
transfer of PCM words in a switching system. A serialized
addressing of the elements of the memory element groups demands,
for example, a further scanning arrangement which is started
by timing pulses in synchronism with the link time slots and
is stepped by the series pulses. On the other hand, a parallel
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transfer means that the elements of a group are addressed
simultaneously when writing PCM words transferred on parallel
lines.
According to Fig. 1 the index memories Ia and Ib are
each read by means of a quickly working high-rate scanning
arrangement HRS and it is assumed that each index memory comp-
rises 32 x n memory element groups. The cyclical quick scanning
is started by frame timing pulses fF and is stepped by timing
pulses 2 in synchronism with the bus time slots so that each
element group of the index memory storing channel indexes za,
zb is read during the bus time slot with length T2. The read
outputs of the index memories are connected to inward and outward
index decoders IDECa and IDECb Which dscode the channel indexes
and acti~ate an element group indicated by a respective channel
index in the inward word memory Wa for reading and in the
outward word memory Wb for writing. It is preferable to use
parallel transfer for the channel indexes, comprising several
binary signs, as indicated in Fig. 1. Arrangements of delay
lines to compensate possible time displacements are not shown
~ ~ .~ 20 since it is assumed that the transfer and decoding of the indexes
do not influence the required frame synchronism in write and
read addressings of the word memories. In the bus time slot with
time index number x, according to Fig. 1, the channel index 160
is transferred to the inward index decoder IDECa, and the channel
index 1 is transferred to the outward index decoder IDECb. The
index 160 activates in the inward word memory Wa for reading the
element group that contains the PCM word 5.32 which, in the
bus time slot having time index number ~ is transferred in
series or in parallel on the bus ~HW. The index 1 acti~ates
in the outward word memory Wb for writing the element group, the
PCM word WhlCh, in this caSe 5.32, is transferred upon reading
theword memory Wb in the first link time slot on the outgoing
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link Lbl.
According to the foregoing description, by using two
channel indexes an information signal which is received in
an arbitrary link time slot on an arbitrary incoming link is
switched to an arbitrary link time slot on an arbitrary out-
going link. Thus, it obviously does not matter which time
index x is chosen for the transfer on the bus. A congestionless
switching re~uires, as it has been assumed above, that there
is for each information signal at least one bus time slot. A
faultless switching requires, as mentioned in the preamble
but for purposes of simple explanation is not shown in Fig. 1,
that the write and read operations in the same memory element
` group never collide. A certainty against such a collision is
- provided, for example, in a computer which chooseseach time
index x so that the bus time slot in question does not fall
within the link time slots tla and tlb for the inward and out-
ward channels, respectively, which are to be switched. By
such exceptional rule the above mentioned dividing up of the
bus time slots into write and read halves is not required.
However, the foregoing rule causes a switching congestion if,
on the bus, a multiplex formation with only r = n q channels
is arranged. But no moreenter into otherwise known congestion
` reducing measures. To sum up, it has to be established that
the demand on the access times of the memory arrangements are
not reduced essentially owing to a repeated time switching
'~ according to Fig. 1 and that up till now described switching
principles without space stages are suitable only for relativ~ly
small exhanges.
Fig. 2 shows a switching system according to the
30 invention, proposed for larger exchanges, wherein all the
memory arrangements are included in a low-rate part LRP. Only
the memory arrangements are shown which cooperate with one of
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the inward links La and with one of the outward links Lb in
order to transfer respective PCM words to and from a high-rate
part HRP which, besides the bus IHW, comprises sluice-in and
sluice-out arrangements Sa and Sb.
Two decentralized time switchings are carried out,
each concerning its link, and at least one exceptional rule is
valid for the selection of a bus time slot so that congestion
risk appears. ~he congestion risk can always be avoided by
arranging on the bus a multiplex ormation with s ~ n q
channels, whereby an advanced demand is placed on the high-rate
part but whereby the access time demand placed on the low-rate
part is not influenced, as it will appear from the following
description. Therefore, only the access times of the high-rate
part limit the switching capacity of the exchange, and it is
assumed that the quick multiplex formation is chosen so that
the high-rate part works reliably.
The fact that the access times of the low-rate part
are not influenced by the size of the exchange, i.e. of the
.. ~ ... .
.~ link number n, is achieved by the decentralization associating
each link with its memory- and sluice arrangements, and by control-
ling each time switching by means of a phase number y and by
means of two index numbers which comprise a channel index
~ B number ~and a time index number z. The memory arrangements
'5, comprise word and index memories Wa, Wb, Ia, Ib for storing
the PCM words and said index numbers. By means of transmission
in parallel, the channel index numbers z are read to an index
decoder IDECa, IDECb associated with the respective word memory
and the time index numbers x are read to a time counter TCa,
i TCb associated with the respective link. The element groups of
.; . .
the word memories are addressed by means of the index decoders
and bymeans of low-rate scanning axrangements LRS completely in
agreement with the manner described in connection with Fig. 1.
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On the contrary, the index memories are read according to Fig. 2
by means of phase-rate scanning arrangements PHRS stepped phase
by phase, and the bus IHW is connected via buffer registers
Ra, Rb, each being associated with its link, to the w~ r]c
memories Wa, Wb. As will be explained hereinbelow using a
switching example, by means of the time counters the time is
controlled during which the PCM words are stored before and
after being transferred on the bus in the buffer registers which,
as with the time counters, are included in the sluice arrange-
ments Sa, Sb of the high-rate part. A time index number x
determines which bus time slot within the phase in question is
used for the transfer on the bus. Generally, the decentraliza-
; tion of the exchange does not require that word and index memories
be controlled by means of their respective scanning arrangements.
Besides, a number of memories of the same kind may be controlled
by a common scanning arrangement. One choses the var~ant which
- gives the best synchronization condition.
Between the link time slQts with length Tl, the bus
time slots with length T2, the phases with length PH used for
stepping of the scanning arrangements PHRS of the index memories,
and the length F of the frame periods, there exist the following
relations which are achieved by means of a synchronizing timing
generator TG and which are shown in the time dia~ram of Fig. 3: Tl =
: F/q and T2 = F/s with q and s as the number of channels on each
of the links and on the bus, respectively. If it is assumed
~t that a phase has a time length PH = F/m, due to the repeating
rule, m has to be an integral number and it must be m ~ q -
otherwise there is no time for the PCM words stored in an inward ; `
word memory to be read completley within a frame. A dimensioning
with m = s would lead to a switching principle corresponding to -
the one shown in Fig. 1. The dimensioning within the limits
q< m< s must however fulfil the equation s = m k with k as an
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integxal number, i.e. that a phase comprises k bus time slots.
For the equation m = c q, it is, however, not required that
c be an integral number. If the size of the exchange, as
mentioned above, is indicated by means of the number n for the
quantity of incoming and outgoing links, the selection s > n q
as well as the selection m >q contribute to reduce the risk for
congestion. This is forced upon the rule by means of the
stepping rate of the index scanning arrangements, that the ele-
ment groups of the word memories are addressed by means of
decoding the channel index only once during a phase. Probability
calculations show that with c = 2 and ~r = n q bus channels,
practically a nonexisting risk for congestion is achieved.
Suitably, the integral number m is chosen so that reliable
accesses are achieved in the memory arrangements.
~ In Fig. 2 it is not shown how a computer or another
-` arrangement selects the above mentioned time index numbers and
phases in order to achieve a connection between an inward and
an outward PCM channel, nor how the index memories are addressed
for a writing without disturbances of channel and time index
numbers because this does not affect the invention. However,
it should be noted that a write- read collision in the index
. memories is avoided simply by controlling the operations with
a mutual time displacement of about half a frame period. A
write - read collision in the word memories is avoided, for
example, if the computer controls the phase allotment so that
the phases which fall whithin respective link time slots tla and ~ -
tlb are excluded. Such a rule for phase allotment, however,
` raises the congestion risk. Another method for avoiding a
write - read collision ls shown by Fig. 3 i.e., in the word
memories in general, Writing is allowed only in the first half ~ -
of the phases and reading only in the second half.
In the switching example of Figs. 2 and 3 having the
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following parameters, frame periods F = 125 ~s, q = 2 = 32
link channels, m = 26 = 64 phases per frame period and with s =
213 = 8192 bus channels, write - read collision is avoided in
the word memories Wa, Wb by means of write and read command
pulses obtained on outputs ~ 1 and ~ 2 of the timing generator
TG. It is assumed that on the inward link La the channel which
is determined by means of the channel index number za = 6 is
switched to a channel determined by means of an arbitrary index
zb on the outward link Lb and that the computer for this connec-
tion has selected the phase determined by means of the phasenumbers y = 11 and y = 12 and the bus time slot with the length
T2 determined by means of the time index number x = 125 within
said phase with the phase number y = 11.
In Fig. 2, the timing generator TG is driven by an
~` oscillator, not shown, operating at a base frequency of 8000 x
8192 = 65536000 Hz. By means of this base frequency and as
a result of known frequency division and time displacements
on the outputs of the timing generator, there is obtained
according to Fig. 3 the following pulse trains: On the output
~, timing pulses are obtained synchronously with the base
frequency for controlling the time counters TCa, TCb of the high-
rate part. On the output ~ F, frame pulses are obtained by
means of dividing the base frequency in the ratio of 1:213.
As a result the link time slot, which is defined by means of
channel index z = 6, comprises the base frequency pulses denoted
by pulses 1281 to 1536 in Fig. 3. Pulses 1283 and 1343 of the
base frequency pulses are used to produce, by means of time -~
displacement, on the output ~ 1 the write command pulses for - -
the inward word memory and the read command pulses for the
outward word memory. Furthermore, the phases determined by means
of said phase numbers y = 11 and y - 12 comprise the pulses
1281 to 1408 and the pulses 1409 to 1536. Of these pulses, the
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pulses 1347 to 1407 and the pulses 1475 to 1535 are used to
produce, by means of time displacement, on the output ~ 2 the
read command pulses for the index memories Ia, Ib. The pulses
1406 and 1534 on the output ~ 3 are used as phase signals in
the high-rate part.
In the foregoing switching example, the writing in the
inward memory element group defined by means of channel index
za = 6 is finished at the pulse 1343. Within said phase with
the phase number y = 11 at the pulse 1347, the read operations
of the index memories Ia and Ib are started. Accordingly, the
memory element group determined by means of za = 6 is accessed
by means of the decoder IDECa for reading. Moreover, there is
transferred in the phase signal pulse 1406 the respective PCM
; word via a word gate WGa to the inward buffer register Ra and
the time index number x = 125 via index gates IGa, IGb to the
inward and outward time counters TCa, TCb. According to Fig. 2
the time counters constitute counters counting backwards which
receive as start values the time index numbers 1 < x ~ 127. The
counting down operation is controlled by means of pulses received
20 from control gates CG, which pulses, except for said phase
signal pulses, consist of the base frequency pulses. In
coincidence with a zero-setting, reached as a result of
counting down, the counters emit activation pulses to sluice
. gates SGa, SGb associated with the respective link and connected
~ to the bus IH~. Consequently, by means of the time counters a
- time displacement is carried out. According to the switching
example, the phase signal pulse 1406 is displaced 125 base
: frequency pulses so that the sluice gates are activated during
the pulse 1531. The sluice-in gate SGa has its information
30 input connected to the output of the inward buffer register Ra,
and the sluice-out gate SGb has its output connected to the
input of the outward buffer register Rb so that the respective
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PCM word is transferred, in the bus time slot defined by means
of pulse 1531, from the inward to the outward buffer register.
Concurrently, in the outward index memory Ib within the
phase number y = 12 defined phase at the pulse 1475, the read
operation has begun as a result of which the memory element
group determined by means of channel index zb and arranged in
` the outward word memory Wb is activated for writing by means
of the index decoder IDECb. For outward switching, the
respective PCM word is trans~erred during the phase signal
pulse 1534 rom the bufer register Rb via a word gate WGb to
the word memory Wb. The PCM word is stored in the memory Wb
and is read out therefrom by means of a low-rate scanning
,
arrangement LRS during the link time slot which is allotted to
` ~ the channel index zb.
. In the above described example, the minimal switching
time of the system is obtained with zb = 7. In another switching
example, with za = zb = 6 in connection with the phase numbers
. .
y = 10 and y = 11, the maximal switching time of the system
is obtained. Due to the two time switchings, the maximal
,
~ 20 switching time constitutes two frame periods which is in agree-
:
ment with kno~n time-space-time systems.
The invention has been described hereinabove by
~
means of an application in an exchange which comprises n inward
and outward links with q information channels. It is, however,
~; obvious that the invention also relates to an exchange which
comprises na inward links with qa channels and nb outward
- links with qb channels. Besides the space and time switching,
, a change of the multiplex formation is also achieved, i.e. from
qa to qb link time slots within a frame period. In the most
general case, i.e. na ~ nb and qa ~ qb, an exchange is designed
principally for nb qb _ na qa. And, within a frame, it
~ must be possible to read all stored qa PCM words in an inward
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word memory and to write in an outward word memory all qb PCM
words switched to the channels of the associated link during
an allotted phase. The phase has to have a time length which,
at its maximum, is less than the link time slots defined due to
the qa and qb channels.
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