Note : Les descriptions sont présentées dans la langue officielle dans laquelle elles ont été soumises.
3070505
This invention relates to electronic timepieces with particular
reference to timepieces having multiple alarm channels.
Conventionally, in electronic alarm timepieces which provide facility
for di6play of the day as well as hours and minutes and seconds as well as
having plural alarm facilities, it has been necessary to provide different
control and settingcircuitry for the time keeping circuitry and for the
alarm clrcuits. Additionally, in alarm time pieces with multiple alarm
channels, problems have arisen in adequately identifying alarm channels
selected for setting,for indicating that alarm channel which has been set.
and subsequently,when an alarm operates,in indicating which of the channels
is responsible for the alarm.
The present disclo6ure meets these difficulties in an elegant and
6implified manner.
Specific embodiments of the invention will now be described having
reference to the accompanying drawings in which;
Figure 1 i8 a general block diagram of a multiple channel alarm
timepiece and,
Flgure 2 show6 a circuit diagram of a multiple channel alarm time-
plece of Figure 1 in more detail.
Referring now to rigure 1, a quartz 06cillator circuit 1 is input
to a divider 2 whose output at 1 Hz is input to an actual time seconds
! counter 3. Counter 3 feeds a minute6 counter 4, which in turn feeds an hours
counter 5. A days counter 6 follows the hours counter 5. Switch circuits 7,
8 and 9 are controlled by signals from setting control circuits 22, 23 and
24 respectively and constitute electronic transmission gates which connect
the inputs of their relative counters, either to the relevant preceding
counter or to the 1 Hz output of the divider 2. In this way, the counters
can be set by stepping at 1 Hz by operation of the appropriate setting
circuit 22, 23 or 24 for the minutes, hours and days counters respectively.
Alarm channels 1, 2 or 3 can be selected by operation of the respect-
ive channel select circuits 25, 26 or 27. Such operation simultaneously
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effects a display of the contents of the respectlve channel memories, which
are memory counters 16, 17 and 18 for minutes and 10, 11 and 12 for hou-s
for the channels 1, 2 and 3 respectively.
In the description which follows, reference will be made to the
setting of channel 1, for illustrative purposes. The function and operation
of alarm channels 2 or 3 are similar.
Memories 16 and 10 are first selected by operation of control circuit
25. Setting of the alarm hours for channel 1 is performed by inputing a
1 Hz signal to the hours counter 10 by operation of circuit 23. Minutes
alarm setting for channel 1 is ~ffected in memory 16 by a control signal
from setting circuit 22. The AND circuits 19, 20, 21, 13, 14 and 15 at the
inputs of ~he respective me ries route the 1 Hz setting signal as required.
The function of the circuitry will now be described in more detail
with reference to Figure 2.
The setting circuits 22, 23 and 24 constitute a triple counter
comprising D type flip flops, however, whenever one of the channel selection
control circuits 25, 26, and 27 i8 operated the triple counter turns into a
dual counter by change over of the transmission gates 71 and 72 to yield
only hours and minutes setting signals. The channel selection circuits
25, 26 and 27 are also D-type flip-flops and all the outputs of the channel
selection control circuitg, when no channel selection and alarm setting is in
process and when actual time is being dlsplayed, rest at "O"
level. The output of the NOR circuit 30 is thus at "1", which causes the
setting circuits 22, 23 and 24 to be connected by the transmission gates
71 and 72 as a triple ring counter.
When SWl is pressed a first time it causes the circuit 22 to be
actuated. The second pressing actuates circuit 23. When the circuits are
connected as a triple counter,the circuit 24 is actuated by a third pressing
of SWl. A fourth pressing actuates circuit 22 again and the se~uence can be
3~ repeated. If, however, circuits 22, 23 and 24 are connected as a dual
counter, the third pressing of SWl actuates circuit 22, circuit 24 being
omitted from the sequence.
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The operation of alarm channel display will now be described in which
the selected channel for setting is indicated on a liquid crystal unit as a
flashing display. Only channel 1 will be described. The operation of the
other channels is similar.
The pulse signal produced by a single pressing of channel selection
switch SW3 acts as an actuating ~ee~ signal for the channel selection
control circuit 25 and this is input at "1" level, so that output ~ of the
channel selection control circuit 25 becomes "1" and the contents of the
channel 1 memories 16 and 10 are displayed by means not shown. The output
of NOR circuit 30 changes from "1" to "0" level by virtue of the "1" output
of circult 25, setting circuits 22, 23 and 24 become connected as a dual
counter by operation of the transmission gates 71 and 72. A switch SW2 is a
reset switch for circuits 22, 23 and 24 and also acts as a safety switch.
When switch SW2 is on, actual time, days, hours and minutes are displayed on
the tlme display unit by means not shown.
The output O of circuit 25 at "1" level is also input to a NAND
~circuit 31. A 1 Hz signal which is output of the dividing circuit 2 is also
lnput to NAND 31. The output of NA~D 31 is thus also a 1 Hz signal. Since
the inputs of NAND circuits 32 and 33 connected to respective selection
circuits 26 and 27 are "0", no output is developed by NAND 32 and 33. The
output of NAND 31 is input to NOR circuit 34, which will produce a 1 Hz
signal output by inverting, since the other input of NOR 34 is at "O" (as
will be described later). This 1 Hz signal is then input to the channel
display driver 41 of a liquid crystal display.
Each channel display drlver 41, 42 and 43 comprises two AND-circuits,
one inverter and one NOR-circuit. Thus, the correct and opposite phase
signals,with respect to common electrode 44, are present once per second
as output of the NOR circuit 39 and are applied to display segment electrode
Sl, of a liquid crystal display. Accordingly, the display segment Sl
flashes on and off once per second. No display appears on the other channel
display segments S2 and S3. A 32 Hz output from the divider circuit 2 is
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applied to the common electrode 44, and also to AND 37 and 38.
Selection of a channel for alarm setting therefore produces a
flashing display indicating that channel. The setting process is terminated
by operation of switch SW2.
When the time counting circuitry (actual minutes and hours) reaches
coincidence with the setting in one of the alarm memories,the relevant
dlsplay for that alarm is caused to flash. This operation will now be
described.
Reset flip-flop circuits 80, 81 and 82 for alarm channels 1, 2 and
3 respectively, memorize the presence or absence of a setting in the channel
concerned. These circuits are respectively connected to NOR circuits 61,
63 and 67, OR-circuits 64, 68 and 69, and input AND circuits 62, 65 and 66.
For simplicity, only the operation of channel 1 will be described, the
others are similar.
When the timepiece is not in the process of being set (the normal
condition), ~afety switch SW2 is on, and, since neither of 25, 26 or 27 is
selected, the inputs to NOR 30 are "0". The output of NAND 70 thus is "0".
If there is no setting in the channel l, me ries 16, 17, the R-S flip-flop
circult 80, which is connected to the memories 16, 17~by means not shown,is
in reset status. The output of NOk 55 is thus "1" and NOR circuit 61
outputs "0". This "0" is one input of OR 64. The other input of OR 64 is
the output of ~ND 62,whose inputs in turn are a 1 Hz signal from the divider
2, the output of a NOR~circuit 52, which constitutes an R-S flip-flop with a
NOR circuit 51, and a third input from the reset line Rl of circuit 80. This
line Rl carries a "O" signal at this point and thus the output of Al~D 62 is
"0". There is thus no output from OR 64 and Sl does not display. This
situation pertalns, whether or not there is a coincidence detected between
the alarm setting of one of the other channels and the actual time. Such a
coincidence detected by coincidence circuit 50 will input a "1" to R-S flip-
flop 51, 52 resulting in a "1" output to AND 62. ~he "0" on line Rl, however,
blocks AND 62.
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By contrast, when there is a setting in memories 16, 1~ of channel 1,
the flip-flop 80 is in set condition. (The clock pulse used for setting the
channel 1 me ries was also input to the set-input terminal Sl of flip-flop
80 by connecting means not shown). The output of NOR 55 thus is "O", indi-
catlng the presence of a memory setting and accordingly, the output of OR
61 becomes "1" (output of NAND 70 is "O") and OR 64 passes this as a "1"
input to NOR 34. The output of NOR 34 is thus held at "O" and a steady
display appears on Sl.
Thus, the presence of an alarm setting in any of the alarm memories
will indicate a steady display for that respective channel or channels.
When now coincidence is detected between actual time and the setting
of one of the channels, coincidence circuit 50 outputs as "1", which appears
at the output of NOR 52 also as a "1'l. By means not shown, this coincidence
signal resets the alarm memories responsible for the coincidence, and the
reset signal also appears as a "1" on line Rl for circuit 80. The reset
causes ~he output of NOR 55 to become "1" and the output of NOR 61 becomes
"O". In consequence, the steady display of Sl is removed. Since, however,
the reset input of NOR 56 is also an input bf AND 62, this AND 62 is now
ensbled to produce a 1 Hz signal output, because the input from NOR 52 is
also "1". This signal is passed by OR 64 and appears at the output of NOR 34.
The segment Sl thus flashes on and off once per second.
The length of time that the flashing display continues is determined
by an input to NOR 52 from the seconds counter 3 which includes a latch
circuit and which outputs a "1" at a suitable time interval after the onset
of a coincidence (such coincidences are initiated only at the start of
any minute of actual time). The "1" input to NOR 52 outputs a "O" which
blocks AND 62 and shuts off the flashing display drive.
The alarm signal "1" on the output of NOR 52 is also used to sound
an audible alarm by being fed to a NAND 53 which drives on alarm buzzer 100
through an inverter 54 and suitable transistor drive means. Comparatively,
higher frequency and lower frequency (16 Hz) signals from divider 2 are
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also fed to NAND 53 for proper drive appropriately matching the buzzer
characteristics.
It can thus be seen that the timepiece described has a plurality of
alarm channels and will give the normal read-out of the actual time. When
an alarm channel i8 selected for setting the contents of the mémories of
that alarm channel are shown on the time display and a separate display
flashes to show the channel concerned. After setting, when the timepiece
i8 in normal condition showing actual time, the display for the channel
which has been set, remains steadily in display condition. When the alarm
operates, an audible alarm sounds and the channel display for the channel t
which has initiated the alarm, flashes. No flashing occurs for any channel
di6play not responsible for the alarm, and no display occurs for any channel
which has not been set.
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