Note : Les descriptions sont présentées dans la langue officielle dans laquelle elles ont été soumises.
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This invention relates to apparatus ~or providing logic circuits as
logic gates to perfo~n logical functions in combinational and sequential digital
logic systems.
This application is a division of our Canadian patent application
Serial No 233,294 filed August 12, 1975.
The advent of large scale integration has mearlt that monolithic in-
tegrated circuits are becoming available with more and more digital system
functions provided therein to the point that substantial portions or all of a
digikal system are provided on a single chip. This increase in functional
density and so in circuit density in a monolithic integrated circuit has sev~
eral advantages. Substantial econo~ies are realized in reduced assembly cost,
etc. Improved reliability results because fewer interconnections need to be
made among the devices making up the system. There is an increase in the rap-
idity of operation since signals which must be transmitted in the system can
be transmitted over small distances.
These advantages and others motivate the desire to increase the
number of logic gates in a monolithic integrated circuit device to further in-
crease the logic function density in such a device. ~dditionally, to accomplish
more rapidly *he logic functions to be performed to thus impr~ve the digital
system capabilities, increasing the rapidity of operation of the logic gates
used in a monolithic integrated circuit device is also very desirable. Yet,
both increases in circuit density and in the rapidity of circuit switching
operations tend to also increase the power dissipated in the monolithic inte-
grated circuit device and so the method chosen to re&ch these two goals must
also provide for achieving a sufficiently low power dissipation if a viable
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monolithic integrated circlut device is to be realized.
Currently, the need for rapidly operating digital monolithic inte-
grated circuit devices is metlmost commonly by transistor-transistor logic
circuits (TTL), particularly Schottky-clamped TTL, and emitter-coupled logic
(ECL). The logic gates provided in these logic families tend to use on the
average more than one transistor per logic function accomplished~ Use of one
transistor per basic logical function would be quite desirable since the use
of further transistors tends to require more space in a monolithic integrated
circuit, tends to slow operation of the logic gate and tends to increase power
consumption.
There have been attempts to develop new logic circuits to improve on
the foregoing logic circuit families and to develop new logic Pamilies. Among
these is a logic circuit shown in U.S. Paten~ 3,769~524 `to ~athews which
teaches use of a NOR gate to perform logical functions. The circuitry shown
in this patent teaches a somewhat simplified logic gate requiring relatively
little power but stiIl shows use of more than one transistor on the average in
achieving the NOR logic function pro~ided.
The present inven~ion uses either multiple base or multiple emitter
bipolar transistors or both to provide a logic family capable o~ accomplishing
a basic logical function with the use of one transistor. Use of such transis-
tors to accomplish a basic logical function per transistor used conserves the
number of circuit components required and~ when provided in a monolithic in-
tegrated circuit, substantial savings in space used ~nd improvements in switch-
ing rapidity also ensue. Both of these latter gains are due again to the use -~
of a single transistor to perform the logic function involvedl Further~ these
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circuits in monolithic integrated circuit form facilitate logic
gate layouts therein due to the convenient logic gate inter-
connections permitted. Also, the logic family of the present
invention allows connection to logic gates. in the TTL and ECL
logic families ~ith little difficulty and without requiring
substantial additional circuitr~.
Thus, in accordance with one. aspect of the present
invention there is pro~ided a circui.t for per~orming logical
functions including a NOR function, said circuit comprising: a
first gate circuit compris~ng: a ~ipolar transistor having a
first gate collector, a fi.rst gate'emi.tter and a plurality of
first gate bases therei:n, said ~i.rs~t gate hases bei.ng inputs to
receive signals from sources of slgnals; a fixst resistor con- . .
nected between s:aid first gate emitte~ and a firs.t terminal means
adapted for connection to a voltage source; and a second
resistor connected between said first gate collector and a
second ter~inal means adapted for connection to a voltage source,
whereby a logic gate circuit capable of performing said NOR
function is provided.
In accordance ~ith another aspect of the invention
there is provided a monolithic integrated circuit provided in a
semi~conductor materi.al for performing logical functions includ-
ing a NOR functi.on, said integxated circuit comprising: a
plurality of isolated regions in said semi-conductor material ,-
each of a ~irst conductiYity type'i.ncluding a first isolated
region; a fi.rs~ hase region of a second conductiYity type located .:
entirely within said fi,rst isolated region, thexe being a first .:
base juncti.on be~ween said first base regi.on and ~aid first
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isolated region; a first emitter region of said ~irst conductiv-
ity type located entirely wi-thin said first base region; a
plurality of ohmic base contacts each made to a base region
located entirely within said second isolated region and made by
base interconnection lead means, said base interconnection lead
means being capable of transmitting siynals :Erom a source,
including a first base contact made to said first base region; an
ohmic first collector contact made to said first isolated region;
an ohmic first emitter cvntact made to said first emitter region;
a first resistive means connecting said first collector contact
and a first voltage supply interconnection lead means adapted ~.
for energization by a voltage source; and a second resistive
means connecting said first emitter contact and a second voltage
supply interconnection lead means adapted for energi~ation by ~
voltage source, ~hereby an integrated circuit logic gate capable
of performing said NOR function is provided.
The invention will now-be further des.cribed in
conjunction with the accompanying dra,~ings, in which:
Figure 1 shows an electrical schematic di.agram of a
portion of the present invention, a NOR gate;
Figure 2 shows ~n electrical schemati.c of a portion
of the present invention, a NOR gate;
Figure 3 shows an electrical schematic o~ a portion o~
the present invention, and AND gate;
Fi~ure 4 shows an electrical schematic of a portion '~
of the present invention, and AND gate;
Figure 5 shows an electrical sche~ati.c o~ a logic
circuit of several stages using logi.c gates o~ the pxe5ent
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invention;
Figure 6 shows an electrical schematic of a logic
circuit of several stages using logic gates of the present
invention plus certain other logic
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gates;
Figure 7 shows a monolithic integrated circuit layout of a logic
gate of the present invention;
Figure 8 shows a monolithic integrated circuit layout of a logic
gate of the present invention; and
Figure 9 shows a monolithic integrated circuit layout of a logic
ga~e of the present invention.
Some aspects of the disclosed invention are claimed in the afore-
mentioned parent application 233,2~4.
Figure 1 shows a circuit diagram for a logic gate for per~orming the
NO~ logical function which is constructed of a multiple base and multiple
e~itter bipolar transistor, 10~ wherein an emitter is formed in each of several
separate bases commonly provided in a collector region with these emitters in-
ternally shorted. Thus, effectively, a multiple base transistor is pro~idedO
A monolithic integrated circuit layout for a NOR gate including such a tran-
sistor is shown in a later drawing and the layout there is indicative of the
construction of a discrete transistor having multiple bases and multiple emit-
ters ~lso
Transistor 10 has three bases~ bases 11~ 12 and 13, and three cor-
responding emitters, emitters 14~ 15 and 16. Bases 11,112 and 13 serve as in-
puts to receive logic signals from a source of such signals such as another
logic gate preceding the gate of Figure 1.
An emitter resistor, 17, connected between the low value voltage
supply terminal3 sho~n in Figure 1 as ground, and the emitter of transistor 10
is used to reduce "current-hogging" ~hich occurs between the various base and
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emitter combinations present :in transistor ~0~ i.e~ base-emit~er combination
11 and 14, base-emitter combination 12 and 15, and base-emitt~r combination 13
and 16. The use of resistor 17 reduces the "current-hogging" problem which
plagued the old DCTL logic family but without the e~cessive use of space re-
quired by another solution to the DCTL problem which became the RrL logic
family.
A load resistor, 18, connected between a te~minal adapted for con-
nection to the high value voltage supply and the collector of transistor 10,
is used to provide a voltage swing at the NOR gate output5 19g in response to
input signals at bases 119 12 or 13. Transistor 10 is shown as a Schottky
clamped transistor, or Schottly transistor, which has a Schottl~y diode con-
nected from each base to the collector (cathode connected to the collector) to
keep transistor 10 out of saturation so as to increase its switching rapidity
The logic gate of Figure 1 provides a NOR logic function between the
base inputs 11 through 13 and output 19. If base 11~ 12 or 13 is in the high
voltage value logic state, then transistor lO is on and output 19 is in the
low voltage value logic state. With bases 11-13 all in the low state, tran-
sistor 10 is in the off condition and a load on output 19 has voltage and cur-
rent applied to it through load resistor 18, and output 19 is in the high state.
As is well known~ any Boolean logic function may be realized by the use of NOR
gates alone.
This NOR gate has many advantages when compared with the gates of
the TT~ and ECL logic families There are advantages also when compared with
the NOR gate taught in the above referenced papent. The primary advantages
follow from the use of a single transistor to realize the entire N~R logic
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function, i.e. a single collector region to contain the other transistor por-
tions. The use of a single active device reduces space used in a monolithic
integrated circuit in which the logic gate is to be provided to improve cir-
cuit density as compared with the use~of two or more transistors to realize a
logic function. The reduced size of the logic gate also means more rapid
operation of the gate in switching from the low state to the high state or
vice versa~ in either monolithic integrated circuits or discrete devices. This
is because the capacitance between the active devices and the s~bstrate
materials, usually silicon, is reduced by reducing the space taken up by what-
ever active devices are required to realize the logic functions.
E~lrther~ the NOR gate circuit of Figure 1 can be operated at a sub-
stantially lower supply voltage than can either the standard TTL NAND gate or
the standard ECL OR/NOR gateO This is due to the former circuit having but
one VBE voltage drop occurring between the high voltage supply terminal and
the low voltage supply terminal. The NOR gate cirucit o~ ~igure 1 could oper~
ate at a supply voltage just exceeding 1 VBE~ but speed and power control
dictate a somewhat higher voltage in practice. Use of a second type of gate
circuit in the logic fæmily of the present invention, as set out below~ re-
quires a supply voltage minimum of approximately 12 VBE, but again speed and
power control lead to use of a some~hat higher voltage in practice.
The result of using a lower supply voltage compared to that used by
another logic family, generally, is, first a lower voltage swing results which
can increase the speed of the circuit since capacitances in the circuit need
not be charged over as large a voltage swing. This potential improvement in
operational rapidity may be nullified by voltage clamping due to the suceeeding
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circuit connected to the output. Such clamping does occur among members of
the logic family of the present invention as set out below. Secondly, the
rapidity of operation of a logic gate is also increased, for a given gate power,
~hen the voltage supplied to it is reduced since the current drive to charge
the circuit capacitances can be increased without exceeding the given gate
power.
A typical monolithic integrated circuit version of the logic circuit
of Figure 1 operated at a 2 volt supply voltage will have a power dissipation
of 4 mw per gate and an average gate delay of less than a nanosecond. Resistor
17 in such a gate would be approximately 650 ohms while resistor 17 would be
approximately 25 to 50 ohms.
Figure 2 shows the circuit diagram of another logic gate performing
the NOR logical function using a multiple base, bipolar Schottky transistor3
20, having the multiple bases formed in a collector region common to them all
and having a single emitter common to the multiple bases. The leads from the
multiple bases are labeled 21, 22 and 23. Again, a resistor, 24, is used to
limit "current-hogging'l and a load resistor, 257 is used to provide a voltage
swing at the output of the log c gate, 26.
The advantages of the NOR gate circ~it shown in Figure 2 are those
o~ the NOR gate circuit shown in ~igure 1, but a transistor of even smaller
physical size can be realized where but one emitter is used. ~or this kind
of a transistor it is difficult to provide very many bases in the one tran-
sistor, i.e. a substantial fan-in, and some interaction occurs between the
bases which must be controlled if the transistor is to be effectively a
multiple base transistor. An example indicating a technique of provid;ng a
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somewhat similar transistor is shown in U.S. Patent 3,569,800 to Collins~
As stated above, a NOR gate can perform all of the Boolean logic
functions without any other type of logic gate being required. However, a
logic gate performing another basic logical function can be useful if that
particular logic function happens to be required in a digital system since
only one logic gate is then needed to achieve this function rather than a com-
bination of the preceding NOR gates Hence~ a furthar and compatible member
of the logic ~amily of the present invention has been found to be quite use-
ful and is shown in Figure 3, anl AND gate This gate~ in addition, has some
further advantages which will be set out below.
The logic gate shown in Figure 3 to perform the AND logi~al function
does so using a multiple emitter, bipolar transistor, 30, which has its mul-
tiple emitters formed in a single base region which in turn is formed in a col-
lector region. The multiple emitters are labeled 31, 32 ~nd 33. ~mitter 31
is shorted internally to the base of transistor 30. Current is supplied to
transistor 30 through a base resistor, 34~ connected to a terminal adapted for
connection to a voltage supply.
The AND logic function occurs between the inputsg which are emitters
32 and 33, and the output, 35, which is the collector lead of the transistor.
When either or both emitter 32 and emitter 33 are in the low state, transistor
30 is in the "on" condition such that output 35 is also in the low state. When
both emitter 32 and emitter 33 are in the high state, transistor 30 is in the
~off" conditlon ~actually transistor 30 is in the inverse transistor mode of
operation) and the load to which output 35 is connected receives current and
voltage through base resistor 34 and the base~colleotor junction of transis*or
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30~ and output 35 is in the high state.
A difficulty with the NOR gates of the present invention described
above is the relatively limited fan-out when other NOR gates are used as loads.
This is due both to the "current-hogging" problem which exists to a degree even
with the use of the emitter resistors in these gates and to the limited amount
of current which these gatés can source. Use of AND gates of the Idnd shown
in Figure 3 as the only kind of loads for the output of one of the above NOR
gates can at least double the fan-out capabilities of the NOR gate. This im-
proved fan-out is due to the relatively little current that each of these AND
gates sinks i~ when atLleast one input emitter is in the high state and at
least one other input emitter is in the low state, or ii) when the logical AND
condition is satisfied with all input emitters in the high state resulting in
transistor 30 of Figure 3 going into the "off" condition, or as pointed out
above, into the inverse mode of operation.
In the inverse mode of operation9 the designed emitters of transistor
30 are oparated as collectors and the designed collector ~f transistor 30 is
operated as an emitter~ such that the preceding~ i~e. driving~ logic stage
becomes the collector load for the in~ersely operated transistor 30. Each AND
gate, connected as a load to the output of a dri~ing NOR circuit, which has its
AND logical function satisified~ and so has the transistor therein operating
inversely, draws an in~erse collector current from the NOR gate A current is
also drawn in the other case i.e. input emitters in opposite states, due to
the always ~orward biased collector-base junction (forward biased in nearly all
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circumstances) facilitating passing of current between those emitters in op_
posite states. These are the eurrents to be kept low to achie~e a substantial
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fan-out of AND gatc circuits loading the NOR gate.
To keep these currents low which the transistor in an AND gate is
dra~ing through input emitters in the high state from the preceding NOR gate
requires either that the transistor itself draw little current through these
emitters or that the current drawn be supplied primarily from some source other
than the preceding NOR gate or both. Shorting emitter 31 to the base of tran-
sistor 30 accomplishes supplying current to high state emitters in a manner
such that the transistor 30 has a source of high state emitter current other
than the preceding logic state~
The current otherwise drawn through those emitters of transistor 30
which are in the high state is supplied instead through base resistor 34 and
the short from the base to emitter 31. ~y making the effective area of emitter
31 larger than the area of emitters 32 and 33, nearly all of the current re-
quired by transistor 30 with one or more emitters in the high state will be
supplied via base resistor 34 and emitter 31. Thus the AND gate of Figure 3
provides a very substantial advantage in the logic family of the present inven-
tisn by allowing an increased fan-out from a NOR gate~
This use of a bipolar transistor having an emitter shorted to a base
therein in a non-inverting switching operation (where an input, in switching a
transistor from on to another condition, and ~ice versa, goes to the same
logic state as the output, i.eO both switch to the high state or both switch
to the low state), as in the AND gate of Figure 3, is to be contrasted with
the use of ~n emitter shorted to the base in a transistor which is used in in-
verted switching operations (where an input, in switching a transistor from on
to another condition, and vice versag goes to the opposite logic state of
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the output~ i.e. the input goes low as the output goes high and vice versa).
When used in inverting switching operation transistors, ~he shorting of an
emitter to the base is for the entirely different purpose of reducing charge
storage, and so deep saturation, to speed up the switohing rapidity of the
transistor used in the inverting switching operation. An example of such use
can be found in U.S Patent 3,233,125 to Buie.
Another very important advantage of the AND gate of Figure 3 is the
extreme rapidity of operation which it can aohieve, a rapidity exceeding that
of the preceding NO~ gate. This high rapidity of operation is achieYed with-
~
out use of a Schottky transistor as is noted by use of the standard symbol for
transistor 30 in Figure 3 rather than a Schottky transistor symbol. This
rapidity ~ollows directly from the use of transistor 30 in a non-inverting
switching mode, as noted above, such that whatever saturation occurs acts to
aid the switching rapidity of the transistor rather than slow it, thus obviating
the need for connecting a Schottky diode from the base to the collector of the
transistor. This can be understood by noting that the effective Miller capa-
citance in the transistor acts to slow the rapidity of switching for a tran-
sistor operating in the in~erting switching mode, but acts to aid the rapidity
of switching in a transistor operating in a non-inverting switching mode.
~0 A further advantage in the use of the AND gate is that it can be
smaller than the NO~ gate set out above as a result of only needing to form
multiple emitters in a single base region in transistor 30 with no special base
region geometry required. This tends to reduoe the si~e of transistor 30 as
compared to transistors effectively having multiple bases and, as will be
seen below, the use of multiple emitters also aids in reducing the layout room
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required in a monolithic integrated circuit by facilitating interconnection
between logic gates.
Figure 4 shows an improved version of the AND gate of Figure 3, im-
proved by the addition of a collector resistor~ 36. This collector resistor
primarily supplies the drive current to the load connected to the output of
the AND gat,e of Figure 4 when the logical AND func-tion is satisfied at khe in-
puts resulting in transistor 30 being in t'he "off" condition, iOe. operating
in the inverse mode. This current must be supplied through the base resistor
34 and the forward biased collector junction of transistor 30 in Figure 3. In
Figure 4~ base resistor 34 can be of a much larger value since most of the
current supplied to the load o~ the logic gate in Figure 4 is supplied through
resistor 36.
Increasing base resistor 34 has a number of advantages including re-
ducing the inverse collector current drawn by transistor 30 when it is operat-
ing in the inverse mode and in reducing the variation in the current through
base resistor 34 due to chAnges in the supply voltage and in the VBE of tran-
sistor 30~ Such variations in the current in base resistor 34 lead to varia-
tions in the power consumed in the logic gate and its speed of operation,
Furtherg the parasitic PNP transistor~ occurring in the base and collectsr of
transistor 30 plus the substrate when this logic gate is fabricated in a mono-
lithic integrated circuit~ no longer affects the current drive to the load on
the logic gate of Figure 4 connected to output 35~ This is so since this cur-
rent drive is now supplied through collector resistor 36. Use of collector
resistor 36 also reduces the undesirablée current which is supplied through
the emitters of the AND gate to preceding logic gates in low logic states ~ -
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which are connected to those emitters of the AND gate.
Typical values for the resistors in Figure 4 are 5gOOO ohms for re-
sistor 34 and 650 ohms for resistor 36 when 2 volts are supplied at the volt-
age supply terminal to which resistors 34 and 36 are connected.
Turning now to Figure 5g a four stage logic circuit is shown using
the logic gates described above, one logic gate per stage~ to show some ~ypi-
cal logic gate combinations. The four logic gates are labeled with a first
gate, 50~ being a NOR gate~ a second gate~ 51, being an AND gate, a third gate,
52, being a NOR gate and a fourth gate7 53, being a NOR gate also. Each of
these logic gates are marked off from one another by dotted lines 54, 55 and
56. The logic gates shown in Figure 5 are the NOR gate of Figure 1 and the
AND gate of Figure 4, although the gates of Figures 2 and 3 could just as well
have been substituted, respectively.
The only difference appearing between the gates used in Figure 5 and
the gates shown in Figures 1 and 4 is the omission of the collector resistor
in NOR gate 50 when compared with the NOR gate of Figure 1 Since NOR gate 50
need only sink current from AND gate 51 there is no need for a collectcr re-
sistor to supply any current to AN~ gate 51 and so the collector resistor may
be omitted to conserve space and power in a monolithic integrated circuit. As
set out above, the power supplied to AND gate 51 and its load is obtained
through the base and collector resistors ~herein.
This combination of logic gates sh~wn in Figure 5 allows estima~ing
what the high and low logic state voltage levels will be for the logic gates
in Figures 1 and 4 when these same gates are interco~nected with one another
and thereby serve as loads on the outputs of one another. First, consider ~OR
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gates 52 and 53. When NOR gate 52 has its ou~put in the low state~ i.e. when
the transistor in NOR gate 52 is in the on condition, clearly the transistor
of NOR gate 53 is in the off condition. In this situation the voltage at the
output of NOR gate 52, the same voltage obviously as that at the pertinent in-
put of NOR gate 53, is the VBE drop of the transistor in NOR gate 52 minus the
forward voltage drop of the Schottky diode in NOR gate 52, i.e. (VBE - Vs h)~
ingnoring the small drop across the relatively small emitter resistor of N~R
gate 52.
On the other hand~ when the transistor of NOR gate 52 is in the off
condition the voltage at the output of NOR gate 529 again the voltage at the
pertinent input of NOR gate 535 is clamped at the V~E drop of NOR gate 53~
ignoring the small drop across the relatively small emitter resistor of NOR
gate 53. Thus, the voltage at the output of NOR gate 52 and the input of NOR
ga~e 53 swings between the V~E of NOR gate 53 when the N~R gate 52 is in the
high state and (VBE - VsCh) of NOR gate 52 when NO~ gate 52 is in the low state.
When~the transistor ofdAND gate 51 is in the "off" condition, i.e.
when operating in the inverse mode, the output of AND gate 51 is in the high
state and the voltage at its output~ or the voltage at the input of NOR gate
$2, is the VBE drop of NOR gate 52 ignoring the drop across the emitter resistor
of that gate. In this situation the input of AND gate 51 (the output of NOR
gate 50 also) is also in the high state and analysis shows that the ~oltage
level at the juncture between these two gates is about one VBE drop just as it
would be if NO~ gate 50 were driving another ~QR gate.
When the transistor of NOR g~te 50 and the transistor of AND gate 51
are both in the on condit~on, the voltage at the juncture between these two
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gates is in the low state and will again by the ~VBE - Vs h) drop of the
transistor of NOR gate 50. The voltage at the connection between AND gate 51
and NOR gate 52 will then be above the voltage at the juncture between gates
50 and 51 by the saturation voltage of the transistor of gate 51.
As mentioned above, the old ~CTL logic family was unsatisfactory be-
cause of the "current~hogging" problem associated therewith and that the ~rL
logic family evolved as a solution to this problem to provide a more usable
logic family. The Rr~ logic family, however, suffers from disadvantages of
its own due to the multiplicity of base resistors required for the logic
family. These base resistors increase the component count and take up addi-
tional space as well as slowing the operation of this logic family. Neverthe-
less, the standard RTL gate and ~ariants thereof have some useful properties
and these gates are compatible with the logic gates of the lo~ic family of the
present invention described in connection with Figures 1 through 4. Some
possibilities using RTL gates are shown in Figure 6.
Shown in Figure 6 is a NOR gate~ 60, driving two RrL logic gates
which also perform the NOR logical function, a gate 61 and a gate 62. RTL
gate 61 drives an AND gate, 63, while RTL gate 62 is an output logic gate in-
tended to drive a transmission line or some other kind of output device, to
supply sig~als to another monol;thic integrated circuit or to provide some oth-
er l;ke function. Another AND gate, 64, is shown dri~ing another input of RTL
gate 62. Each of these logic gates is marked off from one another by dotted
lines 65, 66 and 67.
The use of RTL gates 61 and 62 in the circuit of Figure 6 overcomes
a first restriction on the interconnection of logic gates of #he logic family
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of the present invention. That is when a NOR gate of the type shown in Figures
1 or 2 is used to drive a plurality of similar NOR gates in para]lel with one
another where one or more of this plurality of NOR gates has an AND gate con-
nected to its output in turn, a "curren~-hogging" problem arises between the
second stage plurality of NOR gates. Use of the RTL gates 61 and 62~ and more
as needed substituted in place of the second stage plurality of NOR gates of
the type shown in Figures 1 and 2, ~hen driven commonly by a NOR gate, solves
this "cur~ent-hogging" problem
A second restriction on the interconnection of logic gates of the
pressnt logic familyimight be noted at this ~oint, that being that an AND gate
is not to be connected to drive another AND gate if the desired Boolean logical
function is to be achieved. This is not a significant restric~ion~ however,
since there is no gain in realizing the desired Boolean logic function in this
manner as against operating a sin~le ~ND gate with the necessary number of in-
puts.
Use of an ~TL gate as an output has additional ad~antages beyond its -
already stated use in Figure 6 of sol~ing the "current~hogging" problem in the
circumstance shown therein. First, not using an emitter resistor in gate 62
allows the low state voltage level at the output to be a minimum since re-
moving this resistor removes any ~oltage drop thereacross, As an output logic
stage, this emitter drop may become ~uite substantial since an output gate
very often must sink a considerably larger current than an internal gate in
many logic circuits because of the different kinds of loads which an output
logic gate may be called upon to drive and~he different supply voltage levels
at which it may operate. The output logic gate transistor is usually a large
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transistor to handle this additional current.
Further~ achieving compatibility with a TTL circuit used as the load
for the RTL output logic gate can be accomplished without reducing the noise
margins of the TTL circuit if the output gate is operated from a 5 volt supply
rather than a 2 volt supply. This could be accomplished by connecting another
load resistor, 68, to the collector of RTL gate 62. The other end of resistor
68 would be connected in some manner to a S volt supply. If the 5 volt supply
were available in a monolithic integrated circuit, resistor 68 could be a
resistor provided therein. Otherwise, or in the case of discrete components,
resistor 68 could be an external resistor.
For the same reasons~ higher current loads and compatibility with
other logic families, an RTL gate may be used as an input gate to a logic cir-
cuit, in either a discrete or a monolithic integrated version. However, use
of RTL gates is to be avoided wherever possible since they do increase compon-
ent count, take more space in monolithic integrated circuits and slow the op-
eration of the digital circuit. Hence, the AND gates shown in Figures 3 and 4
are satis~actory input circuits and where special input conditlons need to be
met these AND gates will typically be used.
On the matter of compatibility with other logic families~ the A~D
gates and NOR gates of the logic family of the present invention shown in
Figures 1 through 4 when operated at 2 volts are compatible with TTL~ but with
a reduced noise margin. These logic gates are also compatible in this situa-
tion ~ith standard ECL circuits if the high voltage supply terminal is grounded
and the low voltage supply terminal is operated at a minus (~) 2 volts.
Full compatibility with standard TTL circuits~ including full noise
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margins, can be achi~ved in on~ manner with the logic g~t~s of the logic family
of the present invcntion, on a monolithic integrated circuit chip to monolithic
circuit chip basis, by forming a standard TTL gate at either the input, the
output, or both in the monolithic integrated circuit chips used and operating
the standard TTL gates at 5 volts. Other standard gates such as DTL operated
at 5 volts can be provided at the inputs or outputs of a monolithic integrated
circuit to again provide full compatibility. For that matter, however, the
gates of the logic family of the present invention can be operated at 5 volts
when they àre input or output gates to achieve this same compatîbility as in-
dicated above.
Figwres 7 and 8 are top views of two monolithic integrated circuit
versions of the NOR gates in the logic famil~ of the present invention~ both
views shown without metallization. Clearly, these versions can be adapted to
provide discrete multiple base transistors. The gate shown in Figure 7 cor-
responds ~o the logic gate circuit of ~igure 1. An isolating region~ 70~ is
shown surrounding an isolated region, 71. Emitter regions o~ n+-type con-
ductivity are provided to form transistor emitters, 72, contact regions~ 73,
and an emitter resistor, 74. All these regions are formed in a single n+
diffusion. Base regions of p-type conductivity are provided which include
transistor bases, 75~ and a region provided to isolate resistor 74, region 76.
These regions are provided in a single p diffusion. Isolating region 70 is
also of p-type conductivity and is a diffusion in an n-type epitaxial layer to
form n-type isolated region 71. That portion of isolated region 71 which ;
occurs more or less between the two contact dif~usions 73, that is the region
labeled 779 forms an epitaxial resistor.
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~ 3
Several ClltS are made in the masking and protective film~ typically
silicon dio~ide, f~rmed over the epitaxial layer to accomodate interconnection
leads to electrically connect the various aforesaid regions with one another
and with other regions to form circuits. These cuts are shown here to accept
a metalli~ation deposition or possibly to accept a doped polysilicon deposition
to form these interconnections. Other interconnection means are known in the
art, including diffused regions, which could also be used for interconnections.
Cuts 78 are placed to expose both the several bases 75 and the
portions of the isolateA region 71 across the p-n jl~ction formed between bases
75 and isolated region 71. Upon depositing metal in these cuts, a double con-
tact, one ohmic contact to a base 75 and one Schottky contact to the isolated
region 71~ is made for each of the bases 75 and an interconnection is simul-
taneously provided between these double contacts. This serres to form Schottky
diodes, with one connected from each base 75 to isolated region 71 serving as
a collector with the diode cathode connected to the isolated ~egion 71 to there-
by form a Schottky transistor.
Cuts 79 allow emitter contacts to be made which are all $o be inter-
connected to internally short emitters 72 to one another ~nd these shorted emit-
ters are further to be connected to emitter resistor 74 at cut 80, Emitter
resistor 74 corresponds to resistor 17 i~ Figure 1. Cut 81 allows the connec-
tion of emitter resistor 74 to ground. The deposition in cut 81 will short
the end of emitter resistor 74 to region 76. Region 76 is in contact with
ground through its intersecting isolating region 7Q.
Cut 82 is the collector contact and the interconnection lead here
becomes the output lead for the logic gate. Input leads are intended to extend
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from the m~tallization deposition in cuts 79. Cut 83 allows connecting to the
high level voltage value supply. The region 77 which forms the epitaxial re-
sistor corresponds to resistor 18 of ~igure 1.
The logic gate shown in Figure 7 is constructed using a standard
bipolar processing. This gate is formed in a typical epitaxial layer having
approximately a 4.5 micron thickness and a .35 ohm-cm resistivity. Buried
layers of the usual type are formed under po~tions of isolated region 71 using
standard processing.
The extreme compactness of the resulting logic gate which is achiev-
able is evident in Figure 7. The entire area taken up on the surface of a
monolithic integrated circuit chip would be less than 14 mils2. This allows
a very high logical function density and very rapid switching of the transistor,
there being sub-nanosecond average switching times possible if the construction
processes are chosen to yield suitably thin bases of a satisfactory resistivity.
Figure 8 shows a monolithic integrated circuit version of a two input
logic gate otherwise corresponding to the three input logic gate circuit dia-
gram of Figure 2. This monolithic integrated circuit again is formed using a
standard bipolar processing technique including use of a buried layer. An
isolating region~ 800, again surrounds an isolated region, 801~ which is formed
from an n-type epitaxial layer. Emitter regions are formed by an n~-type dif-
fusion and include a single transistor emitter~ 802, and a contact region, 803.
A p-type diffusion provides base regions which include a single transistor
base, 804, an emitter resistor, 805, and a collector resistor, 806.
Two features of this arrangement should be noted. First, the tran-
sistor base 804, while a single base region, is const~ucted so it operationally
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has essentially two portions, a first portion~ 807, and a second portion~ 808.
These portions are more or less isolated from one another by the location of
emitter 802 which leaves relatively small portions of base 804 joining base
portions 807 and 808. These joining portions therefore have a substantial
resistance so that base portions 807 and 808 act essentially as independent
bases with some resistive connection therebetween. The second feature to be
notéd is the ease by which "crossunders" are provided by resistors 805 and 806.
This is shown by the dotted-in interconnection leads which pass over these re-
sistor leads~ 809~ 810 and 811l Clearly, resistors 805 and 806 could be pro- -
vided by other means such as epitaxial resistors or by doped polysilicon de-
positions.
Several cuts are provided in the protective covering film provided
over the silicon of the epitaxial layer forming isolated region 801 for making
contacts for circuit interconnections via interconnection means such as metal-
liæation. These include emitter cut 812, double contact and interconnection
cuts 813 provided for making the transistor a Schottky transistor and for input
lead connections, a collector contact cut 814 and resistor contact cuts 815
Figure 9 shows the top view of a monolithic integrated circuit cor-
responding to the ~ND gate circuit of Figure 4, but with three inputs, con
structed by standard bipolar processing. Again~ no metallization or other in-
terconnection lead means are shown. As before~ a p-type isolating region, 900,
is diffused into an n-type epitaxial layer to form an isolated region, 901.
Emitter regions are formed by an n -type diffusion and include an enlarged em-
itter, 902, and input transistor emitters, 903, and contact regions, 904. A
p-type base diffusion region forms a transistor baseg 905.
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~ ~ 7 ~ 3
Once again several cuts have been made in the protective film pro-
vided over the silicon of the epitaxial layer forming isolated region 9ol to
pe~nit contact to the various aforesaid regions and others by mterconnection
means. Three emitter contact cuts, 906~ have b~en made for input connections.
A further emitter contact cut 907 has been made which extends beyond the en-
larged emitter 902 and into the base 905. A deposition in emitter cut 907 will
short this larger emitter to the base by fo~ming an ohmic contact to each and
interconnecting them to reduce the input emitter current drawn by the tran-
sistor when operating with one or more emitters in the high state as set out
above.
A collector contact cut, 908~ is provided for an output lead con-
nection. A high le~el voltage value supply contact cutg 909~ allows intercon-
nection to a terminal means adapted for energization by a ~oltage supply. A
resistor contact cut, 910~ is made to allow connection by interconnection means
to the collector through collector contact cut 908. That portion of the epi-
baxial~i layer between contact cuts 908 and 909~ i.e. the portion of isolated
region 901 which is labeled 911, serves as a base resistor corresponding to re-
sistor 34 in Figure 4 That portion of isolated region 901 which is labeled
912 serves as a collector resistor corresponding to resistor 36 in Figure 4.
Again, the compactness of the logic gate shown in Figure 9 is evi-
dent. Further, the dotted lines~ 913, 914 and 915 representing interconnection
leads, can jointly connect se~eral of these AND gates that are similarly orien-
ted ~nd positioned in parallel without any interference with other intercon-
nection lead me~s. This is often done where the 90intly connec~ed gates are
part of a fan-out from a col~non dri~ing gate. Lessconvenientjoint interconnection
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possibilities exist for the ga~e shown in Figure 8 since the special design
required for the base region to operate effectively as several bases may limit
the placement of the contact cuts 813 to some extent possibly causing some in-
convenience. Connecting the logic gate inputs in ~igure 7~ jointly or other-
wise, can become even more difficult than for the logic gate of Figure 8 since
interconnection means must be provided between each emitter to short them in-
ternally which ~ill tend to interfere with input lead connections.
Dotted interconnection lead 916 in ~igure 9 also illustrates the
possibilities of running an interconnection lead over those portions of the
logic gate containing the resistive members to effect a 'tcrossunder". Clearly~
these resistive members could be provided by other means such as resistors made
from base regions as in Figure 8, pinch resistors~ or by doped polysilicon.
Use of one of these other means may facilitate the f`ormation of "crossunders"
or solve other layout problems. Use of e~pitaxial resistors, however, tends
to save space and to reduce parasitic capacitance in monolithic integrated cir-
cuits to improve operational rapidity.
The compactness of a digital logic system constructed in a monolithic
integrated circuit using the NOR gates and the AND gates of Figures 7, 8 and 9
or close "variants" thereof follows from the compactness of these gates indivi-
dually, as described above, and from the layout convenience possible in an in-
tegrated circuit chip allowed by the use of these g~tes due to the geometry
thereof and the possibilities they provide for making l'crossunders" easily,
again as described above. Further~ the availability of two comparably perform-
ing but functionally different logic gate types, each providing a different
basic logical function9 and again, the layout convenience, allows a considerable
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ao~ 3
amo~lt of fl~Yibility in providing a digital system in ~ monolithic integrated
circlut.
In addition to the compactness, convenience and flexibility is the
high performance available by use of the abo~e described gates. The availabil-
ity of average s~itching delays measured in the sub-nanosecond time scale and
the short distances possible ~etween the adjacent logic gates in monolithic
circuit chip me~ns a very rapid performance can be obtained. A computer simula-
tion of the NOR gate of the present logic family~ a standard ECL gate and a
standard Schottky clamped TTL gate~ each having two inputs, was made. Each of
these gates was taken as an internal gate for a digital logic monolithic inte-
grated circuit and each was simulated using the same component device models,
The results showed the average switching delay of the NOR gate of the logic
family of the present invention to be approximately half of the shortest aver-
age delay of the other two logic family gates, that being the ECL logic family
NOR gate.
That a certain arbitrariness must enter into any such computer simula-
tion and that several other facto~s~a~fect~.~he average delay time of a gate
which c~nnot easily or reasonably be included in the simulation model which
can reduce accuracy to a small extent must be admitted, nevertheless~ such a
substantial factor of improvement in switching delay as note.d above indicates
that significant advantages are available in the logic family of the present
invention. As a check on the impact of some of the limitations not accounted
for in the computer simulation which might restrict the validity of the results
of the computer simulation, a comparison has been made of a digital logic sys-
tem actual~y provided in a monolithic integrated circuit chip in each of the
, . .. ., . . , . j.,, . .,, ~ , .. .. .. . . . . .. . ... . . .
fi~3
foregoing logic families. The digital system chosen is an arithmetic logic
unit (ALU) which appears to be about the present state of the art in providing
a digital system on a chip for each of the commercially a~ailable logic families
mentioned above, TTL and ECL. The logic diagrams for each of these arithmetic
logic units were quite compar~ble.
Upon comparing, the A1U constructed from the logic fa~ily of the
present invention took considerably less chip area and had a speed-power-area
prodllct~ as a rough ~igure of merit~ which was approximately half of the smaller
product achieved by the next best ALU, this being the one that was constructed
by gates in the ECL logic family. This result was achieved by use of transis~
tors in the ALU constructed from gates of the logic family of the present in-
vention having an fT which approximately only half that of the transistor
having the highest fT used in either ALU constructed from gates in the other
two logic families in the comparison.
- -26-
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