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Sommaire du brevet 1081862 

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Disponibilité de l'Abrégé et des Revendications

L'apparition de différences dans le texte et l'image des Revendications et de l'Abrégé dépend du moment auquel le document est publié. Les textes des Revendications et de l'Abrégé sont affichés :

  • lorsque la demande peut être examinée par le public;
  • lorsque le brevet est émis (délivrance).
(12) Brevet: (11) CA 1081862
(21) Numéro de la demande: 1081862
(54) Titre français: CELLULE LOGIQUE BISTABLE
(54) Titre anglais: BISTABLE LOGIC ELEMENT
Statut: Durée expirée - après l'octroi
Données bibliographiques
(51) Classification internationale des brevets (CIB):
  • H1L 29/70 (2006.01)
  • H1L 27/02 (2006.01)
  • H1L 27/07 (2006.01)
  • H3K 19/091 (2006.01)
(72) Inventeurs :
  • PHAM, NGU T. (France)
(73) Titulaires :
(71) Demandeurs :
(74) Agent: ROBIC, ROBIC & ASSOCIES/ASSOCIATES
(74) Co-agent:
(45) Délivré: 1980-07-15
(22) Date de dépôt: 1977-02-11
Licence disponible: S.O.
Cédé au domaine public: S.O.
(25) Langue des documents déposés: Anglais

Traité de coopération en matière de brevets (PCT): Non

(30) Données de priorité de la demande:
Numéro de la demande Pays / territoire Date
76 04082 (France) 1976-02-13

Abrégés

Abrégé anglais


A BISTABLE LOGIC ELEMENT
Abstract of the Disclosure
A bistable logic element comprises a pnpn or an npnp
structure with a first transistor having a collector in
two parts of which one surrounds the transistor. It addi-
tionally comprises leakage and bias resistances integrated
on the substrate.

Revendications

Note : Les revendications sont présentées dans la langue officielle dans laquelle elles ont été soumises.


The embodiments of the invention in which an exclusive
property or privilege is claimed are defined as follows:
1. A bistable logic element comprising a first and a
second complementary transistor, integrated into a first zone
of a first type of conductivity and forming three rectifying
junctions, the emitter of the first transistor having connection
to earth, the emitter of said second transistor having connec-
tions to the pole of a bias supply capable of repelling the
majority carriers of said first zone, the current in said second
transistor flowing parallely to the surface of said first zone,
said first transistor comprising a two part collector having a
second type of conductivity opposite to the first, a first part
being a second zone included in said first zone having a shallow
depth and a third zone surrounding said first transistor thus
causing the current to flow in said second transistor both per-
pendicularly and parallely to the surface of said first zone.
2. A bistable element as claimed in claim 1, wherein
a substrate surrounds said first zone, this substrate being of
the second conductivity type, an ohmic contact connecting said
first zone to the bias-voltage source, said first zone having a
portion of small dimensions acting as base to the second transistor,
the remaining part being connected by an ohmic contact to the
bias voltage source and acting as a leakage resistance.
3. An element as claimed in claim 2, wherein the emitter
of the second transistor is formed by a second zone of the first
conductivity type included in said first zone, said second zone
having an ohmic contact for connection to said supply, this second
zone acting both as an emitter to the second transistor and as a
biassing resistance.

4. An element as claimed in claim 1, wherein the base
of the second transistor may receive a voltage with two logic levels,
one zero and the other substantially equal in sign and in absolute
value to said biassing voltage, the output voltage being collected
at the collector of the second transistor.

Description

Note : Les descriptions sont présentées dans la langue officielle dans laquelle elles ont été soumises.


.
11 8~2
,:'. '
This invention relates to a new bistable logic element
; with very small dimensions and a very high switchin~ speed.
According to the invention, a bistable logic element
comprises a first and a second complementary transistor, integra~ted
into a first zone of a first type of conductivity and forming
three rectifying junctions, the emitter of the first transistor
;~ having connection to earth, the emitter of the second transistor
~ having connections to the pole of a bias supply capable of repel-
i~ ling the majority carriers of the first zone, the current in the
second transistor flowing parallely to the surface of the first
zone, the first transistor comprising a two part collector having
a second type of conductivity opposite to the first, a first part -
being a second zone included in the first zone having a shallow
depth and a third zone surrounding the first transistor thus
.
causlng the current to flow in the second transistor both perpen-
dicularly and parallely to thé surface of sa~d first zone.
, . .
Its essential feature is the fact that the first tran-
j sistor comprises two collectors, one of which is responsible for ~-
lateral conduction whilst the other is f~rmed by a heavily doped
zone of sultable conductivity type and surrounds the structure
of the first transistor. -
The invention will be better understood from the following ~
description in conjunctionwith the accompanying drawings, wherein: -
. .
~ Figs. 1 and 2 are respectively a section through and
:~ ,
. a plan view of a first example of embodiment of the invention.
Fiq. 3 shows the equivalent circuit diagram of the
structure illustrated in Fig. 1.
Fig. 4 is one example Oe application Oe the structure
illustrated in the preceeding Figs.
In Figs. 1 and 2, the reference 1 denotes a substrate
weakly doped with silicon for example and of n-type conductivity
(1016-at/cc) for example.

`
; 108~86Z
., .
In the following, all the conductivity types may be
reversed.
The substrate is covered by a thin layer 2 of silica.
A zone 3 of ~-type conductivity (impurity concentration
1017 at/cc, depth approximately 1 micron) is initially implanted
in this substrate by means of suitable masks and by ion implanta-
tion or by diffusion.
Zones 40 and 41 of p+ type conductivity activity both as
collectors are then implanted in this compartment through another
mask. Of these two zones, the zone 41 is the so-called inner
zone of small dimensions, whilst the zone 40 is the so-called outer
zone surrounding the structure. These two collectors are the
collectors of one and the same transistor Tl which is shown in
Fig. 3 and which is of the p np-type. A third zone 42, also of
p+ type conductivity, is the emitter of this transistor.
Accordingly, this transistor comprises two collectors
and one emitter and the current flows through it both parallel
to and perpendicularly to the surface of the substrate. The depth
of these diffusions or implantations is of the order of 0.3 micron
and the doping density is of the order of 1019 to 102 at/cc.
Two n-type zones with adoping density of 1013 at/cc and
a depth of 0.5 micron are then implanted. The first zone 51 is
the base of this transistorand is also the collector of the
second complementary transistor which forms part of the structure.
It is connected to an n+ diffusion 52 with a depth of 0.3 micron '
and a doping density of 1018 at/cc, this diffusion being connected
to a metallic contact B. The second n- type zone 53 with the ~
same depth as and separated from the first zone is the emitter of
the second transistor.
It has the same doping concentration as the first zone.
It is in the shape of a T. The transverse part of this T is the
--2--
: ,. :',.......................... . ... ., ., . . ,. ' .

" . 1~81862 -
actual electrode. The longitudinal part acts as a resistance Rs
and is connected to an n+ di~fusion 54 which is connected through - -
an ohmic contact to the bias voltage source - Vp of the assembly.
Similarly, the emitter 42 is connected to earth through
a contact E. The active zone, the emitter of the second zone 3,
is situated between the zones 53 and 52. The remainder of this
zone connected to the supply - Vp acts as a resistance RCc in
series with said emitter.
The equivalent circuit diagram of Fig. 3 is thus obtained.
This structure is an element with two stable states and
. .
functions in the following manher:
The two transistors Tl and T3 are connected. The first
transistor Tl, of p np conductivity type, is the transistor has
,
two collectors and its emitter E (contact E in Fig. 1) is connected
to earth.
The contact B may receive the voltage O (connection to
earth) or a voltage - V and acts as input contact, being connected
to the base of the transistor Tl.
The output contact is connected to the outer collector
Cex. The contact -Vp is also connected to the emitter of the
transistor T2 and to the base thereof through the resistance RCc
(zone 3 of Fig. 1). The emitter of this transistor is connected
to the bias voltage source - Vp through the resistance RS (n-
type zone 53).
The mode of operation is as follows:
(a) B is connected to earth. The transistor Tl is
blocked, its base and its emitter being connected to earth. The
point Cex, disconnected from earth, is substantially at the po-
tential - Vp. The transistor T2, of whichthe base is at a poten-
tial of the order of - ~p, is also blocked. The point Cex is
substantially at the potential - Vp.
.
. .

. `~ 1t3 8186Z
... . . -.
, ` . .
(b) The point B is at the potential - Vp. The transis-
tor Tl is thus conductive. The point Cex is connected to earth
and also renders the transistor T2 conductive.
Accordingly, the structure has two stable states and
may act as an inverter, the input being at the level "l" and the
output being of necessity at the level "O", and vice versa.
This inverter is made in a single block. The resistances
are integrated into the same substrate as the pn pn structure.
`` The emitter and the collector of n-type conductivity can be im-
1~ planted or diffused simultaneously with the same mask, thereby
providing for perfect control of the thickness of the base of the
lateral npn transitor.
The n-type emitter is in series with an n-type layer
acting as biassing resistance.
The zone P acts as leakage resistance RCc.
Several inverters of the type shown in Fig. 3 may be
connected in series, the point Cex of one being connected to the
polnt B2 of the next. Since the multiple-collector transitor
functions both in the lateral direction and in the transverse
direction, it has a very low resistance in the conductive state.
The end product is thus a structure such as that illus-
trated in Fig. 4 which shows two inverters INVl and INV2, such as
that shown in Fig. 3, or the point Cex of the first is connected
to the point B2 of the second. When one is conductive, the next
is blocked and vice versa.
The re~erences of Fig. 4 with respective indices 1 and
2 designates the same elements as`in Fig. 3.
All the conductivity types may of course be reversed -
with the same doping densities, the bias voltage is reversed and
becomes po~itive.
-4-

Dessin représentatif

Désolé, le dessin représentatif concernant le document de brevet no 1081862 est introuvable.

États administratifs

2024-08-01 : Dans le cadre de la transition vers les Brevets de nouvelle génération (BNG), la base de données sur les brevets canadiens (BDBC) contient désormais un Historique d'événement plus détaillé, qui reproduit le Journal des événements de notre nouvelle solution interne.

Veuillez noter que les événements débutant par « Inactive : » se réfèrent à des événements qui ne sont plus utilisés dans notre nouvelle solution interne.

Pour une meilleure compréhension de l'état de la demande ou brevet qui figure sur cette page, la rubrique Mise en garde , et les descriptions de Brevet , Historique d'événement , Taxes périodiques et Historique des paiements devraient être consultées.

Historique d'événement

Description Date
Inactive : CIB de MCD 2006-03-11
Inactive : CIB de MCD 2006-03-11
Inactive : CIB de MCD 2006-03-11
Inactive : Périmé (brevet sous l'ancienne loi) date de péremption possible la plus tardive 1997-07-15
Accordé par délivrance 1980-07-15

Historique d'abandonnement

Il n'y a pas d'historique d'abandonnement

Titulaires au dossier

Les titulaires actuels et antérieures au dossier sont affichés en ordre alphabétique.

Titulaires actuels au dossier
S.O.
Titulaires antérieures au dossier
NGU T. PHAM
Les propriétaires antérieurs qui ne figurent pas dans la liste des « Propriétaires au dossier » apparaîtront dans d'autres documents au dossier.
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Description du
Document 
Date
(yyyy-mm-dd) 
Nombre de pages   Taille de l'image (Ko) 
Abrégé 1994-04-07 1 15
Dessins 1994-04-07 2 46
Page couverture 1994-04-07 1 11
Revendications 1994-04-07 2 65
Description 1994-04-07 4 167