Note : Les descriptions sont présentées dans la langue officielle dans laquelle elles ont été soumises.
4~
Backgroun~ of the Invention
1. Field of the_Invention.
The invention pertains to the composition Or advertisin~
matter as would be done for a newspaper, classified telephone
. . .
or business directory and to other relate~ uscs. More parti-
cularly, the invention relates to an electronic composition and
display system for permitting an operator to quickly and accur-
ately compose adver~ising display matter without the need for
most hand layout and composition functions.
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2. Description of the Prior Art.
Throughout the modern history of newspapers~ the composition
¦ ~ and layout of advertising ma~ter has been a time consuming and
labor-intensive task. To compose a typical advertisement, an
ad layout operator would ~irst make a rough pencil sketch of
i~ the proposed advertisement in accordance with the instructions
of the advertising customer. The operator would sketch rough
~3
! : areas in which pictures or sketches were to be displayed and
~; block out areas in which textual matter was to be fitted. Large
,~ 20 type headings were sketched in with the composer making only a
rough estimate as to the actual size and length o the particular
heading. Once the rough sketch was made, composing room per-
sonnel would "paste up" the actual pictures upon a mark-up of
the advertisement and attempt to fit the textual matter within
the boundaries set by the composing operator. Often, the text
would not fit witbin the boundaries qstimated. For example, the
large textual headings would extend o~er the boundaries of the
~ advertisement making the entire layout unacceptable. At this
;, point, the mark-up of the advertisement was sent back to the
~ 30 composing room for a second try. Often the process had ~o be
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repeated three or more times before an acceptable copy was
obtained.
Later, electronic composition systems were described for
permitting an opera~or to partially compose an advertisement
upon an electronic interactive terminal. With some of these
systems, the operator could type in textual matter or enter
such textual matter upon a position determined by him upon the
CRT (cathode ray tube) screen. In these systems, data was
displayed upon a CRT screen corresponding to the text and its
positions within the actual advertising copy. These systems
provided an output in the form of a punched paper tape or
other digitized form of output which was transferred to a
phototypesetter or other similar device. The phototypesetter
then produced a copy of the textual matter with which the
photographs or sketches and other non-textual matter were then
, :
pasted up.
Although such systems have somewhat reduced the intensity
~; of labor involved in a typical advertisement composition situ-
ation, the systems heretobefore known were not able ~o perform
many of the most critical advertising composition functions.
.,
For example, the characters produced upon the screens of pre-
viously known systems were not true representations of the
character sizes used in the actual advertising copy. For that
reason, the operator could not be cer~ain that the positions
and spacing chosen would alternately be accep~able in the final
advertising copy. Moreover, in none of the previously known
systems was an operator able to flow text as is so often required
in advertising composition. Purthermore, the number of lines and
the position of lines displayed upon the CRT's in previously
known systems were extremely limited because, inter alia, of
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the memory systems typically employed. Still further, other
problems were encountered in the reaction speed of the system
to operator-initiated commands. For example, if an operator
wished to erase an image of one advertisement and replace it
with an entirely new image of another advertisement, long time
delays were involved. If more than one work station were con-
nected to a common computer or digital processing system
servicing each work station, operation upon one of the work
stations typically completely tied up the digital processing
system making it unavailable for servicing all the other work
~ stations until the first work station had finished its parti-`1 cular operation.
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Su~m~ry of the Invéntion
.
Accordingly, it is an object of the present invention to provide
an operator-interactive digital data and display system particularly adapted -
for use in composing advertising and related matter having displayed
characters which are accurately representative of the actual printed
characters.
;~ Furthermore, it is an object of the present invention to provide
such a digital data and display system in which the entire advertising copy
may be closely simulated thereby.
Also, it is an object of the invention to provide such a dlgital
- data and display system having the capability of displaying as many lines,
symbols, or other data as required to compose an entire advertising copy.
` Moreover, it is further an object of the invention to provide such
a digital data and display system which responds quickly to operator-furnish~
ed inputs and in which interference between work stations operating from a ~ -
common digital processor is substantially minimized. ~ -
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According to one broad aspect of the present invention, there is ,~;
~I provided in combination: means for storing digital data representing a
} plurality of character patterns to be displayed, said character patterns
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being formed as a plurality of rows and columns of dots; and means for
reading said digital data out of said storing means to display predetermined
ones of said character patterns, said reading means varying the number of
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rows and columns of dots within said character patterns in accordance with
i~ the size at which said character patterns are to be displayed.
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According to another broad aspect of the present invention, there ;~ -
is provided a character generator for producing dot character patterns of
, adjustable height and width comprising in combination: means for storing
digital data representing a plurality of character patterns, said character
;~ patterns being formed as a plurality of rows and columns of dots, said
storing means having a plurality of bit outputs, each of said bit outputs
representing one dot within one row of one of said character patterns at a
predetermined address location, each of said rows being s~ored at a different
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address location within said data storing means; means for addressing said "
data storing means to read out data representing each of said rows of dots
one at a time; and means for logically adding preselected ones of said bit
outputs for characters to be displayed having a width less than a first
predetermined width.
According to a further broad aspect of the present invention, there
is provided in combination: means for storing digital data representing a
plurality of character patterns to be displayed, said character patterns being
formed as a plurality of rows and columns of dots; and means for reading said
data out of said storing means, each row being read out in succession for ~
characters to be displayed having a predetermined height and some of said rows ~ ;
. . . . .
being omitted for characters to be displayed having a height less than said `~
; predetermined height.
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J The invention may further be practiced by providing a character
generator for producing dot character patterns of adjustable height and adjust-
able width including the combination of means for storing digital data repre-
1 senting a plurality of character patterns, the character patterns being
:( formed as a plurality of rows and columns of dots, storing means having a :
~j ~ plurality of bit outputs each of which represents one dot within a single
; 20 row of one of the character patterns being stored at a predetermined address
location, each of the rows being stored at a different address location
within the data storing means, means for addressing the data storing means
to read out data representing each of the rows of dots one at a time for
character patterns of a predetermined ixed height and to read out data more
than once for at least some rows for characters having a height greater than
the predetermined fixed height with some of the rows of data not being read
out at all from the data storing means for characters having a height less
than the predetermined fixed height. The combination preferably further
comprises means for coupling the plurality of data outputs from the data
storing means to
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video signal producing means, the data outputs being coupled one
at a time in a predetermined sequence. Furthermore, the data
outputs from the data storing means are coupled by the coupling
means to the video signal producing means once each in sequence
for character patterns to be displayed having a predetermined
fixed width. The coupling means may couple preselected ones of
the outputs from the data storing means to the video signal pro-
ucing means more than once for characters to be displayed with a
width greater than the predetermined fixed width and does not
couple preselected ones of the outputs from the data storing
i~ means within the sequence to the video signal producing means for
` characters to be displayed with a width less than a predetermined
fixed width. The data storing means may comprise either a random
access memory or a preprogrammed read-only memory. The combination
preferably also includes a plurality of signal adding means each
of which has inputs coupled to preselected outputs of the data
storing means with outputs of the signal adding means coupled to
inputs of the coupling means. The coupling means couples outputs
from preselected ones of the signal adding means to the video
'~ ~ 20 signal producing means for characters having a width less than a
,'~ second predetermined fixed width.
,~ More particularly, the invention may be practiced by a char-
acter generator which comprises the combination of a memory for
storing digital data representing character patterns to be dis-
played, the character patterns each comprising a plurality of
rows and columns of dots, the memory having a plurality of output
data bit lines each of which represents a possible dot position
within a row of dots within one of the character patterns, the
memory means having a plurality of address lines with signals
representing one of the rows of dots within the character patterns
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being coupled to the OlltpUt lines for each address input, an
address counter outputs of which are coupled ~o the address inputs
;of the memory, a plurality of logical OR gates, the OR gates bein~
coupled to predetermined ones of the output lines of the memory,
a first multiplexer having a plurality of inputs and a single
output, one of the inputs being coupled to the output multiplexer
in response to a code coupled to select inputs of the first multi-
plexer, inputs of the first multiplexer being coupled to output
lines of the memory and to outputs of the OR gates, a second
multiplexer, the'second multiplexer having a plurali'ty o~ sets
of input lines and a single set of output lines having the same
number of lines as one of the sets of input lines, outputs of the
second multiplexer being coupled to the select inputs of the first
,,
multiplexer, a register for storing a number representing 'he width
of character patterns to be displayed, a read-only memory outputs
of which form one of the sets of inputs to the second multiplexer
and outputs of the register being coupled to address inputs of the
read-only memory, the read-only memory storing digital numbers
representing columns of dots within the character patterns for
character patterns to be displayed having a width less than a
predetermined fixed width, and outputs from the read-only memory
being coupled through the second multiplexer to the select inputs
o the first multiplexer for character patterns to be displayed
having a width less than the predetermined fixed width~ The mem-
ory further comprises preferably a random access memory. The
random access me-mory may be loaded with character patterns from
an external data source upon system initiali~ation or when it is
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desired to vary the character patterns stored therein. The memory
~' may alternatively comprise a read-only memory which has been
preprogrammed with the desired character patterns. In preferred
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embodiments thc address counter is initialized for the start of
the generation of one of the character patterns to a predeter-
mined start address corresponding to a selected one of the
character patterns and is incremented for each row of data to
be read out from the memory. The address counter is incremented
by one count for each row of data for character patterns to be
displayed at a predetermined fixed height. The address counter
; is further incremented by fewer times than there are rows of dots
for data stored in the memory for character patterns which are to
be displayed having a height greater than the predeteTmined fixed
height and is incremented more times than there are rows of data
stored in the memory for character patterns which are to be dis-
played having a height less than the predetermined fixed height.
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Brie~ Description of the Drawlngs
. FIGURE 1 is a sketch of a digital data and display
-- system adapted for advertising copy layout embodying the
present invention;
FIGURE 2 is a planar view of the operator controls and
indicators of one of the work stations of the system shown in
.: Figure l;
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FIGURE 3 is a cross-sectional view of the programmed
function template of the operator controls shown in Figure 2;
FIGURE 4 is a representation of data, symbols, and lines
. as would be displayed upon the screen of a cathode ray tube in
accordance with the invention; .
FIGURE 5, on the first sheet of drawings, is a ~::
generalized block diagram of a digital data and display system - .
.... .
- in accordance with the invention;
:~. FIGURES 6 and 7 taken together are a detailed block ~ ~ -
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' diagram of the system shown in Figure 5, Figure 7 being on the .
second sheet of drawings;
~'. FIGURE 8 is a diagram of one of the trackball symbol
generators of the system shown in Figure 6;
. FIGURE 9 is a detailed block diagram of the character
-, generator of the system shown in Figure 6;
FIGURE 10 is a diagram of the character image generator
o the system shown in Figure 6;
PIGURE 11 is a diagram of a letter "E" as would be
displayed with the present invention;
FIGURE 12, on the fourth sheet of drawings, is a diagram
used to explain the operation of the character image generator
shown in Figure 10;
FIGURE 13 is a diagram of a memory module of the bit
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image memory of the system shown in Figure 6;
FIGURE 14 is a diagram used to explain the operation of
:~ the bit image memory of the system shown in Figure 6;
FIGURE 15 is a timing diagram of the bit image memory
of the system shown in Figure 6;
EIGURE 16, on the seventh sheet of drawings, is a
.~ diagram of the bit image memory access control circuitry of the
: system shown in Figure 6;
FIGURE 17, on the third sheet of drawings, is a diagram
of the direct memory access controller and mi.croprocessor of ~ ~:
the system shown in Figure 6;
FIGURES 18-29 are flow diagrams used to explain the
`. operation of the mlcroprocessor shown in Figure 17, Figures 28
;` and 29 appearing on the seventeenth. sheet of drawings;
FIGURE 30 is a diagram of the ~ideo formatter of the
.~ system shown in Figure 6; and
`~ FIGURE.3I, on the s.ixth sheet of dra~ings, is a diagram
of the displa~ refresh. timing generator of the system shown in
~igure 6.
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Description of the Preferred Embod_ments
:
Referring first to Pigure 1 there is shown therein a ~ -
sketch of a portion of a digital data and display system in ac-
cordance ~ith the present invention which is particularly adapted
for use with composing advertising copy. The basic components of
the system include a control unit 106 and one or more work stations
100 connected thereto. Each work station 100 includes a CRT dis-
pla~ unit 104, operator controls and indicators 103 and a graphic
digitizer tablet 102. Teletype 105 may be provided for entry of -~
externally sampled digital data.
Work stations 100 are the basic input/output devices
of the system which permit an operator to completely compose an
advertising copy with assurance that all text, symbols, and ~i
sketches or photographs fit within predicted space limitations -
and that the advertisements composed thereupon are in all ways
acceptable as final copy for printing. Control unit 106 con-
tains the basic data processing circuitry and memory for oper-
ating each of work stations 100 and suitable output circuitry
:
for producing a digital output to a phototypesetter or remote
computer representative of the composed advertisement.
An operator may enter data into the system in the form
of lines or symbols and characters using either operator controls
and indicators 103 or graphic digitizer tablet 102. Typically
ln an advertising composition sequence, a rough hand-drawn copy
or mark-up of the advertisement upon a piece of paper is attached
.. . .
to the surface of graphic digitizer tablet 102. A number of
commercially- available graphic digitizer tablets may be used
for graphic digitizer tablet 102 for example, a Summagraphics
Company Data Table/Digitizer tablet device. With this tablet,
an operator may move a specially provided pen over outlines of
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photographs or alon~ other lines or boundaries that he wishes
displayed in the advertisement. As he moves the specially
provided pen over the surface of the advertisement in graphic
digitzer tablet 102, digital outputs are relayed back to control
unit 106 continuously indicative of the position of the pen
point upon the surface of graphic digitizer tablet 102. These
digital positions cause the display upon CRT display unit 104
, of corresponding lines or boundaries. ..
1 The ope,rator may also enter data via operator controls
', 10 and indicators 103 which are shown in more detail in FIG. 2.
. There are three basic sections of operator controls and indi-
! cators 103 including trackball unit 1~20, programmed function
i! keyboard 121, and alphanumeric keyboard 122. Alphanumeric key-,,~ board 122 is a standard typewriter style electrical keyboard
having keys corresponding to each letter of the alphabet, each
numeral and other selected symbols such as ,punctuation marks, or
any other character or symbol to be displayed. Depression of a
single one of the keys of alphanumeric. keyboard 122 causes
the production of corresponding digital,~code, which is relayed
Z back to control unit 106. One such keyboard which will fulfill
1~ this function is described in United States Patent No. 3,921,166,
1 ~
issued November 18, 1975 to John W, Volpe~,and assigned to the
present assignee. . .,~.,l .
~: A second keyboard is provided in the orm o:~ programmed
: function keyboard 121. Bach key within,programmed~function
l ~ keyboard 121 performs a predetermined function within the
,, ' ad~tertising copy layout as inclicated by an adjacent label upon
.'. programmed function template 127. For éxample, one such func- ' '
tion may be to flow a selectecl copyblock between a chosen set of
~: 30 lines. Upon depression of a key witkin programmed function
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kcyboard 121 corrcsponding to that function, an in~icated copy
block would be automatically positioned between the selected
lines with each line automatically positioned a predetermined
distance from the left-most boundary.
It has been found that for advertising copy layout many
more keys are desired for performing such functions than is
~ ordinarily convenient to provide. It has also been found that
certain of these types of function keys are needed only for a
predetermined portion of the advertising layout sequence while
others are generally required throughout the entire operation.
Thus, in accordance with the invention, plural programmed
function templates 127 are provided. Each template is labeled
according to the functions performed by the keys within pro-
grammed function keyboard 121 when that template is used.
Each of these templates is formed as a metallic or rigid plate
with apertures therein through which may extend the keys of
programmed function keyboard 121. A knob, slot, or other means
~ is provided ~or an operator to lift off each template and toj:
' replace it with another. Preferably, some of the keys perform
the same function for each template while others perform a
different function according to the template used. The func-
tions which change with each -template are preferably grouped
upon the templates according to their use within the sequence
of advertising composition so that changes in templates are
minimized throughout the sequence.
Each programmed function template 127 is encoded as shown
in the cross-sectional view o FIG. 3. A plurality of photo-
diode 130 and phototransistor 131 pairs are provided attached
permanently to CRT display unit 104 so as to lie immediately
under predetermined portions of the rear side of a programmed
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function template 127 while in place upon programmed function
keyboard 121. The regions of the rear side of programme~
function template 127 immediately above the photodiode-photo-
transistor pairs is colored black so as to be non-reflecting
unless a reflective mirror or strip 132 is placed there. Each
' photodiode 130 produces light of a wavelength which may be
i detected by the corresponding phototransistor 131. Should
j the adjacent portion of the rear side of programmed function
template 127 be black the light emitted by photodiode 130 is
substantially absorbed. The corresponding one of phototran-
sistors 131 receives then substantially no light and, upon
! proper biasing, produces an output voltage corresponding to a
'~1 logical 0. On the other hand, should reflecting strip 132
1'
cause reflection of light from a photodiode 130 to a corre-
sponding phototransistor 131, an output voltage will be pro-
duced which corresponds to a logical 1. The output logic
signals produced by phototransistors 131 are coupled back
to control unit 106 in a manner to be described. Each dif-
ferent programmed function template 127 is encoded thusly
with corresponding pattern,s of logical l's and 0's in accord-
ance with the placement of reflecting strips 132 and black
~i; colored areas. With the knowledge of which programmed function
¦ ~ template 127 is being used control unit 106 produces the corre-
sponding preprogrammed functions.
Referring back to FIG. 2 there is also provided a track-
!~ ~ ball unit 120. Trackball unit 120 includes an operator-rotatable
,
ball 124 which may be rotated in any direction. Rotation of
rotatable ball 124 causes digital pulses to be produced in
proportion to the amount of movement in each of X and Y axes.
~ 30 These pulses cause the movement upon the screen of CRT display
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unit 104 of a trackball symbol or cursor in accordance with the
: direction and amount of rotation.of rotatable ball 124. As an
example for use of trackball unit 120, the system may be so
programmed that a copyblock selected or inputted by alphanumeric
keyboard 122 is positioned at a start location indicated by the
trackball symbol as positioned by operating trackball unit 120
in accordance with a command inputted from programmed function
keyboard 121. There may also be provided a HOME key 125 depres-
i~ sion of which causes the trackball symbol to return to the center
10 of the display screen or another predetermined location. An
inte~ 126 may also be provided which causes the system to
~7~ ~ ' accept a new trackball data input.
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Referring next to FIG. 4 there is shown therein a sketch
of a typical data presentation upon the screen of a CRT display
unlt 104. The presentation is divided into four major areas:
: work area 150, detailed viewing area 151, operator aids area
155, and preview area 154. Upon initialization of the system,
work area 150 displays a list of uncomposed or partially com-
posed advertisements stored within the memory portion of control
~p~ 20 unit 106. To select one advertisement from the list of avail-
able advertisements, the operator positions a cursor symbol
: adjacent to the selected advertisement such as may be done by
operating trackball unit 120, programmed function keyboard 121,
~ or alphanumeric keyboard 122. The operator then presses a key
1
of programmed function keyboard 121 which causes the display of
the selected advertisement or at least that portion which has
-~ been previously digitized and stored within the system within
~ de~tailed viewing area 151. When an advertisement has been
~, ~
f selected the listing of work area 150 becomes a listing of copy-
30 blocks wit~ an identification numb0r correspondin~ to each pre-
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written copyblock.
An operator may select a copyblock for manipulation in
the same way that the entire advertisement is selected from an
available list or, more simply, he may merely enter the number
of the copyblock via alphanumeric keyboard 122 then depress a
preselected key of programmed ~unction keyboard 121. Once a
particular copyblock has been selected, particular indicia con-
cerning that block are displayed within operator aids area 155.
For examplet the type size selected and the style of the type,
~standard or italics with the amount of slant,), the amount of
spacing between lines in the copyblock, and the amount o~ inden-
~; tation may be displayed. Other useful information such as the
l numerical position of the trackball within the advertisement
t~ boundaries which line of the copyblock is selected and the
character then under the trackball symbol may also be displayed.
With this selected information, the operator may thenposition the copyblock as desired within detailed viewing area
, 151, make changes within the copyblock to the wording, type
font and size, flow the lines of the copyblock within straight
or irregular boundaries, or make any other desired changes.
Boundary lines such as boundary line 152 may be produced either
through graphic digitizer tablet 102 by moving the specially
provided pen along the desired boundaries or by use of trackball
unit 120. Boundary lines thus drawn may be used as boundaries
~or copyblock text or as an indicator to the paste-up personnel
OI where sketches or photographs should be positioned.
An operator may also enter new copyblock data which is to
j~ be added to the advertising copy. This is done by typing in
the added material with alphanumeric keyboard 122 which then
' 30 appears within preview area 15~. Corrections may be made to
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the material within preview area 154 before it is move~l to and
positioned within the advertising copy as displayed within
detailed viewing area 151. To move added textual material, an
operator may position the trackball symbol with trackball unit
120 at the preferred start location then press a predetermined
key of programmed function keyboard 121 causing the transfer.
The above recited functions performed by the system of the
invention is for purposes of illustration only. Many other
different kinds of functions may also be performed depending
upon the programs used by control unit 106. It is advantageous
that with the invention advertising composition may be done
much more accurately and quickly than with previously known
systems-
~ Referring next to FIG. 5, there is shown therein in block
3 ~ ~ diagram form an advertising composition system in accordance
with the invention. The text for the copyblocks is entered
into the system through control unit 106 by one or more of
~t~ several available external data entry devices. These devices
include optical character reader 160, text terminal 162, and
. - 20 keyboard 164. The copyblocks entered as digital data at this
point are ordinarily only in the form of text with no position
within the advertisement specified. The copyblocks within a
particular advertisement are identified only as to the copy-
block to which they properly belong.
The digital data rom optical character reader 160, text
terminal 162, or keyboard 16~ is first coupled into minicomputer
167 then stored upon disc memory 166 using well-known data
storage techniques. The data thus stored is addressed by a
- number corresponding to each advertisement for which data is
,
, 30 stored on disc memory 166 and by a number corresponding to each
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cor)y~)lock within an advertisemcnt. l)ata relating to advertise-
ments to be composed may also be entered via peripheral d~ta
cntry dcvices 168 which may, for example, include a high-speed
paper tape reader, magnetic tape unit, or teletype.
Also entered via peripheral data entry devices 168 are
the software programs used to cause minicomputer 167 to perform
various aspects of system operation. Included among these pro-
grams are ones for causing the transfer of data from optical
character reader 160, text terminal 162, keyboard 164 and other
10 data entry devices to disc memory 166. Other programs include
those for manipulating data in response to commands from
operator controls and indicators 103 at each work station 100
~, ~
and it may further include algorithms for performing automatic
hyphenation or similar operations useful in flowing text between
predetermined boundary lines. The programs entered by peripheral
data entry devices 168 may be stored either upon disc memory 166
. .
l~ or within a core memory within minicomputer 167 or within any
`1~ of the number of well-known storage devices. Also stored upon
disc memory 166 may be standard and specialized line patterns
20 such as squares, rectangles, ellipses, and various polyhedron
figures which are useful in producing the advertising copy.
These are stored as sets of digital numbers representing the
end points of individual line segmen~s which make up the
pattern.
Data control commands from operator controls and indicators
103 are assembled by operator interface unit 175 and communicated
to minicomputer 167 after proper formatting through I/O bus
169. ll~e digital signals input upon I/O bus 169 at this point
represent the various symbols and characters typed in by an
30 operator upon alphanumeric keyboard 122 as well as the programmed
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function comman~ produce~ by programme-~ function keyboar~ 121
and further includes digital numbers representing the rotation
or position of the trackball symbol as produced by trackball
unit 120. These control signals, relayed by operator interface
unit 175, actuate selected portions of the stored programs and
furnish input data required in executing the stored programs.
Data produced and assembled by minicomputer 167 to be
displayed upon the CRT display units 104 of work stations 100 is
coupled to I/O bus 169 where it is further coup]ed to vector
generator 170, BIM (bit image memory) 172, and character gener-
ator 173. BIM 172 contains a complete representation therein
of all the data displayed upon the CRT display units 104 of each
i~ of work stations 100. BIM 172 may be divided into predetermined
sections with each section servicing a predetermined one of work
stations 100. The display screen of the CRT display units 104
of each work station 100 are divided into a matrix of display
points with all points falling upon raster scanned lines. For
example, in a preferred embodiment, there are 1,024 display
positions in the matrix along both X and Y axes. Each display
position or point within the matrix is represented by a binary
bit within BIM 172. This bit may be set in either of two logical
states one of which represents a blanked or low light output
condition for the corresponding point upon the CRT screen while
~jj the other represents an unblanked or condition of higher light
intensity. Characters, lines, and geometrical patterns are thus
displayed upon this screen of one of CRT display units 104 by
storing patterns of logic bits within BIM 172 corresponding to
the form of the character, line, or Keometric pattern to be dis-
played and refreshing the CRT display unit 104 directly from
BIM 172 by reading out the data stored therein in sequence with
1 9
.. . . .
.. . . . ... . . . . . . . .
...... . . .
Lt;4~
the generation of the raster scanned pattern used to refresh
the display unit. Characters, lines, and geometric patterns
may be stored either as light intensified portions against a
darkened background or as darkened portions within a light
j background. The latter is preferred for long time viewing.
In previously known systems, data for refreshing the dis-
play units was stored most commonly in a storage tube. The
I data storage capabilities and resolution of such tubes limited
the amount of data which could be displayed and the minimum size
of characters which could be used. Systems using such tubes
for display refresh were also limited in speed as data could
not be changed within the memory during ordinary refresh oper-
ations. Moreover, such tubes are clearly less reliable than
~I digital devices thereby lowering the overall reliability of
systems employing them.
Other systems used a digital refresh memory in which were
~ stored the end points of lines and the codes corresponding to
! characters to be displayed. No actual images of these were
stored. During each refresh cycle it was necessary to produce
each image pattern. As apparatus for producing these patterns
operates relatively slowly, the total number of lines, characters,
and patterns which could be displayed was severely limited.
Vector generator 170 and character generator 173 also re-
ceive data from minicomputer 167 on I/O bus 169. Vector gener-
ator 170 receives as inpwts the beginning and end points of
~! lines to be drawn upon the screen of one of CRT display units
104. These end points correspond to two bit positions with
corresponding addresses within BIM 172. Vector generator 170
calculates the positions of adjacent dots correspondlng to
particular bit locations within BIM 172 which, displayed
- 20 -
,
, ~ ', .',. '' '' ' ' . ' ' ' '
," ' ,' ' ' , ,, .', . . . . . .
together, produce the desired line. The requisite bits within
BIM 172 are set by the outputs of vector generator 170 in the state
corresponding to display conditions. For example, if the logical
1 state corresponds to a darkened screen matrix point and it is
desired to display lines and characters as darkened dot patterns,
logical 1 bits are set within BIM 172 as addresses corresponding
to positions along the length of the line.
' Character generator 173 receives inputs in the form of
character codes corresponding to character or symbol patterns
to be displayed. Also furnished are control bits which deter-
mine the size and font style of each character. Character
generator 173 then alters the basic character pattern stored
I~ ~ therein in accordance with these codes and transfers the char-
acter image into BIM 17Z as a corresponding pattern of logical
l's and O's.
It is to be noted tha~ with the invention only one vector
generator and character generator need be supplied to service
a plurality of work stations and CRT display unlts. Also, the
line and character or symbol patterns need be produced only once
for each character or line input as contrasted with previous
systems in which the line and character or symbol patterns had
to be produced once each re~resh cycle. Therefore~ systems
construc~ed in accordance with the teachings of the present
~ :,
invention are able to display much larger amounts of data than
were previous systems. Systems in accordance with the present
invention are also able to reproduce characters having a smaller
size with greater clarity than was possible with sys~ems using
storage tube memories ~or display refresh.
Referring next simultaneously to PIGs. 6 and 7 there is
shown therein a more detailed block diagram of the 5ystem shown
iY : ,
t, - 21 -
,,':
; ~
-. :- ., : , , ,
~ ,',,' ,'' ,",. ~: ,. . . ,' ' , ' , , "
, ~' ,: '' ' ' '' , ' . . ,
in Figure 5. ~inicomputer 167 i5 shown with disc memory 166
connected thereto along with peripheral data entry devices 168
which here include magnetic tape unit 180, teletype 105, and
high speed paper tape reader and punch 182. The latter two~ -
may be connected to a multiplexer bus input of minicompu~er
167 while the former two are preferably coupled to the memory
bus therein.
; I/0 bus 169 as shown in Figure 5 here includes both
parallel and serial portions. Input and output between the
,~ 10 parallel and serial buses to and from the minicomputer 167 is
controlled by CLU ~Common Logic Unit) I/0 logic 183. CLU I/0 -
- logic 183 includes DMA (Direct Memory Access) I/0 logic 184 and
CPU ~Central Processor Unit) I/0 logic 185. DMA logic 184 com-
municates data to and from the memory bus within minicomputer
167 while CPU I/O logic 185 communicates with the CPU registers.
For minicomputer 167 and Interdata Corporation Model 7/16 mini-
computer may be used, that computer having the required CPU and
DMA bus access for use with the system of the invention. DMA
loglc 184 includes registers for retiming data passed in both
directions along the parallel data bus and also includes
driver circuitry for producing output signals of appropriate
voltage levels. The primary parallel path for transfer of data
representing lines and characters to be displayed is through
DMA I/0 logic 184 while the sole path for control communications
' between TCU (Terminal Control Unit) 176 and CLU 177 is through ;
CPU I/O logic 185.
... .
Por generations of lines, characters, and all geometric
patterns minicomputer 167 produces output data words having two
component parts. The first of these parts is an opcode which
3Q indicates the t~pe of word and hence type of operation to be
. , ,
_ 22 -
.. . .
.. . . . .
,,, ~ .
~. .. . .
performed. The opcode is transferred via CPU I/O logic ~
to TCU message decoder 198. The data portion of the word is
transferred directly from D~IA I/O logic 184 to D~A controller
189 within vector generator and arithmetic unit 188 and thence
to microprocessor l90.
, The types of messages which may be sent from TCU 176 to
; CLU 177 include the following:
~i 1. Load Device Address. This instruction addresses BIM
172 directly. BIM 172 is instructed to receive and load data
from DMA I/O logic 184 via DMA controller 189, microprocessor
;, 190, video formatter 194, and BIM access control 195. BIM 172
will load the data at the address specified within the word.
BIM 172 will continue to receive and load data until a second
~ load device address word is sent.
't 2. Write Fixed Format Character. This instruction causes
,,,
the character generator to send to BIM 172 at a specified loca-
tion therein a character pattern as specified by data bits within
the word. The character is of a preselected fixed size which
cannot be altered by other size or font determining commands.
3. Load Character Point Size Register. This message speci-
..,
fies the point size or dimensions of the characters to be printed
to an integer number of points corresponding directly to actual
print point sizes. The bits o~ this message are stored within an
appropriate register within vector generator and arithmetic unit
188 to control the height and type of the characters within the
next character write operation.
.,,
4. Load X0 Register. I'his command causes a register within
vector generator and arithmetic unit 188 to be loaded with the X
starting position of the next line or character.
S. Load Yo Register. This command performs the same
,
- 23 -
, , ' , . .
. .
~ - ,
6~l1
function as above but for the Y axis.
6. Load Character Set Width Register. Receipt of this
message causes the width register within the character generator
to be set with the width specified within the message. - -
7. Write DVA. This message includes both a character code
and an X axis spacing. The character specified is written next
to the previously written character at the specified distance.
8. Ju~p and Store Return. This instruction causes the
current DMA address +l to be saved in a holding buffer within
TCU message decoder 198 along with other con~rol information
such as the currently addressed BIM and other status information
for future use.
9. Jump To Graphic and Return. This message causes the
next instructions for generation of characters, lines, or geo-
metric patterns to be read from minicomputer 167 starting at
the memory address specified in the word type immediately above.
CLU 177 will then continue to extract its instructions and data
.
,~ words from minicomputer 167 in address sequence. Data words
will continue to be thus extracted until a RF,TURN instruction
is received.
10. Execute Transfer Function. One of five different func-
,,~ tions may be performed depending upon a specified function code.
a. Write Line. A line is written between the last two
received end points (Xo, Y0).
b. Erase Line. A line is erased between the last two
,
received end points. End points may be speci-fied with load X0
register or load Yo register commands.
c. Write Raster. A raster, a solid rectangular figure
~ is displayed with opposite corners specified by load X0 register
', 30 and load Yo messages.
- 24 -
''~ ' ' '' ,
, .
d. Erase Raster. Receipt of this instruction causes
a raster which was previously written to be erased.
e. Italic Select. The characters which are written
following receipt of this type of word are written wlth an
italic slant of an angle specified by control bits within the
word.
Each of these message types is decoded by TCU message de-
coder 198 which produces output control signals to microprocessor
190 and work station driver 210 and trackball symbol generators
`~ 10 201 in accordance with the data type decoded. The larger portions
of the operations specified by these control words as decoded
by TCU message decoder 198 are performed within vector generator
, and arithmetic unit 188.
All input data into CLU 177 must pass first through DMA
controller 189 within vector generator and arithmetic unit 188.
Microprocessor 190 within vector generator and arithmetic unit
~ 188 performs several distinct data display functions. From the
l~ supplied end polnts of lines it computes the addresses with BIM172 which are set in the logic condition corresponding to active
display along the length of the line. Scaling ~unctions for all
displayed characters as well as italics generation are also pro-
i~ duced therein. Moreover, character codes furnished to character' image generator 193 within character generator 192 are also
~ relayed as well as data which is intended to be read directly
i ~ into BIM 172 from minicomputer 167.
Character generator 192 has three major components: characterimage generator 193, video formatter 194, and BIM access control
195. Character image generator 193 includes a random access
memory (RAM) which stores bit patterns corresponding to each
~ 30 character or symbol within the system's repertoire o~ characters
,' ' '
- 25 -
. ' ' .
t;4~L
and symbols. This R~ is loaded upon system initialization from
disc memory 166 through minicomputer 167, CLU I/O logic 183,
DMA controller 189, and microprocessor 190. This data need be
entered within the RAM within character image generator 193 only
once for each system initialization. Data for character images
need not be transferred from a central processor or computer for
each refresh cycle as in some other previous systems. Scaling
and italicization of characters is performed through interaction
between microprocessor 190 and character image generator 193 in
~l 10 a way to be described.
Video formatter 194 prepares character and line data from
character image generator 193 and microprocessor 190 respectively
~ . .
J ~ for input to BIM 172 through BIM access control 195. The source
of the data to be formatted is determined~by the opcode as de-
coded by TCU message decoder 198. All X and Y positions, memoTy
select signals and all video type identification signals are
furnished to video formatter 194 from microprocessor 190.
BIM access control 195 controls the writing in and erasing
of data within BIM 172 by video formatter 194. From the timing
signals produced by display refresh timing generator 200 BIM
access control 195 determines the appropriate time within a
refresh cycle at which data from video formatter 194 may be
entered within BIM 172. Feedback signals from BIM 172 to BI~
access control 195 also determine when data may be entered or
erased.
Clock generator 199 produces output clock or timing signals
1 -
~ ~ o~ predetermined frequencies for operating display reresh timing
¦-~ generator 200, micr~processor 190, and BIM access control 195.
From these clock signals disp:Lay refresh timing generator 200
drives horizonta'l and vertical sync pulses for synchronizing
; - Z6 -
,,
.', .
,"~" ' , ' . , ' ' ,
.. . .
64~
the generation of the raster upon each CRT display unit 104.
These horizontal and vertical sync signals are relayed through
work station driver 210 throu~h cables to each work station 100.
Display refresh timing generator 200 also produces timing or
clock signals for operating trackball symbol generators 201,
one of which is provided for each work station 100. The track-
ball symbol is the only video information which is not displayed
via BIM 172. Activation of trackball symbol generators 201 is
made by TCU.message decoder 198. The trackball symbol, pre-
A 10 ferably a simple cross-hatch, is generated at a time determined
by the input timing signals from display refresh timing ~ener-
ator 200. The trackball symbol video signals are added to the
video data signals produced by BIM 172 by video mixers 202 and
coupled therefrom to work stations 100.
~: The control signals to and from each work station 100 are
relayed through work station driver 210. Therein are contained
. driver circuits which are capable of driving signals over cables
.: of the required length. Termination impedances are also pro-
. vided therein for received signals from each work station 100.
Within work station 100 CRT display unit 104 produces a
, raster display in response to horizon~al and vertical sync
. pulses produced within CLU 177. The video signal produced by
l video mixers 202 causes the modulation of the light intensity
.~ along the raster scanned lines producing the.character, line,
.
and raster patterns thereby. CRT display unit 104 may be any
one of a number of commercially available units such as Ball
; Brothers Company (Minneapolis, Minnesota.) TV Monitor Model
THC-25/R.
f: Operator controls and indicators 103, including the alpha-
numeric keyboard 122, programmed function keyboard 121, and
- 27 -
',, . . , '
.
;4~ :
~` ,
trackball unit 120 produces digital signals which are to be
relayed back to minicomputer 167 for control of program oper- ,
ations. Graphic digitizer tablet 102 also produces digital
signals which must be relayed back to minicomputer 167. Each
key depression, change in position of trackball unit 120, or
movement of the graphic digitizer tablet pen causes the produc-
tion of a digital signal which is sampled and stored within
registers within work station I/O logic 212. When minicomputer
167 is prepared to receive new data from work station I/O logic ' ,
212, a polling signal is sent through CPU I/O logic 185 and work
station driver 210. Upon receipt of the polling signal, work
station I/O logic 212 transmits the newly entered data stored
therein in serial fashion back through work station driver 210
and CPU I/O logic 185 to minicomputer 167. As data entered into '
the registers of work station I/O logic 212 is in the form of
parallel binary bits a conversion to serial form is made. This
.
,~f~ ~ may be done by entering,the data in parallel into a shift regis-
¦~f ter then, upon receipt of the polling signal, shifting the data
~ out in serial fashion. Work sta~ion I/O logic 212 includes
i~ 20 signal drivers capable of driving the signals sent to work
station driver ~ along the length of cable employed.
~,~f ~: Referring now to FIG. 8 there is shown therein generally
at 201 a diagram of one of trackball symbol generators 201 of
;; the system shown in FIG. 6. The X and Y positions from trackball
unit 120 are loaded respectively into X and Y position registers
:1 .: '
' 221 and 222. These registers are cleared and reset to X and Y
'~ ' positions corresponding to the center of the display screen wheni ::
',;~ ' ~ the HOME key 125 of trackball unit 120 is pushed. The position
, j ~
' , upon the display screen of the CRT beam is computed by X and Y
~;f,~ 30 counters and encoders 223 and 224 from the horizontal and vertical
: '
- 28 -
.,. f
,
, .. .. . . .
,-, , ; , . . ..
, . . .
,.~ ', ' , , ' ' ' ~ , .
4~1
load pulses produced by display refresh timing generator 200.
When the difference between the trackball position and the current
position of the CRT beam is within a predetermined range of values
for either axis, X and Y counters and decoders 223 and 224 pro-
duce a logical 1 output signal. These output signals are loaded
into video shift register 225 on a continual basis then coupled
to video mixer 202 for addition with the video signal produced
by BIM 172. In this manner, a trackball symbol is produced upon
the display.screen having the form of a cross-hair having vertical
and horizontal segments.
Referring next to FIG. 9 there is shown a block diagram of
character generator ~ with its connections shown to other
portions of the system. Upon initialization of the system,
character pattern data originally stored upon disc memory 166
is loaded via accumulators within microprocessor 190 into a RAM
within character image generator 193. The characte~ patterns
l~ are in the form of a 20 x 18 bit matrix of binary bits where,
,~ for example, a logical 0 indicates a video level the same as the
, background level upon the CRT screen and a logical 1 indicates
i 20 a change in that level either to a moTe OT less intense light
output. The 18 x 20 bit character image patterns are trans-
ferred into the RAM within character image generator 193 and
a series of eighteen 20-bit words. Sixteen of these come from
a first accumulator while four are transferred from a second
accumulator within microprocessor 190 of vector generator and
arithmetic unit 188. Control data signals from microprocessoT
190 are also coupled to video formatter 194 and to microprocessor
command decoder 245 where they are stored for use within char-
acter image generator 193. Decoded opcode in~ormation from TCU
message decoder lg8 is also stored within microprocessor command
, . . . .
. ,, . . ,,, , , , : .
.
~. ., . ~ . . ..
. .. .
. . . .
69~1
.'''
decoder 245 for use in controlling the size and font character-
istics o$ generated characters. Character image generator 193
produces a digital video signal which is coupled through video
formattex 1~4 which in turn relays the signal to BI~ 172 through
BIM access control circuit 195 at appropriate memory load times.
Plgure 11 is a representation of a character "E" such as -
would be stored upon disc memory 166 and within the RAM of character
image generator 193. This pattern shows the character as it would
be displayed upon the screen of one of CRT display units 104 for
~, 10 a fixed font size character. Each row of dots would be displayçd
upon one raster scanned line with the do~s representing portions
of the raster lines which are varied in intensity from the back-
I ground level. A darkened dot may represent a logical 1 within
the binary matrix for each character while a blank space indicates
a logical 0 although the opposite coding scheme can be used.
With reference now to Figure 10, upon system initializa-
tion such as when power is first turned on, data address RAM 254
is loaded with all character patterns within the system's reper-
toire. To accomplish this function, address counter 252, which is
a binary counter, is reset to the 0 state. The first 20-bit byte
of data is then loaded into daka address RAM 254 upon application
thereto of a clock pulse strobe. Address counter 252 is then
incremented to the 1 state and the next 20-bit byte of data loaded.
This operation continues tmtil all character patterns have been
- completely loaded with data address RAM 254. Alternatively, data
,, address RAM 254 may be replaced by a permanently programmed read-
.,;, ,.
only memory in which are stored the character pattern repertoire.
However, the present system is pre~erred using a RAM as the
, . .
character patterns can be changed without having to change
3Q memories.
,
~ - 30 -
,
~ 34~
To write a fixed format size character into BIM 172 without
scaling of the width or height of the character, the character
patterns are read out of data address RAM 254 one 20-bit byte
at a time preferably starting from the bottom line of the char-
acter. To initiate a character generation operation, data address
RAM 254 is addressed with the address location of the lower line
of the first byte of the selected character. This address is
furnished from the accumulators of microprocessor 190 through
multiplexer 250~ The address thus furnished is jammed into
address counter 252 causing it to begin counting in sequence from
this address number. The digital character pat~erns are thereby
read out of data address RAM 254 one 20-bit byte at a time as
address counter 252 sequences through eighteen counts starting
:i
at the furnished address. The twenty output lines each repre-
, senting one bit of data from data address RAM 254 are coupled
to twenty of the inputs of multiplexer 258. The twenty input
lines to multiplexer 258 are coupled therethrough one at a time
to the single output line in response to the select input there-
to furnished by the accumulator of microprocessor 190 coupled
through multiplexer 250. The serial video bit stream produced
thereby is assembled by video formatter 194 and read into BIM
172 at the appropriate BIM cycle time corresponding to the pre-
determined character location.
j: ~
From the single dot matrix representation of each character
stored within data address RAM 254 the character generator system
in accordance with the invention can produce characters of any
required size ranging from typically 7 points to 96 points upon
-~ a display screen of approximately 14" x 14" having 1,024 raster
scan lines. The width of the characters may also be similarly
- 30 varied. Most generally, the dot matrix representations of a
:
~ - 31 -
,.. .. . . . .. .
~ 6 ~
character that is to be scaled from its stored size value is
stretched or reduced independently in vertical and horizontal
axes to achieve the required height or width. This is done
basically by the deleting rows or columns of dots to shrink
the characters in size or reading out the same row or column
more than once in order to increase the character size. FOI
characters smaller than a predetermined minimum size other
operations are performed in addition to the mere deletion of
rows or columns of dots in order to increase the legibility.
To scale a character in height, microprocessor 190 calcu-
lates its scale factor ~H = 18/character height rin points).
a~
is added to the start address for the selected character for
each row of dots to be displayed. The integer portion of the
accumulated total is transmitted through multiplexer 250 and
;~ jammed into address counter 252 to provide a direct address to
data address RAM 254 from`the accumulator registers of micropro-
cessor 190. Only the integer bits are thus used although frac-
tional bits within the accumulated sum are retained and used in
the computation of succeeding addresses. For example, for an
18-point character height ~H - 1 and each row of the dots is
,~ used. For a character height o 36 points ~H = l/2. For this
~,~ case, as the address is computed, the integer portion of the
calculated address will be the same for two successive addresses
although the fractional part changes. Thus, since only the
, integer portion of the accumulated total is used as the character
address, each row of stored data will be used twice in presenting
the character. For a character height of 9 points ~H - 2. The
calculated addresses for this case thus skip e~ery other integer
value and hence e~ery other row of dots stored within data
address RAM 254 producing a character of half the standard
,::
format height.
A similar function is performed for reducing or increasing
the width of characters with the exception of special operations
performed on characters having widths less than 7 points to
increase their legibility. A width scale factor ,~W = 20/character
width (in points) is calculated by microprocessor 190. ,~W is
calculated to an accuracy of nine bits, four integer bits and
five fractional bits. The four integer bits are coupled throu~h
,~ ,v~
decoder 260 and set into width register 262 with a load
10 pulse from microprocessor 190 at the same time that ~he initial
address code is transmitted. If the most significant bit of
-~ the four most significant bits is a 1, the point size is 8 or
larger. For a most significant bit of 0, the point size is 7
or smaller. The most significant of the integer portion of ,~W
is coupled from width register 262 to a select input of multi-
plexer 250. For character point sizes of 8 or larger, this
select line causes five bits from a fiTst accumulator of micro-
processor 190 to be selected as the select code input to multi-
plexer 258. For character widths less than 7 points, this select
20 line causes the output of read-only memory 264 to be chosen as
the select input to multiplexer 258. In the case that the output
of the first accumulator is selected as the select input to multi-
plexer 258 the generation and output of character patterns pro-
ceeds much in the same fashion as for characters of changed height
with the exception that the accumulator output selects which data
bits among the columns of bits form the output at a particular
bit output time. Por example, for ~W = 2 only every otheT column
of bits within each row of bits is selected producing a characteT
of half the standard format size. For ,~W = 1/2, each column
30 within each row will be selected twice in succession. For each
,,
- 33 -
,
,,~ , ,
..
row of dots a select number is computed starting from 0 for the
first column of dots within the row and adding the full 9-bit
value of ~W each time. This is performed with the first accumu-
lator of microprocessor 190.
For characters of widths less than 7 points, the select
number to multiplexer 258 is formed by the output of read-only
memory 264 in accordance with the chart shown in FIG. 12. In
` accordance with the chart of FIG. 12 for character widths less
than 7 points, other output signals are made available for
selection at ~he input multiplexer 258. These additional si~-
nals are produced by logically OR-ing together preselected ones
of the 20 output data lines from data address RAM 254. Read-only
memory 264 is addressed with a 6-bit number the first three
most significant bits being the three least significant bits of
the integer portion of ~W and the three least significant bits
being a count produced by the N-counter of video formatter 194.
This count is equal to one less than the width point si~e at the
start and is incremented by one for each column to be selected.
Referring to the Table shown in FIG. 12 for character slug
width of 8 p~ints, data bits in columns 0~ 3, 5, 8, 10, 13, 15,
and 18 are selected and sent to the video formatter for each
; selected row. These would be the numbers sent from the accumu-
lator as the outputs from RAM 254 are not used in the case of
- character widths of 8 points. For a character ha~ing a width of
7 points, the outputs from RAM 254 first select columns 0, 3, and
5. Then read-only memory 264 produces an output number 20. This
number used as the select input to multiplexer 258 causes one of
the eight outputs from video decoder Z56 to be selected as the
output line to video formatter 194. Thé selected output from
video decoder 256 is formed as the logical OR between column bits
- 34 -
4t;~
8 and 10 of each row. The outputs from read-only memory 264
;; then select in succession column bits 13 15, and 18.
As another example for a character width of 4 points,
read-only memory 264 produces an output of 22 for the first bit
selection. Output number 22 corresponds to an OR-ing of column
bits 0, 3, and 5 as produced by video decoder 256. The outputs
of read-only memory 264 then select in succession columns 8, 10,
and an OR-ing of columns 13, 15, and 18 selected by an output
number 26. For a character slug width of 1 point, it has been
found that the character is too small to be legible at all for
~` the specified screen dimensions and number of scan lines. Con-
sequently, all of the appropriate column bits are OR'd together
to produce an output signal bit should any one column bit be in
the 1 state. The character will be presented simply as a vertical
, line.
Referring next to FIGs. 13-15 the operation of BIM 172 and
its structure will now be explained. As shown diagrammatically
~;~ in the view of FIG. 14, data is supplied for generation of the
video points along each scan line alternately between two memory
modules within BIM 172. Two such memory modules are provided
i for each CRT display unit 104 within each BIM 172. Along each
~ scan line memory module 1 supplies the first 32 bits and each
. ,: .
succeeding odd numbered 32-bit segment. Memory module 2 supplies
the second and all even-numbered segments. Each 32-bit segment
; is presented serially to the video mixer to provide a continuous single-bit data stream video signal.
In FIG 13 is shown a schematic diagram of one memory
module 281 within BIM 172. I'he memory is preferably organized
as a 4 x 32 chip matrix of 1 x 4,096 bit MOS RAM memory chips.
30 Each memory chip 280 has a 12-bit address input with input
.~
- 35 -
, "
"
6'~
:`
a~dress signals designated A0-All. Each memory chip 280 also
has two enable inputs designated CS and CE. Memory chips 280
further include a single serial data input designated DI and
an open collector-type single data output designated DO. The
DO outputs of each column are interconnected as are the DI
inputs and the column select enable CS. The row enable signals -
CE are interconnected among all 32 memory chips 280 within a
- ro~.
`~ The interconnected DO signals from each memory chip 280 in
a column of memory chips is connected to the seTial ;nput of
. one of 4-bit shift registers 282. Each 4-bit shift register 282
`~~ is located by sequentially enabling the columns of memory chips
`:
280 one row at a time by activating the corresponding enable row
signals. The 4-bit output from 4-bit shift reglsters 282 is
transferred in parallel fashlon to one of 8-bit shift reglsters
285. Each 8-bit shift register 285 receives data from two 4-bit
shift registers 282. Four such 8-bit shift registers 285 are
~ provided. To produce a 32-bit segment of the scan line the
i, ~ outputs from 8-bit shift registers 285 are shifted out in serial
i~ 20 fashion from each 8-bit shift register 285 in sequence. The
~; outputs are combined with OR gate 283 to form the output video
signal to video mixer 202.
The commercially available N-channel MOS dynamic RAM chips
such as are here preferred require that each address line deac-
~,
;'A'~ ~ : tivated within a predetermined time period, typically 2 milli-
seconds, in order to assure data retention. These chips are
s~ organized in a rectangular matrix although only one data input
.,,:~ ~
, ~ and output line is provided. Activation of each address line
,~- therefore assures that each column within the memory chip is
~ 30 activated within the required time. It is a characteristic
" ~ ~
~ - 36 -
,... . .
, "
1~ ~ 46 ~
that with a bi~ image memory system in accordance with the
present invention special chip refresh cycles are not necessary
as chip refresh is performed during the normal CRT refresh dis-
play operations.
Refresh for memory chips 280 is accomplished by performing
one recycle on each of 64 possible memory chip address codes as
specified by chip address inputs A0-A5. The memory modules 281
are organized and designated in such a way as to make the total
display refresh read accesses from the 64-chip address groups
at a sufficiently high rate compatible with the overall display
refresh time.
The addressing mode for the rows, columns, and individual
memory chips 280 for one of memory modules 281 is shown in Table
I. The addTess of a 32-bit line segment as displayed along a
single raster line is specified by an 8-bit address in the X
axis (X0-X7) and an ll-bit address in the Y axis (Y0-Y10). As
individual bits are not addressable within a single 32-bit seg-
ment while each raster line is individually addressable, more
bits are required for the Y axis address than for the X axis.
The most significant bits X0 and Y0 are used as dummy bits.
This is useul in addressing the memory for wri~ing in a char-
acter which overlaps the boundary o~ the display area with a
portion in the display area and a portion outside which is non-
displayable. Thus setting either X0 or Y0 to the logical l
state will produce no response but will prevent a remaining
portion of the character rom being wrapped around and written
at the beginning of the opposite side o~ the display screen.
The address inpuks A0-AIl to memory chips 280, the signals
used for chip reresh, the row select signals, the module select
signal, and the column seleck signals are specified in Table I
- 37 -
.
... . ..
below with their correspondence with the X and Y input signals.
During a display refresh cycle, both memory modules 281 servicing
a single CRT display unit 104 are enabled regardless of the state
of any X, Y, or work station group select inputs. X4 and X3
form the row select signals for the rows of memory chips 280
within each memory module 281. Xl and X2 are decoded upon a
binary to four-line basis to produce the signals ENABLE RO~
ENABLE ROW 2. X2 and Xl combined with Y6 through Y0 form the
6-bit memory chip address. It is to be noted that X0 and Y0 are
, 10 in the logical 0 state for all on-screen positions. A logical 1
i~ for either of these signals indicates an off-screen position and
prevents any write operation on the selected memory module. X5
i5 used to select between the two memory modules 281 between
32-bit segmen~s along a raster scan line. X5 operates an AND/OR
gate structure (not shown) for performing this function. X6 and
f~ X7 are decoded again in a 2-binary bit 2-4 line fashion to produce
the column select signals. During the display refresh cycle, the
column select signals are activated in four 8-bit groups in
sequence.
TABLE I
X0 (MSB) Y0 ~MSB)
~l Xl --- Al l Used for Yl ----- All
~ ~ X2 --- A0 I Chip Refresh Y2 ----- A10
,~ ; X34 --~ ~ Row Select Y4 A8
~ X5 --- Module Select Y5 ----- A7
I X6 --- l Column Y6 ----- A5
X7 (LSB) --- ~ Select Y7 ----- A4 Used for
Y8 ----- A3 Chip Refresh
~ Y9 ----- A2
I Y10 (LSB) A6
FOT a selected type of memory chip 280, predetermined ones
of the address input lines must each be selected during a pre-
l, ,
determined minimum time period in order to insure data retention
i: :
within the memory chip. For example, for an Ir.tel Co. 2107B-4,
1~ .
- 38 -
;t~ '
., . , / . ,
~0~
address inputs A0-A5 must each be activated or selected at least
once during a 2 millisecond interval. To insure that this func-
tion is accomplished during the display refresh cycle without
requiring additional chip refresh cycles, the chip address lines
are connected to the X and Y address inputs as specified. It is
to be noted that these signals are not connected in correspondin~
ascending order but are mixed in such a manner to insure that
each line will be activated at least once during each refresh
time period. The same address code is presented to all memory
10 chip addTess inputs for four sequential display refresh cycles
for reading 32 bits from a row of memory chips 280 but a different
row of chips is activated for each of four cycles. The address
code presented to the address inputs of memory chips 280 is
i incremented after cycling through each of the four rows ana the
',~ four rows are again each selected one at a time over the next
. ~
four cycles. This sequence continues such that over the course
of a single scan line time four of the 64 required chip refresh
; codes will have been used in conjunction with display refresh
i,~ cycles with every memory chip 280 on every memory module 281
zo within the system. The Y LSB(Y10) is not used as one of the chip
refresh address inputs because the display raster line refresh is
preferably upon a 2-to-1 interlaced basis as is done with standard
~ television practice so that address Y10 is unchanged during an
,~ entire vertical field time. Y6 through Y9 form the four most
~' significant bits of the chip refresh code inputs. These address
s signals are cycled through once every 16-scan lines. The total
~ chip refresh cycle time is thus equivalent to the 16-scan line
; times or, for the preferred embodiment, approximately 480 ~sec
which is well below the maximum allowable chip reresh time period
30 of 2 msec for ths preferred chip types. Display refresh and hence
- 39
.... . . . . . . .. . . . .
.
,
,. . . . . .
6~a~
chip refresh does not occur during the vertical retrace time
which lasts for the preferred components for a period of 0.9
msec. This time period added to the 480 llsec results in a
worst case chip refresh period of 1.38 msec, still well within
the maximum allowable period.
Complete memory erasures are initiated with a bulk erase
control signal such as shown in the timing diagram of FIG. 15.
In the bulk erase mode, normal display refresh cycles are changed
into write cycles and the 32 bits per memory board access during
a display refres}i cycle are overwritten with zeros. In this
manner the contents of the memory formed from two memory modules
281 is cleared within one full display update cycle within two
consecutive vertical field times. During the bulk erase time,
a busy signal is produced which is relayed back to the CLII I/O
logic 177 to prevent attempts to write data into BIM 172.
In order to write data into memory, both the proper ENABLE
ROW COLUMN SELECT signals must be activated along with the proper
memory address. Data is read into one of memory modules 281
preferably 8 bits at a time. During a memory data read cycle,
memory data from the selected address is loaded into an 8-bit
bit output buffer register (not shown). The contents of the
~-¦ output buffer register is coupled onto a memory output data
' bus or may be used elsewhere in the system.
l Again as shown in the timing diagram of FIG. 15, a display
Z refresh cycle is initiated with DRF and CE control signals. 32
Z~ bits of data are read out simultaneously from each memory module
' through 4-bit shift registers 282 and into 8-bit shift registers
' 285. E~ery load pulse for 8-bit shift registers 285 is followed
by-seven shift clocks which extract the data in serial form. The
output data streams from all of the bit shift registers 285 on
- 40 -
., .
~ ,:, ........... . .
4~
each of two memory modules 281 are combined to form the one
sin~le bit video stream to one of CRT display units 10~.
Referrin~ next to FIG. 16 there is shown a logic diagram
of BIM access control 195. Included therein are chip select
driver circuits 290 for providing buffer amplification for all
display refresh data and control signals including X and Y
addresses and the DRF (Display Refresh) control signal. The
' outputs from the chip select driver circuit are used to select
` data from one of the two memory modules 281 for each CRT display
10unit 104. Outputs from data driver 290 ~orm the data inputs to
each memory module 281.
: BIM access control 195 also performs the function of
j allocating all DRF memory access cycles upon a priority basis.
The various access request signals from video formatter 19~ are
all coupled to input priority encoder 291 which may be a read-only
memory with appropriate coding. Input priority encoder 291 pro-
¦~ ~ duces a 3-bit output signal in the form of a code representing
the activé one of the access request having the highest priority
as determined by the pre-programmed bits within the read-only
; 20 memory. This 3-bit code is ~ransferred to and held within current
~ address holding register 292 upon each succeeding BIM clock pulse.
i When BIM 172 is able to accept a new data input, the BIM acknow-
ledge enable signal is activated causing acknowledge demulti-
plexer 293 to produce upon a single one of its multiple outputs a
~¦~ signal indicating to video formatter 19~ which access request is
to be satisfied and accordingly what data should then be sent
back to BIM access control 195.
BIM access control 195 also includes multiple~er 295 in the
direct data input path. One set of inputs to demultiplexer 293
is the data from video formatter buffer registers while the other
-', .
~ - 41 -
:
, , -
- ' ' . ' , , ' . , .
set o~ inputs ~re all loglcal Q's. During bulk memor~ erase
cycle~t~e logi~cal Q inputs- are selected and written into all
memory~location~. At all other times ~ultiplexer 295 is set
; to accept data inputs from video formatter buffer registers.
Re~erring next to Figure 17 there is shown a block
diagram of microprocessor 190 within arithmetic unit 188. All
input data, control signals, and timing or clock signals from
TCU 176 are coupled into microprocessor 190 from DMA controller
189, DMA controller 189 temporarily stores the address, data,
and control in~ormation received from TCU 176 then transfers
address information to P/R input logic 306 and data and cohtrol
information to P/R data input multiplexer 304 and control memory
31a. As soon as data, control information, or address informa- - -
l tion i5 transferred out of DMA controller 189, a "BUSY" flag
bl or signal is sent to TCU 176 and an appropriate interrupt signal
. ; is also coupled to control memory 310. The "BUSY" flag is reset
by the program control function of microprocessor 190 when
, ,
~ microprocessor 190 is again able to accept new data or address
,
~,~ information.
;. 20 The basic computing elements of microprocessor 190 in-
,, ,
clude P/R memory 308, control memory 310, two accumulators ~AC0 312
and ACl 3141, and general purpose registers 316. The ~unction of
~i~ P/R memory 308 is generally to provide instructions for per~orm-
ing rsquisite arithmetic computations. P/R memory 308 includes
both random access and permanently programmed portions. Both
portions are addressable with the same address lines from P/R
address input logic 306. In a preferred embodiment, the ~irst
64 addresses ~0-63) are random address locations in which data
may be read in from P/R data input multiplexer 304 and stored.
Addresses from 64 to 255 are unused to permit expansion
. . .
, ' -
- 42 -
,
,
','' ' ': ' ' " ., ' ' - ' ' ' .". ' ' ' '' ' , ' '
,; , . ,, , : .
~,,, ; ,
64~
of the random access portion of P/R memory 308. Addresses from
256 onward correspond to the read-only portion of the memory.
Of course, no data may be read into this portion.
P/R memory 308 stores the basic data inputs from TCU 176
such as line end points, character spacing, character width and
height, and italic slant. In the permanently programmed portion
of the P/R memory 308 are stored instructions in the form of
addresses for permanently programmed control memory 310 for con-
trolling accumulators 312 and 314 and general purpose registers
10 316 for performing the requisite arithmetic functions. For
example, when a set character width instruction is received from
TCU 176, the character width W is stored within the random access
'~ portion of P/R memory 308 within the random access portion at an
1i address location reserved only for this number. Each time a data
word is received at DMA controller 189 for setting the character
width, P/R address input logic 306 produces an output address
corresponding to this location within P/R memory 308.
Also, each time this type of word is received, after W is
loaded into the random access portion of P/R memory 308, P/R
20 memory 308 is addressed by a second address from P/R address
input logic 306 corresponding to the address within the perman-
ently programmed portion of P/R memory 308 at which is stored
th~ start address in control memory 310 for the instruction se-
quence which calculates ~W. This address is coupled from P/R
memory 308 on memory bus 318 to the address inputs of control
memory 310. Control memory 310 then produces at its outputs a
sequence of digital instructions for causing accumulators 312 and
314 and general purpose registers 316 to calculate the function
~ aw = 20/W, These instructions are coupled to accumulators 312 and- 30 314 and general purpose registers 316 upon memory bus 318.
"
- ~3 -
.
,'''', .
6~
Two types o$ control sequences are provided by
control memor~ 31Q: the first invol~es onl~ internal computa-
tion requiring no transfer of data to video formatter 194 while
t~e second re~uires such a transfer of data. With the first
type, control memory~ 310 permits a continuous sequence of
arithmetic operations ~y producing on its outputs a continuous
sequence of control signals until the operation specified has
been completed. ~or the second type of computation involving
transfer of data to video formatter 194 an enable signal is
required from video formatter 194 for each transfer of data
thereto. Thus, as each data computation is completed by
control memor~ 310, a separate enable pulse is required from
video formatter 194 before proceeding with the next operation.
Normal data computation sequences are interrupted
:: .
upon receipt at control memory 310 of an interrupt signal from
DMA controller 189. When normai data computation operations
: .~
are thus interrupted, data and control signals may be trans-
ferred from TCU 176 through DMA controller 189 to microprocessor
190 without TCU 176 having to wait and not able to perform other -
needsd operations until microprocessor 190 was finished with its
`~ immediate operations. In this manner a much faster overall system
operation is obtained whereby an operator's inputs produce a faster
,~ response and display of data upon one of CRT display units 104 than
could be done with previously known systems.
Accumulators 312 and 314 are preferably 16-bit high speed
multiple purpose arithmetic units such as, for example, Texas
Ins-truments Company integrated circuit type SN74181. General pur-
pose registers 316 are preferably 16-bit parallel entry data
registers but may alternatively be a 16-bit parallel input random
, 30 access memory. Control memory 310 provides all of the control
, ,
~ ~4
,, ~
,:. . .~ ,
,~ , " , , ' - , . : . '
inputs to the arithmetic units of accumulators 312 and 314 and
controls the interconnection configuration between accumulators
312 and 314 and general purpose registers 316. Control memory
310 can configure accumulator 312 and 314 either as two separate
16-bit accumulators or as a single 32-bit accumulator with appro-
priate interconnection.
Flow diagrams for all the various character gene~ation for-
mats, line generation procedures and raster operations are shown
in FIGs. 18-29. The system rests at the start location speci-
fied at the top of FIG. 9 while no data is being processed and
, a data or control message is being awaited from TCU 176. At
this time all the various flags such as the interrupt flags are
reset. Once a message from TCU 176 is received, the message
type is examined at DMA controller 189 to determine whether OT
not a change in data processing priority is required. Should
the data message received require higher priority than the data
then being processed, the locations with the random access por-
, tions of P/R memory 308 being used for the previous data process-
~l ing operation are moved to another location having a lower
-~ 20 -priority and the new data read into the previously occupied
locations.
A determination is then made of whether an LDF message type
was received. If the message was other than an LDF message for
character generation, the data within the message is transferred
directly to the character generator memory. If no further data
is then available from TCU 176 which is to be transferred to the
character generator memory, the system is reset to the START
positon. If an LDF message type was received, the particular
type of LDF message is decoded as either an EXF message requiring
generation of a line or as an FF message requiring generation of
- ~5 -
,~ .
one or more characters. The EXF and FF message types are
further decoded as specified in the diagrams of FIGs. 19 and
20. If the message type is EXF the possible operations are:
write line, erase line, write raster, erase raster, set italics,
and bulk elase. If the message type is FF, the required oper-
ations are one of: write fixed format character, set character
width, set point size, load X0 or Y0 positions, or write char-
acters in the tabular format.
The data processing sequence for writing and erasing lines
is specified in FIG. 21. The procedure is the same for both
writing and erasing lines with the exception that in the erase
mode an erase flag is set within video formatter 194 which causes
`~ the video signal produced to erase rather than write in new data.The message word is examined to see whether or not a bit is set
within the data field of the message calling for the line to be
dashed. If the line is to be dashed, a flag is set within video
formatter 194, causing the output data stream to be turned off
and on at a predetermined rate thereby making the line to be dis-
played as dashed.
A computation is then made of the quantities ~Xp a~d ~Yp
equal respectively to the length of the line in the X and Y axes.
These are computed as the difference between the end points of
the line. A comparison is then made between ~Xp and ~Yp to
~ determine which is the greater. If ~Xp is greater than or equal
i~ to ~Yp, the quantity ~X, the distance between adjacent dots in
..~
the line along the X axis, is set equal to 1. AY, the distance
between adjacent dots along the Y axis, is set equal to ~Yp/
I~Xpl. The N-counter within video formatter 194 is initialized
to the numeric value of I~Xpl. The same procedure is followed
should ~Yp be ~reater than ~Xp with X and Y interchanged from
- ~6 -
, .:
:,' ,', ', ,' ', '" ' ' . ' . ' ~ . "' .
,
; the previous case. Accumulators 312 and 314 are next initialized
ith X and Y start position values X0 and Y0. Ac~ual computation
of line dot position is then ready to be~ln.
A flag is set within video formatter 194 indicating that a
write operation is ready to commence as soon as video formatter
. ~ . .
194 is able to accept new data. When an enable signal is received
back from video formatter 194, new X and Y positions are computed
' as the present position plus the respective ~X and ~Y quantities.
This computation continues iteratively with the N-counter within
video formatter 194 decremented by one count for each iteration.
When the output of the N-counter has reached 0, the line is
finished and the system is reset to the start position.
The procedure for writing and erasing rasters is shown in
FIG. 22. Again, the procedure is the same for writing and eras-
{~ ing except that an erase flag is set within video formatter 194
in case of an erasing operation. The quantities ~X and ~Y are
set to the minimum interdot spacing of 1. The N-counter within
video formatter 194 is initialized to the value of ~Yp . The
M-counter is formed by one of accumulators 312 or 314 in a loop
with one of general purpose re~isters 316. The X and Y values
. . ~
are initialized to the start position of X0 and Y0 indicative
of the upper left hand corner oE the raster to be written or
erased. axp and aYp represent the distance from X0 and Y0 to
the opposite corner of the raster.
Video formatter 194 is then signalled with the write flag
,~ to indicate that new data points are then available. As soon as
j~ video formatter 194 pToduces an enable signal indicating that it
is then able to accept new data. At this time, a new X position
is computed as the present X position plus ax. New X positions
are then continually computed while the value in the N-counter
.',
... .
- 47 -
:
. ~ , ,
: ,, , , . : ' '
4~41
is decremented once for each new X position. When the count
within the N-counter reaches 0, the M-counter is decremented by
one count. If the value in the M-counter has not reached 0, the
Y value is recomputed as the present Y position plus aY. The
write flag to video formatter 194 is again reset and the N-
counter reinitialized. New X positions are then computed for
each line in Y. The process continues until the value computed
by the M-counter reaches 0 at which time the system is reset to
START.
'10 For an EXF word indicating setting of italics tilt, the
italics tilt is specified as a binary number indicative of the
distance to the right or left from the start position of the
previous line of a character each succeeding line of data within
the character is to be begun. This value is stored in one of
general purpose registers 316 and a flag is sent to video for-
~,~ matter 194 indicating that the next sequence of characters is
;, to be written in italics with the specified slant.
For the bulk erase mode as shown in FIG. 24, the video for-
matter bulk erase flag is set. As soon as an enable command is
received from video formatter 194, control is returned to the
start position.
. The procedure for writing characters into BIM 172 is specified
in FIG. 25. For fixed format characters the procedure starts at
reference G while for tab characters the procedure starts at
l reference L. For fixed format (i.e., fixed size of 6 point width
i and 12 point height) characters, the character ~ width is first
, set to a fixed format value of 20/6. W is set equal to 6 and
~' ~ the height ~l is set equal to 18/12 while ~l is set equal to 12.
'~! The tab value TAB ~X, the spacing between adjacent characters,
is set equal to 12 also. For tabular characters the TAB ~X value
~8 -
,, . . .,,: ,, ,. .,, " , , , ,, . .:"
,, ., ': .
4~
is set to the tab value specified in the character word from
TCU 176. The X and Y values are initialize~ to thc start positions
XO and Y0. The erase flag is sent to video formatter 194 if the
reverse bit within the character word is set. The M-counter
formed by one of accumulators 312 or 314 and one of general
purpose registers 316 is initialized to the value of H. The width
register withing the character generator is initialized to W as
is the N-counter within video formatter 194. The character start
address code for addressing the character generator RAM is set to
~ 10 the value of the character code multiplied by 18. The character
l video multiplexer code is initialized to a value of 0. The video
i source code to video formatter 194 is set for video formatter 194
to receive data from the character generator.
As soon as an enable signal is received from video formatter
i: :
194, the first line of dots along the X axis for the first char-
acter is read out of the character generator and coupled to video
formatter 194. The X value is then incremented to the present
position plus the value TAB ~X. The character video multiplexer
code is then incremented by a value of W. The N-counter is
,~ 20 ~~decremented by one count for each dot in the X axis for each
,~ character. Once the count output of N-counter has reached 0 the
M-counter ls decremented by one count. If the count within the
~ M-counter has not reached 0, a determination is made whether or
¦ not the italic flag is set. If it is set, the value o~ the X
i~ position is incremented by the value of the italics slant Ix.
,~ The N-counter is then reinitialized to W and the character start
address is incremented by a value of ~H. The Y value is decre-
mented by one scan line. The video source code is again set
~, and the procedure continued until the value within the M-counter
has reached 0 at which time control is returned to the start
position.
- 49 -
.
The operations for setting width, point size, and loading
X and Y positions are simply register loading operations as
specified in the diagrams of FIGs. 26-29. For the set width oper-
ation, ~W is computed as 20/set width (the width specified in the
corresponding character word with W set direct?y equal to the set
width). Similarly, for setting the point size, ~H is computed as
18/point size as specified in the appropriate character word. H
is set equal directly to the value of the point size.
Although the above specified operations may be performed
with a number of commercially available microprocessors or mini-
computers, the structure shown in FIG. 17 is preferred for its
speed of operation as used with the present invention.
Referring next to FIG. 30 there is shown therein a block
diagram of video formatter 194. The clock signal, acknowledge
inputs from BIM 172 and control and data inputs from microprocessor
190 are coupled into video formatter control logic 350 where the
signals are used and distributed as required. Also produced
therein is the enable signal to microprocessoT 190 when video
formatter control lo~gic 350 detects that no further data tTansfer
20 operations are then taking place within video formatteT 194 so
that new data inputs may be accepted.
N-counteT 352 is also provided within video formatteT 194.
,
N-counter 352 is preset by data from P/R memory 308 within micro-
' ~ processor 190 upon application of a load pulse. As explained
earlier, N-counter 352 is loaded with a preset value then decre-
mented once for each bit or byte transferred from micropTocessor
190 to video formatter 194. N-counter 352 is generally decre-
mented by one count for each data transfer between microprocessor
190 and video formatter 194.
~lso provided is bit counter 364 which receives data inputs
- 50 -
.~
, . . . . .
,; '': , ' "' i '' , ' . .;,
, .,. , "
. .
, .. . . . . . . . . .
10~4~
from microprocessor 190 through bit counter holding register 326.
Bit counter holding register 326 is loaded upon application of a
load pulse from microprocessor 190. Bit counter 364 is generally
used to produce dashed lines with the length of the dashes deter-
mined by the cycling rate of bit counter 364 which in turn is
determined by the value of the incoming presetting code. The
output data for both line and character data passes through data
latch 376 and data buffer register 378 before being coupled to BIM --
172. The output of bit counter 364, in the case of dashed lines,
is passed through multiplexer 370 to enable inputs of mask latch
372 and data latch 376 to alternately enable and disable the line
video data so as to produce a dashed line effect.
Data is transferred from video formatter 194 to BIM 172 in
8-bit bytes. In some cases it is desirable to transfer fewer
than 8 bits at one time. Mask bits are thus provided for each
data bit through mask latch 372 and mask buffer 374. Activation
of one of the mask bit output signals from mask buffer 374 in-
structs BIM 172 to ignore the corresponding data bit from data
buffer register 378. The signals from mask buffer register 374
and data buffer register 378 are transferred to BIM 172 simul-
' taneously.
` Also provided is an active code register 354 which stores
the opcode of the particular data type then being acted upon.
Among its functions, active code register 354 produces an enable
~'~ signal to bit counter 364 in the case of dashed lines. Active
, code register 354 also sends a signal to BIM access type decoder
', 358 which in turn produces a signal relayed to BIM 172 indicativeof whether data is to be read in or erased from the memory.
Active flag register 360 is set in the active state when video
formatter 194 is actively processing and transerring data to
':
- 51 -
,'~ '' " ' .
;4~
BI~I 172. Its output is fed back to microprocessor 190.
Video select register 380 stores a code determinative of
the type of data to be loaded into BIM 172. This code is coupled
to the select inputs of multiplexer 370 causing it to select for
the data coupled to BIM 172 one of character, vector (line), or
erase data sources. In the case of vectors, multiplexer 370
selects all logical ones as inputs. However, for dashed ~ectors
or lines, the output of bit counter 364 is selected. For erasing
data previously stored in BIM 172, the all logical 0's input is
selected
The X and Y position inputs used for addressing locations
within BIM 172 are coupled from the first accumulator of micro- -
processor 190 through X and Y position buffers 384 and 386. X
position buffer 384 is loaded with the same load pulse that loads
~,
mask buffer 374 and data buffer register 378. The Y position is
loaded into Y position buffer 386 through an externally supplied
LOAD Y REGISTER pulse. Memory select buffer 382 is loaded with
a code from microprocessor 190 that is indicative of the woTk
station upon which the data then being generated is to be dis-
played~ This code thus selects the memory modules within BIM
172 into which the data is to be written or erased for display
.,
upon the proper work station 104.
Referring next to PIG. 31 there is shown a diagram of clock
generator 199 and display refresh timing generator 200~ Clock
! generator 199 is a square wave or rectangular pulse oscillator
~ of well-known design. Its frequency is preferably crystal con-
i- trolled. The output pulse stream from clock generator 199 is
coupled to high speed counter 402. High speed counter 402
divides the higher frequency output from clock generator 199 to
the various clock ~requencies required within the various
.
- 52 -
;
. ~,,, ; , . . . . . . . .
~; . .. . .
,
~ 346~1
components within the system. Signal buffers 408 amplify the
generated clock pulse streams for use throughout the system.
Ilorizontal counter 404 further counts down the output of
high speed counter 402 producing an output pulse corresponding
to the start time of each horizontal scan line. Vertical counter
406 further divides the output of horizontal counter 404 pro-
ducing an output pulse corresponding to the start time of each
vertical retrace. For a system having 1,024 interlaced scan
' lines, vertical counter 406 produces one pulse for each 512
- 10 pulses from horizontal counter 404. Horizontal signal buffers
412 and vertical signal buffers 414 amplify and distribute the
respective horizontal and vertical sync pulses produced at the
outputs of horizontal counter 404 and vertical counter 406 for
`3:
j~ distribution within the system. X address counter 410 operates
upon the output of horizontal counter 404 to produce a digital
l output number indicative of the 32-bit segment of each horizontalscan line being acted upon at any given instant. X address
counter 410 is reset by horizontal counter 404 at the beginning
of each scan line. In a similar fashion, Y address counte~ 416
,!
produces an output number indicative of the Y position or equi-
~i~ valently the number of the scan line or data within BIM 172 then
being acted upon.
This completes the description of the preferred embodiments
of the invention. Although preferred embodiments of the invention
have been described, it is believed that numerous modifications
i and alterations would be apparent to one having ordinary skill inthe art without departing from the spirit and scope of the
invention.
',
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