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Sommaire du brevet 1085936 

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  • lorsque la demande peut être examinée par le public;
  • lorsque le brevet est émis (délivrance).
(12) Brevet: (11) CA 1085936
(21) Numéro de la demande: 1085936
(54) Titre français: AMPLIFICATEUR PARAMETRIQUE COMPENSE A DIODES
(54) Titre anglais: BALANCED-DIODE PARAMETRIC AMPLIFIER
Statut: Durée expirée - après l'octroi
Données bibliographiques
(51) Classification internationale des brevets (CIB):
  • H3F 7/04 (2006.01)
(72) Inventeurs :
  • MARMIANI, ANTHONY (Etats-Unis d'Amérique)
  • JAMES, DAVID S. (Canada)
  • STUBBS, MALCOLM G. (Canada)
  • MINKUS, ETTORE (Canada)
  • BOUCHARD, J. FERNAND (Canada)
(73) Titulaires :
  • HER MAJESTY THE QUEEN, IN RIGHT OF CANADA, AS REPRESENTED BY THE MINISTER OF COMMUNICATIONS
(71) Demandeurs :
  • HER MAJESTY THE QUEEN, IN RIGHT OF CANADA, AS REPRESENTED BY THE MINISTER OF COMMUNICATIONS (Canada)
(74) Agent: EDWARD RYMEKRYMEK, EDWARD
(74) Co-agent:
(45) Délivré: 1980-09-16
(22) Date de dépôt: 1978-01-19
Licence disponible: S.O.
Cédé au domaine public: S.O.
(25) Langue des documents déposés: Anglais

Traité de coopération en matière de brevets (PCT): Non

(30) Données de priorité de la demande: S.O.

Abrégés

Abrégé anglais


TITLE
BALANCED-DIODE PARAMETRIC AMPLIFIER
INVENTORS
David S. James
Anthony Marmiani
Malcolm G. Stubbs
Ettore Minkus
J. Fernand Bouchard
ABSTRACT OF THE DISCLOSURE
A double-diode parametric amplifier including
a structure having a conductive base with a protruding
conductive pedestal, a non-conductive ring fixed to the
base about the pedestal forming an enclosure, and a non-
conductive cap to enclose the enclosure. The idler
circuit is completely contained within the enclosure and
includes a first varactor diode, a capacitor and a second
varactor diode connected in series; this series circuit
is connected to the conductive base of the package at
each end forming a loop. Leads connected to the two sides
of the capacitor are connected to two terminals on the ring.
These two terminals are used to couple the signal and pump
frequencies to the parametric amplifier, to couple the
output signal from the parametric amplifier and to apply
bias voltage independently to each varactor.

Revendications

Note : Les revendications sont présentées dans la langue officielle dans laquelle elles ont été soumises.


CLAIMS:
1. A parametric amplifier comprising:
- conductive base means having pedestal means
protruding from the base means;
- non-conductive ring means positioned on the base
means forming an enclosure about the pedestal means such that
the pedestal means is located to one side of the enclosure,
the ring means further including first and second terminal
means leading to and protruding beyond the outer wall of
the ring means;
- non-conductive cap means positioned and bonded
over the ring means to seal the enclosure;
- first and second varactor diode means and
capacitor means, the first diode means, the capacitor means
and the second diode means being serially connected between
the pedestal means and the base means; and
- first and second lead means, the first lead means
connecting the first terminal means to one side of the
capacitor means and the second lead means connecting the
second terminal means to the other side of the capacitor
means.
2. A parametric amplifier as claimed in claim 1 which
further includes non-conductive stand-off means positioned
on the conductive base means at the center of the enclosure,
the first varactor diode means and the capacitor means being
located on the non-conductive stand-off means.
3. A parametric amplifier as claimed in claim 2
which further includes first and second parallel conductive
tracks on the non-conductive stand-off means, the capacitor
means having one side connected to the first track and the
other side connected to second track, the first lead means

being connected to the first track and the second lead
means being connected to the second track, the first diode
means being located on the first track and having a first
diode terminal connected directly to the first track and a
second diode terminal connected to third lead means connected
to the pedestal means, the second diode means having a first
diode terminal connected directly to the base means and a
second diode terminal connected to fourth lead means
connected to the second track.
4. A parametric amplifier as claimed in claim 3
wherein the first diode terminal of the first and second
diode means is the anode of the diode means and the second
terminal of the first and second diode is the cathode of
the diode means.
5. A parametric amplifier as claimed in claim 4
wherein the first and second diode means are substantially
balanced GaAs diffused mesa varactors.
6. A parametric amplifier as claimed in claim 4
wherein the first and second diode means are substantially
balanced quasi-planar Schottky varactors.
7. A parametric amplifier as claimed in claim 5
wherein the capacitor means is a thin film parallel
plate capacitor.

Description

Note : Les descriptions sont présentées dans la langue officielle dans laquelle elles ont été soumises.


1~)85936
3~_XGROUND OF THE I~IVENTION
This invention is directed to a parametric
amplifier and in particular to a parametric amplifier ha~ g
a balanced pair of varactor diodes.
Parametric amplifiers having three-frequency paramp
action are usually single diode devices. However these
devices normally operate at low input frequency and narrow
bandwidth. Recently, double-diode parametric amplifiers have
been developed to overcome these limitations to a certain
degree. Such devices include two diodes connected in a
~ack-to-back arrangement or in a parallel arrangement as
described in the following references: "A Broadband
Parametric Amplifier" - J.F. Gittins et al, Int. J. Electron, ;
1968, vol. 24, pp. 333-351; "A Broadband Balanced Idler
Circuit for Parametric Amplifiers" - J. D. Pearson et al,
Radio and Electronic Eng., vol. 27, 1964, p. 331;
I'Bandwidth of a Balanced Micropill-Diode Parametric Amplifier" -
C.S. Aitchison et al, IEEE Trans. MTT, January 1968, pp. 46-47;
"Active Reactance Compensation of Parametric Amplifier"
~20 C. S. Aitchison et al, Electron Letter, April 1968, vol. 5,
no. 7~ pp. 139-140; United States Patent 3,596,197, issued
July 27, 1971 to P. Chorney; United States Patent 3,833,857
:issued September 3, 1974 to J. C. Fletcher; United States
Patent 3,842,359 issued October 15, 1974 to L.E. Dickens; and
United States Patent 3,842,360 issued October 15, 1974 to
L. E. Dickens. ;
SV~IMARY OF T~IE INVENTION
It is therefore an object of this invention to
provide a paxametric amplifier for high frequenc~ input
signals ha~.7ing good bandwldth performance.
~' : . .~ , .: -

1085936
It is another object of this invention to provide
a parametric amplifier which is economic to construct using
MIC technology.
It is a further object of this invention to provide
a parametric amplifier in which idler resonance-frequency of
the diode's assembly may be pretested.
It is another object of this invention to provide
a double-diode parametric amplifier in which each diode may
be independently biased.
It is a further object of this invention to provide
a double-diode parametric amplifier fcr input signals in
the order of 12 giga-hertz. ;
These and other objects are achieved in a parametric
amplifier which structurally includes a conductive base having
a pedestal protruding from the top surface of the base, a non-
conductive ring positioned on the top surface of the base to
form a cavity about the pedestal such that the pedestal is
located to one side o the cavity, a first and second terminal
leading out of the ring wall, and a non-conductive cap
positioned over the ring to enclose the cavity. The para-
metric amplifier circuit includes a first and a second varactor
diode and a capacitor, the first diode, the capacitor and the
second diode being serially connected through the package's
pedestal. A first lead connects the first terminal to
one side of the capacitor and a second lead connects the
second terminal to -the other side of the capacitor.
Structurally the parametric amplifier circuit may
also include a non-conductive stand-off positioned on the
conductive pedestal with the first varactor diode and the
3~ capacitor being located thereon.
--2--

l~B5936
In order to rnake the col~nections between the diodes,
the capacitor and the leads, first and second parallel
conductive tracks are located on the non-conductive stan~-ofr.
The capacitor is connected between these tracks, the firs-
lead is connected to the first track and the second lead is
connected to the second track. The first diode is located on
the first track such that a first diode terminal is connected
directly to the first track, and the second terminal of the
first diode is connected to a third lead which in turn is
connected to the pedestal. The second diode is located on the
base such that a first diode terminal is connected directly
to the base, and the second diode terminal is connected to
a fourth lead which in turn is connected to the second
track. The circuit may further be arranged such that the ~
first diode terminal of the first and second diodes is the '
anode of the diode and the second terminal of the first and
second diode is the cathode of the diode.
BRIEF DESCRIPTION OF THE DRAWINGS
In the drawings~
Figure 1 is ~ simplified schematic circuit
diagram of the parametric amplifier;
Figure 2 is a top view of the parametric amplifier
structure; and
Figure 3 is a side view of the parametric amplifier
structure.
DESCR rPTION OE' THE PREFERRED EMBODIMF.NT
Figure 1 schematically illustrates the circuit
diagram of the parametric amplifier in accordance with the
present invention. The idler circuit consists of a pair
of varactor diodes 1 and 2 connected back to back with the
anode of diode 1 connectecl to ground via a lead inductance
--3--
'

lV8~936
3 and the cathode of diode 2 connected directly to ground.
To complete the idler circuit, the cathode of diode 1 is
connected to capacitor 4 which in turn is connected to the
anode o~ diode 2 through a lead inductance 5. The para- ,!
~netric amplifier further includes two inp~t leads represented
by inductors 6 and 7 to which the signal frequency to be
amplified and the pump frequency are applied as indicated
by arrows 8. These same leads 6 and 7 are also used to
obtain the amplified output signal from the amplifier as
lQ indicated by arrows 9. In addition, leads 6 and 7 are used
to couple back-biasing voltages Vl and V2 respectively to
the diodes 1 and 2. .~ .;
The structure of the parametric amplifier is shown
in detail in figure 2 which is a top-view of the amplifier
arrangement and in figure 3 which is a side-view of the
amplifier arrangement with a section of the outer ring cut
away for clarity. Corresponding components in figures 2 and
3 carry identical reference numbers which are the same as the
reference numbers for corresponding components in figure 1.
The amplifier structure is packaged on a unitary :
metal base (pedestal) 10 having a threaded stud 11
projecting from the bottom and a flat surfaced mounting
section 12 on which the components of the amplifier
are fixed. ~rhe mounting section 12 is circular in shape
as seen in figure 2 and further inclv.des a pedestal 13
rising above the mounting sec-tion 12. The metal base may
be made from Kovar and gold plated to assure good
conductivity as the ground terminal. A ceramic ring i4
; is fixed to the base 10 so as to be hermetically sea~ed
~0 and forms an enclosure about the mounting section 12. The
ring 1~ includes two parallel metal strip terminals 15 and 16
--4--

1~)8S936
which also may be gold plated Kovar, fixed within recesses
in the ceramic riny 14. The amplifier is hermetically
enclosed by a ceramic cap 17 shown in cross secti~n in
figure 3. The cap 17 has a recess 18 of diameter simila~
to the inside diameter of ring 14 and has further small
recesses 19 and 20 above terminals 15 and 16 to provide
space for connecting leads. A quartz stand-off 21 is located
on the mounting section 12 at the center of the enclosure and
two metallized tracks 22 and 23 are located on the stand-off
1~ 21 substantially parallel to the side of the pedestal 13.
As described with respect to figure 1, the idler
circuit consists of a pair of balanced diodes 1 and 2, a
capacitor 4 and lead inductances 3 and 5. The cathode of ~-
diode 1 is fixed to track 22 and its anode is connected
to grounded pedestal 13 by a lead 3. The cathode of diode 2
is fixed to the mounting surface 12 and its anode is
connected to track 23 by a lead 5. A capacitor 4 is coupled
across tracks 22 and 23 to complete the idler circuit. The
idler circuit is connected to terminals 15 and 16 by leads
6 and 7 which do not form part of the idler circuit.
The diodes 1 and 2 may be GaAs diffused mesa
varactor chips or quasi-planar Schottky varactors. It is
preferred that the diodes be perfectly balanced, however
since they are independently biased, any unbalance may be
adjusted by applying voltages Vl and V2 having a slight
difference in amplitude.
For capacitor 4, a MOS or MNS capacitor chip may
be used, however such a capacitor ~lould have the proble~
of undesirable inductance involved in the contact strip. It
~0 ~ould thus be preferrable to use a thin film parallel-plate
capacltor fabricated as an inte~ral part of the ~uartz
stand-off 21, and rî.etallized tracks 22 and 23.
--5-
. - ' : - , ~ , ~

1085936
The pump frequency, the input signal and the
bias voltage are applied to terminal tabs 15 and 16 in
any conventional manner. The pump frequency and the
input signal are equally apnlied to the terminals lS
and 16 while appropriate bias voltages are applied
independently to terminals 15 and 16.
.: :
.
, .~:: . . -
.

Dessin représentatif

Désolé, le dessin représentatif concernant le document de brevet no 1085936 est introuvable.

États administratifs

2024-08-01 : Dans le cadre de la transition vers les Brevets de nouvelle génération (BNG), la base de données sur les brevets canadiens (BDBC) contient désormais un Historique d'événement plus détaillé, qui reproduit le Journal des événements de notre nouvelle solution interne.

Veuillez noter que les événements débutant par « Inactive : » se réfèrent à des événements qui ne sont plus utilisés dans notre nouvelle solution interne.

Pour une meilleure compréhension de l'état de la demande ou brevet qui figure sur cette page, la rubrique Mise en garde , et les descriptions de Brevet , Historique d'événement , Taxes périodiques et Historique des paiements devraient être consultées.

Historique d'événement

Description Date
Inactive : Périmé (brevet sous l'ancienne loi) date de péremption possible la plus tardive 1997-09-16
Accordé par délivrance 1980-09-16

Historique d'abandonnement

Il n'y a pas d'historique d'abandonnement

Titulaires au dossier

Les titulaires actuels et antérieures au dossier sont affichés en ordre alphabétique.

Titulaires actuels au dossier
HER MAJESTY THE QUEEN, IN RIGHT OF CANADA, AS REPRESENTED BY THE MINISTER OF COMMUNICATIONS
Titulaires antérieures au dossier
ANTHONY MARMIANI
DAVID S. JAMES
ETTORE MINKUS
J. FERNAND BOUCHARD
MALCOLM G. STUBBS
Les propriétaires antérieurs qui ne figurent pas dans la liste des « Propriétaires au dossier » apparaîtront dans d'autres documents au dossier.
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Description du
Document 
Date
(yyyy-mm-dd) 
Nombre de pages   Taille de l'image (Ko) 
Abrégé 1994-04-07 1 30
Revendications 1994-04-07 2 67
Page couverture 1994-04-07 1 18
Dessins 1994-04-07 2 38
Description 1994-04-07 6 208