Note : Les descriptions sont présentées dans la langue officielle dans laquelle elles ont été soumises.
M. J. GINGELL - 12
(Revision)
~3~ '7
Backqround of he Invention
This invention relates to digital-to-analog (D/A) converters such
as are used in pulse code modulation systems of communication.
The function of the ideal D/A converter ls to operate on a digital
number and convert it to a voltage or current proportional to the number.
In communication systems the digital numbers represent points taken
at regular samplin~ intervals from a continuous waveform. The ideal
converter should in this case produce a continuous analog output
which is the result of drawing a smooth curve through the sample
points and which contains no component above half sampling irequency.
In practlce this is usually achieved using a precision-switched resistor
ladder network which holds each sample constant for one sample
period and then suppressing unwanted components in the output
spectrum by means of a low pass filter. Ladder networks are expen-
sive and cannot easily be integrated with the degree of precision
required in communication systems.
An alternative that ls more amenable to digital integration uses
a rate multiplier. This is a simple logical device produclng an out-
put pulse stream whose mean denslty is proportional to a clock frequency
times the input number. Since the input number is changed at each
sample instant the clock frequency must be equal to the sampling
frequency times the number of possible levels in the input number.
For example a 12 bit linear PCM at 8kHz (kilohertz) samplirlg rate
would require a clock frequency of 32.768MHz (megahertz). A com-
promise converts the PCM words to sign, magnitude and scaling com~
ponents. The magnitude is applied to a rate multiplier running at a
more modest clock frequency the output of which is scaled and signed
by analog means.
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M. J. GINGELL - 12
~LO~ (Revlsion)
Summary of the Invention
An object of the present invention is to provide an improved D/A
converter .
A feature of the present invention is the provision of a digital-
to-analog converter for a pulse code modulated (PCM) signal having
a plurality of code groups and a given sampling rate comprising: a
source of the PCM signal; first means coupled to the output of the
source for inc`reasing the given sampling rate; second means coupled
to the output of the first means for selecting a predetermined number
of the most significant bits of each of the code groups of the increased
sampling rate PCM signal; and third means coupled to the output of
the second means for converting the most significant bits into a pulse
stream having a mean density which is proportional to an analog
signal represented by the plurality of code groups.
The object of the converter according to the present Invention is
to increase the sampling rate of the signal to a point where, by reducing
the number of bits per sample, only a minimal digital-to-analog con-
verter is required. This may require only 3 or 4 bits and can then be
implemented using a rate multiplier to produce an output pulse stream
the mean density of which is proportional to analog signal amplitude.
Brief Description of the Drawincr
Above-mentioned and other features and objects of this invention
will become more apparent by reference to the following description
taken in conjunction with the accompanying drawing, in which:
Fig. 1 is a block dia~ram illustrating the basic principle of a
converter according to the principles of the present invention;
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(Revlsion)
Fig. 2 is a block diagram of a simple rate multiplier and logic
waveforms therefor;
Fig. 3 is a block diagram of a modification of the converter of
Fig. 1 incorporating a simple error correction arrangement;
Fig. 4 is a block diagram of a more complex form of error cor-
recting arrangement;
Fig. 5 illustrates graphically the noise spectrum of the digital-
to-analog converter of Fig. 1 when it incorporates the error correcting
arrangement of Fig. 4;
Fig. 6 is a block diagram of a simple interpolator for increasing
the signal sampling rate and a curve illustrating the operation of the
interpolator;
Fig. 7 is a block diagram of an alternative form of interpolator;
Flg. 8 is a block diagram of a practical form of digital-to-analog
lS converter according to the principles of the present invention;
` Fig. 9 is a block diagram of a prescaling arrangement to prevent
overflow iD the adders of Fig. 8;
Flg. 10 is a block diagram of a modified converter for use in a
digltal FDM (frequency division multiplex) system; and
Flg. 11 is a block diagram of a non-recursive filter suitable for
use in the converter of Fi~. 10 and curves illustrating the operation of
;` ' the non-recurs ive filter .
Description of the Preferred Embodiments
In the arrangcment shown in Fig. 1 a pulse code modulation signal,
typically 12-bit code groups at an 8kHz sampling frequency, is applied
to an interpolator 1, where the sampling frequency is increased, for
example to 2561~Hz. The signal still consists of 12-bit ~roups at the
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M. J. GINGELL - 12
(Revis ion)
higher sampling frequency. The signal is then passed through a
quantizer 2, which rounds the 12-bit groups to the four most signifi-
cant bits, and applied to a rate multiplier 3. The pulse density modulated
signal output from the rate multiplier is then passed through a low pass
filter 4 to yield an analog signal.
The rate multiplier is a simple logic arrangement as shown in Fig.
2. A clock frequency fc is fed to a synchronous counter 5, the outputs
of which are fed to four AND gates 6 - 9 where they are gated with the
four most significant digits of the signal. The AND gate outputs are
combined in an OR gate 10 yielding the pulse density output.
However, this arrangement is very crude and considerable quantiz-
ing noise will result. The noise is given by
-2N
fB .2 . Ps Watts
Nolse Power = 0.75 fs
where fB is the noise bandwidth
fs is the sampling frequency
N is the number of blts
Ps is the rms (root meansquare) power of the
peak sinewave slgnal that can be
transmitted .
For example, in a PCM system where
fB = 3. lkHz (300 - 3400Hz)
fs = 256kHz
N = 4
Ps = 2mW (milliwatts) (+3dBmO crash point)
the noise would be 0.126`uW (microwatts) = -39dBmO (decibel referred
o~
to s~Ke milliwatts)
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(Revision)
This performance would be insufficient for most purposes so
suppose that an error signal is generated and fed back through a
digital transfer function G(Z) as shown in Figure 3.
The 12-bit input to the quantizer 2 has subtracted from it the
4-bit output in circuit 11, and the difference (error) is applied to an
error filter 12 to generate an error signal. The error signal is then
fed back to the quantizer input, with the appropriate polarity, via
adder 13.
The original quantized output can be equated to noise plus a
straight through transfer of the signal. The error corrected output
then becomes
VOUT = VIN + (l-G(Z)) * Noise
where
Z = Cj~T = Cos ~T + jSin L~T
T = Delay time
For stablllty G(Z) must contain at least one sample time delay
and so the most elementary form ls when G(Z) = z-l i.e. a single
delay. In this case the noise is multiplied by l-Z~l which causes con-
siderable attenuation at low frequencies at the expense of noise
enhancement at higher frequencies. The attenuation in dB (decibel)
is given by
- 20 log 11 _ z-l~
= - 20 log ¦1 - (Cos 0 + j Sin 0~1
= - 10 lo~ (2(1 - Cos 0)) = - 20 log (2 Sln ~)
2 5 where 0 = 2 ~f/f s
For example the already cited attenuation at D. C. (direct current)
is infinity falling to 27.6dB at 3400Hz (hertz). Although this is a
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worthwhile improvement it is not enough to satisfy the requirements
of such systems as 30 time slot PCM.
Once the principle is established it is easy to see how to extend
the design for improved performance. It is generally expedient to use
round numbers for the coefficients of G(Z) and to use a low order
function to keep the hardware complexity down. The next step in
improving the performance ls to make l-G(Z) = (l-Z-1)2 i.e. G(Z) =
2Z 1 _ z-2 ~,vhich doubles the noise attenuation over the band of
interest while keeping the arithmetic operations simple. This is shown
in Flg. 4. Again, for the example already cited, the noise will now
rise from zero at D. C. to 3.94 pW/kHz at 3400Hz. Total noise over
the band 300 to 3400Hz is 2.70pWO (picowatts with reference to :z~
o~
milllwatts) or 1.25 pWOp (picowatts with reference to zoro plcowatts).
The noise spectrum for this case is shown in Fig. 5.
It should be emphasized that the theoretical noise figure formula
ls approxlmate and assumes that the quantlzatlon errors are uncor-
related wlth the slgnal. Thls ls not entirely true, partlcularly at low
slgnal levels, but the theory can at least provide a good flrst estlmate
on which to base further work. The table below gives an estimate
of the expected performance of the arrangement of Figure 4 for various
conditions .
~ Noise .3 - 3.4kHz
Sampllng Frequency No. of
kHz BltspWO dBmO
1024 2.042 - 103.7
512 3.337 - 94.7
256 42.69 - 85.7
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For any given sampling frequency an extra bit will improve the
signal to noise ratio by 6dB.
Fig. 6 shows the use of an interpolator for stepping up the sampling
rate from 8kHz to 256kHz. In fact, for correct operation of the con-
verter a complicated interpolator is not necessary. The converter
will work perfectly well lf the same 8kHz sample is delivered to it
32 times (i.e. at 256kHz rate) follcwed by the next sample 32 times
and so on. This is illustrated in Fig. 6. The 12-bit serial groups are
read into a shift register 14 at the 8kHz sample frequency and trans-
ferred in parallel to a second register 15 where they are read out
serially at the 256kHz sample rate.
The effect, however, will be to introduce components in the out-
put spectrum at m. 8kHz +- f which will have to be suppressed by an
analog low pass filter of sufficient quality, (e.g. 4th or 5th order
for PCM).
Improved interpolating filters can be used to reduce the analog
filterlng requirements. One simple improvement is to interpolate
between the given points using a straight line approximation.
Interpolating filters can be equated to an arrangement where N-l
additional zero value samples are inserted between the given ones
followed by a digital filter at N.fs. The simple arrangement of Fig.
6 gives an equivalent spectrum filtering of
G(Z) = l+z-l +z-2 +z-3 z-(N-l)
= l_z-N (Gain)
1 -Z
which gives attenuation peaks at fs and all its harmonics together
with a rising loss characteristic. At low frequencies (i.e. up to
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M. J. GINGELL - 12
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4kHz for PCM when fs = 8kHz) the effect is very close to the normal
aperture distortion of an ordinary digital-to-analog converter.
A straight line interpolator which inserts extra data values on a
straight line drawn between the given values can be shown to give a
spectrum filterlng equivalent
G~Z) =[~
which gives double the attenuation of the previous case. Such an
interpolator can be made quite simply as shown in Fig. 7. The input
signal Sn is fed to a delay 16. The delayed signal Sn_l is subtracted
from the original signal and the difference fed to a divide-by-N circuit
17. The divider output is fed to an increment store 18 where it is
circulated until replaced by a fresh input. The contents of store 18
are repeatedly added to the circulating contents of output store 19, these contents
belng originally the signal Sn. When the next sample Sn arrives it replaces
the previous contents of store 19 and is then incremented N times by an
amount which ls l/N th of the difference between that sample and the
prevlous sample.
More sophisticated interpolating can be achieved by first stepping
up the sampling rate to an intermediate value uslng a recursive filter
followed by a second step up to the final rate. A practical arrangement
for this is outllned below.
PCM data is normally presented to the converter as 8kHz 8 bit-
companded words. For use with the type of converter described here
it is necessary to first expand each 8 bit compressed word into a
12-bit linear word which can be done by a standard logical method.
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(Revision)
Fig. 8 shows a circuit for direct conversion of 8kHz linear words
to 256kHz 4 bit words. For the sake of simplifying the clock arrange-
ments an extra four bits are added to the 12-bit words in register lS
to make them up to 16-bit words. All the arithmetic is processed
serially at 4.096MHz = 256kHz x 16 bits but to save shift register
bits the clocks to the various registers could be gated with timing
signals to stop shifting after the appropriate operation is complete.
It is assumed that the data is in serial 2's complement, least
significant bit first format so that the arithmetic operations become
very simple. Multiplication by -1 is achieved by complementing the
data which gives a negllgible error of one least significant bit (1
part in 16384). Multiplication by two is done with a one bit delay
which will always naturally be clear at the end of each 16 bit cycle.
The adders 20 and 21 each require two full adder cells with an
associated carry flip flop. Any residual carry at the end of a word
cycle must also be cleared.
The 16 blt words in register 22 that result from addition are
truncated to 4 bits and staticlsed in staticiser 23 for a 4 bit rate
multiplier. The error which ls contained in the 12 least significant
blts in register 22 is allowed to pro~ress round the feedback loop.
The 4 most slgnificant bits are inhibited from circulating by INHIBIT
gate 24.
Since the rate multiplisr cannot handle negative data the most
significant bit (i.e. the sign bit) should be complemented. Then the
output which was from -8 to +7 is offset by 8 and becomes from 0 to
+15 .
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(Revision)
It should be pointed out that expansion from A or ,u law to linear
format can be achieved very simply by implementing the followlng
formula. Each compressed word contains a sign bit S, 3 exponent
bits E, and 4 magnitude bits M and then for ~1 law the output is
O~l = S . ~33 + 2 M) .2 E _ 3
- 8031 ~ Oll ~ + 8031
and for A law
OA = S. ~1 + X + 2M) 2
where X = 0 for E = 0
X= 32forE ~ 0
Note that the A law outp~t has been scaled by a factor of two to be of
the same magnitude approximately as the/u law
i.e. - 8064 ~ OA ~ + 8064
To implement the formula it is simply necessary to add a constant
to the magnitude, shift E places and subtract a constant.
- It should also be noted that it is possible for the adder to overflow
for large positive input signals. In the case of Fig. 8 where the input
number range is from +l to -1 the adder may overflow fo. signals
exceeding -7/8 or +3/4. There are two p~ssible countermeasures for
this. The first is to preattenuate the signal so that overflow cannot
occur. The second method ls to add an extra most signiflcant blt to
the data and lncorp~rate overflow protectlon in the adder.
In the case under consideratlon the worst cases before overflow
occurs are
(1) posltive input, register R3 contains maxlmum error
00001111 1111 1111, register 2Z zero.
then N + 0001111....~/ 011111111....
therefore N /~, 011000... i.e. ~ + 3/4
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(Revision)
(2) negative input, register R3 zero, register
2Z contains 00001111 1111 1111
then N - 00001111....,~ 1000 0000...
therefore N~ 100001111
~ - 7/8 - one L . S . B .
Therefore to prevent overflow and including the fact that signals
should be symmetrical abo;lt zero then input numbers must be restricted
to the range - 3/4 ~ N ~ + 3/4. The simplest means of effecting
this is to premultiply the data by scaling a factor of 3/4. This is
easily done by adding together half and quarter of the input obtained
asshowninFig. 9.
As a further example the audio digital-to-analog converter in
another digital system might be required to convert 18 bit samples at
16kHz to audio with a minimum increase in noiseO Wlth standard
techniques it is necessary to preround the slgnal to 13 or 14 bits
since an 18 bit converter is not practical. Wlth the converter descrlbed
here this is avoided by retalnlng the fu11 18 bits thus glving improved
performance at 4MHz logic clock rates compared with the previous
best of a scaled rate multipller needing 8MHz clocklng.
The system clock rate ls 4.032MHz = 16kHz x 14 channels x 18
bits. It ls feasible to step up the sampling rate 14 times to 224kHz
retaining serlal arithmetic since 224kHz x 18 bits = 4.032MHz. This
is done in two steps, first to 32kHz with a non recursive fllter,
secondly to 224kHz with a shlft re~ister store whlch repeats each
32kHz sample 7 times. Fig. 10 shows the overall block diagram.
The 16 - 32kHz non-recursive filter and its response are shown
in Fig. 11. A three stage delay is used, and the input signal and
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M. J. GINGELL - 12
(Revision)
delayed signals from each stage are each multiplied by a given factor.
All the signals are then summed in the adder.
While I have described above the principles of my invention in
connection with specific apparatus it is to be clearly understood
that this description is made only by way of example and not as a
limitation to the scope of my invention as set forth in the objects
thereof and in the accompanying claims.
AC H:vm/g s
1 1/6/75
