Note : Les descriptions sont présentées dans la langue officielle dans laquelle elles ont été soumises.
~.~9E;5~)~
A-31105/HMS Background of the Invention
This invention relates to weighted capacitor
analog/digital conversion circuitry and techniques and
more particularly to such conversion techniques utilizing
metal oxide semiconductor circuitry providing conversion
with either a linear relationship between the analog and
digital signals or a nonlinear relationship therebetween.
Conventional techniques for performing analog/
digital conversion generally require sophisticated analog
circuitry including operational amplifiers, and digital
circuitry for counting, sequencing, and data storage.
Consequently, hybrid circuits have resulted including one
e/en~ ~S
or more bipolar analog circuit clcmtns together with metal
oxide semiconductor circuit elements for performance of the
digital functions while remaining within reasonable economic
limits. Applications exist for coding analog signals in
;~~ nonlinear digital codes and for subsequent decoding to an
analog form. Voice signals for telephone transmission and
subsequent reception are often subjected to such nonlinear
coding and decoding. Present coder/decoder installations
are complex and expensive, therefore requiring multiplexing
for sharing of the installations so that they may accommodate
.,
multiple telephone transmissions simultaneously. A low cost
, .
~'! configuration of minimal complexity if desirable for use in
both linear and nonlinear conversion between analog and
digital signal forms, while mainta~ning low error and dis-
tortion levels through the conversions.
Summary and Objects of the Invention
In general, the electronic circuitry disclosed
herein for converting between analog and digital signal
.,
6~
forms includes an array of weighted capacitors having
capacitance values corresponding to individual digits within
a predetermined range of digits from a most to a least signifi-
cant digit in the range. An additional capacitor having a
capacitance value equivalent to the value of the capacitor in
the array corresponding to the least significant digit is
connected to the array. All of the capacitors in the array
and the additional capacitor have one terminal connected to a
common point and to one input of a voltage comparator. Another
1~ input on the voltage comparator is connected to a comparator
reference voltage and the other terminals on the array of
capacitors are connected to individual ones in a plurality of
switches. Each of the plurality of switches is capable of
selecting one of several terminals to which are connected the
comparator reference level, an analog signal level, and an
analog signal reference level. The plurality of switches are
operated in predetermined sequence by a digital control circuit
coupled to receive a serial digit output from the voltage
comparator. Thus, an analog signal connected to one of the
several terminals produces a digital combination from the digital
control circuit and a digital combination connected to the
digital control circuit produces an analog signal at another
of the several terminals.
In accordance with the invention there is provided
an analog/digital converter for converting between an analog
and a digital signal having a nonlinear relation therebetween,
comprising first and second arrays of binary weighted capacitors
having capacitance values corresponding to a predetermined
number of binary bits ranging from a most to a least signigicant
bit, a common plate node within each of said first and second
- 1~J96S~
arrays, a voltage comparator having first and second input
terminals and an output terminal, said first array common plate
node being connected to said comparator first input terminal,
said comparator second input terminal being connected to a first
predetermined reference, a digital control circuit coupled to
said comparator output term;nal, a first switch operated by said
digital control circuit to selectively connect said first array
common plate node to said first predetermined reference, a
second switch operated by said digital control to alternately
select the analog signal and a second predetermined reference,
a first plurality of additional switches operated by said digital
control circuit, each of said first plurality of additional
switches being configured to selectively connect ones of said
first array of binary weighted capacitors to said first pre-
determined reference and said second switch, a buffer amplifier
having a pair of input terminals and an output terminal, said
second array common plate node being connected to one of said
pair of amplifier input terminals, said first predetermined . -
reference being connected to the other of said pair of amplifier
input terminals, said first plurality of additional switches
each having an additional configuration for selectively connect-
ing ones of said first array of binary weighted capacitors to
said buffer amplifier output terminal, and a second plurality
of additional switches operated by said digital control circuit,
each of said second plurality of additional switches being
configured to selectively connect ones of said second array of
binary weighted capacitors to said first and second predetermined
references, said digital control circuit being responsive to a
serial digit input sequence so that said first array of binary
weighted capacitors sequentially samples and holds the analog
- 4a -
p
s~
signal~ divides said second predetermined reference signal into
binary weighted portions, combines the binary weighted portions
with the analog signal to provlde combined signal levels, and
said comparator compares each of said combined signal levels
with said first predetermined reference, said first plurality
of additional switches operating to select a predetermined portion
of the nonlinear relation, and said second plurality of addition-
al switches operating to select a predetermined step within said
predetermined portion, whereby said voltage comparator quantizes
said analog signal as a serial digit output at said comparator
`~ output terminal.
In accordance with another aspect of the invention
there is provided a method of converting between an analog and
a digital indication comprising the steps of weighting an array
of capacitors to assume capacitance values in digital relation
from a most to a least significant digit, connecting one side
of each capacitor in the array to a common point, discharging
; the array of capacitors, sampling an analog signal by charging
the uncommon sides in the array of capacitors with the analog
signal, holding the sampled charge on the array of capacitors
by coupling the uncommon sides to a first charge reference level,
connecting a second reference charge level from a reference
energy source to the uncommon side of each capacitor in the
array in predetermined se~uence/ thereby redistributing charge
therebetween and producing a predetermined sequence of trial
signals on the common point, coupling the common point to a
comparator input, coupling another input on the comparator to
the first charge reference level so that a serial digit output
is proviaed at the output of the comparator in accordance with
serial comparisons between the second reference and trial
- 4b - -
9~iiO~
signals, said step of connecting a second reference charge
level in predetermined seguence operating to cause the trial
signals to converge toward the first charge reference level,
whereby charge on parasitic capacitance in the converter appear-
ing between the common point and the second reference charge
level converges toward the charge level attained during the
step of holding, sequencing the steps of discharging, sampling,
holding and redistributing so that the serial digital output
is in a predetermined digit sequence, converting a digital
signal to an additional analog signal, wherein the digital
signal is determined by the serial digit output and the
additional analog signal is a corresponding portion of the
reference energy source output, coupling the additional analog
signal to the last capacitor in the array of capacitors to
which the second reference level charge ~as applied, so that
the signal on the common point assumes a level indicative of a
combination of the trial and additional analog signals, and
the serial digital output is in a predetermined digit and sub- -
digit sequence corresponding to the trial and additional analog
signals respectively, whereby the analog and digital indications
are in a nonlinear relation.
It is an object of the present invention to provide
conversion between analog and digital signals in minimal time
with a high degree of accuracy using simple easily fabricated
circuitry.
Another object of the invention is to provide
conversion between analog and digital signal forms
- 4c -
~109~
A-31105/HMS wherein parasitic capacitance is removed as an error
factor.
Another object of the present invention is,t~
provide conversion between analog and digital signal forms
utilizing circuitry having inherent sample and hold functions.
Another object of the present invention is to
provide conversion between analog and digital signal forms
~, wherein component offset voltages are compensated prior to
the conversion.
, 10 Another objec-t of the present invention is to
provide conversion between ana],og and digital signal forms
~ wherein there is a nonlinear relation between the analog
,` and digital signals.
Another object of the present invention is to
provide conversion between analog and digital signal forms
in a device which may be used as a coder or a decoder.
Another object of the present invention is to
provide conversion between analog and digital signal forms
which is inexpensive enough to allow elimination of multi-
; 20 plexing and instltution of per channel coding and decoding.
Additiona1 objectssand features of the invention
will appear from the following description in which the
preferred embodiment has been set forth in detail in con~
junction with the accompanying dr,awings.
Brief Description of the Drawings
Figure 1 is a block di~gram of the weighted
capacitor analog/digital converter.
Figure 2 is a schematic diagram of the weighted
capacitor array and a plurality of switches included in the
digital control and sequencing circuit.
~ 1~96~
A-31105/HMS Figure 3 is a timing diagram showing a typical
example of successive approximation accomplished by the
; embodiments of Figures 1 and 2.
Figure 4 is a chart showing the positions of the
` 5 switches of Figure 2 in sequence for obtaining the timing
diagram of Figure 3.
Figure 5 is an electrical schematic diagram of
; one stage of a comparator used in the invention.
Figure 6 is a combination block and electrical
schematic diagram demonstrating one form of offset voltage
compensation.
~- Figure 7 is a block diagram illustrating a non-
linear analog/digital converter.
Figure 8 is an electrical schematic diagram
illustrating the arrangement of the weighted capacitor
arrays and switches of the digital control and sequencing
circuit of Figure 7.
Figure 9 is a chart showing nonlinearity between
the digital and analog signals.
Figure 10 is a detail view of the segment A-B of
Figure 9.
Figure 11 is a timing diagram showing a sequence
of analog signals produced by a sequence of digital signals
with nonlinear relationship therebetween.
Figure 12 is a chart showing the switching sequence
for the circuit of Figure 8 to obtain the timing diagram of
Figure 11.
Figure 13 is a timing diagram showing conversion
of an analog signal to a digital signal utilizing the circuit
of Figure 8.
5~
A-31105/HMS Figure 14 is the CCITT standard ~ulse code
modulation presentation for the companded siynal associated
with the timing diagram of Figure 13.
Figure 15 is a chart showing the switch sequencing
in the circuit of Figure 8 for obtaining the successive
approxlmation of Figure 13.
Description of the Preferred Embodiments
Referring to Figure l~of the drawings, a block
diagram of one embodiment of the devlce for converting be-
tween analog and digital signal forms is shown. A weightedcapacitor array 11 is shown receiving an analog reference
signal V and an analog signal V . Weighted capacitor
REF IN
array 11 produces a successive approximation signal V which
is connected to a comparator 12. Comparator 12 produces
a serial digital output which is coupled to a digital
control and sequencing circuit 13. A plurality of digital
data output terminals 14 is available at digital control
sequencing circuit 13. Digital control sequencing circuit
13 receives a clock input for providing sequence dwell
time and produces a series of switching funetions on a
plurality of switching function terminals 16 coupled to
weighted eapaeitor array 11 and 17 coupled to comparator 12.
Figure 2 shows the weighted capacitor array 11 in
eireuit with a plurality of switches 18 included in digital
eontrol and sequencing circuit 13 for controlling charge
fh~
^~ placed on individual ones of tch capacitors in the capacitor
array 11 and for eonnecting thereto predetermined ones of the
analog signal V , analog reference signal V and the refer-
IN REF
enee signal for comparator 12, which is shown in Figure 2 as
ground. One terminal of all of the capacitors in the array is
~6~0~
A-31105~HMS connected to a common point and in turn connected to one
input of comparator 12. The voltage at the common point or
~ - the input to comparator 12 is designated as V . A s~Jitch
:~ X
Sl is provided for selectively placing the common point
for the capacitors in the array at ground potential. Another
switch S7 is provided for selecting the analog signal V
IN
or the analog reference signal V . It should be noted
REF
that digital control and sequencing circuit 13 includes
sequencing and control logic which controls all of the
switches in the circuit on the time base provided by the
clock input to the digital control and sequencing circuit
13. The capacitors in the weighted capacitor array 11 have
values as indicated in the example of Figure 2 corresponding
to a predetermined number of binary bits ranging from a
most to a least significant bit. The capacitor representing
the most significant bit is marked C and that representing
the least significant bit is marked C~8. An additional
capacitor 19 is provided having a capacitance value equiva-
lent to that of the capacitor representing the least sig-
nificant bit, which is in this example C/8. It is seen inFigure 2 that one terminal on additional capacitor 19 is
also connected to the common point at one input to comparator
12.
The plurality of switches 18 are designated S2
through S6 in this example, each having terminals ~arked
1 and 2. Switches S2 through S6 selectively place the other
terminal on individual capacitors in the capacitor array 11
to ground potential in position 1 or to switch S7 in position
2. Switch S7 in turn has two positions 1 and 2 for selecting
the analog signal V or the analog reference signal V
- IN REF
I -8-
~319~i5~1
A-31105/HMS respectively. As indicated in Figure 2, a digit serial
output is provided by comparator 12 in accordance with
the successive approximation signal level V . The digit
serial output is connected to digit control and sequencing
circuit 13 as mentioned above for controlling the sequence
and control logic and the switching sequence of switches
Sl through S7.
Turning to Figure 3 the manner in which the device
of Figure 1 and 2 operates will be described. The successive
approximation signal level V is shown on the ordinate of
the chart of Figure 3 and the abscissa is divided into time
periods as indieated and as provided by the clock input
to digital control and sequencing circuit 13. In this example
to be presented a conversion from an analog signal V to a
IN
digital signal will be followed. The sequence begins at
time t and during the first period, t - t , switch Sl is
O 1 0
closed to ground and switches S2 through S6 are also placed
in position 1 to ground; In this fashion, all of the
capacitors in the array and additional capacitor 19 are
discharged. It will be noted that the total of all of the
capacitance values in the array 11 and additional capacitor
19 is 2C. Consequently when switch S7 is placed in position
1 to select V and switehes S2 through S6 are placed in
IN
position 2, a eharge is stored in the capaeitors of 2CV at
IN
the eommon point or plates of the capaeitors. Thus, the
analog signal V is sampled during the second period t - t .
IN 2
~uring the third period, t - t , switch Sl is opened, removing
3 2
the common capacitor plates from ground. During the fourth
S~Z
period, t - t , switches ~1 through S6 are conneeted to ground,
~' 30 and since the charge on the eommon plate is eonserved, V
X
6~
A-31105/HMS assumes a potential of -V in the absence of parasitic
IN
capacitance to ground. Switch S7 is placed in position 2
during the fourth period, preparatory to applying portions
of the analog reference voltage V to the common plate
REF
of the capacitors for modifying the voltage V .
During the fifth period, t - t , switch S2 is
placed in position 2 thereby connecting V to one terminal
REF
of capacitor C. It may be seen that the circuit arrangement
existing in the fifth period is such as to divide V in
REF
the series capacitance voltage divider between V and
REF
ground consisting of capacitance C in series with the remainder
of the capacitance, which is also equivalent to C. Therefore,
V /2 is present at the common plate of the capacitors during
REF
the fifth period and V is the combination of -V and V /2.
X IN REF
Comparator 12 provides an output signifying V as being
in excess of the ground reference to the comparator 12 and
the serial digit output produced thereby and connected to
digital control and sequencing circuit 13 causes switch S2
to be repositioned in position 1 during the sixth period
t - t .
6 5
During the seventh period, t - t , switch S3 is
7 6
placed in position 2 to select V to be applied to one
REF
terminal of the capacitance C/2. In the same fashion as
explained above, a series capacitance voltage divider is
in existance during the seventh period wherein V /4 is
REF
added to V , so that the successive approximation signal
X
assumes a value ~hich is the combination of -V and V /4.
IN REF
- This produces a serial digit output from comparator 12 to
digital control and sequencing circuit 13 which retains
switch S3 in position 2 and, during the eighth period t - t ,
8 7
--10--
... .
501
A-31105JHMS places switch S4 in position 2 to provide 3/8 of V in
REF
successive approximation signal V . Thus, during the
e!~67~S
period the input to comparator 12 is the combination
of -V and 3/8 V . The serial digit output from comparator
IN REF
5 12 connected to digital control and sequencing circuit 13
retains S4 in position 2 as well as S3 and during the ninth
period, t - t , switch S5 is placed in poistion 2. It may
9 8
be seen by reference to Figure 3 that the combination voltage
produced during the ninth period is in excess of the com-
parator reference voltage and the serial digit output directsthe digital control and sequencing circuit 13 to reposition
switch S5 in position 1 during the tenth period, t - t .
10 9
The successive approximation at the input of comparator 12
is complete and the analog voltage V is presented at the
IN
15 data output terminals 14 of digital control and sequencing
: circuit 13 as the four bit binary number 0110.
Remaining with Figure 3 it may be shown that
parasitic capacitance existing at the input of comparator
12 will not affect the accuracy of the conversion as it has
: 20 in prior conversion schames. A property of the conversion
technique is that, since the successive approximation signal
V is nulled back toward the zero or comparator reference
: position as the bit decisions are made, the parasitic capa-
citance from the common plate of the capacitors to ground
in this example does not affect accuracy. When the comparator
input voltage V is nulled back to the comparator threshold,
which is ground in this example, the charge on the parasitic
capacitor is identical to that which exists at the end of
the sample mode during the third period t - t . Therefore
: 3 2
~ 30 the error charge placed on the parasitic capacitor by sampling
-
~119~5~
A-31105/HMS is conserved and error contributed thereby during the ensuing
redistribution periods is zero. The parasitic capacitance
increases the total capacitance in the array of capacitors.
This decreases the voltage division characteristics of each
eapacitor in the array. Thus, smaller fraetions of the
analog reference signal V are subtracted from the analog
REF
signal V , but the analog signal V appears as a lower
IN IN
signal level at the common poini for the capaeitors, so the-
/~seffect is inhe~er.tly compensated. The dashed line signify--
ing t'ne level of the successive auproximation -ignal V in
Figure 3 represent a situation which is a gross case and is
presented here for illustrative purposes only. Where, as
shown, the level of the analog voltaae V is cut in half,
IN
the parasitie capaeitanee is equivalent to 2C. Thus the
eapaeitanee array actually contains 4C, but only the 2C
eontaining eharge distrlbuted and redistributed by the
digital eontrol and sequeneing eircuit 13 enters into the
suecessive approximation. While the successiv~ approximation
signal levels V are lower in this latter case, the eom-
. , X
20 parative levels have the same sense and the serial digitaloutput from comparator 12 for sequeneing the operative
~- switehes S2 through S5 for redistribution of eharge is the
same.
Another error souree in ,the diselosed eircuitry
derives from what is known as comparator offset. Comparator
offset is that value ofi eomparator output which exists
for zero differential eomparator input. The eomparator
output is proportional to eomparator input, but the output
is amplified and the slope of the output as a funetion of
input signal is steep. Therefore, the output from eomparator
. -12- ~
~096~
A-31105/HMS 12 is such as to be either near zero or at some large ~alue
thereby providing the serial digital output indicative of
an input which is either in excess or not in excess of the
comparator reference. Offset is the departure from this
ideal situation wherein some small output exists at the
bof~7
comparator when the input terminals are ~3~ placed at
the same input potential. Referring to Figure 5, a
differential amplifier circuit 21 is shown wherein the
offset characteristic is caused by a mismatch of field
effect transistor characteristics. The mismatch which pri-
marily produces the offset is between transistors Q3 and Q4
of Figure 5. Metal oxide semieonductor contruction of all
of the eircuit elements necessary to this invention is
made possible by the concept of this invention. However,
metal oxide semiconductor (MOS) construction of the
comparator of Figure 5 is especially susceptible to offset
voltage errors. The offset exists as a DC differential
voltage at the output of the comparator when the input
differential is zero. Described in an alternate manner,
a signal differential occurring between the input terminals
of the comparator may produce an output modified by the
offset voltage of the comparator which is not a true indi-
eation of the differential between the input terminals.
Consequently, an error in the serlal digital output could
oeeur and an error would aeerue in the eonversion.
One manner of compensating for the offset voltage
in the comparator 12 is to couple the offset output through
a buffering element and switch to the common point for the
capaeitor array 11 during the sampling mode to thereby
compensate for the offset voltage in the signal at the input
5~
A-31105/HMS of the comparator prior to beginning the redistribution
of charge and successive approximation sequencing.
Referring to Figure 6 of the drawing the voltage
comparator 12 is shown as a multistage circuit containing,
in this example, three stages of the differential amplifier
circuit 21 of Figure 5 utilizing MOS field ef~ect transis-
tors (FETS) Ql through Q4 and having input and output
terminals as shown. The offset voltage may be stored in
the circuit of comparator 12 by means of the capacitors
Cl through C4 and switches S8 through Sll shown in Figure
6. Prior to the sampling mode while switch Sl of Figure
2 is closed, all switches S8 through Sll are also closed.
In this fashion, any offset voltage e~isting at the output
of the first stage of comparator 12 is stored as a difference
voltage bet~een capacitors Cl and C2. When switches S8 and
S9 are open together with Sl of Figure 2, a compensation
voltage is stored at the input to the second stage of
comparator 12 which is equivalent to the offset of the
first stage.
.
In Figure 6 it should be noted that compensation
is made only for the offset voltages of the first and second
stages. The offsets in the multistage circuit are divided
by the gains of the previous stages. Therefore assuming a
~; gain of ten in e~ch staye in the circuit of Figure 6 and a
50 millivolt offset for the first stage, a 0.5 millivolt
offset would be the residual offset therefrom at the input
to the third stage. Thus correction for each of the three
stages is unnecessary and a practical circuit is seen in
Figure 6 having no offset correction in the third stage. It
should be noted that the inherent offset characteristic
~lti50~L
A-31105/HMS obtalned in MOS circuitry technology is conveniently com-
pensated through the use of MOS circuit technology to provide
the circuit seen in Figure 6. While offset errors are less
severe in bipolar circuitry, such a correction technique
could not be utilized in bipolar circuitry because of the
discharge paths presented in the bipolar elements which
would prevent storage of th~ offset compensation signals on
capacitors in the bipolar circuitry.
The initial voltage V established at the common
plate of the capacitor array by closing switch Sl need not
be ground as shown, but must only be the threshold voltage
of the comparator 12. With this in mind, a method has been
disclosed for converting between an analog and a digital
indication which includes the steps of weighting an array of
capacitors so that they assume capacitance values which are
in digital relation from a most to a least significant digi-.
Further steps ~nclude connecting one end of each of the
capacitors in the array to a common point and discharging
the array of capacitors so that zero charge is stored thereon.
Subsequently the step of charging the array of capacitors
with an analog signal is undertaken. A reference signal for
the analog signal is divided in the array of capacitors
thereby imparting a reference charge to the common point by
sequentially connecting ones of the array of capacitors
between the reference signal and the common polnt while the
remainder of the array of capacitors is in series connection
between the common point and a discharge reference. A trial
signal is thereby constructed at the common point which is
thereafter coupled to a comparator having the discharge level
as a reference input. In this fashion, a serial digital
~9~5C~
A-31105/HMS output is provided as the output of the comparator in
accordance with serial comparisons between the discharge
level and the trial signal. The step of connecting a
reference charge in a predetermined Sequence to the capacitors
in the array operates to cause the trial signal to converge
toward the discharge reference level. In this fashion, any
charge imposed on parasitic capacitance in the converter
appearing between the common point and the discharge reference
level converges toward the initial charge on the parasitic
capacitance imposed during the sampling period. The method
is completed by sequencing the steps of discharging the
capacitor array, sampling and charging the capacitor array,
and redistributing the charge on the capacitor array so that
the serial digital output from the comparator is in a
predetPrmined digit sequence in accordance with the analog
signal.
The block diagram of Figure 7 shows the major
elements in a nonlinear converter between analog and digital
signals. The nonlinear converter will be disclosed in terms
of a device which finds utility as a companded pulse code
modulation voice coder/decoder and which uses monolithic
arrays of binary weighted MOS capacitors providing a standard
fifteen segment approximation to the 255~ compression law in
a coder for pulse code modulation PCM telephony. The level of
- 25 expense and complexity of the nonlinear converter disclosed
herein suggests that a per channel voice coder/decoder is
realizable in a single MOS chip. The arrangement of Figure 7
will allow coding of voice signals in nonlinear digital codes
for digital telephone transmission while maintaining an except-
ably high ratio of signal to noise and low distortion over a
-16-
,
~()9~i~0~
-31105/HMS wide dynamic range without requiring an excessive digital
transmission bandwidth. Widely used in the United States
is the fifteen segment approximation of the ~ = 255 com-
pression law~ which is illustrated in Figure 9 and 10
to be discussed hereinafter. Returning to Figure 7, a
weighted capacitor array 22 similar to array 11 above is
attached to terminals for connection to an analog voltage
V and an analog voltage reference V . Weighted
IN REF
capacitor array 22 provides a successive approximation
voltage V which is connected to a comparator 23, which
provides a serial digital output connected to a digital
control and sequencing circuit 24. A plurality of sequencing
outputs 26 are directed to weighted capacitor array 22.
A plurality of digital data output terminals 27 are pro-
vided on digital control and sequencing circuit 24. Anadditional weighted capacitor array 28 is provided which
receives the analog signal reference voltage V as well
REF
as a plurality of sequencing outputs 29 from digital control
and sequencing circuit 24. Additional weighted capacitor
array 28 provides an output signal V connected to a buffer
element 31. Buffer element 31 provides an output signal
V for coupling to weighted capacitor array 22. A plurality
of sequencing outputs 32 are connected from digital control
and sequencing circuit 24 to comparator 23. The time base
for the sequencing outputs 26, 29 and 32 are provided by
a clock input to digital control and sequence circuit 24.
Fiyure 8 shows a circuit diagram~dls~closes the
interconnections between weighted capacitor array 22,
comparator 23, buffer 31, additional weighted capacitor
array 28 and certain of the switches included in the digital
65Q~
A-31105/HMS control and sequencing circuit 24. Figure 8 does not
include the sequenci~g and control logic utilized for
controlling the switches seen in Figure 8, as that control
logic is well known and not part of this invention.
Weighted capacitor array 22 includes capacitors C13 through
C C C C C C
C21, having capacitance values of C, 2, 4, 8, 16, 32, 64,
C C
128 and 1~ respectively. One terminal of all of the
capacitors C13 through C21 is common and is connected to
one input on the comparator 23. Another input on the
comparator 23 is connected to the comparator reference which
; is ground in this example. A switch S12 is provided for
connecting the common plate of the capacitors to the com-
parator reference voltage level, ground in this example,
when closed. It then may be seen that the total of all of
the capacitances C13 through C21 is 2C.
A plurality of switches 33 are included in digital
control and sequencing circuit 24 and are designated as S13
through S20 in Figure 8. Switches 33 are configured to
connect the noncommon terminal on each one of the capacitors
C13 through C20 to one of three terminals. The first of
the three terminals selected by any of switches S13 through
S20 is connected to a switch S21 having positions 1 and 2
thereon, for selecting the voltage comparator reference,
ground in this example, or an analog voltage V on position
2. The second terminal on each of the switches S13 through
S20 is connected to a switch S22 having positions 1 and 2
thereon for selecting a positive or negative analog reference
signal level V respectively for application to ones of the
REF
noncommon terminals of capacitors C13 through C20. The third
position selectable at switches S13 through S20 connects a
-18-
, . . .
5U~
A-31105/HMS buffered step signal V to individual ones of the noncommon
terminals of capacitor C13 through C20. The additional
weighted capacitor array 28 has included therein an array
of capacitors C24 through C28 having one plate connected
to a common point and to one ~nput of unity buffer amplifier
; 31. Capacitors C24 through C28 are weighted in this example C' C' C' C'
to assume capacitance values of C', 2 , 4 , 8 and 8
respectively. The common point between capacitors C24
through C28 is connected to one terminal of a switch S23
which connectes the common point to the reference voltage
level for comparator 23, ground in this instance. The
noncommon terminals of capacitors C24 through C27 are
connected to an additional plurality of switches 34 designated
S24 through S26 having positions 1 and 2 thereon for alter-
nately selecting the reference signal level for comparator 23on position 1 or a connection to switch S28 on position 2.
Switch S28 has positions l and 2 for selecting either positive
or negative analog reference voltage V respectively.
REF
The two binary weighted capacitor arrays 22 and
28 are the key precision elements. Other elements as men-
tioned above include a binary comparator 23, a near unity
gain buffer amplifier 31 with high input impedance, numerous
analog switches S12 through S28 and binaxy sequencing and
control logic totaling approximately sixty gates and flip-
flops. These elements are all realizable on a single MOSchip. A conversion utilizing the circuitry of Figure 8
proceeds as follows. Ini~ially switches S12 through S21
and S23 through S27 are thrown to the reference voltage level
swi -f o,~S~5
for comparator 23, ground in this example. Next, ~t~tiches
S13 through S20 are retained in position 1 and switch S21 is
--19--
, . ,
1~65~
A-31105/HMS thrown to position 2 to store V on the capaci~or array 22.
IN
Next, S12 is opened and S21 is returned to position 1 to
select ground while switches S13 through S20 are retained
in the number 1 position. The sign of the successive approx-
imation voltage V is negative in this example which deter-
mines the sign bit of the PCM code. Thus, the analog signal
V is sampled and the sample is held on the capacitor array
IN
22. Referring to Figure 9, the segment in the line repre-
senting the relationship between the analog and digital
signals is determined by successively throwing switches S20
through S13 in inverse order starting with switch S20 from
ground position 1 to analog reference voltage position 2
; until the sign of successive approximation voltages V changes.
Switch S22 is thrown to position 1 to select the positive
analog reference voltage if the sign of analog voltage V was
IN
previously determined to be positive and to position 2 to
select the negative analog reference voltage if the sign of
V was determined to be negative. If, for e~ample, the out-
IN
put from comparator 23 changes after switch S18 is thrown,
this indicates that the analog input voltage V lies within
IN
the segment A-B shown in Figure 9.
The final stage in the conversion is the determination
~- of the step within the segment. The capacitor array 28 is
used in this process. Initiallv, as described above all
switches S23 through S27 are thrown to the ~eference level
for comparator 23, ground in this example. To follow the
example entered into above, actuation of any of the switches
S13 through S20 applies a trial voltage to the common point
for the capacitor array 22 and the trial voltage applied by
actuating swtich S18 to position 2 provided the first trial
-20-
, .. ..
65~1~
A-31105/HMS voltage which caused comparator 23 to change output states
; at the serial digital output thereof. Consequently, switch
S18 is thrown to position 3 to select a buffered subtrial
voltage V provided at the output of unity gain buffer 31.
Next S23 is opened and switches S24 through S27 are thrown
in sequence from position 1, ground, to position 2 to connect
the noncommon terminals of individual ones of capacitors C24
through C27 to switch S28 and to the appropriate analog voltage
reference as provided at either terminal 1 or 2 on switch S28.
The successive approximation algorithm is used for the l'in
chord" coding which determines within which of the sixteen
steps of the chord A-B of Figure 10 the analog sample signal
lies. Thus, the subtrial voltage V is obtained at the input
to unity gain buffer amplifier 31 which is provided as the
; 15 buffered subtrial voltage V connected to terminals 3 for
switches S13 through S20, and through switch S18 in this
example to be combined with the trial voltage V . The
combined trial and subtrial voltage levels provide the
appropriate serial digital output from comparator 23 which
- 20 is connected as shown in Figure 7 to digital control and
sequencing circuit 24 for providing the corresponding digital
data output there~rom.
Referring to Figure 13 a timing diagram is shown
illustrating the successive approximation described above
for the circuit of Figure 8. The successive approximation
voltage V is plotted along the ordinate of the chart of
Figure 13 and the digital response is plotted along the
abscissa thereof. V is shown at the reference level for
X
the comparator 23, zero potential or ground in this example,
through the first period, t - t , when S12 is closed. S21
1 o
5~
A-31105/HMS is set to position 2 to select the analog sample to be applied
to the noncommon terminals of the capacitor array C13 throu~h
C21 simultaneously. Switch S12 is opened during the second
period, t - t , and during the third period, t - t , switch
2 1 3 2
S21 is returned to position 1 to select the reference for
comparator 23 so that -V appears at the common terminal
: IN
for the capacitor array 22. Next, S22 is placed in position
1 to select positive V at position 2 on switches S13
REF
through S20. During the period t - t , switch S20 is thrown
to position 2 to determine if the analog voltage V is
IN
within the first positive chord in the curve of Figure 9.
Figure 13 shows that the analog voltage V is greater than
IN
-~ that portion of the analog reference voltage applied as a
trial voltage to the common point for the capacitor array 22.
Switch 520 being retained in position 2, switch Sl9 is
thrown to position 2 during the sixth period to see if a
trial voltage has been obtained at the common point of the
~ capacitor array 22 which indicates the chord has ~ reached
: wherein the analog voItage V lies. Figure 13 shows a
IN -~-
~ailure during the sixth period, t - t , and switch S18 is
- 6 5
therefore sequenced to position 2 to presen~ a greater pre- ;
determined portion of the analog reference voltage V to
REF
the common point of the capacitor array 22. The level of
the trial voltage during the seventh period is seen to exceed
the reference level for the comparator 23 and the sequencing
Cl'l r~a 7Cs
and control circuit 24 ~4~es switch S18 to position 3
thereby dropping the trial voltage to the lëvel obtained by
the positioning of switches Sl9 and S20 to position 2 and in-
dicating that the third chord on the positive side of the
curve of Figure 9, designated A-B, contains the analog signal
I -22-
,
~0~s~
A-31105/HMS V . During the ninth period, switch S24 is sequenced to
IN
position 2 to select a portion of the analog voltaye re~erence
to be presented at the common point of capacitor array 28
as the subtrial voltage for subsequent application to the
common point of capacitor array 22 as described above. The
combination of trial and subtrial voltages during period
nine may be seen to be in excess of the reference voltage
for comparator 23 and switch S24 is returned to position 1
during the tenth period of the conversion as seen in Figure
13. Switch S25 is subsequently thrown to position 2 to pro-
vide a subtrial voltage as described above to the common
point of capacit~r array 22 which may be seen in Figure 13
to be less than the reference voltage level for comparator
23. Conseguently, switch S25 is left in the position 2 and
switch 26 is thrown to pOSLtiOn 2 during period twelve pro-
ducing the signal shown in Figure 13 in excess of the com-
parator reference voltage. Switch S26 is returned to position
1 and switch S27 is thrown to position 2 providing a subtrial
voltage for combination with the trial voltage at the common
point of capacitor array 22 which is less than the reference
voltage level for comparator 23. The conversion sequence
is ended for the companded analog to digital conversion and
the CCITT standard PCM representation of the companded digital
signal is seen in Figure 14. The first digit represents the
sign or sense of the analog to digital relation. The second,
third and fourth digits represent thechord in the analog/
digital relation curve as determined by the trial signal.
This ma~ be seen to be the thirdchord A-B in Figure 9. The
fifth through the eighth digits represent the step wi~hin
the third chord throùgh which the analog signal V passes as
IN
1~650~L
A-31105/HMS determined by the combination of the trial and subtrial
signals. This may be seen to be the fifth step in the
chord A-B as seen in Figure 10 of the drawings. The switch-
ing sequence directed by the digital control and sequencing
circuit 24 may be seen in the chart of Figure 15, The
chart shows that fourteen clock periods have been utilized
for the determination of the companded digital code, but
some operations may be combined so that the coding may take
place in fewer clock periods than shown in the chart of
Figure 15.
The device shown in the block diagram of Figure 7
and the electrical schematic diagram of Figure 8 may be
used as a decoder or a digital to analog converter as well.
The timing diagram of Figure 11 shows the two analog voltages
15 V and V being generated in sequence according to digital ~-
: Y X
control and sequencing provided by the circuit 24 including
the switches of Figure 8 in accordance with the sequence
shown in the chart of Figure 12. Figure 11 shows the analog
voltages V and V on the ordinatP and the sequential time
~' X Y
; 20 period on the abscissa. Note that the first sequence shows
switches S12 and S23 closed and all other switches in the
plurality o~ switches 33 and 34 as well as switch 21 placed
in the number 1 position for selecting the reference signal
level for the comparator 23, ground in this example. Thus,
all capacitors in arrays 22 and 28 are dischar~ed initially.
Next, switches S12 and S23 are opened in the second sequence.
In the third sequence switch S28 is connected to the analog
reference voltage on position 1, switch S27 is selected to
position 2 and switch S20 is selected to position 3. In
this fashion what has previously been referred to as the
-2~
. . .
1~9~
A-31105/EIMS subtrial voltage is transferred through the voltage division
provided by the additional capacitor array 28, through unit~
gain buffer amplifier 31, through switch S20 and the voltage
division provided by capacitor array 22 to appear at the input
of comparator 23 as V seen in the third sequence of Figure
11. The plurality of switches 34 are sequenced through the
entire sixteen bit succession to provide the sixteen steps
in the first chord shown in sequences two through seventeen.
Corresponding switching combinations for the plurality of
switches 34 are shown in the sequences two through seventeen
of ~igure 12. The variation of V is shown for these
y
corresponding switching combinations in Figure 11.
Switch S20 is placed in position 2 during the
~` eighteenth sequence and switch Sl9 is placed in position
- 15 3 during the ninteenth sequence. The plurality of switches
34 are sequenced through the entire sixteen bit succession
as described above providing the sixteen steps in the second
chord of Figure 11. Switch Sl9 is returned to position 2
in the thirty-fourth sequence and switch S18 is placed in
the number 3 position in the thirty-fifth sequence. The
plurality of switches 34 are sequenced through the entire
;~ sixteen bit succession as before, providing the sixteen
steps between the letters A-B as seen in Figure 11. The
i ~ analog voltage oup~ut decoded with the standard PCM repre-
,~, ....
sentation of Figure 14 is shown as V in Figure 11 inter-
IN
cepting the fifth step of the third chord in the digital/
! analog relationship. It should be noted that Figure 11
represents a decoded analog voltage for a successive series
of digital inputs. When a specific standard PCM representation
is applied to the decoder it is not necessary to generate
-25-
6~
A-31105/HMS the analog values in sequence when using the circuit as
a digital to analog device. By one set of switch closures
any analog output voltage may be generated for a particular
PCM companded digital input.
A device for conversion between an analog and a
digital indication is provided which is all MOS contruction,
which contains compensation for parasitic capacitance and
comparator offset errors and which may be applied on a per
channel basis in nonlinear analog/digital coding and decoding.
The basic converting circuit structure for conversion
between analog and digital forms of signal is utilized in
both the linear and nonlinear conversion structures.
, -26-
