Note : Les descriptions sont présentées dans la langue officielle dans laquelle elles ont été soumises.
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This is a divisional application of Canadian Patent
Application Serial No. 267,016, filed on December 2, 1976.
The present invention relates to a frequency synthe-
sizer for use in a transmitter/receiver. More specifically, the
present invention relates to a frequency synthesizer for use in
a transmitter/receiver adapted to be capable of providing an
oscillation frequency signal of various desired frequencies.
A digital frequency synthesizer has been proposed by
the prior art and is now in practical use. Such a frequency
synthesizer is more advantageous in that it can provide a more
stabilized oscillation frequency. A typical frequency synthe-
sizer of the prior art is one which employs a phase locked loop
and which is often simply referred to as "PLL".
A frequency synthesizer employing a phase locked loop
usually comprises a voltage controlled oscillator the oscilla-
tion frequency of which is controllable as a function of an
output voltage, as low pass filte~ed, obtainable from a phase
detector, which is adapted to compare the phase or the frequency
of the output from a reference oscillator and the phase or the
frequency of an output from a programmable frequency divider
adapted to frequency divide the output frequency from the said
voltage controlled oscillator at the frequency division ratio
which is adapted to be variable as a function of a control
signal. Automatic scanning of the oscillation frequency of the
output from the said voltage controlled oscillator is effected
by varying the said control signal and thus the frequency divi-
sion ratio of the programmable frequency divider.
Such a frequency synthesizer has been utilized by way
of a frequency signal generator in s citizen's band transceiver,
for example. However, since in a citizen's band transceiver the
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frequency of the received signal in the receiving mode is in any
one frequency band within the frequency range of 26.965 MHz
through 27.255 depending on the channel of the received signal,
the oscillation frequency of the frequency signal generator
should also be changed within the frequency range of 37.66 MHz
through 37.92 MHz depending on the receiving channel in order
to obtain a constant intermediate frequency of 10.695 MHz. On
the other hand, in the transmitting mode, the oscillation fre-
quency of the frequency signal generator should be changed with-
in the frequency range of 26.965 MHz through 27.255 MHz depend-
ing on the channel in which a modulated carrier wave is trans-
mitted. A typical approach for changing the frequency variable
range depending on the transmitting and receiving modes in such
a frequency signal generator employing a frequency synthesizer
comprises two reference oscillators, which are typically crystal
oscillators. One of them is a reference oscillator to be in-
cluded basically in a frequency synthesizer for providing a
reference signal of the frequency of 26.965 MHz to be phase
detected and the other oscillator is a reference oscillator to
be used only upon reception for providing a reference frequency
of 10.695 MHz to be mixed with the output from a voltage con-
trolled oscillator to be used by way of a local oscillator.
Since provision of one such crystal oscillator entails
an increase of cost of approximately ten per cent of the whole
apparatus, reduction of cost in this connection is advantageous.
If any scheme can be implemented which is capable of effectively
selecting the transmitting and receiving modes with a lesser
number of crystal oscillators, then it would be more advantageous
from the stand point of cost, even if a configuration of the
circuit concerned becomes complicated, insofar as the circuit is
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implemented by an integrated circuit.
According to the present invention, then, there is
provided a frequency synthesizer for providing an oscillation
frequency signal, the signal being in at least one of first
and second variable frequency ranges; the frequency synthesizer
comprising voltage controlled oscillating means for providing
an oscillation frequency signal the oscillation frequency of
which is variable as a function of a given control voltage;
means for modifying the oscillation frequency of the output
from the voltage controlled oscillating means; means for con-
trolling the ratio of frequency modification of the oscillation
frequency modifying means; means responsive to the output from
the oscillation frequency modifying means, as modified at the
frequency modification ratio controlled by the frequency modi-
fication ratio controlling means, for providing a control voltage
associated with the frequency of the output from the oscillation
frequency modifying means to the voltage controlled oscillating
means, whereby the frequency synthesizer is adapted to provide
an oscillation frequency signal the frequency of which is assoc-
iated with the frequency modification ratio, as controlled bythe frequency modification ratio controlling means; means for
selecting a first operation mode for providing a frequency with-
in the first variable frequency range or a second operation
mode for providing a frequency within the second variable fre-
quency range; means responsive to the output from the mode sel-
ecting means for accommodating the control of the frequency mod-
ification ratio by the frequency modification ratio ~ntrolling
means for enabling generation of the frequencies in the selected
operation mode; and first and second output withdrawing means .;~
responsive to the output from the mode selecting means for
selectively withdrawing an oscillation frequency signal in the
selected first and second operation modes, respectively, from
the voltage controlled oscillating means; the control voltage
providing means comprising means for providing a reference fre-
quency signal; and means responsive to the output from the os-
cillation frequency modifying means and the output from the
said reference frequency signal providing means for detecting
the frequency difference between the frequency of the output from
the oscillation frequency modifying means and the frequency of
the reference frequency signal for providing the control voltage
to the voltage controlled oscillating means; the apparatus fur-
ther comprising first detectingmeans having a detection point in
the vicinity of the operation limit of the oscillation frequency
modifying means and for detecting the oscillation frequency of
the voltage controlled oscillating means having reached the
detection point; and means responsive to the detected output from
the first detecting means for correcting the control voltage from
the control voltage providing means such that the oscillation
frequency from the voltage controlled oscillating means may be a
frequency within the stabilized operation region of the oscilla-
tion frequency modifying means.
The present invention, as well as that described in the
parent application Serial No. 267,016, will be better understood
from the following detailed description of the preferred embodi-
ment of the present invention when taken in conjunction with the
accompanying drawings in which:
Fig. 1 shows a block diagram of a typical prior art
transceiver in which a frequency synthesizer of the present
invention can be advantageously employed;
Fig. 2 shows a block diagram of one embodiment of the
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inventive frequency synthesizer that can be advantageously
utilized as the frequency signal generator of the Fig. 1
transceiver;
Fig. 2A is a block diagram showing in more detail
the transmitting/receiving mode selection circuit and the
peripheral portion associated therewith constituting a feature
of the frequency synthesizer shown in Fig. 2;
Fig. 2B shows waveforms of the programmable counter
of the Fig. 2A embodiment for use in explaining the operation
thereof;
Fig. 2C is a schematic diagram of another embodiment
of the transmitting/receiving mode selection circuit in the Fig.
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2 embodiment, which can be employed in place of the Fig. 2A
embodiment;
Fig. 2D shows the connection between the column and
row lines at the intersections therebetween in the matrix in
the Fig. 2C embodiment;
Fig. 2E shows the connection of the final outputs
from the read only memory shown in Fig. 2C;
Fig. 3 is a block diagram of another embodiment of
the present frequency synthesizer;
Fig. 3A is a schematic diagram of the transmitting/
receiving mode selection circuit in the Fig. 3 embodiment;
Fig. 4 is a block diagram of a further embodiment
of the present frequency synthesizer;
Fig. 4A is a schematic diagram showing in more detail
the transmitting/receiving mode selection circuit in the Fig.
3 embodiment;
Fig. 5 is a block diagram of still a further embodiment
of the present frequency synthesizer;
Fig. SA shows in more detail a schematic diagram of
the operation limit detector and associated blocks in the Fig.
5 embodiment; and
Fig. SB shows waveforms at various portions in the
Fig. SA embodiment.
Fig. 1 shows a block diagram of a typical prior art
transceiver in which a frequency synthesizer of the present
invention can be advantageously employed. The transceiver shown
comprises a receiver portion REC for receiving a transmitted
wave signal to convert the same into an audible sound, and a
transmitter portion TRN for converting an audible sound into
a transmitting wave to transmit the same. Such transceiver
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may comprise a frequency signal generator 3 for providing a
local oscillation frequency output and a carrier frequency
output to the receiver portion REC and the transmitter portion
TRN, respectively, and a transmitter/receiver selection switch
16, such as a press talk switch, for selectively switching
a transmitting mode or a receiving mode of the frequency signal
generator 3.
The receiver portion REC comprises an antenna 1 for
receiving a transmitted wave, a high frequency amplifier 2
for amplifying the received wave signal, a first mixer 4 for
mixing the high frequency output from the amplifier 2 with
a first local oscillation frequency output from the frequency
signal generator 3 to be described subsequently for providing
an intermediate frequency output, a first intermediate frequency
amplifier 10 for amplifying the intermediate frequency output
from the mixer 4, a second mixer 11 for mixing the intermediate
frequency output from the first intermediate frequency amplifier
10 with a second local oscillation frequency output from the
frequency signal generator 3, a second intermediate frequency
amplifier 12 for amplifying the second intermediate output
from the mixer 11, a detector 13 for detecting the intermediate
frequency output from the second amplifier 12 for providing
an audio frequency output, an audio frequency amplifier 14
for amplifying the audio frequency output from the detector
13, and a loud speaker 15 for transducing the audio frequency
output from the amplifier 14 into a sound output.
The transmitter portion TRN comprises a microphone
5 for converting a sound into an audio electrical signal,
an audio amplifier 6 for amplifying the audio electrical signal
from the microphone 5, a modulator 7 for modulating a carrier
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signal of the carrier frequency output from the frequency signal
generator 3 with the amplified audio signal for providing a
modulated signal, a high frequency amplifier 8 for amplifying
the modulated signal from the modulator 7, and a transmitting
antenna 9 for transmitting the high frequency output of the
modulated signal from the amplifier 8.
The present inven-tion is directed to an improvement
in the frequency signal generator 3 for use in such a transceiver
comprising a receiver portion REC and a transmitter portion
TRN as described above. Such a frequency signal generator
3 is adapted to provide different frequency outputs selectively
to the mixers 4 and 11 of the receiver portion REC and the
modulator 7 of the transmitter portion TRN, respectively, on
the occasion of the receiving mode and the transmitting mode,
respectively. In the case of the receiving mode, for example,
the frequency of the carrier wave signal as received by the
antenna 1 ranges from 26.965 MHz to 27.255 MHz, for example,
such that each channel dominates a corresponding frequency
band. Therefore, in order to obtain a constant intermediate
frequency of 10.695 MHz, the frequency signal generator 3 should
be adapted such that the frequency signal output from the gener-
ator 3 is adaptably changed ranging from 37.66 MHz to 37.92
MHz in association with the receiving channels. On the other
hand, in the case of the transmitting mode, in order to change
the frequency of the carrier wave ranging from 26.965 MHz to
27.255 MHz in association with the transmitting channels, the
frequency signal generator 3 should be adapted such that the
frequency of the frequency signals from the generator 3 is
adaptably changed accordingly within the above described frequency
range. In other words, the frequency signal generator 3 should provide
an output of a variable frequency in association with the trans-
mitting channels and the receiving channels. To that end,
the frequency signal generator 3 is provided with thetransmitter/
receiver selection switch 16 for selectively switching the
transmitting mode or the receiving mode. The present invention
employs a frequency synthesizer capable of providing an oscil-
lation frequency variable within the above described frequency
range that serves as the above described frequency signal
generator 3.
Fig. 2 shows a block diagram of one embodiment of
the inventive frequency synthesizer that can be advantageously
utilized as the frequency signal generator 3 of the Fig. 1
transceiver. The inventive frequency synthesizer basically
comprises a voltage controlled oscillator 20. The voltage
controlled oscillator 20 is structured such that the oscillation
frequency thereof is varied as a function of a control voltage
applied thereto. The oscillation output from the voltage
controlled oscillator 20 is withdrawn through a buffer 21
from an output terminal fT. The oscillation output from the
voltage controlled oscillator 20 is also applied to a first
mixer 22, where the oscillation output is mixed with the refer-
ence frequency output from a reference signal oscillator 23
of preferably a crystal oscillator. The frequency converted
output thus obtained is withdrawn from an output terminal
fR. Thus, it is appreciated that the frequency synthesizer
shown comprises two output terminals, i.e. the output terminal
f T for a transmitting mode and the output terminal fR for
a receiving mode. The output obtained from the transmitting
mode terminal fT is applied to the modulator 7 in the Fig.
1 transceiver to be used by way of a carrier wave signal,
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whereas the output obtained from the receiving mode terminal
fR is applied to the mixer 4 in the Fig. 1 transceiver to be
used by way of a local oscillation frequency signal. In the
frequency synthesizer shown, the control voltage to be applied
to the voltage controlled oscillator 20 is provided as an output
from a phase detector 31, as filtered by means of a low pass
filter 32. The phase detector 31 is connected to receive, at
one input thereto, an output from a frequency divider or a ref-
erence counter 26, which is connected to receive an output from
10 the reference oscillator 23. The reference oscillator 23 is
preferably a crystal oscillator as described previously. The
reference counter 26 is operatively coupled to a first frequency
division ratio setting counter 27 which serves as a transmitter/
receiver mode selection circuit to provide a set control signal
to the reference counter 26 which serves as a programmable fre-
quency divider for setting the ratio of counting by the reference
counter 26, whereby the oscillation frequency obtained from
the first crystal oscillator 23 is divided adaptably in associa-
tion with the transmitting and receiving modes to provide a
20 reference signal of the frequency to be a reference to the res-
pective modes. The phase detector 31 is also connected to receive,
at the other input thereto, an output from a programmable frequency
divider 28, which typically comprises a programmable counter.
The programmable frequency divider 28 is connected to receive
a pulse output from a prescaler PRE for the purpose of counting
the number of pulses at the programmed ratio and is also
connected to receive a control signal from a control CTL for
the purpose of controlling the said programmed ratio. The pre-
scaler PRE comprises a reference oscillator 25 and a mixer 24
30 for mixing the oscillation frequency output from the voltage
controlled oscillator 20 with the reference frequency output
from the reference oscillator 25. I'he output from the mixer
24 is applied to the above described programmable counter 28
to be frequency divided at a given frequency division ratio.
The control CTL comprises a channel designating circuit 29 for
selectively changing the frequency division ratio in association
with the channel to be selected by the transceiver, and a second
frequency division ratio setting counter 30 which serves as
a transmitting/receiving mode selection circuit to provide a
set control signal to the programmable frequency divider 28
for setting the ratio of counting by the counter 28. The trans-
mitting/receiving mode selection circuits 27 and 30 are
operatively coupled to the above described transmitter/receiver
selection switch 16 in the Fig. 1 transceiver. The control
CTL is shown in more detail in Fig. 2B, which is described
subsequently.
The above described phase detector 31 serves to compare
the frequency of the reference signal obtained from the reference
counter 26 with the frequency of the signal being controlled
obtained from the programmable counter 28 to provide a signal
associated with the difference between the frequencies of the
signal being controlled from the programmable counter 28 and
the reference signal from the reference counter 26 such that
the above described frequency difference associated signal may
be positive if and when the frequency of the signal being con-
trolled from the programmable counter 28 is higher than the
frequency of the reference signal from the reference counter
and vice versa.
Now description will be made of the operation of the
frequency synthesizer shown in Fig. 2.
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(1) Receiving Mode
In the receiving mode of the transceiver, the frequency
synthesizer is utilized as a local oscillator of the transceiver.
According to the above described example, the frequency of the
output obtained from the output terminal fR ranges from 26.965
MHz to 27.255 MHz in association with the receiving channels
and should be variable at a predetermined frequency difference
to provide a given frequency band to the respective receiving
channels. As described previously, the output signal from the
terminal fR is obtained by mixing the output from the voltage
controlled oscillator 20 with the output from the first crystal
oscillator 23, where the oscillation frequency of the output
from the first crystal oscillator 23 is fixed at, say, 10.24
MHz. Accordingly, the control voltage to be applied to the
voltage controlled oscillator 20 should be controlled stepwise
such that the oscillation frequency of the output from the oscil-
lator 20 is changed stepwise ranging from 27.42 MHz to 27.71
MHz. In the following, description will be made of how such
control is effected.
At the outset, the transmitter/receiver selection
switch 16 is turned to the receiver side. Accordingly, the
transmitting/receiving mode selection circuits 27 and 28 are
also turned to the receiving mode. Now consider a case where
a transmitted signal of the carrier the frequency of which
is 26.965 MHz is to be received among the signals received
by the antenna 1 of the transceiver. Accordingly, the channel
designating circuit 29 is actuated to designate the desired
channel. In order to obtain an intermediate frequency signal
of 10.695 MHz based on the signal of 26.965 MHz, the frequency
of the signal obtainable from the output terminal fR must be
37.660 MHz. On the other hand, since the oscillation frequency
of the first crystal oscillator 23 is 10.24 MHz, as described
previously, the oscillation frequency of the voltage controlled
oscillator 20 must be 27.42 MHz. If and when the voltage control-
led oscillator 20 is oscillating properly at the frequency
of 27.42 MHz, this oscillation signal is mixed by means of
the second mixer 24 with the oscillation signal of 25.76 MHz
from the second crystal oscillator 25, thereby to provide a
signal of the frequency difference of 1.66 MHz. This frequency
difference signal is frequency divided by means of the program-
mable eounter 28. The frequency division ratio of the ;~
programmable counter 28 has been set to 1/166 at that time
in response to seleetion of the reeeiving mode by the transmit-
ting/reeeiving mode seleetion eireuit 30 and switching of the
ehannel designating cireuit 29 in assoeiation with the above
deseribed reeeiving frequeney. As a result, the signal being
eontrolled as eounted by the programmable eounter 28 turns
to be 10 KHz. On the other hand, the frequeney division ratio
of the referenee eounter 26 has also been set to 1/1024 at
that time in response to the receiving mode selected by the
transmitting/receiving mode selection eircuit 27. Accordingly,
a referenee signal of 10 KHz is also obtained from the reference
eounter 26. This frequeney is not varied, insofar as the
reeeiving mode is seleeted by the transmitting/receiving mode
selection cireuit 27. The signal from the programmable counter
28 and the signal from the reference counter 26 are fed to
the phase detector 31. However, there is no difference between
the frequencies of these signals. Therefore, the phase detec-
tor 31 does not provide a control signal. As a result, the
voltage eontrolled oscillator 20 continues to oscillate at
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the frequency of 27.42 MHz.
Assuming that the oscillation frequency of the voltage
controlled oscillator 20 varies because of variation of the
voltage of the power source, the ambient temperature and the
like, the frequency of the signal from the second mixer 24
accordingly varies and thus the frequency of the signal being
controlled from the programmable counter 28 also varies, with
the result that there occurs a frequency difference between
the signals being applied to the phase detector 31. As a result,
10 the phase detector 31 provides a positive or negative control
signal in accordance with the frequency difference, thereby
to properly correct the oscillation frequency of the voltage
controlled oscillator 20. Thus, the oscillation frequency of t
the voltage controlled oscillator 20 is always corrected to
; provide an output signal of the desired frequency at the output
terminal fR.
Now consider a case where the receiving channel is
changed. First the channel designating circuit 29 is switched
in association with selection of a new receiving channel, so
20 that the frequency division ratio of the programmable counter
28 is accordingly changed. Now let it be assumed that the fre-
quency division ratio is changed from the previous value of
1/166 to a new value of 1/195. Since the voltage controlled
oscillator 20 is still oscillating at the previous frequency
of 27.42 MHz at that time, the frequency of the output from
the second mixer 24 is 1.66 MHz. This signal of the frequency
of 1.66 MHz is frequency divided by means of the programmable
counter 28. Since the frequency division ratio of the programm-
able counter 28 is 1/195, a signal being controlled of the fre-
30 quency of 8.5 KHz is obtained from the programmable counter 28.
Since the frequency of the reference signal obtained from the
reference counter 26 is always constant i.e. 10 KHz, there occurs
a frequency difference between the signals being applied to
the phase detector 31 and accordingly the oscillation frequency
of the voltage controlled oscillator 20 increases. The oscilla-
tion frequency of the voltage controlled oscillator 20 continues
to increase in such a manner, until the frequency of the signal
being controlled from the programmable counter 28 reaches 10
KHz. In other words, if and when the oscillation frequency
10 of the voltage controlled oscillator 20 reaches 27.71 MHz, the
frequency of the signal from the second mixer 24 becomes 1.95
MHz, which is frequency divided by the programmable counter
28 at the frequency division ratio of 1/195 to provide a signal
being controlled of 10 KHz, with the result that the oscillation
frequency of the voltage controlled oscillator 20 increases
to reach the above described frequency of 10 KHz. Since the
frequency of the signal obtainable at the output terminal fR
becomes 37.95 MHz at that time, only a transmitted wave signal
of the carrier of the frequency 27.255 MHz is selected by the
20 transceiver among the transmitted wave signals received by the
antenna.
(2) Transmitting Mode
In the transmitting mode of the transceiver, the fre-
quency synthesizer is utilized to provide a carrier wave for
the transmitter portion of the transceiver. Since in the trans-
mitting mode the signal obtained from the output terminal fT
is used by way of a carrier wave signal, the frequency of the
output obtained from the output terminal fT must be stepwise
variable within the range of 26.965 MHz to 27.255 MHz in associa-
30 tion with a transmitting channel. To that end, the transmitter/
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receiver selection switch 16 is first turned to the transmittingside. Accordingly, the transmitting/receiving mode selection
circuits 27 and 30 are switched to the transmitting mode. The
channel designating circuit 29 is also operated to obtain a
carrier wave of a desired frequency. Let is be assumed that
the frequency division ratio of the programmable counter 28
at that time is 1/241, for example. Assuming now that the
oscillation frequency of the voltage controlled oscillator 20
is 26.965 MHz, the frequency of the signal from the second mixer
24 turns to be 1.205 MHz and the frequency of the signal from
' the programmable counter 28 turns accordingly to 5 KHz. On
the other hand, since the frequency division ratio of the refer-
ence counter 26 has been set to the value of 1/2048 at that
time in response to the selection of the transmitting mode by
the transmitting/receiving mode selection circuit 27. According-
ly, the frequency of the reference signal obtainable from the
reference counter 26 turns to be 5 KHz and the frequency differ-
ence between the signals being applied to the phase detector
31 turns to zero. As a result, the phase detector 31 does not
provide a control signal and thus the voltage controlled oscilla~
tor 20 oscillates at the previous frequency of 26.965 MHz. The
oscillation signal of 26.965 MHz is withdrawn frcm the output
terminal fT by way of a carrier wave. If and when the oscillation
frequency of the voltage controlled oscillator 20 varies, the
frequency of the signal from the programmable counter 28 also
varies, so that a control signal is obtained from the phase
detector, which serves to properly correct the oscillation
frequency of the voltage controlled oscillator 20.
If it is desired to change the transmitting channel,
the channel designating circuit 29 is switched in such a manner
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as described previously, whereby the frequency division ratio
of the programmable counter 28 is changed. Assuming that the
oscillation frequency of the voltage controlled oscillator 20
remains as before, the frequency of the signal from the program~
mable counter 28 differs from the frequency of the signal from
the reference counter 26, with the result that the phase detector
31 provides a control signal. Therefore, the oscillation
frequency of the voltage controlled oscillator 20 is corrected
until the frequency of the signal being controlled from the
programmable counter 28 becomes the same as the frequency of
the reference signal from the reference counter 26. The
oscillation frequency of the voltage controlled oscillator 20,
; thus corrected, is used as a carrier wave signal for the selected
transmitted channel.
Fig. 2A is a block diagram showing in more detail
the transmitting/receiving selection circuit 30 and the peri-
pheral portion associated therewith constituting the esential
feature of the frequency synthesizer shown in Fig. 2. As de-
scribed with reference to Fig. 2, the frequency division ratio
of the programmable counter 28 is controlled by means of the
channel designating circuit 29 and the transmitting/receiving
mode selection circuit 30. The manner of such control will
be described with reference to Fig. 2B, which shows waveforms
at various portions in the Fig. 2A diagram.
Referring to Fig. 2A, the channel designating circuit
29 comprises nine switches SW1 through SW9. These switches
SWl through SW9 are connected at one end thereof commonly to
a signal source representing the logic one and at the other
terminals individually to the corresponding inputs of the trans-
mitting/receiving mode selection circuit 30. Assuming that the
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total number of the channels to be selected is 40, -these switches
are selectively operated to achieve forty kinds of combinations
by means of these nine switches. For example, one channel is
selected by selectively turning on the switches SWl and SW3,
another channel is selected by turning on the switches SW2,
SW4 and SW8, and so on. The transmitting/receiving mode select-
; ing circuit 30 comprises nine full adders FAl through FA9
provided in a cascade fashion and nine gate groups Gl through
G9, each group comprising two AND gates and one OR gate. Each
of these full adders FAl through FA9 has a carry-in input
terminal c, an addend input terminal a, a summand input terminal
b, a sum output terminal S, and a carry-out output terminal
CO. The truth table of these factors is shown in Table 1.
TABLE 1
ai bi Ci S Co
O O O O O
O 0 1 1 0
0 1 1 0
0 1 0 1 0
1 1 l
0 1 0
0 0 1 0
The carry-out terminal CO of each of the full adders
FAl through FA9 is connected to the carry-in terminal C of the
respective adjacent full adder in the more significant bit posi-
tion. The carry-in terminal of the full adder FAl corresponding
to the least significant bit position is coupled to the voltage
source of the logic zero. The addend input terminal a of each
of the full adders FAl through FA9 is connected to the other
end of the corresponding one of the switches SWl through SW9
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in the channel designating circuit 29. The summand input
terminal b of each of the full adders FAl through FA9 is con-
nectecl to any one of four logical signal lines Ql through Q4
in the manner to be described subsequently. The logical signal
line ~1 is adapted to represent the logic one, while the signal
line Q2 is adapted to represent the logic zero. The signal
line Q3 is connected through an inverter I to the transmitter/
receiver selection switch 16 and the signal line Q4 is directly
connected to the transmitter/receiver selection switch 16, so
that in case of the transmitting mode the switch 16 is closed
and the signal line Q3 is brought to the logic zero while the
signal line Q4 is brought to the logic 1 whereas in case of
the receiving mode the transmitter/receiver selection switch
16 is open and the logical state of the signal lines Q3 and Q4 is
reversed. In other words, the logical states of the signal
lines Q3 and Q4 are complementary to each other.
Each of the above described gate groups Gl through
G9 in the transmitting/receiving mode selection circuit 30 com-
prises two AND gates and one OR gate, as described previously.
One input to one AND gate of these two AND gates is connected
to the corresponding one of the sum input in terminals Sl through
S9 of the full adders FAl through FA9 and the other input to
the said one AND gate of these two AND gates is connected to
the logical signal line Q4. One input to the other AND gate
of these two AND gates is connected to the logical signal line
Q3 and the other input to the other AND gate of these two AND
gates is connected to the sum output S of the adjacent full
adder in the more significant bit position. The outputs from
these two AND gates are applied through the corresponding OR
gate to the programmable counter 28. The bit parallel output
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withdrawn from the OR gates are utilized by way of a jam data.
These gate groups Gl through G9 are generally referred to as
a bit shifter 30A, because in case of the receiving mode, i.e.
when the signal line ~3 is the logic one, the right side AND
gates, as viewed in the figure, of the respective gate groups
Gl through G9 are enabled, so that the output from the sum output
terminal S of the adjacent full adder in the more significant
bit position is withdrawn from the gate group corresponding
to one less significant adjacent bit position, with the result
that the bit parallel output from nine full adders FAl through
FA9 are shifted as a whole by one bit.
The above described programmable counter 28 comprises
flip-flops FFl through FF9 each having a reset terminal. The
output terminals Q of these flip-flops are connected to the
inputs to an AND gate 101 and the output from the AND gate 101
is connected through an inverter to cross connected NAND gates
102 and 103 and the input terminal R of each flip-flop is indi-
vidually connected to the corresponding AND gate. Each of these
AND gates is connected, at one input thereto, to the output
of the corresponding one of the gate groups Gl through G9 and,
at the other input thereto, commonly to the output of the above
described cross connected NAND gates 102 and 103. The terminal
T of the flip-flop FFl corresponding to the least bit position
is connected to receive an inverted output of the above described
mixer 24. The output of the NAND gate 102 is also applied to
the phase detector 31 as the output of the programmable counter
28.
The above described reference counter 26 comprises
eleven toggle flip-flops (simply referred to as T flip-flop
hereinafter) connected in a cascade fashion, structured to
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provide the frequency division ratio of 1/1024 on the occasion
of reception and the frequency division ratio of 1/2048 on the
occasion of transmission. The transmitting/receiving mode selec-
tion circuit 27 for selecting the transmitting mode and the
recelving mode comprises an inverter 271, two AND gates 272
and 273 and an OR gate 274. Briefly described, selection of
the transmitting mode and the receiving mode is achieved by
selectively withdrawing the output of the reference counter
26 comprising T flip-flops from the terminal Q of the right
most T flip-flop, as viewed in the figure, or from the terminal
Q of T flip-flop next to the right most one. To that end, one
input to one AND gate 272 of the above described selection cir-
cuit 27 is connected to the terminal Q of the right most T flip-
flop and one input to the other AND gate 273 is connected to
the terminal Q of the T flip-flop next to the right most one.
The other inputs to these AND gates 272 and 273 are connected
to receive complementary logical signals, respectively, which
may be the output from the transmitter/receiver selection switch
16 and an inverted output thereof. It is readily understood
that on the occasion of the transmitting mode, i.e. the frequen-
cy division ratio 1/2048 the said one AND gata 272 should be
enabled and on the occasion of the receiving mode, i.e. the
frequency division ratio 1/1024 the said other AND gate 273
should be enabled. The outputs from these AND gates 272 and
273 are applied through the OR gate 274 to the phase detector
31.
Now referring to Fig. 2, the operation shown in Fig.
2B and setting of the frequency division ratio will be described.
Assuming that the frequency division ratio of the programmable
counter 28 is l/N, the frequencies at various portions of the
~ ~ r~
Fig. 2 diagram can be evaluated based on the values described
previously with reference to Fig. 2.
(1) Output from Second Mixer
(5 x N) KHz....on the occasion of transmission
(10 x N) KHz....on the occasion of reception
(2) Output from Voltage Controlled Oscillator 20
(5 x N + 25760) KHz....on the occasion of
transmission
(10 x N + 25760) KHz....on the occasion of
reception
(3) Output from Buffer 21 (Limited to transmission)
fT = (5 x N + 25760) KHz
(4) Output from First Mixer 22 (Limited to reception)
fR = [(10 x N + 25760) + 10240] KHz = (10 x N +
36000) KHz
where N is set as follows:
N = NRo + ~N ... (reception)
(QN: 0,1,2)
N NTo + AN ... (transmission)
Considering a case where such values of NTo and NRo
that satisfy
fT = 26965 KHz ... (transmission)
fR = 37660 KHz ... (reception)
When N = 0 (as is clear from the subsequent description
the value of ~N is dependent on the value set in the channel
designating circuit 29 and ~N = 0 indicates that the value set in
the channel designating circuit 29 is zero), the following
equations are obtained:
5NTo + 25760 = 26965
N = 26965 25760 241
- 23 -
2S
lONRo + 36000 = 37660
NRO = 7660036 = 166
It is appreciated from the foregoing NTo and NRo
equations thus obtained that on the occasion of the transmission
the frequency fT is increased by 5 KHz each time the number
~ N is increased by one and on the occasion of the reception
the frequency fR is varied by 10 KHz each time the number
~ N is varied by one. Accordingly, in order to vary the
frequency fT by 10 KHz, the number ~ N should be varied
by two.
Connection of the summand input terminal b of
each of the full adders FAl through FA9 in the above described
transmitting/receiving mode selection circuit 30 and any
one of the four signal lines Ql through Q4 is inherently
determined as described in the following by the values
of NTo and NRo thus obtained.
N = 241 = (011110001) binarY
NRo = 166 = (010100110) binary
connection of
,~ signal lines (OlTlTORRT)
4' i~ where T designates the singal line Q4 and R designates
~:.
the signal line Q3. More specifically, on the occasion
of transmission where T = 1, the number NTo = 241 = (011110001)
binary is applied, in the bit parallel code, to the summand
input terminals b of the full adders FAl through FA9, while
on the occaslon of reception where R = 1 the number of
NRo = 166 = (OlOlOOllO)binary is applied, in the bit parallel
code, to the summand input terminals b of the full adders
FAl through FA9. Assuming that the value set in the channel
- 24 -
desigllating circuit 29 is zero, i.e. all the switches are opened,
the said value NTo or NRo may be applied ultimately to the
programmable counter 28. However, in the Fig. 2A embodiment,
the channel designating circuit 29 has been structured such
that the rate of variation of the set value caused by changes
of the channel setting remains always constant irrespective
of whether the apparatus is in the transmitting mode or in
the receiving mode, i.e. the set value changes by two for each
channel setting. In other words, the frequencies fR and fT
are determined by the value set by designation of the channel
designating circuit 29, i.e. the logical state P in which
P = ~ SWi21 1, where SWg is a binary number in the least signi-
ficant bit position and SWg is a binary number of the mostsignificant bit position and SWi is the logic one if and when
the corresponding switch is turned on and is the logic zero
if and when the corresponding switch is turned off. Thus it
is appreciated that these gate groups Gl through G9 are provided
to constitute a bit shifter 30A for the purpose of changing
the frequencies fR and fT by 10 KHz each time the value of
the above described logical state combination is changed by
2. The bit shifter 30A is aimed to achieve, at the receiving
mode, the following equation:
tP + NRo,)/2 = NRo + A N
the above described equation may be expressed as follows:
P + RO' = NRo + ~ N
Assuming RO' = NRo~ the following equation is
obtained, P = ~ N
When P is increased by 2,~ N increased by one and
- 25 -
thus the frequency fR increases by 10 KHz. Thus, since the
bit shifter 30A is utilized, the value NRol = 2NRo - 2 x 166
= 332 obtained from the above described equation NRO' = NRo
is utilized as a data for determining connection of any one
of the signal lines Q1 through Q4 and the summand input terminals
b of the full adders FAl through FA9. Namely,
NTo = 241 = (OllllOOOl)binary
NRo~= 332 = (lOlOOllOO)binary
connection of
signal lines (RTlTTRROT) ................... ~
Referring to the equation ~ the right most end cor-
responds to the least significant bit position and the left
most end corresponds to the most significant bit position.
The connection between the four signal lines Ql through Q4 and
the full adders FAl through FA9 in Fig. 2A is determined based
on such equation.
Fig. 2B shows waveforms of the programmable counter
28 of Fig. 2A for use in explaining the operation thereof.
Referring to Fig. 2B, the waveform (1) shows the output from
the second mixer 24 and the waveform (2) shows the inverted
waveform thereof. The T flip-flop FFl through FF9 are adapted
to be set responsive to the fall of the waveform (2). All
the Q outputs from the T flip-flops FFl through FF9 become
"1" if and when the count number by these flip-flops reaches
the number "511", and as soon as the count number 511 is reached,
a triggering signal shown as the waveform (3) is withdrawn,
whereby the frequency divided output of the waveform (4) is
obtained from the NAND gate 102. It is to be noted that in
the circuit configuration shown the time period corresponding
- 26 -
2~
to the count number "511" also corresponds to the count of
the numbers corresponding to the reset state by the data from
the circuit 30. Assuming, for example, that the bit parallel
output value of the T flip-flops FFl through FF9 when these
have been reset is "270", it follows that if and when the above
described number 511 is counted the count value becomes 270
simultaneously. In other words, it can be said that the fre-
quency division ratio N = 511 270 = 241.
The transmitting mode/receiving mode selection circuit
27 and the bit shifter 30A in Fig. 2A comprise an improvement
aimed to eliminate leakage of the lock up time and the reference
frequency on the occasion of the phase locked loop operation,
with the reference frequency at the time of reception being
10 KHz, and if it is desired to make the reference frequency
be 5 KHz on the occasion of both transmission and reception,
T in the above described circuit 27 and the bit shifter 30A
may be fixed to "1".
Fig. 2C is a schematic diagram of another embodiment
of the transmitting/receiving mode selection circuit 30 in
Fig. 2, which can be employed in place of the Fig. 2A embodi-
ment. The Fig. 2C embodiment is characterized in that the
above described mode selection circuit 30 is implemented by
a read only memory (ROM). The read only memory shown comprises
a first matrix MXl comprising row lines rlOl through rll2 in-
dividually connected to the outputs from the switches SW2
through SW6 of the channel designating circuit 29 and the
inverted outputs thereof and column lines T01 through T20 and
R01 through R20, and a second matrix MX2 comprising the above
described column lines T01 through T20 and R01 through R20
withdrawn from the above described first matrix MXl and column
- 27 -
~3~
lines r201 -through r209. The outputs withdrawn from the row
lines r201 through r209 of the above described second matrix
MX2 are applied to the gate groups Gl through G9 in Fig. 2A,
thereby to represent the ratio of frequency division correspond-
ing to a designated channel. The embodiment shown has been
structured such that 20 channels can be designated by means
of the channel designating circuit 29 on each occasion of trans-
mission or reception. To that end, the column lines T01 through
T20 and R01 through R20 are provided in the embodiment shown.
The truth table of the bit parallel output of the frequency
division ratio N obtained at row lines Sl through S9 from the
above described second matrix MX2 ultimately is shown in Table
2.
Table 2
DecimalBinary
NS9 S8 S7 S6 S5 S4 S3 S2
T01 241 0 1 1 1 1 0 0 0
T02 243 0 1 1 1 1 0 0
T03 245 0 1 1 1 1 0 1 0
T04 247 0 1 1 1 1 0
T05 249 0 1 1 1 1 1 0 0
T06 251 0 1 1 1 1 1 0
T07 253 0 1 1 1 1 1 1 0
T08 255 0
T09 257 1 0 0 0 0 O 0 0
T10 259 1 0 0 0 0 0 0
Tll 261 1 0 0 0 0 0 1 0
T12 263 1 0 0 0 0 0
T13 265 1 0 0 0 0 1 0 0
T14 267 1 0 0 0 0 1 0
T15 269 1 0 0 0 0 1 1 O
T16 271 1 0 0 0 0
T17 273 1 0 0 0 1 0 0 0
T18 275 1 0 0 0 1 0 0 1 1 9 n-l
Tl9 277 1 0 0 0 1 0 1 0 1N = ~ Sn2
T20 279 1 0 0 0 1 0 1 1 1 n-l
R01 332 1 0 1 0 0 1 1 0 0
R02 334 1 0 1 0 0 1 1 1 0
- 28 -
~J~
~f~?~
Decimal Binary
N sg s3 S7 S6 ~5 S4 S3 2
R03 336 1 0 1 0 1 0 0 0 0
R04 338 1 0 1 0 1 0 0 1 0
R05 340 1 0 1 0 1 0 1 0 0
R06 342 1 0 1 0 1 0 1 1 0
R07 344 1 0 1 0 1 1 0 0 0
R08 346 1 0 1 0 1 1 0 1 0
RO9 348 1 0 1 0 1 1 1 0 0
R10 350 1 0 1 0 1 1 1 1 0
Rll 352 1 0 1 1 0 0 0 0 0
R12 354 1 0 1 1 0 0 0 1 0
R13 356 1 0 1 1 0 0 1 0 0
R14 358 1 0 1 1 0 0 1 1 0
R15 360 1 0 1 1 0 1 0 0 0
R16 362 1 0 1 1 0 1 0 1 0
R17 364 1 0 1 1 0 1 1 0 0
R18 366 1 0 1 1 0 1 1 1 0
Rl9 368 1 0 1 1 1 0 0 0 0
R20 370 1 0 1 1 1 0 0 1 0
TA~LE 2
In order to obtain such outputs as determined in
the truth table shown, the matrixes MXl and MX2 are structured
such that the circle marked intersections therein are selected
to have the following meaning. More specifically, the matrixes
are structured such that the outputs obtained in the column
lines TOl through R20 in the matrix MX1 may be a NANDed output
of the inputs as circle marked at the intersections between
the said column lines and the row lines rlOl through rll2,
as shown in Fig. 2D, and the final outputs from the read only
memory withdrawn through the lines Sl through S9 in the matrix
MX2 may be a NANDed output of the inputs as circle marked of
the intersections between the said row lines and the column
lines TOl through R20, as shown in Fig. 2E.
Now consider a case where the transmitting channel
TOl is set, for facility of understanding. In such a situation,
the switch SW2 of the channel designating circuit 29 is turned
on. Therefore, the column lines rlOl, rlO4, rlO6, rlO8, rllO
- 29 -
and rlll become the logic one. Accordingly, the column line
T01 becomes the logic zero and all the remaining column lines
T02 through R20 become the logic one. Therefore, it is appreci-
ated that the logic state combination withdrawn from the lines
Sl through S9 is dependent solely on the logic zero of the
column line T01 and becomes (011110001). From the foregoing
description, it is further appreciated that in case where a
given channel is designated the logic state of only the column
line corresponding to the said given channel becomes the logic
"0", while all the remaining column lines become the logic
"1", with the result that the logic "1" is withdrawn from the
circle marked portions of the intersections between the said
particular line and the row lines r201 through r209. Thus,
it is apparent that the circle mark at the intersections between
the column lines T01 through R20 and the row lines r201 through
r209 are selected to correspond to the logic "1" in the truth
table of Table 2.
Fig. 3 is a block diagram of another embodiment of
the inventive frequency synthesizer. The point of the Fig.
3 embodiment different from the Fig. 2 embodiment is that the
first crystal oscillator 23 is used as the first and second
crystal oscillators in terms of the Fig. 2 embodiment and instead
a ~ frequency divider 33 and a 5 frequency multiplier 34 are
additionally employed. The oscillation signal of the voltage
controlled oscillator 20 is directly withdrawn from the output
terminal fT and the oscillation signal thus obtained is utilized
by way of a carrier wave signal of the transceiver. Since
the second mixer 24 is supplied with the signal of the frequency
25.60 MHz (= 10.24 x ~ x 5) obtained from the first crystal
oscillator 23 through the ~ frequen_y divider 33 and the 5
- 30 -
frequency multlplier 34 and the oscillation signal of the
frequencies 27.42 through 27.71 MHz obtained from the voltage
controlled oscillator 20, -the signal of the frequencies 1.365
MHz through 1.655 MHz iS obtained from the second mixer 24.
Therefore, if a given channel is set by the channel designating
circuit 29 and the frequency division ratio of the programmable
counter is selected to a value within the range of 273 to 331
in accordance with the set channel, the signal being controlled
of approximately 5 KHz is obtained at the output of the program-
mable counter 28. On the other hand, the reference counter26 always provides the reference signal of a fixed frequency
of 5 KHz. Accordingly, as in case of the Fig. 2 embodiment,
the phase detector 31 serves to compare the frequencies of
the above described signal being controlled and the reference
signal, thereby to provide a positive or negative control signal,
if and when there is a frequency difference therebetween, to
control the frequency of the voltage controlled oscillator
20 to the correct value.
Fig. 3A is a schematic diagram of the transmittingj
receiving mode selection circuit 30 in Fig. 3 and portions
associated therewith. The relation of the Fig. 3A to Fig.
3 is similar to the relation of Fig. 2A to Fig. 2. Since the
Fig. 3 embodiment has been structured such that the reference
frequency of the reference counter 26 may be the same value
of 5 KHz both in the transmitting mode and in the receiving
mode, the bit shifter included in the transmitting/receiving
mode selection circuit 30 shown in Fig. 2A has notbeen employed
in the Fig. 3A embodiment. Similarly, the frequency division
ratio of the reference counter 26 remains constant to be 1/1024,
only ten T flip-flops are employed. Connection of any one
- 31 -
of the logic signal lines Ql through Q4 and the summand input
terminals b of the full adders FAl through FA9 is determined
in the manner same as that described with reference to Fig.
2A.
Fig. 4 is a block diagram of a further embodiment
of the inventive frequency synthesizer. The Fig. 4 embodiment
is substantially the same as the Fig. 3 embodiment in the block
diagram structure, but employs a three-frequency multipler
35 in place of the five-frequency multiplier 34 in the Fig.
3 embodiment. The Fig. 4 embodiment is further different from
the Fig. 3 embodiment in that the signal obtainable from the
output terminal fT for withdrawing the carrier wave signal
of the transceiver is obtained by mixing the oscillation signal
of the first crystal oscillator 23 with the oscillation signa-l
of the voltage controlled oscillator 20 and the signal obtain-
able from the output terminal fR for withdrawing the local
oscillation signal for supply to the mixer 4 of the transceiver
is directly withdrawn from the voltage controlled oscillator
20. A further difference therebetween is that the Fig. 3 embodi-
ment utilizes, by way of the local oscillation signal, the signal10.695 MHz higher than the signal obtained from the antenna
1, whereas the Fig. 4 embodiment uses, by way of the local
oscillation signal, the signal of 16.27 through 16.56 MHz which
is 10.695 MHz lower than the signal of the frequencies 26.965
MHz through 27.255 MHz received by the antenna.
Fig. 4A is a schematic diagram showing in more detail
the transmitting/receiving mode selection circuit 30 and the
portions associated therewith shown in Fig. 3. The structure
of the Fig. 4B embodiment is substantially the same as that
of the Fig. 3B embodiment, the difference therebetween being
that the frequency division ratio of the programmable counter
28 is different, as shown in Fig. 4, and accordingly connection
of any one of the logic signal lines Ql through Q4 and the
summand input terminals b of the full adders FAl through FA9
determinable based thereon is accordingly different.
In the foregoing, the embodiments were described
by taking an example of the channels for transceivers to be
borne in automobiles. Therefore, the embodiments were structured
such that the frequency division ratio of the reference counter
is different in the receiving and transmitting modes so that
the reference signal of different frequencies is used for the
purpose of controlling. However, in a different transmitting/
receiving system, a reference signal of the same frequency
may be used in the transmitting and receiving modes. In the
latter situation, a frequency synthesizer can be implemented
that employs a minimum number of voltage controlled oscillators
and crystal oscillators, by making different the frequency
division ratio of the programmable counter in the transmitting
and receiving modes in the manner as described above.
As described in the foregoing, the inventive frequency
synthesizer is structured such that a signal being controlled
having the frequency similar to that of a reference signal
from a voltage controlled oscillator is obtained by means of
a programmable counter. Therefore, the signals of many oscil-
lation frequencies can be obtained with a less number of crystal
oscillators. The inventive frequency synthesizer has been
further structured such that the frequency division ratio of
the above described programmable counter is variable in accord-
ance with the channels and also in accordance with the terminals
to be used by -the transmitting/receiving mode selection circuit.
,,., -
Therefore, even in cases where the output frequency signalof different frequency variable range is obtained from two
or more output terminals, a voltage controlled oscillator can
be commonly used, with the result that the circuit configuration
of the inventive apparatus is very simple.
In general, a programmable counter to be used by
way of a frequency dividing means most often comprises field
effect transistors, of such as MOS type. Assuming that the
output frequency of the above described voltage controlled
oscillator becomes abnormally high such as in a case where
the oscillator is diverted from a balanced state in channel
switching, for example, such MOS type field effect transistors
come to exceed the operating limit to cause a malfunction of
the programmable counter, whereby an output of the frequency
is obtained which is lower than that normally obtained by the
frequency division. If and when the frequency of such an
abnormal output signal becomes lower than that of the frequency
divided output of the oscillation signal from the crystal oscil-
lator, the control signal obtained from the phase detector
serves to further enhance the oscillation frequency of the
voltage controlled oscillator, so that the feed back operation
in the system is lost. As a result, the output signal of the
frequency fixed to a possible upper limit frequency is obtained
from the voltage controlled oscillator. Accordingly, it is
also desired that any problems whatsoever for causing the above
described malfunction is solved.
Fig. 5 is a block diagram of still a further embodiment
of the inventive frequency synthesizer aimed to solve the above
described problem, wherein consideration has been given to
prevent any malfunction of a programmable counter for frquency
- 34 -
z~
dividing the oscillation signal of the voltage controlled
oscillator. The structure of the Fig. 5 embodiment is based
on the Fig. 2 embodiment and therefore the same or like portions
have been denoted by the same reference characters. By way
of a characteristic feature of the Fig. 5 embodiment, the embod-
iment shown comprises an operation limit detector 500 coupled
to the reference counter 26 and the programmable counter 28
for preventing the above described malfunction, and a gate
circuit 600 connected between the above described programmable
counter 28 and the phase detector 31. The gate circuit 600
comprises a set of first and second AND gates 610 and 620,
an inverter 630 connected between these AND gates 610 and 620,
and an OR gate 640. One input terminal of the respective first
and second AND gates 610 and 620 are connected directly and
through the inverter 630 to the above described operation limit
detector 500. The other input terminal of the first AND gate
610 is connected to the output of the signal being controlled
of the programmable counter 28 and the other input terminal
of the second AND gate 620 is connected to the stage preceding
the final stage of the reference counter 26. In other words,
the gate circuit 600 serves to prevent the signal being control-
led from the programmable counter 28 from being applied to
the phase detector 31 and instead to allow the output of the
stage preceding the final stage of the reference counter 26
to be applied to the phase detector 31, if and when the operation
limit detected output is obtained from the operation limit
detector 500.
Referring to Fig. 5A, which shows in more detail
a schematic diagram of the operation limit detector 500 and
associated blocks, the detector 500 comprises one-shot
- 35 -
multivibrators 510 and 520 connected to the reference counter
26 and the programmable counter 28, respectively, a pair of
MOS type transistors 540 and 530 on/off controlled responsive
to the outputs from these multivibrators 510 and 520, a capaci-
tor 550 connected to be charged or discharged responsive to
on/off control of these transistors 530 and 540, and a Schmitt
circuit 560 for providing a pulse output if and when the charged
voltage in the capacitor 550 reaches a predetermined value.
The frequency of the signal supplied from the programmable
counter 28 to the one-shot multivibrator 520 on the occasion
of a normal operation is selected to be larger than the frequency
of the signal supplied from the reference counter 26 to the
one-shot multivibrator 510. Accordingly, on the occasion of
the normal operation, the quantity of electricity discharged
from the capacitor 550 while the MOS type transistor 530 is
turned on is larger than the quantity of electricity charged
in the capacitor 550 while the MOS type transistor 540 is turned
on. Therefore, the charged voltage of the capacitor 550 does
not reach a value high enough to turn on the Schmitt circuit
560. Now assuming that the programmable counter 28 causes
a malfunction whereby the frequency of the output signal becomes
extremely decreased to be lower than the frequency of the signal
from the reference counter 26, then the quantity of electricity
charged to the capacitor 550 while the MOS type transistor
540 is turned on is larger than the quantity of electrically
discharged from the capacitor 550 while the MOS type transistor
530 is turned on. As a result, the charged voltage in the
capacitor 550 becomes a levelhigher than the threshold voltage
where the Schmitt circuit 560 is operable, whereby an output
signal is obtained from the Schmitt circuit 560. In other
- 36 -
words, this operating point is the detection point of the limit
detector 500. The above described operation has been best
seen in Fig. 5B, wherein the waveform (a) shows a time period
when the MOS transistor 540 is turned on, the waveform (b)
shows the time period when the MOS type transistor 530 is turned
on, and the waveform (c) shows the charging and discharging
state of the capacitor 550. In Fig. 5, the waveform (b) has
been drawn at a larger interval at the right half portion to
show a decrease of the frequency and the point d shown in the
waveform (c) denotes the above described detection point.
Now the operation of the Fig. 5 embodiment will be
described with reference to Fig. 5A. The fundamental operation
of the frequency synthesizer shown in Fig. 5 is substantially
the same as that described previously centering on the Figs.
2 and 2A embodiment. Therefore, only a characteristic feature
of the Fig. 5 embodiment will be described. As described pre-
viously with reference to Fig. 2, if and when the oscillation
frequency of the voltage controlled oscillator 20 is varied
as a function of variation of the source voltage or an ambient
temperature, the frequency of the output from the second mixer
25 is varied accordingly and thus the frequency of the output
from the programmable counter 28 is also varied, with the result
that a frequency difference is caused between the input signals
to the phase detector 31 and a control signal associated with
the frequency difference is obtained from the phase detector
31, which served to correct the oscillation frequency of the
voltage controlled oscillator 20. If and when variation of
the frequency of the voltage controlled oscillator 20 is small,
such variation is sufficien-tly corrected by such embodiment. ;
However, assuming that the frequency of the voltage controlled
- 37 -
2~
oscillator 20 varies abnormally to a higher value because of
a noise in channel switching, for example, it could happen
that MOS type transistors constituting the programmable counter
28 exceeds a frequency limit to cause a miss count by means
of the programmable counter 28 or to fully stop the count.
This could cause an extreme decrease of the frequency of the
signal supplied from the programmable counter 28 to the opera-
tion limit detector 500, with the result that the charged volt-
age in the capacitor 550 in the operation limit detector 500
becomes high enough to provide a signal from the Schmitt circuit
560 (see the waveform (c) in Fig. 5B). If and when the detection
point d of the operation limit detector 500 is reached, as shown
in Fig. 5B, the signal obtainable from the Schmitt circuit
560 is applied to the second AND gate 620 in the gate circuit
600, so that the second AND gate 620 is turned on while the
first AND gate 610 is turned off. As a result, the signal
of the higher frquency obtained from the stage preceding the
final stage of the reference counter 26 is applied through
the gate circuit 600 to the phase detector 31. Therefore,
the frequency difference between the input signals to the phase
detector 31 becomes larger, whereby the increase in the
frequency of the input signal to the programmable counter 28
is emphasized, whereby a larger positive control signal is
obtained from the phase detector 31. Since the control signal
reduces the oscillation frequency of the voltage controlled
oscillator 20 to the lower limit of the stabilized operation
region thereof, it does not follow that the oscillation
frequency of the voltage controlled oscillator 20 exceeds
- 38 -
the operation limit of the programmable counter to loose the
feed back function of the system.
In the foregoing, the description was made of a case
where an operation limit detector is employed which is opera-
tive when the frequency of the programmable counter exceeds
the allowable upper limit value. Alternatively, however, a
different frequency synthesizer can also be obtained that is
characterized in that the detection point resides in the
frequency slightly lower than the allowable maximum limit
value of the programmable counter, an operation limit detector
responsive to the detection point for providing an output
signal is employed, and if and when the frequency of the input
signal to the programmable counter reaches the above described
detection point the signal from the programmable counter to
the phase detector is forcibly switched to the signal of the
frequency higher than that of the reference signal, in
response to the output signal from the operation limit
detector, as in a case where the above described limit value is
exceeded, whereby operation of the apparatus is always achieved
within the stabilized operation region.
In case where the allowable operable frequency of
the programmable counter has the maximum value such as in case
where the programmable counter is implemented by an MOS dynamic
logic, an operation limit detector may be employed that provides
an output signal when a frequency slightly higher than the ;
allowable lower limit value is reached and the signal from
the programmable counter to the phase detector may be forcibly
switched to the frequency lower than that of the reference
sisnal in response to the output from the detector, whereby
the freqllency of the volta~e controlled oscillator can ~e enhanced to a
- 39 -
Z~
stabilization region of the programmable counter and hence
a malfunction of the apparatus can be prevented.
Although this invention has been described and illus-
trated in detail, it is to be clearly understood that the same :~
is by way of illustration and example only and is not to be
taken by way of limitation, the spirit and scope of this
invention being limited only by the terms of appended claims.
~ . ' '
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~ 10 ~ ~
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